{"payload":{"header_redesign_enabled":false,"results":[{"id":"16964283","archived":false,"color":"#3572A5","followers":1128,"has_funding_file":false,"hl_name":"olofk/fusesoc","hl_trunc_description":"Package manager and build abstraction tool for FPGA/ASIC development","language":"Python","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":16964283,"name":"fusesoc","owner_id":2194902,"owner_login":"olofk","updated_at":"2024-05-26T08:53:42.849Z","has_issues":true}},"sponsorable":false,"topics":["python","package-manager","fpga","vhdl","eda","verilog","reuse"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":60,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aolofk%252Ffusesoc%2B%2Blanguage%253APython","metadata":null,"csrf_tokens":{"/olofk/fusesoc/star":{"post":"0eq4YnlkRI8ppW5OttPuHM0xF2agPMNf2OuF82WGstdb6KT4pk8CiGXIEeahf-qZVjAqH0IvsKjfQdsKslDAXA"},"/olofk/fusesoc/unstar":{"post":"ep1pPAwRuD_yd1-TH-x27aM4zmrR1URs2PtRz_KDYvDsyZjvpPxuVpyTyjGgQOcCqemBx1JvaOSsJQPE04IpZQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"_znx3_6LlWPudMxHSfHwoeVZwfuhPDEuKfj0K4UxwzFb6V0AT5pHPUsh0_l5aRy5nOhwwieyYF0ely_h3xx2Uw"}}},"title":"Repository search results"}