{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"VexRiscv","owner":"SpinalHDL","isFork":false,"description":"A FPGA friendly 32 bit RISC-V CPU implementation","allTopics":["fpga","vhdl","riscv","verilog","spinalhdl","softcore","cpu","soc"],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":5,"issueCount":101,"starsCount":2301,"forksCount":387,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T13:44:26.515Z"}},{"type":"Public","name":"riscv-compliance","owner":"SpinalHDL","isFork":true,"description":"","allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":183,"license":"BSD 3-Clause \"New\" or \"Revised\" License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-03-15T13:52:18.159Z"}},{"type":"Public","name":"VexRiscvRegressionData","owner":"SpinalHDL","isFork":false,"description":"Used to store heavy data required to run full VexRiscv regressions","allTopics":[],"primaryLanguage":{"name":"Assembly","color":"#6E4C13"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":8,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2019-04-21T15:53:28.573Z"}}],"repositoryCount":3,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}