+
+//*****************************************************************************
+//
+// Enable the IAR extensions for this source file.
+//
+//*****************************************************************************
+#pragma language=extended
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+static void NmiSR(void);
+static void FaultISR(void);
+static void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// External declaration for the interrupt handler used by the application.
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern void __iar_program_start(void);
+extern void xPortPendSVHandler(void);
+extern void xPortSysTickHandler(void);
+extern void vPortSVCHandler(void);
+extern void vDualTimer1Handler( void );
+extern void TIMER0_Handler( void );
+extern void TIMER1_Handler( void );
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+#ifndef STACK_SIZE
+#define STACK_SIZE 120
+#endif
+static unsigned long pulStack[STACK_SIZE] @ ".noinit";
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table. The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+ void (*pfnHandler)(void);
+ unsigned long ulPtr;
+}
+uVectorEntry;
+
+//*****************************************************************************
+//
+// The minimal vector table for a Cortex-M3. Note that the proper constructs
+// must be placed on this to ensure that it ends up at physical address
+// 0x0000.0000.
+//
+//*****************************************************************************
+__root const uVectorEntry __vector_table[] @ ".intvec" =
+{
+ { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },
+ // The initial stack pointer
+ __iar_program_start, // The reset handler
+ NmiSR, // The NMI handler
+ FaultISR, // The hard fault handler
+ IntDefaultHandler, // The MPU fault handler
+ IntDefaultHandler, // The bus fault handler
+ IntDefaultHandler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ vPortSVCHandler, // SVCall handler
+ IntDefaultHandler, // Debug monitor handler
+ 0, // Reserved
+ xPortPendSVHandler, // The PendSV handler
+ xPortSysTickHandler, // The SysTick handler
+ 0, // uart0 receive 0
+ 0, // uart0 transmit
+ 0, // uart1 receive
+ 0, // uart1 transmit
+ 0, // uart 2 receive
+ 0, // uart 2 transmit
+ 0, // GPIO 0 combined interrupt
+ 0, // GPIO 2 combined interrupt
+ TIMER0_Handler, // Timer 0
+ TIMER1_Handler, // Timer 1
+ 0, // Dual Timer
+ 0, // SPI0 SPI1
+ 0, // uart overflow 1, 2,3
+ 0 // Ethernet 13
+};
+
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI. This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+static void
+NmiSR(void)
+{
+ //
+ // Enter an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a fault
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+FaultISR(void)
+{
+ //
+ // Enter an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+ //
+ // Go into an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
diff --git a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h
index 41861eed2..8a9e27ebf 100644
--- a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h
+++ b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c
index d8af2cbc9..e5807b08a 100644
--- a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c
+++ b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/GCC_Specific/RegTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c
index 233548dae..cbb738c73 100644
--- a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c
+++ b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/Keil_Specific/RegTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c
index 38bda4f76..bb45013db 100644
--- a/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c
+++ b/Demo/CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h
index 794443c1c..2f8e864c7 100644
--- a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h
+++ b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c
index 83f84b092..f8b774d77 100644
--- a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c
+++ b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c
index 28684c8f6..15d8e99f4 100644
--- a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c
+++ b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h
index f0cfb95a9..929b81570 100644
--- a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h
+++ b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
#ifndef __MPU_DEMO_H__
@@ -38,7 +37,7 @@
* by the task with Read Only access and if so, it recovers from the fault
* greacefully by moving the Program Counter to the next instruction to the one
* which generated the fault. If any other memory access violation occurs, the
- * fault handler will get stuck in an inifinite loop.
+ * fault handler will get stuck in an infinite loop.
*/
void vStartMPUDemo( void );
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/libs/libpower_hardabi.a b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/libs/libpower_hardabi.a
new file mode 100644
index 000000000..0e5c92f49
Binary files /dev/null and b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/libs/libpower_hardabi.a differ
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/libs/libpower_softabi.a b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/libs/libpower_softabi.a
new file mode 100644
index 000000000..78e7c633e
Binary files /dev/null and b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/libs/libpower_softabi.a differ
diff --git a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c
index c2b143a43..504c1b8eb 100644
--- a/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c
+++ b/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h
index 1731b8f11..79a5a1bbd 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Config/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/fault_handler.s b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/fault_handler.s
index 76482897e..8323fc11f 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/fault_handler.s
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/fault_handler.s
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c
index 94a8b5b77..03704f108 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/NonSecure/main_ns.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c
index c8a4bf135..3f9274422 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/IAR/Secure/main_s.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h
index 1731b8f11..79a5a1bbd 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Config/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c
index e6a0e7160..5941e2a13 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/NonSecure/main_ns.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c
index 848dd2c50..c3800c945 100644
--- a/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c
+++ b/Demo/CORTEX_MPU_M23_Nuvoton_NuMaker_PFM_M2351_IAR_GCC/Projects/Keil/Secure/main_s.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h
deleted file mode 100644
index dfea7460e..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_common_tables.h
- * Description: Extern declaration for common tables
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /* ARM_COMMON_TABLES_H */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h
deleted file mode 100644
index 80a3e8bbe..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_const_structs.h
- * Description: Constant structs that are initialized for user convenience.
- * For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_math.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_math.h
deleted file mode 100644
index 3288e37ca..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/arm_math.h
+++ /dev/null
@@ -1,7210 +0,0 @@
-/******************************************************************************
- * @file arm_math.h
- * @brief Public header file for CMSIS DSP Library
- * @version V1.6.0
- * @date 18. March 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * Introduction
- * ------------
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of functions each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transform functions
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * Using the Library
- * ------------
- *
- * The library installer contains prebuilt versions of the libraries in the Lib folder.
- * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
- * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
- * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
- * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
- * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
- * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
- * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
- * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
- * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
- * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
- * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
- * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
- * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
- * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
- * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
- * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
- * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
- * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
- * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
- *
- * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- *
- *
- * Examples
- * --------
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * Toolchain Support
- * ------------
- *
- * The library has been developed and tested with MDK version 5.14.0.0
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * Building the Library
- * ------------
- *
- * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder.
- * - arm_cortexM_math.uvprojx
- *
- *
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
- *
- * Preprocessor Macros
- * ------------
- *
- * Each library project have different preprocessor macros.
- *
- * - ARM_MATH_BIG_ENDIAN:
- *
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * - ARM_MATH_MATRIX_CHECK:
- *
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
- *
- * - ARM_MATH_ROUNDING:
- *
- * Define macro ARM_MATH_ROUNDING for rounding on support functions
- *
- * - ARM_MATH_LOOPUNROLL:
- *
- * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
- *
- * ARM::CMSIS Pack directories:
- * |File/Folder |Content |
- * |---------------------------------|------------------------------------------------------------------------|
- * |\b CMSIS\\Documentation\\DSP | This documentation |
- * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite |
- * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |
- * |\b CMSIS\\DSP\\Include | DSP_Lib include files |
- * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries |
- * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries |
- * |\b CMSIS\\DSP\\Source | DSP_Lib source files |
- *
- *
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size numRows X numCols
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- *
- * pData[i*numCols + j]
- *
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
- * for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- *
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns
- * specifies the number of columns, and pData points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- *
- * ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return
- *
- * ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- *
- * ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return ARM_MATH_SUCCESS.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-
-
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* Compiler specific diagnostic adjustment */
-#if defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wsign-conversion"
- #pragma GCC diagnostic ignored "-Wconversion"
- #pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
- #error Unknown compiler
-#endif
-
-
-#include "cmsis_compiler.h"
-#include "string.h"
-#include "math.h"
-
-/* evaluate ARM architecture */
-#if defined (__ARM_ARCH_6M__)
- #define ARM_MATH_CM0_FAMILY 1
-#elif defined (__ARM_ARCH_7M__)
-//#define ARM_MATH_CM0_FAMILY 0
-#elif defined (__ARM_ARCH_7EM__)
-//#define ARM_MATH_CM0_FAMILY 0
-#elif defined (__ARM_ARCH_8M_BASE__)
- #define ARM_MATH_CM0_FAMILY 1
-#elif defined (__ARM_ARCH_8M_MAIN__)
-//#define ARM_MATH_CM0_FAMILY 0
-#else
- #error "Unknown Arm Architecture!"
-#endif
-
-/* evaluate ARM DSP feature */
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
- #define ARM_MATH_DSP 1
-#endif
-
-
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#ifndef PI
- #define PI 3.14159265358979f
-#endif
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE 512
-#define FAST_MATH_Q31_SHIFT (32 - 10)
-#define FAST_MATH_Q15_SHIFT (16 - 10)
-#define CONTROLLER_Q31_SHIFT (32 - 9)
-#define TABLE_SPACING_Q31 0x400000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
-
-/**
- @brief definition to read/write two 16 bit values.
- @deprecated
- */
-#if defined ( __CC_ARM )
- #define __SIMD32_TYPE int32_t __packed
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
- #define __SIMD32_TYPE int32_t
-#elif defined ( __GNUC__ )
- #define __SIMD32_TYPE int32_t
-#elif defined ( __ICCARM__ )
- #define __SIMD32_TYPE int32_t __packed
-#elif defined ( __TI_ARM__ )
- #define __SIMD32_TYPE int32_t
-#elif defined ( __CSMC__ )
- #define __SIMD32_TYPE int32_t
-#elif defined ( __TASKING__ )
- #define __SIMD32_TYPE __unaligned int32_t
-#else
- #error Unknown compiler
-#endif
-
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
-#define __SIMD64(addr) (*( int64_t **) & (addr))
-
-/* SIMD replacement */
-
-/**
- @brief Read 2 Q15 from Q15 pointer.
- @param[in] pQ15 points to input value
- @return Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2 (
- q15_t * pQ15)
-{
- q31_t val;
-
- memcpy (&val, pQ15, 4);
-
- return (val);
-}
-
-/**
- @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
- @param[in] pQ15 points to input value
- @return Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2_ia (
- q15_t ** pQ15)
-{
- q31_t val;
-
- memcpy (&val, *pQ15, 4);
- *pQ15 += 2;
-
- return (val);
-}
-
-/**
- @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
- @param[in] pQ15 points to input value
- @return Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2_da (
- q15_t ** pQ15)
-{
- q31_t val;
-
- memcpy (&val, *pQ15, 4);
- *pQ15 -= 2;
-
- return (val);
-}
-
-/**
- @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
- @param[in] pQ15 points to input value
- @param[in] value Q31 value
- @return none
- */
-__STATIC_FORCEINLINE void write_q15x2_ia (
- q15_t ** pQ15,
- q31_t value)
-{
- q31_t val = value;
-
- memcpy (*pQ15, &val, 4);
- *pQ15 += 2;
-}
-
-/**
- @brief Write 2 Q15 to Q15 pointer.
- @param[in] pQ15 points to input value
- @param[in] value Q31 value
- @return none
- */
-__STATIC_FORCEINLINE void write_q15x2 (
- q15_t * pQ15,
- q31_t value)
-{
- q31_t val = value;
-
- memcpy (pQ15, &val, 4);
-}
-
-
-/**
- @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
- @param[in] pQ7 points to input value
- @return Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q7x4_ia (
- q7_t ** pQ7)
-{
- q31_t val;
-
- memcpy (&val, *pQ7, 4);
- *pQ7 += 4;
-
- return (val);
-}
-
-/**
- @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
- @param[in] pQ7 points to input value
- @return Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q7x4_da (
- q7_t ** pQ7)
-{
- q31_t val;
-
- memcpy (&val, *pQ7, 4);
- *pQ7 -= 4;
-
- return (val);
-}
-
-/**
- @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
- @param[in] pQ7 points to input value
- @param[in] value Q31 value
- @return none
- */
-__STATIC_FORCEINLINE void write_q7x4_ia (
- q7_t ** pQ7,
- q31_t value)
-{
- q31_t val = value;
-
- memcpy (*pQ7, &val, 4);
- *pQ7 += 4;
-}
-
-
-#ifndef ARM_MATH_DSP
- /**
- * @brief definition to pack two 16 bit values.
- */
- #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
- #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
-#endif
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
- #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
- #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
- __STATIC_FORCEINLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y) ) );
- }
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
- __STATIC_FORCEINLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- const q31_t * pRecipTable)
- {
- q31_t out;
- uint32_t tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if (in > 0)
- {
- signBits = ((uint32_t) (__CLZ( in) - 1));
- }
- else
- {
- signBits = ((uint32_t) (__CLZ(-in) - 1));
- }
-
- /* Convert input sample to 1.31 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 24);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0U; i < 2U; i++)
- {
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);
- tempVal = 0x7FFFFFFFu - tempVal;
- /* 1.31 with exp 1 */
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1U);
- }
-
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
- __STATIC_FORCEINLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- const q15_t * pRecipTable)
- {
- q15_t out = 0;
- uint32_t tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if (in > 0)
- {
- signBits = ((uint32_t)(__CLZ( in) - 17));
- }
- else
- {
- signBits = ((uint32_t)(__CLZ(-in) - 17));
- }
-
- /* Convert input sample to 1.15 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 8);
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0U; i < 2U; i++)
- {
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFFu - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
- }
-
-
-/*
- * @brief C custom defined intrinsic functions
- */
-#if !defined (ARM_MATH_DSP)
-
- /*
- * @brief C custom defined QADD8
- */
- __STATIC_FORCEINLINE uint32_t __QADD8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB8
- */
- __STATIC_FORCEINLINE uint32_t __QSUB8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QADD16
- */
- __STATIC_FORCEINLINE uint32_t __QADD16(
- uint32_t x,
- uint32_t y)
- {
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
- q31_t r = 0, s = 0;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHADD16
- */
- __STATIC_FORCEINLINE uint32_t __SHADD16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB16
- */
- __STATIC_FORCEINLINE uint32_t __QSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSUB16
- */
- __STATIC_FORCEINLINE uint32_t __SHSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QASX
- */
- __STATIC_FORCEINLINE uint32_t __QASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHASX
- */
- __STATIC_FORCEINLINE uint32_t __SHASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSAX
- */
- __STATIC_FORCEINLINE uint32_t __QSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSAX
- */
- __STATIC_FORCEINLINE uint32_t __SHSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SMUSDX
- */
- __STATIC_FORCEINLINE uint32_t __SMUSDX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
- /*
- * @brief C custom defined SMUADX
- */
- __STATIC_FORCEINLINE uint32_t __SMUADX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined QADD
- */
- __STATIC_FORCEINLINE int32_t __QADD(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined QSUB
- */
- __STATIC_FORCEINLINE int32_t __QSUB(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined SMLAD
- */
- __STATIC_FORCEINLINE uint32_t __SMLAD(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLADX
- */
- __STATIC_FORCEINLINE uint32_t __SMLADX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLSDX
- */
- __STATIC_FORCEINLINE uint32_t __SMLSDX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALD
- */
- __STATIC_FORCEINLINE uint64_t __SMLALD(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALDX
- */
- __STATIC_FORCEINLINE uint64_t __SMLALDX(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMUAD
- */
- __STATIC_FORCEINLINE uint32_t __SMUAD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SMUSD
- */
- __STATIC_FORCEINLINE uint32_t __SMUSD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SXTB16
- */
- __STATIC_FORCEINLINE uint32_t __SXTB16(
- uint32_t x)
- {
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
- }
-
- /*
- * @brief C custom defined SMMLA
- */
- __STATIC_FORCEINLINE int32_t __SMMLA(
- int32_t x,
- int32_t y,
- int32_t sum)
- {
- return (sum + (int32_t) (((int64_t) x * y) >> 32));
- }
-
-#endif /* !defined (ARM_MATH_DSP) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] S points to an instance of the Q7 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- const q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- const q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] S points to an instance of the Q15 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q15 FIR filter (fast version).
- * @param[in] S points to an instance of the Q15 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns either
- * ARM_MATH_SUCCESS if initialization was successful or
- * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value.
- */
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- const q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] S points to an instance of the Q31 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q31 FIR filter (fast version).
- * @param[in] S points to an instance of the Q31 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- const q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] S points to an instance of the floating-point FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- const float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q15;
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_casd_df1_inst_f32;
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- const q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- const q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- const float32_t * pCoeffs,
- float32_t * pState);
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float64_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f64;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q31;
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pScratch);
-
- /**
- * @brief Q31, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either ARM_MATH_SIZE_MISMATCH
- * or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] pDst points to the output matrix
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
- */
-arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
-void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData);
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
-void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData);
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
-void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData);
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
- q15_t A1;
- q15_t A2;
-#else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the q15 PID Control structure
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues; /**< nValues */
- float32_t x1; /**< x1 */
- float32_t xSpacing; /**< xSpacing */
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q7(
- const q7_t * pSrcA,
- const q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q15(
- const q15_t * pSrcA,
- const q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q31(
- const q31_t * pSrcA,
- const q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_f32(
- const float32_t * pSrcA,
- const float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- const q15_t *pTwiddle; /**< points to the twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q31(
- const arm_cfft_radix2_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- const q31_t *pTwiddle; /**< points to the twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_f32(
- const arm_cfft_radix2_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
- const arm_cfft_instance_q15 * S,
- q15_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
- const arm_cfft_instance_q31 * S,
- q31_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_f32;
-
- void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct
- {
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
- uint16_t fftLenRFFT; /**< length of the real sequence */
- const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
- } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen);
-
-arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S );
-
-
- void arm_rfft_fast_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut,
- uint8_t ifftFlag);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- const float32_t *pTwiddle; /**< points to the twiddle factor table. */
- const float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
- */
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- const q31_t *pTwiddle; /**< points to the twiddle factor table. */
- const q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
- */
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q31 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- const q15_t *pTwiddle; /**< points to the twiddle factor table. */
- const q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
- */
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q15 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_f32(
- const float32_t * pSrcA,
- const float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q7(
- const q7_t * pSrcA,
- const q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q15(
- const q15_t * pSrcA,
- const q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q31(
- const q31_t * pSrcA,
- const q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_f32(
- const float32_t * pSrcA,
- const float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q7(
- const q7_t * pSrcA,
- const q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q15(
- const q15_t * pSrcA,
- const q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q31(
- const q31_t * pSrcA,
- const q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_f32(
- const float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q7(
- const q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q15(
- const q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q31(
- const q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q7(
- const q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_f32(
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q15(
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q31(
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_f32(
- const float32_t * pSrcA,
- const float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q7(
- const q7_t * pSrcA,
- const q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q15(
- const q15_t * pSrcA,
- const q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q31(
- const q31_t * pSrcA,
- const q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q7(
- const q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q15(
- const q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q31(
- const q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_f32(
- const float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q7(
- const q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q15(
- const q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q31(
- const q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_f32(
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q7(
- const q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q15(
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q31(
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_f32(
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q7(
- const q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q15(
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q31(
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_f32(
- const float32_t * pSrcA,
- uint32_t srcALen,
- const float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_fast_opt_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q31(
- const q31_t * pSrcA,
- uint32_t srcALen,
- const q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q31(
- const q31_t * pSrcA,
- uint32_t srcALen,
- const q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q7(
- const q7_t * pSrcA,
- uint32_t srcALen,
- const q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q7(
- const q7_t * pSrcA,
- uint32_t srcALen,
- const q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_f32(
- const float32_t * pSrcA,
- uint32_t srcALen,
- const float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_opt_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q31(
- const q31_t * pSrcA,
- uint32_t srcALen,
- const q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q31(
- const q31_t * pSrcA,
- uint32_t srcALen,
- const q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q7 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q7(
- const q7_t * pSrcA,
- uint32_t srcALen,
- const q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q7(
- const q7_t * pSrcA,
- uint32_t srcALen,
- const q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q31;
-
-/**
- @brief Instance structure for floating-point FIR decimator.
- */
-typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_f32;
-
-
-/**
- @brief Processing function for floating-point FIR decimator.
- @param[in] S points to an instance of the floating-point FIR decimator structure
- @param[in] pSrc points to the block of input data
- @param[out] pDst points to the block of output data
- @param[in] blockSize number of samples to process
- */
-void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
-/**
- @brief Initialization function for the floating-point FIR decimator.
- @param[in,out] S points to an instance of the floating-point FIR decimator structure
- @param[in] numTaps number of coefficients in the filter
- @param[in] M decimation factor
- @param[in] pCoeffs points to the filter coefficients
- @param[in] pState points to the state buffer
- @param[in] blockSize number of input samples to process per call
- @return execution status
- - \ref ARM_MATH_SUCCESS : Operation successful
- - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
- */
-arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- const float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- */
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- const q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q31(
- const arm_fir_decimate_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * blockSize is not a multiple of M.
- */
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- const q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- */
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- const q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- */
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- const q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length numTaps is not a multiple of the interpolation factor L.
- */
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- const float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- const q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_stereo_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f64;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_stereo_df2T_f32(
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f64(
- const arm_biquad_cascade_df2T_instance_f64 * S,
- float64_t * pSrc,
- float64_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- const float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_stereo_df2T_init_f32(
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- uint8_t numStages,
- const float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f64(
- arm_biquad_cascade_df2T_instance_f64 * S,
- uint8_t numStages,
- float64_t * pCoeffs,
- float64_t * pState);
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- const q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- const q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- const float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the Q15 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- */
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- const q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- const q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_f32(
- const float32_t * pSrcA,
- uint32_t srcALen,
- const float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
-/**
- @brief Correlation of Q15 sequences
- @param[in] pSrcA points to the first input sequence
- @param[in] srcALen length of the first input sequence
- @param[in] pSrcB points to the second input sequence
- @param[in] srcBLen length of the second input sequence
- @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-*/
-void arm_correlate_opt_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
-/**
- @brief Correlation of Q15 sequences.
- @param[in] pSrcA points to the first input sequence
- @param[in] srcALen length of the first input sequence
- @param[in] pSrcB points to the second input sequence
- @param[in] srcBLen length of the second input sequence
- @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
-/**
- @brief Correlation of Q15 sequences (fast version).
- @param[in] pSrcA points to the first input sequence
- @param[in] srcALen length of the first input sequence
- @param[in] pSrcB points to the second input sequence
- @param[in] srcBLen length of the second input sequence
- @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
- @return none
- */
-void arm_correlate_fast_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
-/**
- @brief Correlation of Q15 sequences (fast version).
- @param[in] pSrcA points to the first input sequence.
- @param[in] srcALen length of the first input sequence.
- @param[in] pSrcB points to the second input sequence.
- @param[in] srcBLen length of the second input sequence.
- @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
-void arm_correlate_fast_opt_q15(
- const q15_t * pSrcA,
- uint32_t srcALen,
- const q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q31(
- const q31_t * pSrcA,
- uint32_t srcALen,
- const q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
-/**
- @brief Correlation of Q31 sequences (fast version).
- @param[in] pSrcA points to the first input sequence
- @param[in] srcALen length of the first input sequence
- @param[in] pSrcB points to the second input sequence
- @param[in] srcBLen length of the second input sequence
- @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_fast_q31(
- const q31_t * pSrcA,
- uint32_t srcALen,
- const q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_correlate_opt_q7(
- const q7_t * pSrcA,
- uint32_t srcALen,
- const q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q7(
- const q7_t * pSrcA,
- uint32_t srcALen,
- const q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- const float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- const float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- const q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- const q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- const q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- const q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- const q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- const q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cos output.
- */
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCosVal);
-
-
- /**
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cosine output.
- */
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_f32(
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q31(
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q15(
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_f32(
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q31(
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q15(
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * S points to an instance of the PID control data structure. in
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- *
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd
- *
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return processed output sample.
- */
- __STATIC_FORCEINLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
-/**
- @brief Process function for the Q31 PID Control.
- @param[in,out] S points to an instance of the Q31 PID Control structure
- @param[in] in input sample to process
- @return processed output sample.
-
- \par Scaling and Overflow Behavior
- The function is implemented using an internal 64-bit accumulator.
- The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- Thus, if the accumulator result overflows it wraps around rather than clip.
- In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-__STATIC_FORCEINLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31U);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
-
-/**
- @brief Process function for the Q15 PID Control.
- @param[in,out] S points to an instance of the Q15 PID Control structure
- @param[in] in input sample to process
- @return processed output sample.
-
- \par Scaling and Overflow Behavior
- The function is implemented using a 64-bit internal accumulator.
- Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-__STATIC_FORCEINLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
-#if defined (ARM_MATH_DSP)
- /* Implementation of PID controller */
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
-#else
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0) * in;
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0];
- acc += (q31_t) S->A2 * S->state[1];
-#endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f64(
- const arm_matrix_instance_f64 * src,
- arm_matrix_instance_f64 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
- * in the two-phase orthogonal stator axis Ialpha and Ibeta.
- * When Ialpha is superposed with Ia as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
- * can be calculated using only Ia and Ib.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where Ia and Ib are the instantaneous stator phases and
- * pIalpha and pIbeta are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate a
- * @param[in] Ib input three-phase coordinate b
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @return none
- */
- __STATIC_FORCEINLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
- }
-
-
-/**
- @brief Clarke transform for Q31 version
- @param[in] Ia input three-phase coordinate a
- @param[in] Ib input three-phase coordinate b
- @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- @return none
-
- \par Scaling and Overflow Behavior
- The function is implemented using an internal 32-bit accumulator.
- The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- There is saturation on the addition, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where pIa and pIb are the instantaneous stator phases and
- * Ialpha and Ibeta are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate a
- * @param[out] pIb points to output three-phase coordinate b
- * @return none
- */
- __STATIC_FORCEINLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
- }
-
-
-/**
- @brief Inverse Clarke transform for Q31 version
- @param[in] Ialpha input two-phase orthogonal vector axis alpha
- @param[in] Ibeta input two-phase orthogonal vector axis beta
- @param[out] pIa points to output three-phase coordinate a
- @param[out] pIb points to output three-phase coordinate b
- @return none
-
- \par Scaling and Overflow Behavior
- The function is implemented using an internal 32-bit accumulator.
- The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- There is saturation on the subtraction, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
- }
-
- /**
- * @} end of inv_clarke group
- */
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where Ialpha and Ibeta are the stator vector components,
- * pId and pIq are rotor vector components and cosVal and sinVal are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none
- *
- * The function implements the forward Park transform.
- *
- */
- __STATIC_FORCEINLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
- }
-
-
-/**
- @brief Park transform for Q31 version
- @param[in] Ialpha input two-phase vector coordinate alpha
- @param[in] Ibeta input two-phase vector coordinate beta
- @param[out] pId points to output rotor reference frame d
- @param[out] pIq points to output rotor reference frame q
- @param[in] sinVal sine value of rotation angle theta
- @param[in] cosVal cosine value of rotation angle theta
- @return none
-
- \par Scaling and Overflow Behavior
- The function is implemented using an internal 32-bit accumulator.
- The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where pIalpha and pIbeta are the stator vector components,
- * Id and Iq are rotor vector components and cosVal and sinVal are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none
- */
- __STATIC_FORCEINLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
- }
-
-
-/**
- @brief Inverse Park transform for Q31 version
- @param[in] Id input coordinate of rotor reference frame d
- @param[in] Iq input coordinate of rotor reference frame q
- @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- @param[in] sinVal sine value of rotation angle theta
- @param[in] cosVal cosine value of rotation angle theta
- @return none
-
- @par Scaling and Overflow Behavior
- The function is implemented using an internal 32-bit accumulator.
- The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- There is saturation on the addition, hence there is no risk of overflow.
- */
-__STATIC_FORCEINLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- *
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- *
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * S points to an instance of the Linear Interpolate function data structure.
- * x is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
- __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (int32_t) ((x - S->x1) / xSpacing);
-
- if (i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if ((uint32_t)i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues - 1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i + 1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(
- q31_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (q31_t)0xFFF00000) >> 20);
-
- if (index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if (index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1U);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(
- q15_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (int32_t)0xFFF00000) >> 20);
-
- if (index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if (index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (q15_t) (y >> 20);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
- __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(
- q7_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- uint32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- if (x < 0)
- {
- return (pYData[0]);
- }
- index = (x >> 20) & 0xfff;
-
- if (index >= (nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (q7_t) (y >> 20);
- }
- }
-
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
- float32_t arm_sin_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q31_t arm_sin_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q15_t arm_sin_q15(
- q15_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
- float32_t arm_cos_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q31_t arm_cos_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- *
- * x1 = x0 - f(x0)/f'(x0)
- *
- * where x1 is the current estimate,
- * x0 is the previous estimate, and
- * f'(x0) is the derivative of f() evaluated at x0.
- * For the square root function, the algorithm reduces to:
- *
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- *
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
-/**
- @brief Floating-point square root function.
- @param[in] in input value
- @param[out] pOut square root of input value
- @return execution status
- - \ref ARM_MATH_SUCCESS : input value is positive
- - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
- */
-__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
- float32_t in,
- float32_t * pOut)
- {
- if (in >= 0.0f)
- {
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- *pOut = __sqrtf(in);
- #else
- *pOut = sqrtf(in);
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
- #else
- *pOut = sqrtf(in);
- #endif
-
-#else
- *pOut = sqrtf(in);
-#endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
- }
-
-
-/**
- @brief Q31 square root function.
- @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
- @param[out] pOut points to square root of input value
- @return execution status
- - \ref ARM_MATH_SUCCESS : input value is positive
- - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
- */
-arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut);
-
-
-/**
- @brief Q15 square root function.
- @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
- @param[out] pOut points to square root of input value
- @return execution status
- - \ref ARM_MATH_SUCCESS : input value is positive
- - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
- */
-arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
- /**
- * @brief floating-point Circular write function.
- */
- __STATIC_FORCEINLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0U;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0U)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- __STATIC_FORCEINLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0U;
- int32_t rOffset;
- int32_t* dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = dst_base + dst_length;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0U)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q15 Circular write function.
- */
- __STATIC_FORCEINLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0U;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0U)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- __STATIC_FORCEINLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset;
- q15_t* dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = dst_base + dst_length;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0U)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
- __STATIC_FORCEINLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0U;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0U)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- __STATIC_FORCEINLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset;
- q7_t* dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = dst_base + dst_length;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0U)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q7(
- const q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q7(
- const q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_f32(
- const float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q31(
- const q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q15(
- const q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q15(
- const q15_t * pSrcA,
- const q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
-
- /**
- * @brief Q31 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q31(
- const q31_t * pSrcA,
- const q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_f32(
- const float32_t * pSrcA,
- const float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q15(
- const q15_t * pSrcCmplx,
- const q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q31(
- const q31_t * pSrcCmplx,
- const q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_f32(
- const float32_t * pSrcCmplx,
- const float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- */
- void arm_min_q7(
- const q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[in] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q7(
- const q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q15(
- const q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q31(
- const q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_f32(
- const float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q15(
- const q15_t * pSrcA,
- const q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q31(
- const q31_t * pSrcA,
- const q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_f32(
- const float32_t * pSrcA,
- const float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q31(
- const float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q15(
- const float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q7(
- const float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_float(
- const q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q15(
- const q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q7(
- const q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_float(
- const q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q31(
- const q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q7(
- const q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q7_to_float(
- const q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q31(
- const q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q15(
- const q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * Algorithm
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- *
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- *
- *
- * \par
- * where numRows specifies the number of rows in the table;
- * numCols specifies the number of columns in the table;
- * and pData points to an array of size numRows*numCols values.
- * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
- *
- * \par
- * Let (x, y) specify the desired interpolation point. Then define:
- *
- * XF = floor(x)
- * YF = floor(y)
- *
- * \par
- * The interpolated output point is computed as:
- *
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- *
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
- /**
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
- __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
- {
- return (0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- * @brief Q31 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11U;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11U;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return ((q31_t)(acc << 2));
- }
-
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return ((q15_t)(acc >> 36));
- }
-
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return ((q7_t)(acc >> 40));
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM )
- /* Enter low optimization region - place directly above function definition */
- #if defined( __ARM_ARCH_7EM__ )
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #if defined ( __ARM_ARCH_7EM__ )
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
- #else
- #define LOW_OPTIMIZATION_EXIT
- #endif
-
- /* Enter low optimization region - place directly above function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
- #define LOW_OPTIMIZATION_ENTER \
- __attribute__(( optimize("-O1") ))
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
- /* Enter low optimization region - place directly above function definition */
- #if defined ( __ARM_ARCH_7EM__ )
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define LOW_OPTIMIZATION_EXIT
-
- /* Enter low optimization region - place directly above function definition */
- #if defined ( __ARM_ARCH_7EM__ )
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
- #error Unknown compiler
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h
index 174d74403..59f173ac7 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version V5.0.5
- * @date 14. December 2018
+ * @version V5.1.0
+ * @date 08. May 2019
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -104,6 +104,31 @@
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h
index 6a8867d57..e917f357a 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
- * @version V5.1.0
- * @date 14. March 2019
+ * @version V5.2.0
+ * @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -110,7 +110,31 @@
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h
index e4002a3fc..feec32405 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_armclang_ltm.h
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_armclang_ltm.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
- * @version V1.0.1
- * @date 19. March 2019
+ * @version V1.2.0
+ * @date 08. May 2019
******************************************************************************/
/*
* Copyright (c) 2018-2019 Arm Limited. All rights reserved.
@@ -110,6 +110,31 @@
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
+#endif
/* ########################### Core Function Access ########################### */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h
index fdb1a971c..adbf296f1 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h
@@ -123,6 +123,10 @@
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
/*
@@ -192,6 +196,10 @@
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
/*
@@ -260,6 +268,10 @@
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
#else
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
index d86b0a2d5..3ddcc58b6 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_gcc.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler GCC header file
- * @version V5.1.0
- * @date 20. December 2018
+ * @version V5.2.0
+ * @date 08. May 2019
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -113,7 +113,74 @@
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
+#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
index 20b50ce38..12d68fd9a 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h
@@ -1,13 +1,14 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version V5.0.8
- * @date 04. September 2018
+ * @version V5.1.0
+ * @date 08. May 2019
******************************************************************************/
//------------------------------------------------------------------------------
//
-// Copyright (c) 2017-2018 IAR Systems
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
@@ -110,6 +111,10 @@
#define __ASM __asm
#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
#ifndef __INLINE
#define __INLINE inline
#endif
@@ -239,6 +244,25 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#endif
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h
index 660f612aa..f2e274662 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
- * @version V5.0.2
- * @date 19. April 2017
+ * @version V5.0.3
+ * @date 24. June 2019
******************************************************************************/
/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,7 +33,7 @@
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_armv81mml.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_armv81mml.h
deleted file mode 100644
index db6d9f236..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/core_armv81mml.h
+++ /dev/null
@@ -1,2967 +0,0 @@
-/**************************************************************************//**
- * @file core_armv81mml.h
- * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
- * @version V1.0.0
- * @date 15. March 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV81MML_H_GENERIC
-#define __CORE_ARMV81MML_H_GENERIC
-
-#include
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv81MML */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED6[580U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
- uint32_t RESERVED6[4U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
- uint32_t RESERVED32[934U];
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
- uint32_t RESERVED33[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
- uint32_t RESERVED0[1];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
-#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#else
- uint32_t RESERVED0[3];
-#endif
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Grouping (non-secure)
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB_NS->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB_NS->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping (non-secure)
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device .h
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- uint32_t RESERVED0[6U];
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
- uint32_t RESERVED3[809U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
- uint32_t RESERVED4[4U];
- __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI Periodic Synchronization Control Register Definitions */
-#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
-#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
-
-/* TPI Software Lock Status Register Definitions */
-#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
-#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
-
-#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
-#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
-
-#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
-#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- uint32_t RESERVED0[7U];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
-#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
-#else
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
-#endif
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping() (0U)
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device .h
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED6[580U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[32U];
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
- uint32_t RESERVED6[4U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
- uint32_t RESERVED32[934U];
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
- uint32_t RESERVED33[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
- uint32_t RESERVED3[809U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
- uint32_t RESERVED4[4U];
- __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI Periodic Synchronization Control Register Definitions */
-#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
-#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
-
-/* TPI Software Lock Status Register Definitions */
-#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
-#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
-
-#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
-#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
-
-#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
-#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
- uint32_t RESERVED0[1];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#else
- uint32_t RESERVED0[3];
-#endif
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
-#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
-#else
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
-#endif
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Grouping (non-secure)
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB_NS->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- SCB_NS->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping (non-secure)
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable __Vendor_SysTickConfig is set to 1, then the
- function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
- function TZ_SysTick_Config_NS is not included. In this case, the file device .h
-
-#include "serial_manager.h"
-#include "serial_port_internal.h"
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-#include "generic_list.h"
-
-/*
- * The OSA_USED macro can only be defined when the OSA component is used.
- * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
- * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
- * also cannot be defined.
- * The source code path of the OSA component is /components/osa.
- *
- */
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-#include "common_task.h"
-#else
-#include "fsl_os_abstraction.h"
-#endif
-
-#endif
-
-#endif
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-#ifndef NDEBUG
-#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
-#undef assert
-#define assert(n)
-#endif
-#endif
-
-#define SERIAL_EVENT_DATA_RECEIVED (1U << 0)
-#define SERIAL_EVENT_DATA_SENT (1U << 1)
-
-#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U
-#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-typedef enum _serial_manager_transmission_mode
-{
- kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/
- kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/
-} serial_manager_transmission_mode_t;
-
-/* TX transfer structure */
-typedef struct _serial_manager_transfer
-{
- uint8_t *buffer;
- volatile uint32_t length;
- volatile uint32_t soFar;
- serial_manager_transmission_mode_t mode;
- serial_manager_status_t status;
-} serial_manager_transfer_t;
-#endif
-
-/* write handle structure */
-typedef struct _serial_manager_send_handle
-{
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- list_element_t link; /*!< list element of the link */
- serial_manager_transfer_t transfer;
-#endif
- struct _serial_manager_handle *serialManagerHandle;
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- serial_manager_callback_t callback;
- void *callbackParam;
- uint32_t tag;
-#endif
-} serial_manager_write_handle_t;
-
-typedef serial_manager_write_handle_t serial_manager_read_handle_t;
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-/* receive state structure */
-typedef struct _serial_manager_read_ring_buffer
-{
- uint8_t *ringBuffer;
- uint32_t ringBufferSize;
- volatile uint32_t ringHead;
- volatile uint32_t ringTail;
-} serial_manager_read_ring_buffer_t;
-#endif
-
-#if defined(__CC_ARM)
-#pragma anon_unions
-#endif
-/* The serial manager handle structure */
-typedef struct _serial_manager_handle
-{
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- list_label_t runningWriteHandleHead; /*!< The queue of running write handle */
- list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */
-#endif
- serial_manager_read_handle_t *volatile openedReadHandleHead;
- volatile uint32_t openedWriteHandleCount;
- union
- {
- uint8_t lowLevelhandleBuffer[1];
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE];
-#endif
- };
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- serial_manager_read_ring_buffer_t ringBuffer;
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
- common_task_message_t commontaskMsg;
-#else
- uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */
- uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */
-#endif
-
-#endif
-
-#endif
-
- serial_port_type_t type;
-} serial_manager_handle_t;
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-static void SerialManager_Task(void *param);
-#endif
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-
-#else
- /*
- * \brief Defines the serial manager task's stack
- */
-OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);
-#endif
-
-#endif
-
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node)
-{
- (void)LIST_AddTail(queue, &node->link);
-}
-
-static void SerialManager_RemoveHead(list_label_t *queue)
-{
- (void)LIST_RemoveHead(queue);
-}
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle)
-{
- serial_manager_status_t status = kStatus_SerialManager_Error;
- serial_manager_write_handle_t *writeHandle =
- (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
-
- if (writeHandle != NULL)
- {
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- writeHandle->transfer.buffer, writeHandle->transfer.length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- writeHandle->transfer.buffer, writeHandle->transfer.length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- writeHandle->transfer.buffer, writeHandle->transfer.length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- writeHandle->transfer.buffer, writeHandle->transfer.length);
- break;
-#endif
- default:
- status = kStatus_SerialManager_Error;
- break;
- }
- }
- return status;
-}
-
-static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
- serial_manager_read_handle_t *readHandle,
- uint8_t *buffer,
- uint32_t length)
-{
- serial_manager_status_t status = kStatus_SerialManager_Error;
-
- if (NULL != readHandle)
- {
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- if (handle->type == kSerialPort_UsbCdc)
- {
- status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- }
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- if (handle->type == kSerialPort_UsbCdcVirtual)
- {
- status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- }
-#endif
- }
- return status;
-}
-
-#else
-
-static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle,
- serial_manager_write_handle_t *writeHandle,
- uint8_t *buffer,
- uint32_t length)
-{
- serial_manager_status_t status = kStatus_SerialManager_Error;
-
- if (NULL != writeHandle)
- {
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
- default:
- status = kStatus_SerialManager_Error;
- break;
- }
- }
- return status;
-}
-
-static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,
- serial_manager_read_handle_t *readHandle,
- uint8_t *buffer,
- uint32_t length)
-{
- serial_manager_status_t status = kStatus_SerialManager_Error;
-
- if (NULL != readHandle)
- {
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);
- break;
-#endif
- default:
- status = kStatus_SerialManager_Error;
- break;
- }
- }
- return status;
-}
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-static void SerialManager_IsrFunction(serial_manager_handle_t *handle)
-{
- uint32_t regPrimask = DisableGlobalIRQ();
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
- default:
- /*MISRA rule 16.4*/
- break;
- }
- EnableGlobalIRQ(regPrimask);
-}
-
-static void SerialManager_Task(void *param)
-{
- serial_manager_handle_t *handle = (serial_manager_handle_t *)param;
- serial_manager_write_handle_t *serialWriteHandle;
- serial_manager_read_handle_t *serialReadHandle;
- uint32_t primask;
- serial_manager_callback_message_t msg;
-
- if (NULL != handle)
- {
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-#else
- osa_event_flags_t ev = 0;
-
- do
- {
- if (KOSA_StatusSuccess ==
- OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev))
- {
- if (ev & SERIAL_EVENT_DATA_SENT)
-#endif
-
-#endif
- {
- serialWriteHandle =
- (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
- while (NULL != serialWriteHandle)
- {
- SerialManager_RemoveHead(&handle->completedWriteHandleHead);
- msg.buffer = serialWriteHandle->transfer.buffer;
- msg.length = serialWriteHandle->transfer.soFar;
- serialWriteHandle->transfer.buffer = NULL;
- if (NULL != serialWriteHandle->callback)
- {
- serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg,
- serialWriteHandle->transfer.status);
- }
- serialWriteHandle =
- (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead);
- }
- }
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-#else
- if (ev & SERIAL_EVENT_DATA_RECEIVED)
-#endif
-
-#endif
- {
- primask = DisableGlobalIRQ();
- serialReadHandle = handle->openedReadHandleHead;
- EnableGlobalIRQ(primask);
-
- if (NULL != serialReadHandle)
- {
- if (NULL != serialReadHandle->transfer.buffer)
- {
- if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
- {
- msg.buffer = serialReadHandle->transfer.buffer;
- msg.length = serialReadHandle->transfer.soFar;
- serialReadHandle->transfer.buffer = NULL;
- if (NULL != serialReadHandle->callback)
- {
- serialReadHandle->callback(serialReadHandle->callbackParam, &msg,
- serialReadHandle->transfer.status);
- }
- }
- }
- }
- }
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-#else
- }
- } while (gUseRtos_c);
-#endif
-
-#endif
- }
-}
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-static void SerialManager_TxCallback(void *callbackParam,
- serial_manager_callback_message_t *message,
- serial_manager_status_t status)
-{
- serial_manager_handle_t *handle;
- serial_manager_write_handle_t *writeHandle;
-
- assert(callbackParam);
- assert(message);
-
- handle = (serial_manager_handle_t *)callbackParam;
-
- writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead);
-
- if (NULL != writeHandle)
- {
- SerialManager_RemoveHead(&handle->runningWriteHandleHead);
- (void)SerialManager_StartWriting(handle);
- writeHandle->transfer.soFar = message->length;
- writeHandle->transfer.status = status;
- if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)
- {
- SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle);
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
- handle->commontaskMsg.callback = SerialManager_Task;
- handle->commontaskMsg.callbackParam = handle;
- COMMON_TASK_post_message(&handle->commontaskMsg);
-#else
- (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT);
-#endif
-
-#else
- SerialManager_Task(handle);
-#endif
- }
- else
- {
- writeHandle->transfer.buffer = NULL;
- }
- }
-}
-
-static void SerialManager_RxCallback(void *callbackParam,
- serial_manager_callback_message_t *message,
- serial_manager_status_t status)
-{
- serial_manager_handle_t *handle;
- uint32_t ringBufferLength;
- uint32_t primask;
-
- assert(callbackParam);
- assert(message);
-
- handle = (serial_manager_handle_t *)callbackParam;
-
- status = kStatus_SerialManager_Notify;
-
- for (uint32_t i = 0; i < message->length; i++)
- {
- handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i];
- if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize)
- {
- handle->ringBuffer.ringHead = 0U;
- }
- if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail)
- {
- status = kStatus_SerialManager_RingBufferOverflow;
- handle->ringBuffer.ringTail++;
- if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
- {
- handle->ringBuffer.ringTail = 0U;
- }
- }
- }
-
- ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
- ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;
-
- primask = DisableGlobalIRQ();
- if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->transfer.buffer))
- {
- if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
- {
- uint32_t remainLength =
- handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar;
- for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++)
- {
- handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] =
- handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
- handle->ringBuffer.ringTail++;
- handle->openedReadHandleHead->transfer.soFar++;
- if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
- {
- handle->ringBuffer.ringTail = 0U;
- }
- }
- ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);
- }
-
- if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)
- {
- }
- else
- {
- if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode)
- {
- handle->openedReadHandleHead->transfer.buffer = NULL;
- }
- else
- {
- handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;
-
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
- handle->commontaskMsg.callback = SerialManager_Task;
- handle->commontaskMsg.callbackParam = handle;
- COMMON_TASK_post_message(&handle->commontaskMsg);
-#else
- (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED);
-#endif
-
-#else
- SerialManager_Task(handle);
-#endif
- }
- }
- }
-
- if (0U != ringBufferLength)
- {
- message->buffer = NULL;
- message->length = ringBufferLength;
- if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback))
- {
- handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status);
- }
- }
-
- ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength;
-
- if (NULL != handle->openedReadHandleHead)
- {
- (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength);
- }
- EnableGlobalIRQ(primask);
-}
-
-static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,
- uint8_t *buffer,
- uint32_t length,
- serial_manager_transmission_mode_t mode)
-{
- serial_manager_write_handle_t *serialWriteHandle;
- serial_manager_handle_t *handle;
- serial_manager_status_t status = kStatus_SerialManager_Success;
- uint32_t primask;
- uint8_t isEmpty = 0U;
-
- assert(writeHandle);
- assert(buffer);
- assert(length);
-
- serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
- handle = serialWriteHandle->serialManagerHandle;
-
- assert(handle);
- assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
- assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));
-
- primask = DisableGlobalIRQ();
- if (NULL != serialWriteHandle->transfer.buffer)
- {
- EnableGlobalIRQ(primask);
- return kStatus_SerialManager_Busy;
- }
- serialWriteHandle->transfer.buffer = buffer;
- serialWriteHandle->transfer.length = length;
- serialWriteHandle->transfer.soFar = 0U;
- serialWriteHandle->transfer.mode = mode;
-
- if (NULL == LIST_GetHead(&handle->runningWriteHandleHead))
- {
- isEmpty = 1U;
- }
- SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle);
- EnableGlobalIRQ(primask);
-
- if (0U != isEmpty)
- {
- status = SerialManager_StartWriting(handle);
- if ((serial_manager_status_t)kStatus_SerialManager_Success != status)
- {
- return status;
- }
- }
-
- if (kSerialManager_TransmissionBlocking == mode)
- {
- while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)
- {
-#if defined(__GIC_PRIO_BITS)
- if (0x13 == (__get_CPSR() & CPSR_M_Msk))
-#else
- if (0U != __get_IPSR())
-#endif
- {
- SerialManager_IsrFunction(handle);
- }
- }
- }
- return kStatus_SerialManager_Success;
-}
-
-static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,
- uint8_t *buffer,
- uint32_t length,
- serial_manager_transmission_mode_t mode,
- uint32_t *receivedLength)
-{
- serial_manager_read_handle_t *serialReadHandle;
- serial_manager_handle_t *handle;
- uint32_t dataLength;
- uint32_t primask;
-
- assert(readHandle);
- assert(buffer);
- assert(length);
-
- serialReadHandle = (serial_manager_read_handle_t *)readHandle;
- handle = serialReadHandle->serialManagerHandle;
-
- assert(handle);
- assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
- assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));
-
- primask = DisableGlobalIRQ();
- if (NULL != serialReadHandle->transfer.buffer)
- {
- EnableGlobalIRQ(primask);
- return kStatus_SerialManager_Busy;
- }
- serialReadHandle->transfer.buffer = buffer;
- serialReadHandle->transfer.length = length;
- serialReadHandle->transfer.soFar = 0U;
- serialReadHandle->transfer.mode = mode;
-
- dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
- dataLength = dataLength % handle->ringBuffer.ringBufferSize;
-
- for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length);
- serialReadHandle->transfer.soFar++)
- {
- buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];
- handle->ringBuffer.ringTail++;
- if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)
- {
- handle->ringBuffer.ringTail = 0U;
- }
- }
-
- dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
- dataLength = dataLength % handle->ringBuffer.ringBufferSize;
- dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength;
-
- (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength);
-
- if (NULL != receivedLength)
- {
- *receivedLength = serialReadHandle->transfer.soFar;
- serialReadHandle->transfer.buffer = NULL;
- EnableGlobalIRQ(primask);
- }
- else
- {
- if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)
- {
- serialReadHandle->transfer.buffer = NULL;
- EnableGlobalIRQ(primask);
- if (kSerialManager_TransmissionNonBlocking == mode)
- {
- if (NULL != serialReadHandle->callback)
- {
- serial_manager_callback_message_t msg;
- msg.buffer = buffer;
- msg.length = serialReadHandle->transfer.soFar;
- serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success);
- }
- }
- }
- else
- {
- EnableGlobalIRQ(primask);
- }
-
- if (kSerialManager_TransmissionBlocking == mode)
- {
- while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)
- {
- }
- }
- }
-
- return kStatus_SerialManager_Success;
-}
-
-#else
-
-static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
-{
- serial_manager_write_handle_t *serialWriteHandle;
- serial_manager_handle_t *handle;
-
- assert(writeHandle);
- assert(buffer);
- assert(length);
-
- serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
- handle = serialWriteHandle->serialManagerHandle;
-
- assert(handle);
-
- return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length);
-}
-
-static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
-{
- serial_manager_read_handle_t *serialReadHandle;
- serial_manager_handle_t *handle;
-
- assert(readHandle);
- assert(buffer);
- assert(length);
-
- serialReadHandle = (serial_manager_read_handle_t *)readHandle;
- handle = serialReadHandle->serialManagerHandle;
-
- assert(handle);
-
- return SerialManager_StartReading(handle, serialReadHandle, buffer, length);
-}
-#endif
-
-serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config)
-{
- serial_manager_handle_t *handle;
- serial_manager_status_t status = kStatus_SerialManager_Error;
-
- assert(config);
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- assert(config->ringBuffer);
- assert(config->ringBufferSize);
-#endif
- assert(serialHandle);
- assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t));
-
- handle = (serial_manager_handle_t *)serialHandle;
-
- (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE);
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-
- COMMON_TASK_init();
-
-#else
- if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true))
- {
- return kStatus_SerialManager_Error;
- }
-
- if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle))
- {
- return kStatus_SerialManager_Error;
- }
-#endif
-
-#endif
-
-#endif
-
- handle->type = config->type;
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- handle->ringBuffer.ringBuffer = config->ringBuffer;
- handle->ringBuffer.ringBufferSize = config->ringBufferSize;
-#endif
-
- switch (config->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
- {
- status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_TxCallback, handle);
- if ((serial_manager_status_t)kStatus_SerialManager_Success == status)
- {
- status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_RxCallback, handle);
- }
- }
-#endif
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- if (kStatus_SerialManager_Success == status)
- {
- status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_TxCallback, handle);
- if (kStatus_SerialManager_Success == status)
- {
- status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_RxCallback, handle);
- }
- }
-#endif
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- if (kStatus_SerialManager_Success == status)
- {
- status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_TxCallback, handle);
- }
-#endif
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- if (kStatus_SerialManager_Success == status)
- {
- status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_TxCallback, handle);
- if (kStatus_SerialManager_Success == status)
- {
- status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),
- SerialManager_RxCallback, handle);
- }
- }
-#endif
- break;
-#endif
- default:
- /*MISRA rule 16.4*/
- break;
- }
-
- return status;
-}
-
-serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)
-{
- serial_manager_handle_t *handle;
- uint32_t primask;
-
- assert(serialHandle);
-
- handle = (serial_manager_handle_t *)serialHandle;
-
- primask = DisableGlobalIRQ();
- if ((NULL != handle->openedReadHandleHead) || (0U != handle->openedWriteHandleCount))
- {
- EnableGlobalIRQ(primask);
- return kStatus_SerialManager_Busy;
- }
- EnableGlobalIRQ(primask);
-
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- (void)Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
- default:
- /*MISRA rule 16.4*/
- break;
- }
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
-#else
- OSA_EventDestroy((osa_event_handle_t)handle->event);
- OSA_TaskDestroy((osa_task_handle_t)handle->taskId);
-#endif
-
-#endif
-
-#endif
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)
-{
- serial_manager_handle_t *handle;
- serial_manager_write_handle_t *serialWriteHandle;
- uint32_t primask;
-
- assert(serialHandle);
- assert(writeHandle);
- assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t));
-
- handle = (serial_manager_handle_t *)serialHandle;
- serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
-
- (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
-
- primask = DisableGlobalIRQ();
- handle->openedWriteHandleCount++;
- EnableGlobalIRQ(primask);
-
- serialWriteHandle->serialManagerHandle = handle;
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;
-#endif
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)
-{
- serial_manager_handle_t *handle;
- serial_manager_write_handle_t *serialWriteHandle;
- uint32_t primask;
-
- assert(writeHandle);
-
- serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
- handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle;
-
- assert(handle);
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- (void)SerialManager_CancelWriting(writeHandle);
-#endif
- primask = DisableGlobalIRQ();
- if (handle->openedWriteHandleCount > 0U)
- {
- handle->openedWriteHandleCount--;
- }
- EnableGlobalIRQ(primask);
-
- (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)
-{
- serial_manager_handle_t *handle;
- serial_manager_read_handle_t *serialReadHandle;
- uint32_t primask;
-
- assert(serialHandle);
- assert(readHandle);
- assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t));
-
- handle = (serial_manager_handle_t *)serialHandle;
- serialReadHandle = (serial_manager_read_handle_t *)readHandle;
-
- primask = DisableGlobalIRQ();
- if (handle->openedReadHandleHead != NULL)
- {
- EnableGlobalIRQ(primask);
- return kStatus_SerialManager_Busy;
- }
- handle->openedReadHandleHead = serialReadHandle;
- EnableGlobalIRQ(primask);
-
- (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
-
- serialReadHandle->serialManagerHandle = handle;
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;
-#endif
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)
-{
- serial_manager_handle_t *handle;
- serial_manager_read_handle_t *serialReadHandle;
- uint32_t primask;
-
- assert(readHandle);
-
- serialReadHandle = (serial_manager_read_handle_t *)readHandle;
- handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle;
-
- assert(handle && (handle->openedReadHandleHead == serialReadHandle));
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- (void)SerialManager_CancelReading(readHandle);
-#endif
-
- primask = DisableGlobalIRQ();
- handle->openedReadHandleHead = NULL;
- EnableGlobalIRQ(primask);
-
- (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)
-{
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);
-#else
- return SerialManager_Write(writeHandle, buffer, length);
-#endif
-}
-
-serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
-{
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);
-#else
- return SerialManager_Read(readHandle, buffer, length);
-#endif
-}
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
- uint8_t *buffer,
- uint32_t length)
-{
- return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);
-}
-
-serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)
-{
- return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);
-}
-
-serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)
-{
- serial_manager_write_handle_t *serialWriteHandle;
- uint32_t primask;
- uint8_t isNotUsed = 0;
-
- assert(writeHandle);
-
- serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
-
- assert(serialWriteHandle->serialManagerHandle);
- assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
-
- if ((NULL != serialWriteHandle->transfer.buffer) &&
- (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))
- {
- return kStatus_SerialManager_Error;
- }
-
- primask = DisableGlobalIRQ();
- if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead(
- &serialWriteHandle->serialManagerHandle->runningWriteHandleHead))
- {
- (void)LIST_RemoveElement(&serialWriteHandle->link);
- isNotUsed = 1;
- }
- EnableGlobalIRQ(primask);
-
- if (0U != isNotUsed)
- {
- serialWriteHandle->transfer.soFar = 0;
- serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;
-
- SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);
-#if defined(OSA_USED)
-
-#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))
- serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;
- serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle;
- COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);
-#else
- (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT);
-#endif
-
-#else
- SerialManager_Task(serialWriteHandle->serialManagerHandle);
-#endif
- }
- else
- {
- switch (serialWriteHandle->serialManagerHandle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- (void)Serial_UartCancelWrite(
- ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- (void)Serial_UsbCdcCancelWrite(
- ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- (void)Serial_SwoCancelWrite(
- ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- (void)Serial_UsbCdcVirtualCancelWrite(
- ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));
- break;
-#endif
- default:
- /*MISRA rule 16.4*/
- break;
- }
- }
-
- (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)
-{
- serial_manager_read_handle_t *serialReadHandle;
- serial_manager_callback_message_t msg;
- uint8_t *buffer;
- uint32_t primask;
-
- assert(readHandle);
-
- serialReadHandle = (serial_manager_read_handle_t *)readHandle;
-
- assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
-
- if ((NULL != serialReadHandle->transfer.buffer) &&
- (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))
- {
- return kStatus_SerialManager_Error;
- }
-
- primask = DisableGlobalIRQ();
- buffer = serialReadHandle->transfer.buffer;
- serialReadHandle->transfer.buffer = NULL;
- serialReadHandle->transfer.length = 0;
- msg.buffer = buffer;
- msg.length = serialReadHandle->transfer.soFar;
- EnableGlobalIRQ(primask);
-
- if (NULL != buffer)
- {
- if (NULL != serialReadHandle->callback)
- {
- serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled);
- }
- }
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
- uint8_t *buffer,
- uint32_t length,
- uint32_t *receivedLength)
-{
- assert(receivedLength);
-
- return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);
-}
-
-serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
- serial_manager_callback_t callback,
- void *callbackParam)
-{
- serial_manager_write_handle_t *serialWriteHandle;
-
- assert(writeHandle);
-
- serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;
-
- assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);
-
- serialWriteHandle->callbackParam = callbackParam;
- serialWriteHandle->callback = callback;
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
- serial_manager_callback_t callback,
- void *callbackParam)
-{
- serial_manager_read_handle_t *serialReadHandle;
-
- assert(readHandle);
-
- serialReadHandle = (serial_manager_read_handle_t *)readHandle;
-
- assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);
-
- serialReadHandle->callbackParam = callbackParam;
- serialReadHandle->callback = callback;
-
- return kStatus_SerialManager_Success;
-}
-#endif
-
-serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)
-{
- serial_manager_handle_t *handle;
- serial_manager_status_t status = kStatus_SerialManager_Error;
-
- assert(serialHandle);
-
- handle = (serial_manager_handle_t *)serialHandle;
-
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- status = Serial_UartEnterLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- break;
-#endif
- default:
- /*MISRA rule 16.4*/
- break;
- }
- return status;
-}
-
-serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)
-{
- serial_manager_handle_t *handle;
- serial_manager_status_t status = kStatus_SerialManager_Error;
-
- assert(serialHandle);
-
- handle = (serial_manager_handle_t *)serialHandle;
-
- switch (handle->type)
- {
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- case kSerialPort_Uart:
- status = Serial_UartExitLowpower(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- case kSerialPort_UsbCdc:
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- case kSerialPort_Swo:
- break;
-#endif
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- case kSerialPort_UsbCdcVirtual:
- break;
-#endif
- default:
- /*MISRA rule 16.4*/
- break;
- }
- return status;
-}
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h
deleted file mode 100644
index 01f8f3027..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SERIAL_MANAGER_H__
-#define __SERIAL_MANAGER_H__
-
-/*!
- * @addtogroup serialmanager
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
-#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
-#else
-#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
-#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
-#endif
-#endif
-
-/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_UART
-#define SERIAL_PORT_TYPE_UART (0U)
-#endif
-
-/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_USBCDC
-#define SERIAL_PORT_TYPE_USBCDC (0U)
-#endif
-
-/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_SWO
-#define SERIAL_PORT_TYPE_SWO (0U)
-#endif
-
-/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
-#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
-#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
-#endif
-
-/*! @brief Set serial manager write handle size */
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
-#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
-#else
-#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
-#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-#include "serial_port_uart.h"
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
-
-#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#error The serial manager blocking mode cannot be supported for USB CDC.
-#endif
-
-#include "serial_port_usb.h"
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
-#include "serial_port_swo.h"
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
-
-#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#error The serial manager blocking mode cannot be supported for USB CDC.
-#endif
-
-#include "serial_port_usb_virtual.h"
-#endif
-
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-
-#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
-#endif
-
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
-
-#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
-#endif
-
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
-
-#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
-#endif
-
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
-
-#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
-#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
-#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
-#endif
-
-#endif
-
-/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
-#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
-#else
-#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
-#else
-#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
-#endif
-
-#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
-#define SERIAL_MANAGER_TASK_PRIORITY (2U)
-#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
-
-typedef void *serial_handle_t;
-typedef void *serial_write_handle_t;
-typedef void *serial_read_handle_t;
-
-/*! @brief serial port type*/
-typedef enum _serial_port_type
-{
- kSerialPort_Uart = 1U, /*!< Serial port UART */
- kSerialPort_UsbCdc, /*!< Serial port USB CDC */
- kSerialPort_Swo, /*!< Serial port SWO */
- kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
-} serial_port_type_t;
-
-/*! @brief serial manager config structure*/
-typedef struct _serial_manager_config
-{
- uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.
- Besides, the memory space cannot be free during the lifetime of the serial
- manager module. */
- uint32_t ringBufferSize; /*!< The size of the ring buffer */
- serial_port_type_t type; /*!< Serial port type */
- void *portConfig; /*!< Serial port configuration */
-} serial_manager_config_t;
-
-/*! @brief serial manager error code*/
-typedef enum _serial_manager_status
-{
- kStatus_SerialManager_Success = kStatus_Success, /*!< Success */
- kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
- kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
- kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
- kStatus_SerialManager_Canceled =
- MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
- kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
- kStatus_SerialManager_RingBufferOverflow =
- MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
-} serial_manager_status_t;
-
-/*! @brief Callback message structure */
-typedef struct _serial_manager_callback_message
-{
- uint8_t *buffer; /*!< Transferred buffer */
- uint32_t length; /*!< Transferred data length */
-} serial_manager_callback_message_t;
-
-/*! @brief callback function */
-typedef void (*serial_manager_callback_t)(void *callbackParam,
- serial_manager_callback_message_t *message,
- serial_manager_status_t status);
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
- *
- * This function configures the Serial Manager module with user-defined settings. The user can configure the
- * configuration
- * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
- * allocated by the caller.
- * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
- * CDC.
- * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
- * #serial_manager_config_t.
- *
- * Example below shows how to use this API to configure the Serial Manager.
- * For UART,
- * @code
- * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
- * static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
- * static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];
- * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
- *
- * serial_manager_config_t config;
- * serial_port_uart_config_t uartConfig;
- * config.type = kSerialPort_Uart;
- * config.ringBuffer = &s_ringBuffer[0];
- * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
- * uartConfig.instance = 0;
- * uartConfig.clockRate = 24000000;
- * uartConfig.baudRate = 115200;
- * uartConfig.parityMode = kSerialManager_UartParityDisabled;
- * uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
- * uartConfig.enableRx = 1;
- * uartConfig.enableTx = 1;
- * config.portConfig = &uartConfig;
- * SerialManager_Init(s_serialHandle, &config);
- * @endcode
- * For USB CDC,
- * @code
- * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)
- * static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
- * static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];
- * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
- *
- * serial_manager_config_t config;
- * serial_port_usb_cdc_config_t usbCdcConfig;
- * config.type = kSerialPort_UsbCdc;
- * config.ringBuffer = &s_ringBuffer[0];
- * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
- * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
- * config.portConfig = &usbCdcConfig;
- * SerialManager_Init(s_serialHandle, &config);
- * @endcode
- *
- * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
- * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
- * @param config Pointer to user-defined configuration structure.
- * @retval kStatus_SerialManager_Error An error occurred.
- * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
- */
-serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
-
-/*!
- * @brief De-initializes the serial manager module instance.
- *
- * This function de-initializes the serial manager module instance. If the opened writing or
- * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
- * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
- */
-serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
-
-/*!
- * @brief Opens a writing handle for the serial manager module.
- *
- * This function Opens a writing handle for the serial manager module. If the serial manager needs to
- * be used in different tasks, the task should open a dedicated write handle for itself by calling
- * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
- * handle at the same time, multiple writing handles need to be opened when the multiple transmission
- * is needed for a task.
- *
- * @param serialHandle The serial manager module handle pointer.
- * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
- * @param writeHandle The serial manager module writing handle pointer.
- * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
- * @retval kStatus_SerialManager_Error An error occurred.
- * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
- * @retval kStatus_SerialManager_Success The writing handle is opened.
- *
- * Example below shows how to use this API to write data.
- * For task 1,
- * @code
- * static uint32_t s_serialWriteHandleBuffer1[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /
- * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle1 =
- * (serial_write_handle_t)&s_serialWriteHandleBuffer1[0]; static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking
- * writing log for task1!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
- * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
- * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
- * @endcode
- * For task 2,
- * @code
- * static uint32_t s_serialWriteHandleBuffer2[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /
- * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle2 =
- * (serial_write_handle_t)&s_serialWriteHandleBuffer2[0]; static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking
- * writing log for task2!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
- * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
- * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
- * @endcode
- */
-serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
-
-/*!
- * @brief Closes a writing handle for the serial manager module.
- *
- * This function Closes a writing handle for the serial manager module.
- *
- * @param writeHandle The serial manager module writing handle pointer.
- * @retval kStatus_SerialManager_Success The writing handle is closed.
- */
-serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
-
-/*!
- * @brief Opens a reading handle for the serial manager module.
- *
- * This function Opens a reading handle for the serial manager module. The reading handle can not be
- * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
- * the previous reading handle is not closed. And There can only be one buffer for receiving for the
- * reading handle at the same time.
- *
- * @param serialHandle The serial manager module handle pointer.
- * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
- * @param readHandle The serial manager module reading handle pointer.
- * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
- * @retval kStatus_SerialManager_Error An error occurred.
- * @retval kStatus_SerialManager_Success The reading handle is opened.
- * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
- *
- * Example below shows how to use this API to read data.
- * @code
- * static uint32_t s_serialReadHandleBuffer[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1) /
- * sizeof(uitn32_t))]; static serial_read_handle_t s_serialReadHandle =
- * (serial_read_handle_t)&s_serialReadHandleBuffer[0]; SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
- * static uint8_t s_nonBlockingBuffer[64];
- * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
- * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
- * @endcode
- */
-serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
-
-/*!
- * @brief Closes a reading for the serial manager module.
- *
- * This function Closes a reading for the serial manager module.
- *
- * @param readHandle The serial manager module reading handle pointer.
- * @retval kStatus_SerialManager_Success The reading handle is closed.
- */
-serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
-
-/*!
- * @brief Transmits data with the blocking mode.
- *
- * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
- * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for transmission for the writing handle at the same time.
- *
- * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
- * cannot be used at the same time.
- * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to write.
- * @param length Length of the data to write.
- * @retval kStatus_SerialManager_Success Successfully sent all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
- uint8_t *buffer,
- uint32_t length);
-
-/*!
- * @brief Reads data with the blocking mode.
- *
- * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
- * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for receiving for the reading handle at the same time.
- *
- * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
- * cannot be used at the same time.
- * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to store the received data.
- * @param length The length of the data to be received.
- * @retval kStatus_SerialManager_Success Successfully received all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-/*!
- * @brief Transmits data with the non-blocking mode.
- *
- * This is a non-blocking function, which returns directly without waiting for all data to be sent.
- * When all data is sent, the module notifies the upper layer through a TX callback function and passes
- * the status parameter @ref kStatus_SerialManager_Success.
- * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for transmission for the writing handle at the same time.
- *
- * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
- * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to write.
- * @param length Length of the data to write.
- * @retval kStatus_SerialManager_Success Successfully sent all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
- uint8_t *buffer,
- uint32_t length);
-
-/*!
- * @brief Reads data with the non-blocking mode.
- *
- * This is a non-blocking function, which returns directly without waiting for all data to be received.
- * When all data is received, the module driver notifies the upper layer
- * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
- * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
- * And There can only one buffer for receiving for the reading handle at the same time.
- *
- * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
- * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to store the received data.
- * @param length The length of the data to be received.
- * @retval kStatus_SerialManager_Success Successfully received all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
- uint8_t *buffer,
- uint32_t length);
-
-/*!
- * @brief Tries to read data.
- *
- * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
- * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
- * After the data is copied, the actual data length is passed by the parameter length.
- * And There can only one buffer for receiving for the reading handle at the same time.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param buffer Start address of the data to store the received data.
- * @param length The length of the data to be received.
- * @param receivedLength Length received from the ring buffer directly.
- * @retval kStatus_SerialManager_Success Successfully received all data.
- * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
- uint8_t *buffer,
- uint32_t length,
- uint32_t *receivedLength);
-
-/*!
- * @brief Cancels unfinished send transmission.
- *
- * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
- * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
- *
- * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
- * the function #SerialManager_WriteBlocking.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Get successfully abort the sending.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
-
-/*!
- * @brief Cancels unfinished receive transmission.
- *
- * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
- * layer
- * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
- *
- * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
- * the function #SerialManager_ReadBlocking.
- *
- * @param readHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
- * @retval kStatus_SerialManager_Error An error occurred.
- */
-serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
-
-/*!
- * @brief Installs a TX callback and callback parameter.
- *
- * This function is used to install the TX callback and callback parameter for the serial manager module.
- * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
- * function. And the status is also passed as status parameter when the callback is called.
- *
- * @param writeHandle The serial manager module handle pointer.
- * @param callback The callback function.
- * @param callbackParam The parameter of the callback function.
- * @retval kStatus_SerialManager_Success Successfully install the callback.
- */
-serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-
-/*!
- * @brief Installs a RX callback and callback parameter.
- *
- * This function is used to install the RX callback and callback parameter for the serial manager module.
- * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
- * function. And the status is also passed as status parameter when the callback is called.
- *
- * @param readHandle The serial manager module handle pointer.
- * @param callback The callback function.
- * @param callbackParam The parameter of the callback function.
- * @retval kStatus_SerialManager_Success Successfully install the callback.
- */
-serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-
-#endif
-
-/*!
- * @brief Prepares to enter low power consumption.
- *
- * This function is used to prepare to enter low power consumption.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Successful operation.
- */
-serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
-
-/*!
- * @brief Restores from low power consumption.
- *
- * This function is used to restore from low power consumption.
- *
- * @param serialHandle The serial manager module handle pointer.
- * @retval kStatus_SerialManager_Success Successful operation.
- */
-serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
-
-#if defined(__cplusplus)
-}
-#endif
-/*! @} */
-#endif /* __SERIAL_MANAGER_H__ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h
deleted file mode 100644
index a1a933906..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright 2019 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SERIAL_PORT_INTERNAL_H__
-#define __SERIAL_PORT_INTERNAL_H__
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
-serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-void Serial_UartIsrFunction(serial_handle_t serialHandle);
-#endif
-serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
-serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
-serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
-serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
-serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
-serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-#endif
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
-serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-void Serial_SwoIsrFunction(serial_handle_t serialHandle);
-#endif
-#endif
-
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
-serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
-serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
-serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
-serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam);
-void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
-#endif
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __SERIAL_PORT_INTERNAL_H__ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c
deleted file mode 100644
index 9aca4d03d..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_common.h"
-#include "serial_manager.h"
-#include "serial_port_internal.h"
-
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-#include "uart.h"
-
-#include "serial_port_uart.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#ifndef NDEBUG
-#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
-#undef assert
-#define assert(n)
-#endif
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
-
-typedef struct _serial_uart_send_state
-{
- serial_manager_callback_t callback;
- void *callbackParam;
- uint8_t *buffer;
- uint32_t length;
- volatile uint8_t busy;
-} serial_uart_send_state_t;
-
-typedef struct _serial_uart_recv_state
-{
- serial_manager_callback_t callback;
- void *callbackParam;
- volatile uint8_t busy;
- uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
-} serial_uart_recv_state_t;
-#endif
-
-typedef struct _serial_uart_state
-{
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- serial_uart_send_state_t tx;
- serial_uart_recv_state_t rx;
-#endif
- uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];
-} serial_uart_state_t;
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-/* UART user callback */
-static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
-{
- serial_uart_state_t *serialUartHandle;
- serial_manager_callback_message_t msg;
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- hal_uart_transfer_t transfer;
-#endif
-
- if (NULL == userData)
- {
- return;
- }
-
- serialUartHandle = (serial_uart_state_t *)userData;
-
- if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
- {
- if ((NULL != serialUartHandle->rx.callback))
- {
- msg.buffer = &serialUartHandle->rx.readBuffer[0];
- msg.length = sizeof(serialUartHandle->rx.readBuffer);
- serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);
- }
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- transfer.data = &serialUartHandle->rx.readBuffer[0];
- transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
- if (kStatus_HAL_UartSuccess ==
- HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
-#else
- if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==
- HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
- &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
-#endif
- {
- serialUartHandle->rx.busy = 1U;
- }
- else
- {
- serialUartHandle->rx.busy = 0U;
- }
- }
- else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
- {
- if (0U != serialUartHandle->tx.busy)
- {
- serialUartHandle->tx.busy = 0U;
- if ((NULL != serialUartHandle->tx.callback))
- {
- msg.buffer = serialUartHandle->tx.buffer;
- msg.length = serialUartHandle->tx.length;
- serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);
- }
- }
- }
- else
- {
- }
-}
-#endif
-
-serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
-{
- serial_uart_state_t *serialUartHandle;
- serial_port_uart_config_t *uartConfig;
- hal_uart_config_t config;
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- hal_uart_transfer_t transfer;
-#endif
-#endif
-
- assert(serialConfig);
- assert(serialHandle);
- assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
-
- uartConfig = (serial_port_uart_config_t *)serialConfig;
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- config.baudRate_Bps = uartConfig->baudRate;
- config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;
- config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;
- config.enableRx = uartConfig->enableRx;
- config.enableTx = uartConfig->enableTx;
- config.srcClock_Hz = uartConfig->clockRate;
- config.instance = uartConfig->instance;
-
- if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))
- {
- return kStatus_SerialManager_Error;
- }
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- if (kStatus_HAL_UartSuccess !=
- HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
- Serial_UartCallback, serialUartHandle))
-#else
- if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
- Serial_UartCallback, serialUartHandle))
-#endif
- {
- return kStatus_SerialManager_Error;
- }
-
- if (0U != uartConfig->enableRx)
- {
- serialUartHandle->rx.busy = 1U;
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- transfer.data = &serialUartHandle->rx.readBuffer[0];
- transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
- if (kStatus_HAL_UartSuccess !=
- HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
-#else
- if (kStatus_HAL_UartSuccess !=
- HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
- &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
-#endif
- {
- serialUartHandle->rx.busy = 0U;
- return kStatus_SerialManager_Error;
- }
- }
-#endif
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
-#else
- (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
-#endif
-#endif
- (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- serialUartHandle->tx.busy = 0U;
- serialUartHandle->rx.busy = 0U;
-#endif
-
- return kStatus_SerialManager_Success;
-}
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-
-serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
-{
- serial_uart_state_t *serialUartHandle;
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- hal_uart_transfer_t transfer;
-#endif
-
- assert(serialHandle);
- assert(buffer);
- assert(length);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- if (0U != serialUartHandle->tx.busy)
- {
- return kStatus_SerialManager_Busy;
- }
- serialUartHandle->tx.busy = 1U;
-
- serialUartHandle->tx.buffer = buffer;
- serialUartHandle->tx.length = length;
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- transfer.data = buffer;
- transfer.dataSize = length;
- if (kStatus_HAL_UartSuccess !=
- HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
-#else
- if (kStatus_HAL_UartSuccess !=
- HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))
-#endif
- {
- serialUartHandle->tx.busy = 0U;
- return kStatus_SerialManager_Error;
- }
- return kStatus_SerialManager_Success;
-}
-
-#else
-
-serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
- assert(buffer);
- assert(length);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
- buffer, length);
-}
-
-serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
- assert(buffer);
- assert(length);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- return (serial_manager_status_t)HAL_UartReceiveBlocking(
- ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
-}
-
-#endif
-
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
-{
- serial_uart_state_t *serialUartHandle;
- serial_manager_callback_message_t msg;
- uint32_t primask;
- uint8_t isBusy = 0U;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- primask = DisableGlobalIRQ();
- isBusy = serialUartHandle->tx.busy;
- serialUartHandle->tx.busy = 0U;
- EnableGlobalIRQ(primask);
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
-#else
- (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
-#endif
- if (0U != isBusy)
- {
- if ((NULL != serialUartHandle->tx.callback))
- {
- msg.buffer = serialUartHandle->tx.buffer;
- msg.length = serialUartHandle->tx.length;
- serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);
- }
- }
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- serialUartHandle->tx.callback = callback;
- serialUartHandle->tx.callbackParam = callbackParam;
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
- serial_manager_callback_t callback,
- void *callbackParam)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- serialUartHandle->rx.callback = callback;
- serialUartHandle->rx.callbackParam = callbackParam;
-
- return kStatus_SerialManager_Success;
-}
-
-void Serial_UartIsrFunction(serial_handle_t serialHandle)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
-}
-#endif
-
-serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- if (kStatus_HAL_UartSuccess != HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))
- {
- return kStatus_SerialManager_Error;
- }
-
- return kStatus_SerialManager_Success;
-}
-
-serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)
-{
- serial_uart_state_t *serialUartHandle;
-
- assert(serialHandle);
-
- serialUartHandle = (serial_uart_state_t *)serialHandle;
-
- if (kStatus_HAL_UartSuccess != HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))
- {
- return kStatus_SerialManager_Error;
- }
-
- return kStatus_SerialManager_Success;
-}
-
-#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h
deleted file mode 100644
index c099aec40..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SERIAL_PORT_UART_H__
-#define __SERIAL_PORT_UART_H__
-
-#include "uart.h"
-
-/*!
- * @addtogroup serial_port_uart
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief serial port uart handle size*/
-#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
-#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE)
-#else
-#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
-#endif
-
-/*! @brief serial port uart parity mode*/
-typedef enum _serial_port_uart_parity_mode
-{
- kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
- kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */
- kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */
-} serial_port_uart_parity_mode_t;
-
-/*! @brief serial port uart stop bit count*/
-typedef enum _serial_port_uart_stop_bit_count
-{
- kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
- kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
-} serial_port_uart_stop_bit_count_t;
-
-/*! @brief serial port uart config struct*/
-typedef struct _serial_port_uart_config
-{
- uint32_t clockRate; /*!< clock rate */
- uint32_t baudRate; /*!< baud rate */
- serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
- serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
- uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
- please refer to the SOC corresponding RM. */
- uint8_t enableRx; /*!< Enable RX */
- uint8_t enableTx; /*!< Enable TX */
-} serial_port_uart_config_t;
-/*! @} */
-#endif /* __SERIAL_PORT_UART_H__ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h
new file mode 100644
index 000000000..7d8bc4441
--- /dev/null
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_uart.h
@@ -0,0 +1,812 @@
+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#include "fsl_common.h"
+#if defined(SDK_OS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (25U)
+#endif
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#endif
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#ifndef HAL_UART_ISR_PRIORITY
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+#endif
+
+#ifndef HAL_UART_ADAPTER_LOWPOWER
+#define HAL_UART_ADAPTER_LOWPOWER (0U)
+#endif /* HAL_UART_ADAPTER_LOWPOWER */
+
+#ifndef HAL_UART_ADAPTER_FIFO
+#define HAL_UART_ADAPTER_FIFO (0U)
+#endif /* HAL_UART_ADAPTER_FIFO */
+
+#ifndef HAL_UART_DMA_ENABLE
+#define HAL_UART_DMA_ENABLE (0U)
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */
+#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT
+#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U)
+#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */
+
+/*! @brief Definition of uart adapter handle size. */
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#else
+#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4)
+#endif
+
+/*! @brief Definition of uart dma adapter handle size. */
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U))
+#define HAL_UART_DMA_HANDLE_SIZE (124U)
+#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U))
+#define HAL_UART_DMA_HANDLE_SIZE (140U)
+#else
+#error This SOC does not have DMA or EDMA available!
+#endif
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*!
+ * @brief Defines the uart handle
+ *
+ * This macro is used to define a 4 byte aligned uart handle.
+ * Then use "(hal_uart_handle_t)name" to get the uart handle.
+ *
+ * The macro should be global and could be optional. You could also define uart handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * UART_HANDLE_DEFINE(uartHandle);
+ * @endcode
+ *
+ * @param name The name string of the uart handle.
+ */
+#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#define UART_DMA_HANDLE_DEFINE(name) \
+ uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#ifndef HAL_UART_TRANSFER_MODE
+#define HAL_UART_TRANSFER_MODE (0U)
+#endif
+
+/*! @brief The handle of uart adapter. */
+typedef void *hal_uart_handle_t;
+
+/*! @brief The handle of uart dma adapter. */
+typedef void *hal_uart_dma_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+ kStatus_HAL_UartBaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(
+ kStatusGroup_HAL_UART,
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.
+ For transactional transfer, The up layer needs to abort the transfer and then starts again */
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+ kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */
+ kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief UART Block Mode. */
+typedef enum _hal_uart_block_mode
+{
+ kHAL_UartNonBlockMode = 0x0U, /*!< Uart NonBlock Mode */
+ kHAL_UartBlockMode = 0x1U, /*!< Uart Block Mode */
+} hal_uart_block_mode_t;
+#endif /* UART_ADAPTER_NON_BLOCKING_MODE */
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+ uint32_t srcClock_Hz; /*!< Source clock */
+ uint32_t baudRate_Bps; /*!< Baud rate */
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
+ uint8_t enableRx; /*!< Enable RX */
+ uint8_t enableTx; /*!< Enable TX */
+ uint8_t enableRxRTS; /*!< Enable RX RTS */
+ uint8_t enableTxCTS; /*!< Enable TX CTS */
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+ SOC corresponding RM.
+ Invalid instance value will cause initialization failure. */
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_block_mode_t mode; /*!< Uart block mode */
+#endif /* UART_ADAPTER_NON_BLOCKING_MODE */
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+ uint8_t txFifoWatermark;
+ uint8_t rxFifoWatermark;
+#endif
+} hal_uart_config_t;
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+/*! @brief UART DMA status */
+typedef enum _hal_uart_dma_status
+{
+ kStatus_HAL_UartDmaSuccess = 0U,
+ kStatus_HAL_UartDmaRxIdle = (1U << 1U),
+ kStatus_HAL_UartDmaRxBusy = (1U << 2U),
+ kStatus_HAL_UartDmaTxIdle = (1U << 3U),
+ kStatus_HAL_UartDmaTxBusy = (1U << 4U),
+ kStatus_HAL_UartDmaIdleline = (1U << 5U),
+ kStatus_HAL_UartDmaError = (1U << 6U),
+} hal_uart_dma_status_t;
+
+typedef struct _hal_uart_dma_config_t
+{
+ uint8_t uart_instance;
+ uint8_t dma_instance;
+ uint8_t rx_channel;
+ uint8_t tx_channel;
+#if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT
+ uint8_t dma_mux_instance;
+ dma_request_source_t rx_request;
+ dma_request_source_t tx_request;
+#endif
+#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
+ uint32_t dma_rx_channel_mux;
+ uint32_t dma_tx_channel_mux;
+#endif
+} hal_uart_dma_config_t;
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+typedef struct _dma_callback_msg
+{
+ hal_uart_dma_status_t status;
+ uint8_t *data;
+ uint32_t dataSize;
+} hal_dma_callback_msg_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle,
+ hal_dma_callback_msg_t *msg,
+ void *callbackParam);
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ * UART_HANDLE_DEFINE(g_UartHandle);
+ * hal_uart_config_t config;
+ * config.srcClock_Hz = 48000000;
+ * config.baudRate_Bps = 115200U;
+ * config.parityMode = kHAL_UartParityDisabled;
+ * config.stopBitCount = kHAL_UartOneStopBit;
+ * config.enableRx = 1;
+ * config.enableTx = 1;
+ * config.enableRxRTS = 0;
+ * config.enableTxCTS = 0;
+ * config.instance = 0;
+ * HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config);
+ * @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #UART_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+
+/*!
+ * @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure.
+ *
+ * This function configures the UART dma module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated
+ * by the caller. Example below shows how to use this API to configure the UART.
+ * @code
+ *
+ * Init TimerManager, only used in UART without Idleline interrupt
+ * timer_config_t timerConfig;
+ * timerConfig.srcClock_Hz = 16000000;
+ * timerConfig.instance = 0;
+ * TM_Init(&timerConfig);
+ *
+ * Init the DMA module
+ * DMA_Init(DMA0);
+ *
+ * Define a uart dma handle
+ * UART_HANDLE_DEFINE(g_uartHandle);
+ * UART_DMA_HANDLE_DEFINE(g_UartDmaHandle);
+ *
+ * Configure uart settings
+ * hal_uart_config_t uartConfig;
+ * uartConfig.srcClock_Hz = 48000000;
+ * uartConfig.baudRate_Bps = 115200;
+ * uartConfig.parityMode = kHAL_UartParityDisabled;
+ * uartConfig.stopBitCount = kHAL_UartOneStopBit;
+ * uartConfig.enableRx = 1;
+ * uartConfig.enableTx = 1;
+ * uartConfig.enableRxRTS = 0;
+ * uartConfig.enableTxCTS = 0;
+ * uartConfig.instance = 0;
+ *
+ * Init uart
+ * HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig);
+ *
+ * Configure uart dma settings
+ * hal_uart_dma_config_t dmaConfig;
+ * dmaConfig.uart_instance = 0;
+ * dmaConfig.dma_instance = 0;
+ * dmaConfig.rx_channel = 0;
+ * dmaConfig.tx_channel = 1;
+ *
+ * Init uart dma
+ * HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig);
+ * @endcode
+ *
+ * @param handle UART handle pointer.
+ * @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #UART_DMA_HANDLE_DEFINE(handle);
+ * or
+ * uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param dmaConfig Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartDmaError UART dma initialization failed.
+ * @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed.
+ */
+hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
+ hal_uart_dma_handle_t dmaHandle,
+ hal_uart_dma_config_t *dmaConfig);
+
+/*!
+ * @brief Deinitializes a UART DMA instance.
+ *
+ * This function will abort uart dma receive/send transfer and deinitialize UART.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed
+ */
+hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle);
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART DMA module.
+ * When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully install the callback.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_dma_transfer_callback_t callback,
+ void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an dma method.
+ *
+ * This function receives data using an dma method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART DMA driver.
+ * When all data is received, the UART DMA adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle.
+ *
+ * When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function,
+ * and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline
+ * interrupt(like usart), it will use a software idleline detection method with the help of TimerManager.
+ *
+ * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
+ *
+ * @param handle UART handle pointer.
+ * @param data data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @param receiveAll Idleline interrupt will not end transfer process if set true.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive.
+ * @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
+ uint8_t *data,
+ size_t length,
+ bool receiveAll);
+
+/*!
+ * @brief Transmits a buffer of data using an dma method.
+ *
+ * This function sends data using an dma method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register by DMA, the UART DMA driver calls the callback
+ * function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter.
+ *
+ * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API.
+ *
+ * @param handle UART handle pointer.
+ * @param data data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished.
+ */
+hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param reCount Receive bytes count.
+ * @retval kStatus_HAL_UartDmaError An error occurred.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount.
+ */
+hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the DMA method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartDmaError An error occurred.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount.
+ */
+hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the DMA-driven data receiving.
+ *
+ * This function aborts the DMA-driven data receiving.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving.
+ */
+hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the DMA-driven data sending.
+ *
+ * This function aborts the DMA-driven data sending.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle);
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_usart.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_usart.c
new file mode 100644
index 000000000..4261752b8
--- /dev/null
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/fsl_adapter_usart.c
@@ -0,0 +1,1086 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "fsl_adapter_uart.h"
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+#include "fsl_component_timer_manager.h"
+#include "fsl_usart_dma.h"
+#endif /* HAL_UART_DMA_ENABLE */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_dma_receive_state
+{
+ uint8_t *volatile buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+ volatile uint32_t timeout;
+ volatile bool receiveAll;
+} hal_uart_dma_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_dma_send_state
+{
+ uint8_t *volatile buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+ volatile uint32_t timeout;
+} hal_uart_dma_send_state_t;
+
+typedef struct _hal_uart_dma_state
+{
+ struct _hal_uart_dma_state *next;
+ uint8_t instance; /* USART instance */
+ hal_uart_dma_transfer_callback_t dma_callback;
+ void *dma_callback_param;
+ usart_dma_handle_t dmaHandle;
+ dma_handle_t txDmaHandle;
+ dma_handle_t rxDmaHandle;
+ hal_uart_dma_receive_state_t dma_rx;
+ hal_uart_dma_send_state_t dma_tx;
+} hal_uart_dma_state_t;
+
+typedef struct _uart_dma_list
+{
+ TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle);
+ hal_uart_dma_state_t *dma_list;
+ volatile int8_t activeCount;
+} hal_uart_dma_list_t;
+
+static hal_uart_dma_list_t s_dmaHandleList;
+#endif /* HAL_UART_DMA_ENABLE */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_transfer_callback_t callback;
+ void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ usart_handle_t hardwareHandle;
+#endif
+ hal_uart_receive_state_t rx;
+ hal_uart_send_state_t tx;
+#endif
+ uint8_t instance;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+ hal_uart_dma_state_t *dmaHandle;
+#endif /* HAL_UART_DMA_ENABLE */
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \
+ (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+ switch (status)
+ {
+ case kStatus_Success:
+ uartStatus = kStatus_HAL_UartSuccess;
+ break;
+ case kStatus_USART_TxBusy:
+ uartStatus = kStatus_HAL_UartTxBusy;
+ break;
+ case kStatus_USART_RxBusy:
+ uartStatus = kStatus_HAL_UartRxBusy;
+ break;
+ case kStatus_USART_TxIdle:
+ uartStatus = kStatus_HAL_UartTxIdle;
+ break;
+ case kStatus_USART_RxIdle:
+ uartStatus = kStatus_HAL_UartRxIdle;
+ break;
+ case kStatus_USART_BaudrateNotSupport:
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+ break;
+ case kStatus_USART_NoiseError:
+ case kStatus_USART_FramingError:
+ case kStatus_USART_ParityError:
+ uartStatus = kStatus_HAL_UartProtocolError;
+ break;
+ default:
+ /* This comments for MISRA C-2012 Rule 16.4 */
+ break;
+ }
+ return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ if (kStatus_Success == status)
+ {
+ return kStatus_HAL_UartSuccess;
+ }
+ else
+ {
+ return kStatus_HAL_UartError;
+ }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ assert(callbackParam);
+
+ uartHandle = (hal_uart_state_t *)callbackParam;
+
+ if (kStatus_HAL_UartProtocolError == uartStatus)
+ {
+ if (0U != uartHandle->hardwareHandle.rxDataSize)
+ {
+ uartStatus = kStatus_HAL_UartError;
+ }
+ }
+
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+ }
+}
+
+#else
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+ uint32_t status;
+ uint8_t instance;
+
+ if (NULL == uartHandle)
+ {
+ return;
+ }
+ instance = uartHandle->instance;
+
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+ /* Receive data register full */
+ if ((0U != (USART_FIFOSTAT_RXNOTEMPTY_MASK & status)) &&
+ (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK)))
+ {
+ if (NULL != uartHandle->rx.buffer)
+ {
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((0U != (USART_FIFOSTAT_TXNOTFULL_MASK & status)) &&
+ (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK)))
+ {
+ if (NULL != uartHandle->tx.buffer)
+ {
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+#if 1
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+
+static void HAL_UartInterruptHandle_Wapper(void *base, void *handle)
+{
+ HAL_UartInterruptHandle((USART_Type *)base, handle);
+}
+#endif
+
+#endif
+
+static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *config)
+{
+ usart_config_t usartConfig;
+ status_t status;
+
+ assert(handle);
+ assert(config);
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+ assert(s_UsartAdapterBase[config->instance]);
+ assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t));
+
+ USART_GetDefaultConfig(&usartConfig);
+ usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+ if ((0U != config->enableRxRTS) || (0U != config->enableTxCTS))
+ {
+ usartConfig.enableHardwareFlowControl = true;
+ }
+
+ if (kHAL_UartParityEven == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityEven;
+ }
+ else if (kHAL_UartParityOdd == config->parityMode)
+ {
+ usartConfig.parityMode = kUSART_ParityOdd;
+ }
+ else
+ {
+ usartConfig.parityMode = kUSART_ParityDisabled;
+ }
+
+ if (kHAL_UartTwoStopBit == config->stopBitCount)
+ {
+ usartConfig.stopBitCount = kUSART_TwoStopBit;
+ }
+ else
+ {
+ usartConfig.stopBitCount = kUSART_OneStopBit;
+ }
+ usartConfig.enableRx = (bool)config->enableRx;
+ usartConfig.enableTx = (bool)config->enableTx;
+ usartConfig.txWatermark = kUSART_TxFifo0;
+ usartConfig.rxWatermark = kUSART_RxFifo1;
+
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+ if (kStatus_Success != status)
+ {
+ return HAL_UartGetStatus(status);
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t status;
+
+ /* Init serial port */
+ status = HAL_UartInitCommon(handle, config);
+ if (kStatus_HAL_UartSuccess != status)
+ {
+ return status;
+ }
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartHandle->instance = config->instance;
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+ uartHandle->dmaHandle = NULL;
+#endif /* HAL_UART_DMA_ENABLE */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+ /* Enable interrupt in NVIC. */
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], HAL_UartInterruptHandle_Wapper, handle);
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+ (void)EnableIRQ(s_UsartIRQ[config->instance]);
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (NULL != uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+#endif
+
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (NULL != uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+#endif
+
+ (void)USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer, NULL);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (usart_transfer_t *)transfer);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status =
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+
+ uartHandle->rx.bufferLength = length;
+ uartHandle->rx.bufferSofar = 0;
+ uartHandle->rx.buffer = data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+ uartHandle->tx.bufferLength = length;
+ uartHandle->tx.bufferSofar = 0;
+ uartHandle->tx.buffer = (volatile uint8_t *)data;
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(reCount);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ *reCount = uartHandle->rx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(seCount);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ *seCount = uartHandle->tx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+ uartHandle->rx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+ uartHandle->tx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U != HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(0U == HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif
+
+#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))
+static void USART_DMACallbacks(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData)
+{
+ hal_uart_dma_state_t *uartDmaHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ hal_dma_callback_msg_t msg;
+ assert(handle);
+
+ uartDmaHandle = (hal_uart_dma_state_t *)userData;
+
+ if (NULL != uartDmaHandle->dma_callback)
+ {
+ if (kStatus_HAL_UartTxIdle == uartStatus)
+ {
+ msg.status = kStatus_HAL_UartDmaTxIdle;
+ msg.data = uartDmaHandle->dma_tx.buffer;
+ msg.dataSize = uartDmaHandle->dma_tx.bufferLength;
+ uartDmaHandle->dma_tx.buffer = NULL;
+ }
+ else if (kStatus_HAL_UartRxIdle == uartStatus)
+ {
+ msg.status = kStatus_HAL_UartDmaRxIdle;
+ msg.data = uartDmaHandle->dma_rx.buffer;
+ msg.dataSize = uartDmaHandle->dma_rx.bufferLength;
+ uartDmaHandle->dma_rx.buffer = NULL;
+ }
+
+ uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param);
+ }
+}
+
+static void TimeoutTimer_Callbcak(void *param)
+{
+ hal_uart_dma_list_t *uartDmaHandleList;
+ hal_uart_dma_state_t *uartDmaHandle;
+ hal_dma_callback_msg_t msg;
+ uint32_t newReceived = 0U;
+
+ uartDmaHandleList = &s_dmaHandleList;
+ uartDmaHandle = uartDmaHandleList->dma_list;
+
+ while (NULL != uartDmaHandle)
+ {
+ if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll))
+ {
+ /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */
+ USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle,
+ &msg.dataSize);
+ newReceived = msg.dataSize - uartDmaHandle->dma_rx.bufferSofar;
+ uartDmaHandle->dma_rx.bufferSofar = msg.dataSize;
+
+ /* 1, If it is in idle state. */
+ if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
+ {
+ uartDmaHandle->dma_rx.timeout++;
+ if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT)
+ {
+ /* HAL_UartDMAAbortReceive(uartDmaHandle); */
+ USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance],
+ &uartDmaHandle->dmaHandle);
+ msg.data = uartDmaHandle->dma_rx.buffer;
+ msg.status = kStatus_HAL_UartDmaIdleline;
+ uartDmaHandle->dma_rx.buffer = NULL;
+ uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param);
+ }
+ }
+ /* 2, If got new data again. */
+ if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar))
+ {
+ uartDmaHandle->dma_rx.timeout = 0U;
+ }
+ }
+
+ uartDmaHandle = uartDmaHandle->next;
+ }
+}
+
+hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle,
+ hal_uart_dma_handle_t dmaHandle,
+ hal_uart_dma_config_t *dmaConfig)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+ assert(dmaHandle);
+
+ /* DMA init process. */
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle;
+
+ uartHandle->dmaHandle = uartDmaHandle;
+
+ uartDmaHandle->instance = dmaConfig->uart_instance;
+
+ DMA_Type *dmaBases[] = DMA_BASE_PTRS;
+ DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
+ DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
+
+ DMA_CreateHandle(&uartDmaHandle->txDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel);
+ DMA_CreateHandle(&uartDmaHandle->rxDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel);
+
+ /* Timeout timer init. */
+ if (0U == s_dmaHandleList.activeCount)
+ {
+ s_dmaHandleList.dma_list = uartDmaHandle;
+ uartDmaHandle->next = NULL;
+ s_dmaHandleList.activeCount++;
+
+ timer_status_t timerStatus;
+ timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle);
+ assert(kStatus_TimerSuccess == timerStatus);
+
+ timerStatus =
+ TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, NULL);
+ assert(kStatus_TimerSuccess == timerStatus);
+
+ (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1);
+
+ (void)timerStatus;
+ }
+ else
+ {
+ uartDmaHandle->next = s_dmaHandleList.dma_list;
+ s_dmaHandleList.dma_list = uartDmaHandle;
+ }
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+ hal_uart_dma_state_t *prev;
+ hal_uart_dma_state_t *curr;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ uartHandle->dmaHandle = NULL;
+
+ assert(uartDmaHandle);
+
+ /* Abort rx/tx */
+ /* Here we should not abort before create transfer handle. */
+ if (NULL != uartDmaHandle->dmaHandle.txDmaHandle)
+ {
+ USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+ }
+ if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle)
+ {
+ USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+ }
+
+ /* Disable rx/tx channels */
+ /* Here we should not disable before create transfer handle. */
+ if (NULL != uartDmaHandle->dmaHandle.txDmaHandle)
+ {
+ DMA_DisableChannel(uartDmaHandle->txDmaHandle.base, uartDmaHandle->txDmaHandle.channel);
+ }
+ if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle)
+ {
+ DMA_DisableChannel(uartDmaHandle->rxDmaHandle.base, uartDmaHandle->rxDmaHandle.channel);
+ }
+
+ /* Remove handle from list */
+ prev = NULL;
+ curr = s_dmaHandleList.dma_list;
+ while (curr != NULL)
+ {
+ if (curr == uartDmaHandle)
+ {
+ /* 1, if it is the first one */
+ if (prev == NULL)
+ {
+ s_dmaHandleList.dma_list = curr->next;
+ }
+ /* 2, if it is the last one */
+ else if (curr->next == NULL)
+ {
+ prev->next = NULL;
+ }
+ /* 3, if it is in the middle */
+ else
+ {
+ prev->next = curr->next;
+ }
+ break;
+ }
+
+ prev = curr;
+ curr = curr->next;
+ }
+
+ /* Reset all handle data. */
+ (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t));
+
+ s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0;
+ if (0 == s_dmaHandleList.activeCount)
+ {
+ (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle);
+ }
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_dma_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ uartDmaHandle->dma_callback = callback;
+ uartDmaHandle->dma_callback_param = callbackParam;
+
+ USART_TransferCreateHandleDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle,
+ USART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txDmaHandle,
+ &uartDmaHandle->rxDmaHandle);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle,
+ uint8_t *data,
+ size_t length,
+ bool receiveAll)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+ usart_transfer_t xfer;
+
+ assert(handle);
+ assert(data);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ if (NULL == uartDmaHandle->dma_rx.buffer)
+ {
+ uartDmaHandle->dma_rx.buffer = data;
+ uartDmaHandle->dma_rx.bufferLength = length;
+ uartDmaHandle->dma_rx.timeout = 0U;
+ uartDmaHandle->dma_rx.receiveAll = receiveAll;
+ }
+ else
+ {
+ /* Already in reading process. */
+ return kStatus_HAL_UartDmaRxBusy;
+ }
+
+ xfer.data = data;
+ xfer.dataSize = length;
+
+ USART_TransferReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+ usart_transfer_t xfer;
+
+ assert(handle);
+ assert(data);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ if (NULL == uartDmaHandle->dma_tx.buffer)
+ {
+ uartDmaHandle->dma_tx.buffer = data;
+ uartDmaHandle->dma_tx.bufferLength = length;
+ uartDmaHandle->dma_tx.bufferSofar = 0U;
+ uartDmaHandle->dma_tx.timeout = 0U;
+ }
+ else
+ {
+ /* Already in writing process. */
+ return kStatus_HAL_UartDmaTxBusy;
+ }
+
+ xfer.data = data;
+ xfer.dataSize = length;
+
+ USART_TransferSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ if (kStatus_Success != USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance],
+ &uartDmaHandle->dmaHandle, reCount))
+ {
+ return kStatus_HAL_UartDmaError;
+ }
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ /* No get send count API */
+ return kStatus_HAL_UartDmaError;
+}
+
+hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+
+hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_dma_state_t *uartDmaHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartDmaHandle = uartHandle->dmaHandle;
+
+ assert(uartDmaHandle);
+
+ USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle);
+
+ return kStatus_HAL_UartDmaSuccess;
+}
+#endif /* HAL_UART_DMA_ENABLE */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/uart.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/uart.h
deleted file mode 100644
index a45883fb0..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/uart.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __HAL_UART_ADAPTER_H__
-#define __HAL_UART_ADAPTER_H__
-
-#if defined(FSL_RTOS_FREE_RTOS)
-#include "FreeRTOS.h"
-#endif
-
-/*!
- * @addtogroup UART_Adapter
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
-#else
-#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
-#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
-#else
-#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
-#endif
-#endif
-
-#if defined(__GIC_PRIO_BITS)
-#define HAL_UART_ISR_PRIORITY (25U)
-#else
-#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
-#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
-#else
-/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
- * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
- * priority is 3 (2^2 - 1). So, the default value is 3.
- */
-#define HAL_UART_ISR_PRIORITY (3U)
-#endif
-#endif
-
-#ifndef HAL_UART_ADAPTER_LOWPOWER
-#define HAL_UART_ADAPTER_LOWPOWER (0U)
-#endif /* HAL_UART_ADAPTER_LOWPOWER */
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-#define HAL_UART_HANDLE_SIZE (90U + HAL_UART_ADAPTER_LOWPOWER * 16U)
-#else
-#define HAL_UART_HANDLE_SIZE (4U + HAL_UART_ADAPTER_LOWPOWER * 16U)
-#endif
-
-/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
-#define HAL_UART_TRANSFER_MODE (0U)
-
-typedef void *hal_uart_handle_t;
-
-/*! @brief UART status */
-typedef enum _hal_uart_status
-{
- kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */
- kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
- kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
- kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
- kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
- kStatus_HAL_UartBaudrateNotSupport =
- MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
- kStatus_HAL_UartProtocolError = MAKE_STATUS(
- kStatusGroup_HAL_UART,
- 6), /*!< Error occurs for Noise, Framing, Parity, etc.
- For transactional transfer, The up layer needs to abort the transfer and then starts again */
- kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
-} hal_uart_status_t;
-
-/*! @brief UART parity mode. */
-typedef enum _hal_uart_parity_mode
-{
- kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
- kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */
- kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */
-} hal_uart_parity_mode_t;
-
-/*! @brief UART stop bit count. */
-typedef enum _hal_uart_stop_bit_count
-{
- kHAL_UartOneStopBit = 0U, /*!< One stop bit */
- kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
-} hal_uart_stop_bit_count_t;
-
-/*! @brief UART configuration structure. */
-typedef struct _hal_uart_config
-{
- uint32_t srcClock_Hz; /*!< Source clock */
- uint32_t baudRate_Bps; /*!< Baud rate */
- hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
- hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
- uint8_t enableRx; /*!< Enable RX */
- uint8_t enableTx; /*!< Enable TX */
- uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
- SOC corresponding RM.
- Invalid instance value will cause initialization failure. */
-} hal_uart_config_t;
-
-/*! @brief UART transfer callback function. */
-typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
-
-/*! @brief UART transfer structure. */
-typedef struct _hal_uart_transfer
-{
- uint8_t *data; /*!< The buffer of data to be transfer.*/
- size_t dataSize; /*!< The byte count to be transfer. */
-} hal_uart_transfer_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes a UART instance with the UART handle and the user configuration structure.
- *
- * This function configures the UART module with user-defined settings. The user can configure the configuration
- * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
- * the caller. Example below shows how to use this API to configure the UART.
- * @code
- * uint32_t g_UartHandleBuffer[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
- * hal_uart_handle_t g_UartHandle = (hal_uart_handle_t)&g_UartHandleBuffer[0];
- * hal_uart_config_t config;
- * config.srcClock_Hz = 48000000;
- * config.baudRate_Bps = 115200U;
- * config.parityMode = kHAL_UartParityDisabled;
- * config.stopBitCount = kHAL_UartOneStopBit;
- * config.enableRx = 1;
- * config.enableTx = 1;
- * config.instance = 0;
- * HAL_UartInit(g_UartHandle, &config);
- * @endcode
- *
- * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
- * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
- * @param config Pointer to user-defined configuration structure.
- * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
- * @retval kStatus_HAL_UartSuccess UART initialization succeed
- */
-hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);
-
-/*!
- * @brief Deinitializes a UART instance.
- *
- * This function waits for TX complete, disables TX and RX, and disables the UART clock.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
- */
-hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
-
-/*! @}*/
-
-/*!
- * @name Blocking bus Operations
- * @{
- */
-
-/*!
- * @brief Reads RX data register using a blocking method.
- *
- * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
- * have data, and reads data from the RX register.
- *
- * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
- * cannot be used at the same time.
- * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
- *
- * @param handle UART handle pointer.
- * @param data Start address of the buffer to store the received data.
- * @param length Size of the buffer.
- * @retval kStatus_HAL_UartError An error occurred while receiving data.
- * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
- * @retval kStatus_HAL_UartSuccess Successfully received all data.
- */
-hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
-
-/*!
- * @brief Writes to the TX register using a blocking method.
- *
- * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
- * to have room and writes data to the TX buffer.
- *
- * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
- * cannot be used at the same time.
- * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
- *
- * @param handle UART handle pointer.
- * @param data Start address of the data to write.
- * @param length Size of the data to write.
- * @retval kStatus_HAL_UartSuccess Successfully sent all data.
- */
-hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
-
-/*! @}*/
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
-
-/*!
- * @name Transactional
- * @note The transactional API and the functional API cannot be used at the same time. The macro
- * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
- * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
- * @{
- */
-
-/*!
- * @brief Installs a callback and callback parameter.
- *
- * This function is used to install the callback and callback parameter for UART module.
- * When any status of the UART changed, the driver will notify the upper layer by the installed callback
- * function. And the status is also passed as status parameter when the callback is called.
- *
- * @param handle UART handle pointer.
- * @param callback The callback function.
- * @param callbackParam The parameter of the callback function.
- * @retval kStatus_HAL_UartSuccess Successfully install the callback.
- */
-hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
- hal_uart_transfer_callback_t callback,
- void *callbackParam);
-
-/*!
- * @brief Receives a buffer of data using an interrupt method.
- *
- * This function receives data using an interrupt method. This is a non-blocking function, which
- * returns directly without waiting for all data to be received.
- * The receive request is saved by the UART driver.
- * When the new data arrives, the receive request is serviced first.
- * When all data is received, the UART driver notifies the upper layer
- * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
- *
- * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
- * cannot be used at the same time.
- *
- * @param handle UART handle pointer.
- * @param transfer UART transfer structure, see #hal_uart_transfer_t.
- * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
- * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
- * @retval kStatus_HAL_UartError An error occurred.
- */
-hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
-
-/*!
- * @brief Transmits a buffer of data using the interrupt method.
- *
- * This function sends data using an interrupt method. This is a non-blocking function, which
- * returns directly without waiting for all data to be written to the TX register. When
- * all data is written to the TX register in the ISR, the UART driver calls the callback
- * function and passes the @ref kStatus_UART_TxIdle as status parameter.
- *
- * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
- * cannot be used at the same time.
- *
- * @param handle UART handle pointer.
- * @param transfer UART transfer structure. See #hal_uart_transfer_t.
- * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
- * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
- * @retval kStatus_HAL_UartError An error occurred.
- */
-hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
-
-/*!
- * @brief Gets the number of bytes that have been received.
- *
- * This function gets the number of bytes that have been received.
- *
- * @param handle UART handle pointer.
- * @param count Receive bytes count.
- * @retval kStatus_HAL_UartError An error occurred.
- * @retval kStatus_Success Get successfully through the parameter \p count.
- */
-hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
-
-/*!
- * @brief Gets the number of bytes written to the UART TX register.
- *
- * This function gets the number of bytes written to the UART TX
- * register by using the interrupt method.
- *
- * @param handle UART handle pointer.
- * @param count Send bytes count.
- * @retval kStatus_HAL_UartError An error occurred.
- * @retval kStatus_Success Get successfully through the parameter \p count.
- */
-hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
-
-/*!
- * @brief Aborts the interrupt-driven data receiving.
- *
- * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
- * how many bytes are not received yet.
- *
- * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
- * the function #HAL_UartReceiveBlocking.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_Success Get successfully abort the receiving.
- */
-hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
-
-/*!
- * @brief Aborts the interrupt-driven data sending.
- *
- * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
- * how many bytes are not sent out.
- *
- * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
- * the function #HAL_UartSendBlocking.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_Success Get successfully abort the sending.
- */
-hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
-
-/*! @}*/
-
-#else
-
-/*!
- * @name Functional API with non-blocking mode.
- * @note The functional API and the transactional API cannot be used at the same time. The macro
- * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
- * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
- * @{
- */
-
-/*!
- * @brief Installs a callback and callback parameter.
- *
- * This function is used to install the callback and callback parameter for UART module.
- * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
- * function. And the status is also passed as status parameter when the callback is called.
- *
- * @param handle UART handle pointer.
- * @param callback The callback function.
- * @param callbackParam The parameter of the callback function.
- * @retval kStatus_HAL_UartSuccess Successfully install the callback.
- */
-hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
- hal_uart_transfer_callback_t callback,
- void *callbackParam);
-
-/*!
- * @brief Receives a buffer of data using an interrupt method.
- *
- * This function receives data using an interrupt method. This is a non-blocking function, which
- * returns directly without waiting for all data to be received.
- * The receive request is saved by the UART adapter.
- * When the new data arrives, the receive request is serviced first.
- * When all data is received, the UART adapter notifies the upper layer
- * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
- *
- * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
- * cannot be used at the same time.
- *
- * @param handle UART handle pointer.
- * @param data Start address of the data to write.
- * @param length Size of the data to write.
- * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
- * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
- * @retval kStatus_HAL_UartError An error occurred.
- */
-hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
-
-/*!
- * @brief Transmits a buffer of data using the interrupt method.
- *
- * This function sends data using an interrupt method. This is a non-blocking function, which
- * returns directly without waiting for all data to be written to the TX register. When
- * all data is written to the TX register in the ISR, the UART driver calls the callback
- * function and passes the @ref kStatus_UART_TxIdle as status parameter.
- *
- * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
- * cannot be used at the same time.
- *
- * @param handle UART handle pointer.
- * @param data Start address of the data to write.
- * @param length Size of the data to write.
- * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
- * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
- * @retval kStatus_HAL_UartError An error occurred.
- */
-hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
-
-/*!
- * @brief Gets the number of bytes that have been received.
- *
- * This function gets the number of bytes that have been received.
- *
- * @param handle UART handle pointer.
- * @param count Receive bytes count.
- * @retval kStatus_HAL_UartError An error occurred.
- * @retval kStatus_Success Get successfully through the parameter \p count.
- */
-hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
-
-/*!
- * @brief Gets the number of bytes written to the UART TX register.
- *
- * This function gets the number of bytes written to the UART TX
- * register by using the interrupt method.
- *
- * @param handle UART handle pointer.
- * @param count Send bytes count.
- * @retval kStatus_HAL_UartError An error occurred.
- * @retval kStatus_Success Get successfully through the parameter \p count.
- */
-hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
-
-/*!
- * @brief Aborts the interrupt-driven data receiving.
- *
- * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
- * how many bytes are not received yet.
- *
- * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
- * the function #HAL_UartReceiveBlocking.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_Success Get successfully abort the receiving.
- */
-hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
-
-/*!
- * @brief Aborts the interrupt-driven data sending.
- *
- * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
- * how many bytes are not sent out.
- *
- * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
- * the function #HAL_UartSendBlocking.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_Success Get successfully abort the sending.
- */
-hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
-
-/*! @}*/
-
-#endif
-#endif
-
-/*!
- * @brief Prepares to enter low power consumption.
- *
- * This function is used to prepare to enter low power consumption.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_HAL_UartSuccess Successful operation.
- * @retval kStatus_HAL_UartError An error occurred.
- */
-hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
-
-/*!
- * @brief Restores from low power consumption.
- *
- * This function is used to restore from low power consumption.
- *
- * @param handle UART handle pointer.
- * @retval kStatus_HAL_UartSuccess Successful operation.
- * @retval kStatus_HAL_UartError An error occurred.
- */
-hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-/*!
- * @brief UART IRQ handle function.
- *
- * This function handles the UART transmit and receive IRQ request.
- *
- * @param handle UART handle pointer.
- */
-void HAL_UartIsrFunction(hal_uart_handle_t handle);
-#endif
-
-#if defined(__cplusplus)
-}
-#endif
-/*! @}*/
-#endif /* __HAL_UART_ADAPTER_H__ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/usart_adapter.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/usart_adapter.c
deleted file mode 100644
index 1628a9e6d..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/component/uart/usart_adapter.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_common.h"
-#include "fsl_usart.h"
-#include "fsl_flexcomm.h"
-
-#include "uart.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#ifndef NDEBUG
-#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
-#undef assert
-#define assert(n)
-#endif
-#endif
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-/*! @brief uart RX state structure. */
-typedef struct _hal_uart_receive_state
-{
- volatile uint8_t *buffer;
- volatile uint32_t bufferLength;
- volatile uint32_t bufferSofar;
-} hal_uart_receive_state_t;
-
-/*! @brief uart TX state structure. */
-typedef struct _hal_uart_send_state
-{
- volatile uint8_t *buffer;
- volatile uint32_t bufferLength;
- volatile uint32_t bufferSofar;
-} hal_uart_send_state_t;
-#endif
-/*! @brief uart state structure. */
-typedef struct _hal_uart_state
-{
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
- hal_uart_transfer_callback_t callback;
- void *callbackParam;
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- usart_handle_t hardwareHandle;
-#endif
- hal_uart_receive_state_t rx;
- hal_uart_send_state_t tx;
-#endif
- uint8_t instance;
-} hal_uart_state_t;
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-
-#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
-/* Array of USART IRQ number. */
-static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
-#endif
-
-#endif
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
-static hal_uart_status_t HAL_UartGetStatus(status_t status)
-{
- hal_uart_status_t uartStatus = kStatus_HAL_UartError;
- switch (status)
- {
- case kStatus_Success:
- uartStatus = kStatus_HAL_UartSuccess;
- break;
- case kStatus_USART_TxBusy:
- uartStatus = kStatus_HAL_UartTxBusy;
- break;
- case kStatus_USART_RxBusy:
- uartStatus = kStatus_HAL_UartRxBusy;
- break;
- case kStatus_USART_TxIdle:
- uartStatus = kStatus_HAL_UartTxIdle;
- break;
- case kStatus_USART_RxIdle:
- uartStatus = kStatus_HAL_UartRxIdle;
- break;
- case kStatus_USART_BaudrateNotSupport:
- uartStatus = kStatus_HAL_UartBaudrateNotSupport;
- break;
- case kStatus_USART_NoiseError:
- case kStatus_USART_FramingError:
- case kStatus_USART_ParityError:
- uartStatus = kStatus_HAL_UartProtocolError;
- break;
- default:
- break;
- }
- return uartStatus;
-}
-#else
-static hal_uart_status_t HAL_UartGetStatus(status_t status)
-{
- if (kStatus_Success == status)
- {
- return kStatus_HAL_UartSuccess;
- }
- else
- {
- return kStatus_HAL_UartError;
- }
-}
-#endif
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
-static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
-{
- hal_uart_state_t *uartHandle;
- hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
- assert(callbackParam);
-
- uartHandle = (hal_uart_state_t *)callbackParam;
-
- if (kStatus_HAL_UartProtocolError == uartStatus)
- {
- if (uartHandle->hardwareHandle.rxDataSize)
- {
- uartStatus = kStatus_HAL_UartError;
- }
- }
-
- if (uartHandle->callback)
- {
- uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
- }
-}
-
-#else
-
-static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
-{
- hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
- uint32_t status;
- uint8_t instance;
-
- if (NULL == uartHandle)
- {
- return;
- }
- instance = uartHandle->instance;
-
- status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
-
- /* Receive data register full */
- if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&
- (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))
- {
- if (uartHandle->rx.buffer)
- {
- uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
- if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
- {
- USART_DisableInterrupts(s_UsartAdapterBase[instance],
- USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
- uartHandle->rx.buffer = NULL;
- if (uartHandle->callback)
- {
- uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
- }
- }
- }
- }
-
- /* Send data register empty and the interrupt is enabled. */
- if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&
- (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))
- {
- if (uartHandle->tx.buffer)
- {
- USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
- if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
- {
- USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
- uartHandle->tx.buffer = NULL;
- if (uartHandle->callback)
- {
- uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
- }
- }
- }
- }
-
-#if 1
- USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
-#endif
-}
-#endif
-
-#endif
-
-hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)
-{
- hal_uart_state_t *uartHandle;
- usart_config_t usartConfig;
- status_t status;
- assert(handle);
- assert(config);
- assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
- assert(s_UsartAdapterBase[config->instance]);
-
- if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))
- {
- return kStatus_HAL_UartError;
- }
-
- USART_GetDefaultConfig(&usartConfig);
- usartConfig.baudRate_Bps = config->baudRate_Bps;
-
- if (kHAL_UartParityEven == config->parityMode)
- {
- usartConfig.parityMode = kUSART_ParityEven;
- }
- else if (kHAL_UartParityOdd == config->parityMode)
- {
- usartConfig.parityMode = kUSART_ParityOdd;
- }
- else
- {
- usartConfig.parityMode = kUSART_ParityDisabled;
- }
-
- if (kHAL_UartTwoStopBit == config->stopBitCount)
- {
- usartConfig.stopBitCount = kUSART_TwoStopBit;
- }
- else
- {
- usartConfig.stopBitCount = kUSART_OneStopBit;
- }
- usartConfig.enableRx = config->enableRx;
- usartConfig.enableTx = config->enableTx;
- usartConfig.txWatermark = kUSART_TxFifo0;
- usartConfig.rxWatermark = kUSART_RxFifo1;
-
- status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
-
- if (kStatus_Success != status)
- {
- return HAL_UartGetStatus(status);
- }
-
- uartHandle = (hal_uart_state_t *)handle;
- uartHandle->instance = config->instance;
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
- USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
- (usart_transfer_callback_t)HAL_UartCallback, handle);
-#else
- /* Enable interrupt in NVIC. */
- FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,
- handle);
- NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
- EnableIRQ(s_UsartIRQ[config->instance]);
-#endif
-
-#endif
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
-
- assert(handle);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
-{
- hal_uart_state_t *uartHandle;
- status_t status;
- assert(handle);
- assert(data);
- assert(length);
-
- uartHandle = (hal_uart_state_t *)handle;
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
- if (uartHandle->rx.buffer)
- {
- return kStatus_HAL_UartRxBusy;
- }
-#endif
-
- status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
-
- return HAL_UartGetStatus(status);
-}
-
-hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(data);
- assert(length);
-
- uartHandle = (hal_uart_state_t *)handle;
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
- if (uartHandle->tx.buffer)
- {
- return kStatus_HAL_UartTxBusy;
- }
-#endif
-
- USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
-{
- assert(handle);
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
-{
- assert(handle);
-
- return kStatus_HAL_UartSuccess;
-}
-
-#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
-
-hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
- hal_uart_transfer_callback_t callback,
- void *callbackParam)
-{
- hal_uart_state_t *uartHandle;
-
- assert(handle);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- uartHandle->callbackParam = callbackParam;
- uartHandle->callback = callback;
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
-{
- hal_uart_state_t *uartHandle;
- status_t status;
- assert(handle);
- assert(transfer);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
- (usart_transfer_t *)transfer, NULL);
-
- return HAL_UartGetStatus(status);
-}
-
-hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
-{
- hal_uart_state_t *uartHandle;
- status_t status;
- assert(handle);
- assert(transfer);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
- (usart_transfer_t *)transfer);
-
- return HAL_UartGetStatus(status);
-}
-
-hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
-{
- hal_uart_state_t *uartHandle;
- status_t status;
- assert(handle);
- assert(count);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- status =
- USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
-
- return HAL_UartGetStatus(status);
-}
-
-hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
-{
- hal_uart_state_t *uartHandle;
- status_t status;
- assert(handle);
- assert(count);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
-
- return HAL_UartGetStatus(status);
-}
-
-hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
-
- return kStatus_HAL_UartSuccess;
-}
-
-#else
-
-/* None transactional API with non-blocking mode. */
-hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
- hal_uart_transfer_callback_t callback,
- void *callbackParam)
-{
- hal_uart_state_t *uartHandle;
-
- assert(handle);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- uartHandle->callbackParam = callbackParam;
- uartHandle->callback = callback;
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(data);
- assert(length);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- if (uartHandle->rx.buffer)
- {
- return kStatus_HAL_UartRxBusy;
- }
-
- uartHandle->rx.bufferLength = length;
- uartHandle->rx.bufferSofar = 0;
- uartHandle->rx.buffer = data;
- USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(data);
- assert(length);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- if (uartHandle->tx.buffer)
- {
- return kStatus_HAL_UartTxBusy;
- }
- uartHandle->tx.bufferLength = length;
- uartHandle->tx.bufferSofar = 0;
- uartHandle->tx.buffer = (volatile uint8_t *)data;
- USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(reCount);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- if (uartHandle->rx.buffer)
- {
- *reCount = uartHandle->rx.bufferSofar;
- return kStatus_HAL_UartSuccess;
- }
- return kStatus_HAL_UartError;
-}
-
-hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(seCount);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- if (uartHandle->tx.buffer)
- {
- *seCount = uartHandle->tx.bufferSofar;
- return kStatus_HAL_UartSuccess;
- }
- return kStatus_HAL_UartError;
-}
-
-hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- if (uartHandle->rx.buffer)
- {
- USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
- USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
- uartHandle->rx.buffer = NULL;
- }
-
- return kStatus_HAL_UartSuccess;
-}
-
-hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
- if (uartHandle->tx.buffer)
- {
- USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
- uartHandle->tx.buffer = NULL;
- }
-
- return kStatus_HAL_UartSuccess;
-}
-
-#endif
-
-#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
-
-void HAL_UartIsrFunction(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
-#if 0
- DisableIRQ(s_UsartIRQ[uartHandle->instance]);
-#endif
- USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
-#if 0
- NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
- EnableIRQ(s_UsartIRQ[uartHandle->instance]);
-#endif
-}
-
-#else
-
-void HAL_UartIsrFunction(hal_uart_handle_t handle)
-{
- hal_uart_state_t *uartHandle;
- assert(handle);
- assert(!HAL_UART_TRANSFER_MODE);
-
- uartHandle = (hal_uart_state_t *)handle;
-
-#if 0
- DisableIRQ(s_UsartIRQ[uartHandle->instance]);
-#endif
- HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
-#if 0
- NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
- EnableIRQ(s_UsartIRQ[uartHandle->instance]);
-#endif
-}
-
-#endif
-
-#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h
index 4c8645d38..a0ace9af3 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0.h
@@ -11,13 +11,13 @@
**
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
-** Build: b191017
+** Build: b210603
**
** Abstract:
** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0
**
** Copyright 1997-2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2019 NXP
+** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -44,7 +44,7 @@
*/
#ifndef _LPC55S69_CM33_CORE0_H_
-#define _LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */
+#define _LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
@@ -52,6 +52,7 @@
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
+
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
@@ -62,92 +63,92 @@
*/
/** Interrupt Number Definitions */
-#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */
-
-typedef enum IRQn
-{
- /* Auxiliary constants */
- NotAvail_IRQn = -128, /**< Not available device specific interrupt */
-
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
- SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
-
- /* Device specific interrupts */
- WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
- DMA0_IRQn = 1, /**< DMA0 controller */
- GINT0_IRQn = 2, /**< GPIO group 0 */
- GINT1_IRQn = 3, /**< GPIO group 1 */
- PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
- PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
- PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
- PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
- UTICK0_IRQn = 8, /**< Micro-tick Timer */
- MRT0_IRQn = 9, /**< Multi-rate timer */
- CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
- CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
- SCT0_IRQn = 12, /**< SCTimer/PWM */
- CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
- FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
- FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
- ADC0_IRQn = 22, /**< ADC0 */
- Reserved39_IRQn = 23, /**< Reserved interrupt */
- ACMP_IRQn = 24, /**< ACMP interrupts */
- Reserved41_IRQn = 25, /**< Reserved interrupt */
- Reserved42_IRQn = 26, /**< Reserved interrupt */
- USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
- USB0_IRQn = 28, /**< USB device */
- RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
- Reserved46_IRQn = 30, /**< Reserved interrupt */
- MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */
- PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
- PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
- PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
- PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
- CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
- CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
- OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
- Reserved55_IRQn = 39, /**< Reserved interrupt */
- Reserved56_IRQn = 40, /**< Reserved interrupt */
- Reserved57_IRQn = 41, /**< Reserved interrupt */
- SDIO_IRQn = 42, /**< SD/MMC */
- Reserved59_IRQn = 43, /**< Reserved interrupt */
- Reserved60_IRQn = 44, /**< Reserved interrupt */
- Reserved61_IRQn = 45, /**< Reserved interrupt */
- USB1_PHY_IRQn = 46, /**< USB1_PHY */
- USB1_IRQn = 47, /**< USB1 interrupt */
- USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
- SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */
- SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */
- SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */
- PLU_IRQn = 52, /**< PLU interrupt */
- SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */
- HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */
- CASER_IRQn = 55, /**< CASPER interrupt */
- PUF_IRQn = 56, /**< PUF interrupt */
- PQ_IRQn = 57, /**< PQ interrupt */
- DMA1_IRQn = 58, /**< DMA1 interrupt */
- FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */
+ DMA0_IRQn = 1, /**< DMA0 controller */
+ GINT0_IRQn = 2, /**< GPIO group 0 */
+ GINT1_IRQn = 3, /**< GPIO group 1 */
+ PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
+ PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
+ PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
+ PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
+ UTICK0_IRQn = 8, /**< Micro-tick Timer */
+ MRT0_IRQn = 9, /**< Multi-rate timer */
+ CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
+ CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
+ SCT0_IRQn = 12, /**< SCTimer/PWM */
+ CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
+ FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+ ADC0_IRQn = 22, /**< ADC0 */
+ Reserved39_IRQn = 23, /**< Reserved interrupt */
+ ACMP_IRQn = 24, /**< ACMP interrupts */
+ Reserved41_IRQn = 25, /**< Reserved interrupt */
+ Reserved42_IRQn = 26, /**< Reserved interrupt */
+ USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
+ USB0_IRQn = 28, /**< USB device */
+ RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
+ Reserved46_IRQn = 30, /**< Reserved interrupt */
+ MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */
+ PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
+ PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
+ PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
+ PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
+ CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
+ CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
+ OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+ Reserved55_IRQn = 39, /**< Reserved interrupt */
+ Reserved56_IRQn = 40, /**< Reserved interrupt */
+ Reserved57_IRQn = 41, /**< Reserved interrupt */
+ SDIO_IRQn = 42, /**< SD/MMC */
+ Reserved59_IRQn = 43, /**< Reserved interrupt */
+ Reserved60_IRQn = 44, /**< Reserved interrupt */
+ Reserved61_IRQn = 45, /**< Reserved interrupt */
+ USB1_PHY_IRQn = 46, /**< USB1_PHY */
+ USB1_IRQn = 47, /**< USB1 interrupt */
+ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
+ SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */
+ SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */
+ SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */
+ PLU_IRQn = 52, /**< PLU interrupt */
+ SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */
+ HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */
+ CASER_IRQn = 55, /**< CASPER interrupt */
+ PUF_IRQn = 56, /**< PUF interrupt */
+ PQ_IRQn = 57, /**< PQ interrupt */
+ DMA1_IRQn = 58, /**< DMA1 interrupt */
+ FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
+
/* ----------------------------------------------------------------------------
-- Cortex M33 Core Configuration
---------------------------------------------------------------------------- */
@@ -157,20 +158,21 @@ typedef enum IRQn
* @{
*/
-#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
-#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
-#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */
+#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */
-#include "core_cm33.h" /* Core Peripheral Access Layer */
+#include "core_cm33.h" /* Core Peripheral Access Layer */
#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
+
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
@@ -199,47 +201,49 @@ typedef enum IRQn
*/
typedef enum _dma_request_source
{
- kDma0RequestHashCrypt = 0U, /**< HashCrypt */
- kDma1RequestHashCrypt = 0U, /**< HashCrypt */
- kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
- kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
- kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
- kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
- kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
- kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
- kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
- kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
- kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
- kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
- kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
- kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
- kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
- kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
- kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
- kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
- kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
- kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
- kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */
- kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */
- kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */
- kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */
- kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */
- kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */
- kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */
- kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */
- kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */
- kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */
- kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */
- kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */
- kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */
+ kDma0RequestHashCrypt = 0U, /**< HashCrypt */
+ kDma1RequestHashCrypt = 0U, /**< HashCrypt */
+ kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
+ kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */
+ kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
+ kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */
+ kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
+ kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */
+ kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
+ kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */
+ kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
+ kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */
+ kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
+ kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */
+ kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
+ kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */
+ kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
+ kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */
+ kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
+ kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */
+ kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */
+ kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */
+ kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */
+ kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */
+ kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */
+ kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */
+ kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */
+ kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */
+ kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */
+ kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */
+ kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */
+ kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */
+ kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */
} dma_request_source_t;
/* @} */
+
/*!
* @}
*/ /* end of group Mapping_Information */
+
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -249,23 +253,24 @@ typedef enum _dma_request_source
* @{
*/
+
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
-#if (__ARMCC_VERSION >= 6010050)
-#pragma clang diagnostic push
-#else
-#pragma push
-#pragma anon_unions
-#endif
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
#elif defined(__GNUC__)
-/* anonymous unions are enabled by default */
+ /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
-#pragma language = extended
+ #pragma language=extended
#else
-#error Not supported compiler type
+ #error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
@@ -278,43 +283,41 @@ typedef enum _dma_request_source
*/
/** ADC - Register Layout Typedef */
-typedef struct
-{
- __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
- __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
- uint8_t RESERVED_0[8];
- __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
- __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
- __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
- __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
- __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
- __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
- uint8_t RESERVED_1[12];
- __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
- __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
- uint8_t RESERVED_2[4];
- __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
- uint8_t RESERVED_3[92];
- __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
- __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
- uint8_t RESERVED_4[8];
- __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
- __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
- struct
- { /* offset: 0x100, array step: 0x8 */
- __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
- __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
- } CMD[15];
- uint8_t RESERVED_5[136];
- __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
- uint8_t RESERVED_6[240];
- __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
- uint8_t RESERVED_7[248];
- __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
- uint8_t RESERVED_8[124];
- __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
- uint8_t RESERVED_9[2680];
- __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
+ __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
+ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
+ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
+ __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
+ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
+ uint8_t RESERVED_1[12];
+ __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
+ __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */
+ uint8_t RESERVED_3[92];
+ __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
+ __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */
+ __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */
+ struct { /* offset: 0x100, array step: 0x8 */
+ __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
+ __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
+ } CMD[15];
+ uint8_t RESERVED_5[136];
+ __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_6[240];
+ __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_7[248];
+ __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */
+ uint8_t RESERVED_8[124];
+ __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */
+ uint8_t RESERVED_9[2680];
+ __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */
} ADC_Type;
/* ----------------------------------------------------------------------------
@@ -328,65 +331,74 @@ typedef struct
/*! @name VERID - Version ID Register */
/*! @{ */
-#define ADC_VERID_RES_MASK (0x1U)
-#define ADC_VERID_RES_SHIFT (0U)
+
+#define ADC_VERID_RES_MASK (0x1U)
+#define ADC_VERID_RES_SHIFT (0U)
/*! RES - Resolution
* 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
* 0b1..Up to 16-bit differential/16-bit single ended resolution supported.
*/
-#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
-#define ADC_VERID_DIFFEN_MASK (0x2U)
-#define ADC_VERID_DIFFEN_SHIFT (1U)
+#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
+
+#define ADC_VERID_DIFFEN_MASK (0x2U)
+#define ADC_VERID_DIFFEN_SHIFT (1U)
/*! DIFFEN - Differential Supported
* 0b0..Differential operation not supported.
* 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.
*/
-#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
-#define ADC_VERID_MVI_MASK (0x8U)
-#define ADC_VERID_MVI_SHIFT (3U)
+#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
+
+#define ADC_VERID_MVI_MASK (0x8U)
+#define ADC_VERID_MVI_SHIFT (3U)
/*! MVI - Multi Vref Implemented
* 0b0..Single voltage reference high (VREFH) input supported.
* 0b1..Multiple voltage reference high (VREFH) inputs supported.
*/
-#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
-#define ADC_VERID_CSW_MASK (0x70U)
-#define ADC_VERID_CSW_SHIFT (4U)
+#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
+
+#define ADC_VERID_CSW_MASK (0x70U)
+#define ADC_VERID_CSW_SHIFT (4U)
/*! CSW - Channel Scale Width
* 0b000..Channel scaling not supported.
* 0b001..Channel scaling supported. 1-bit CSCALE control field.
* 0b110..Channel scaling supported. 6-bit CSCALE control field.
*/
-#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
-#define ADC_VERID_VR1RNGI_MASK (0x100U)
-#define ADC_VERID_VR1RNGI_SHIFT (8U)
+#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
+
+#define ADC_VERID_VR1RNGI_MASK (0x100U)
+#define ADC_VERID_VR1RNGI_SHIFT (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
* 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
* 0b1..Range control required. CFG[VREF1RNG] is implemented.
*/
-#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
-#define ADC_VERID_IADCKI_MASK (0x200U)
-#define ADC_VERID_IADCKI_SHIFT (9U)
+#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
+
+#define ADC_VERID_IADCKI_MASK (0x200U)
+#define ADC_VERID_IADCKI_SHIFT (9U)
/*! IADCKI - Internal ADC Clock implemented
* 0b0..Internal clock source not implemented.
* 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
*/
-#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
-#define ADC_VERID_CALOFSI_MASK (0x400U)
-#define ADC_VERID_CALOFSI_SHIFT (10U)
+#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
+
+#define ADC_VERID_CALOFSI_MASK (0x400U)
+#define ADC_VERID_CALOFSI_SHIFT (10U)
/*! CALOFSI - Calibration Function Implemented
* 0b0..Calibration Not Implemented.
* 0b1..Calibration Implemented.
*/
-#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
-#define ADC_VERID_NUM_SEC_MASK (0x800U)
-#define ADC_VERID_NUM_SEC_SHIFT (11U)
+#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
+
+#define ADC_VERID_NUM_SEC_MASK (0x800U)
+#define ADC_VERID_NUM_SEC_SHIFT (11U)
/*! NUM_SEC - Number of Single Ended Outputs Supported
* 0b0..This design supports one single ended conversion at a time.
* 0b1..This design supports two simultanious single ended conversions.
*/
-#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
-#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
-#define ADC_VERID_NUM_FIFO_SHIFT (12U)
+#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
+
+#define ADC_VERID_NUM_FIFO_MASK (0x7000U)
+#define ADC_VERID_NUM_FIFO_SHIFT (12U)
/*! NUM_FIFO - Number of FIFOs
* 0b000..N/A
* 0b001..This design supports one result FIFO.
@@ -394,28 +406,32 @@ typedef struct
* 0b011..This design supports three result FIFOs.
* 0b100..This design supports four result FIFOs.
*/
-#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
-#define ADC_VERID_MINOR_MASK (0xFF0000U)
-#define ADC_VERID_MINOR_SHIFT (16U)
+#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
+
+#define ADC_VERID_MINOR_MASK (0xFF0000U)
+#define ADC_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
-#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
-#define ADC_VERID_MAJOR_MASK (0xFF000000U)
-#define ADC_VERID_MAJOR_SHIFT (24U)
+#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
+
+#define ADC_VERID_MAJOR_MASK (0xFF000000U)
+#define ADC_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
-#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
+#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
-#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
-#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
+
+#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
+#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
/*! TRIG_NUM - Trigger Number
*/
-#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
-#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
-#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
+#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
+
+#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
+#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
/*! FIFOSIZE - Result FIFO Depth
* 0b00000001..Result FIFO depth = 1 dataword.
* 0b00000100..Result FIFO depth = 4 datawords.
@@ -424,72 +440,82 @@ typedef struct
* 0b00100000..Result FIFO depth = 32 datawords.
* 0b01000000..Result FIFO depth = 64 datawords.
*/
-#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
-#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
-#define ADC_PARAM_CV_NUM_SHIFT (16U)
+#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
+
+#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
+#define ADC_PARAM_CV_NUM_SHIFT (16U)
/*! CV_NUM - Compare Value Number
*/
-#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
-#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
-#define ADC_PARAM_CMD_NUM_SHIFT (24U)
+#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
+
+#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
+#define ADC_PARAM_CMD_NUM_SHIFT (24U)
/*! CMD_NUM - Command Buffer Number
*/
-#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
+#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */
/*! @name CTRL - ADC Control Register */
/*! @{ */
-#define ADC_CTRL_ADCEN_MASK (0x1U)
-#define ADC_CTRL_ADCEN_SHIFT (0U)
+
+#define ADC_CTRL_ADCEN_MASK (0x1U)
+#define ADC_CTRL_ADCEN_SHIFT (0U)
/*! ADCEN - ADC Enable
* 0b0..ADC is disabled.
* 0b1..ADC is enabled.
*/
-#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
-#define ADC_CTRL_RST_MASK (0x2U)
-#define ADC_CTRL_RST_SHIFT (1U)
+#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
+
+#define ADC_CTRL_RST_MASK (0x2U)
+#define ADC_CTRL_RST_SHIFT (1U)
/*! RST - Software Reset
* 0b0..ADC logic is not reset.
* 0b1..ADC logic is reset.
*/
-#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
-#define ADC_CTRL_DOZEN_MASK (0x4U)
-#define ADC_CTRL_DOZEN_SHIFT (2U)
+#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
+
+#define ADC_CTRL_DOZEN_MASK (0x4U)
+#define ADC_CTRL_DOZEN_SHIFT (2U)
/*! DOZEN - Doze Enable
* 0b0..ADC is enabled in Doze mode.
* 0b1..ADC is disabled in Doze mode.
*/
-#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
-#define ADC_CTRL_CAL_REQ_MASK (0x8U)
-#define ADC_CTRL_CAL_REQ_SHIFT (3U)
+#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
+
+#define ADC_CTRL_CAL_REQ_MASK (0x8U)
+#define ADC_CTRL_CAL_REQ_SHIFT (3U)
/*! CAL_REQ - Auto-Calibration Request
* 0b0..No request for auto-calibration has been made.
* 0b1..A request for auto-calibration has been made
*/
-#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
-#define ADC_CTRL_CALOFS_MASK (0x10U)
-#define ADC_CTRL_CALOFS_SHIFT (4U)
+#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)
+
+#define ADC_CTRL_CALOFS_MASK (0x10U)
+#define ADC_CTRL_CALOFS_SHIFT (4U)
/*! CALOFS - Configure for offset calibration function
* 0b0..Calibration function disabled
* 0b1..Request for offset calibration function
*/
-#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
-#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
-#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
+#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)
+
+#define ADC_CTRL_RSTFIFO0_MASK (0x100U)
+#define ADC_CTRL_RSTFIFO0_SHIFT (8U)
/*! RSTFIFO0 - Reset FIFO 0
* 0b0..No effect.
* 0b1..FIFO 0 is reset.
*/
-#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
-#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
-#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
+#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
+
+#define ADC_CTRL_RSTFIFO1_MASK (0x200U)
+#define ADC_CTRL_RSTFIFO1_SHIFT (9U)
/*! RSTFIFO1 - Reset FIFO 1
* 0b0..No effect.
* 0b1..FIFO 1 is reset.
*/
-#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
-#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)
-#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
+#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
+
+#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)
+#define ADC_CTRL_CAL_AVGS_SHIFT (16U)
/*! CAL_AVGS - Auto-Calibration Averages
* 0b000..Single conversion.
* 0b001..2 conversions averaged.
@@ -500,126 +526,142 @@ typedef struct
* 0b110..64 conversions averaged.
* 0b111..128 conversions averaged.
*/
-#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
+#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)
/*! @} */
/*! @name STAT - ADC Status Register */
/*! @{ */
-#define ADC_STAT_RDY0_MASK (0x1U)
-#define ADC_STAT_RDY0_SHIFT (0U)
+
+#define ADC_STAT_RDY0_MASK (0x1U)
+#define ADC_STAT_RDY0_SHIFT (0U)
/*! RDY0 - Result FIFO 0 Ready Flag
* 0b0..Result FIFO 0 data level not above watermark level.
* 0b1..Result FIFO 0 holding data above watermark level.
*/
-#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
-#define ADC_STAT_FOF0_MASK (0x2U)
-#define ADC_STAT_FOF0_SHIFT (1U)
+#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
+
+#define ADC_STAT_FOF0_MASK (0x2U)
+#define ADC_STAT_FOF0_SHIFT (1U)
/*! FOF0 - Result FIFO 0 Overflow Flag
* 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
* 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
*/
-#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
-#define ADC_STAT_RDY1_MASK (0x4U)
-#define ADC_STAT_RDY1_SHIFT (2U)
+#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
+
+#define ADC_STAT_RDY1_MASK (0x4U)
+#define ADC_STAT_RDY1_SHIFT (2U)
/*! RDY1 - Result FIFO1 Ready Flag
* 0b0..Result FIFO1 data level not above watermark level.
* 0b1..Result FIFO1 holding data above watermark level.
*/
-#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
-#define ADC_STAT_FOF1_MASK (0x8U)
-#define ADC_STAT_FOF1_SHIFT (3U)
+#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
+
+#define ADC_STAT_FOF1_MASK (0x8U)
+#define ADC_STAT_FOF1_SHIFT (3U)
/*! FOF1 - Result FIFO1 Overflow Flag
* 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
* 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
*/
-#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
-#define ADC_STAT_TEXC_INT_MASK (0x100U)
-#define ADC_STAT_TEXC_INT_SHIFT (8U)
+#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
+
+#define ADC_STAT_TEXC_INT_MASK (0x100U)
+#define ADC_STAT_TEXC_INT_SHIFT (8U)
/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
* 0b0..No trigger exceptions have occurred.
* 0b1..A trigger exception has occurred and is pending acknowledgement.
*/
-#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
-#define ADC_STAT_TCOMP_INT_MASK (0x200U)
-#define ADC_STAT_TCOMP_INT_SHIFT (9U)
+#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
+
+#define ADC_STAT_TCOMP_INT_MASK (0x200U)
+#define ADC_STAT_TCOMP_INT_SHIFT (9U)
/*! TCOMP_INT - Interrupt Flag For Trigger Completion
* 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
* 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
*/
-#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
-#define ADC_STAT_CAL_RDY_MASK (0x400U)
-#define ADC_STAT_CAL_RDY_SHIFT (10U)
+#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
+
+#define ADC_STAT_CAL_RDY_MASK (0x400U)
+#define ADC_STAT_CAL_RDY_SHIFT (10U)
/*! CAL_RDY - Calibration Ready
* 0b0..Calibration is incomplete or hasn't been ran.
* 0b1..The ADC is calibrated.
*/
-#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
-#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
-#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
+#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)
+
+#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)
+#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)
/*! ADC_ACTIVE - ADC Active
* 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
* 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
*/
-#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
-#define ADC_STAT_TRGACT_MASK (0xF0000U)
-#define ADC_STAT_TRGACT_SHIFT (16U)
+#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
+
+#define ADC_STAT_TRGACT_MASK (0xF0000U)
+#define ADC_STAT_TRGACT_SHIFT (16U)
/*! TRGACT - Trigger Active
* 0b0000..Command (sequence) associated with Trigger 0 currently being executed.
* 0b0001..Command (sequence) associated with Trigger 1 currently being executed.
* 0b0010..Command (sequence) associated with Trigger 2 currently being executed.
* 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
*/
-#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
-#define ADC_STAT_CMDACT_MASK (0xF000000U)
-#define ADC_STAT_CMDACT_SHIFT (24U)
+#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
+
+#define ADC_STAT_CMDACT_MASK (0xF000000U)
+#define ADC_STAT_CMDACT_SHIFT (24U)
/*! CMDACT - Command Active
* 0b0000..No command is currently in progress.
* 0b0001..Command 1 currently being executed.
* 0b0010..Command 2 currently being executed.
* 0b0011-0b1111..Associated command number is currently being executed.
*/
-#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
+#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */
/*! @name IE - Interrupt Enable Register */
/*! @{ */
-#define ADC_IE_FWMIE0_MASK (0x1U)
-#define ADC_IE_FWMIE0_SHIFT (0U)
+
+#define ADC_IE_FWMIE0_MASK (0x1U)
+#define ADC_IE_FWMIE0_SHIFT (0U)
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
* 0b0..FIFO 0 watermark interrupts are not enabled.
* 0b1..FIFO 0 watermark interrupts are enabled.
*/
-#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
-#define ADC_IE_FOFIE0_MASK (0x2U)
-#define ADC_IE_FOFIE0_SHIFT (1U)
+#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
+
+#define ADC_IE_FOFIE0_MASK (0x2U)
+#define ADC_IE_FOFIE0_SHIFT (1U)
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
* 0b0..FIFO 0 overflow interrupts are not enabled.
* 0b1..FIFO 0 overflow interrupts are enabled.
*/
-#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
-#define ADC_IE_FWMIE1_MASK (0x4U)
-#define ADC_IE_FWMIE1_SHIFT (2U)
+#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
+
+#define ADC_IE_FWMIE1_MASK (0x4U)
+#define ADC_IE_FWMIE1_SHIFT (2U)
/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
* 0b0..FIFO1 watermark interrupts are not enabled.
* 0b1..FIFO1 watermark interrupts are enabled.
*/
-#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
-#define ADC_IE_FOFIE1_MASK (0x8U)
-#define ADC_IE_FOFIE1_SHIFT (3U)
+#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
+
+#define ADC_IE_FOFIE1_MASK (0x8U)
+#define ADC_IE_FOFIE1_SHIFT (3U)
/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
* 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
* 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
*/
-#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
-#define ADC_IE_TEXC_IE_MASK (0x100U)
-#define ADC_IE_TEXC_IE_SHIFT (8U)
+#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
+
+#define ADC_IE_TEXC_IE_MASK (0x100U)
+#define ADC_IE_TEXC_IE_SHIFT (8U)
/*! TEXC_IE - Trigger Exception Interrupt Enable
* 0b0..Trigger exception interrupts are disabled.
* 0b1..Trigger exception interrupts are enabled.
*/
-#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
-#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
-#define ADC_IE_TCOMP_IE_SHIFT (16U)
+#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
+
+#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)
+#define ADC_IE_TCOMP_IE_SHIFT (16U)
/*! TCOMP_IE - Trigger Completion Interrupt Enable
* 0b0000000000000000..Trigger completion interrupts are disabled.
* 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
@@ -627,31 +669,34 @@ typedef struct
* 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
* 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
*/
-#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
+#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
/*! @} */
/*! @name DE - DMA Enable Register */
/*! @{ */
-#define ADC_DE_FWMDE0_MASK (0x1U)
-#define ADC_DE_FWMDE0_SHIFT (0U)
+
+#define ADC_DE_FWMDE0_MASK (0x1U)
+#define ADC_DE_FWMDE0_SHIFT (0U)
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
* 0b0..DMA request disabled.
* 0b1..DMA request enabled.
*/
-#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
-#define ADC_DE_FWMDE1_MASK (0x2U)
-#define ADC_DE_FWMDE1_SHIFT (1U)
+#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
+
+#define ADC_DE_FWMDE1_MASK (0x2U)
+#define ADC_DE_FWMDE1_SHIFT (1U)
/*! FWMDE1 - FIFO1 Watermark DMA Enable
* 0b0..DMA request disabled.
* 0b1..DMA request enabled.
*/
-#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
+#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
/*! @} */
/*! @name CFG - ADC Configuration Register */
/*! @{ */
-#define ADC_CFG_TPRICTRL_MASK (0x3U)
-#define ADC_CFG_TPRICTRL_SHIFT (0U)
+
+#define ADC_CFG_TPRICTRL_MASK (0x3U)
+#define ADC_CFG_TPRICTRL_SHIFT (0U)
/*! TPRICTRL - ADC trigger priority control
* 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
* and the new command specified by the trigger is started.
@@ -662,202 +707,226 @@ typedef struct
* completed (averaging, looping, compare) before servicing the higher priority trigger.
* 0b11..RESERVED
*/
-#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
-#define ADC_CFG_PWRSEL_MASK (0x30U)
-#define ADC_CFG_PWRSEL_SHIFT (4U)
+#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
+
+#define ADC_CFG_PWRSEL_MASK (0x30U)
+#define ADC_CFG_PWRSEL_SHIFT (4U)
/*! PWRSEL - Power Configuration Select
* 0b00..Lowest power setting.
* 0b01..Higher power setting than 0b0.
* 0b10..Higher power setting than 0b1.
* 0b11..Highest power setting.
*/
-#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
-#define ADC_CFG_REFSEL_MASK (0xC0U)
-#define ADC_CFG_REFSEL_SHIFT (6U)
+#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
+
+#define ADC_CFG_REFSEL_MASK (0xC0U)
+#define ADC_CFG_REFSEL_SHIFT (6U)
/*! REFSEL - Voltage Reference Selection
* 0b00..(Default) Option 1 setting.
* 0b01..Option 2 setting.
* 0b10..Option 3 setting.
* 0b11..Reserved
*/
-#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
-#define ADC_CFG_TRES_MASK (0x100U)
-#define ADC_CFG_TRES_SHIFT (8U)
+#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+
+#define ADC_CFG_TRES_MASK (0x100U)
+#define ADC_CFG_TRES_SHIFT (8U)
/*! TRES - Trigger Resume Enable
- * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or
- * restarted. 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or
- * restarted.
+ * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.
+ * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.
*/
-#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
-#define ADC_CFG_TCMDRES_MASK (0x200U)
-#define ADC_CFG_TCMDRES_SHIFT (9U)
+#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
+
+#define ADC_CFG_TCMDRES_MASK (0x200U)
+#define ADC_CFG_TCMDRES_SHIFT (9U)
/*! TCMDRES - Trigger Command Resume
* 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.
- * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing
- * before the exception.
+ * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.
*/
-#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
-#define ADC_CFG_HPT_EXDI_MASK (0x400U)
-#define ADC_CFG_HPT_EXDI_SHIFT (10U)
+#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
+
+#define ADC_CFG_HPT_EXDI_MASK (0x400U)
+#define ADC_CFG_HPT_EXDI_SHIFT (10U)
/*! HPT_EXDI - High Priority Trigger Exception Disable
* 0b0..High priority trigger exceptions are enabled.
* 0b1..High priority trigger exceptions are disabled.
*/
-#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
-#define ADC_CFG_PUDLY_MASK (0xFF0000U)
-#define ADC_CFG_PUDLY_SHIFT (16U)
+#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
+
+#define ADC_CFG_PUDLY_MASK (0xFF0000U)
+#define ADC_CFG_PUDLY_SHIFT (16U)
/*! PUDLY - Power Up Delay
*/
-#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
-#define ADC_CFG_PWREN_MASK (0x10000000U)
-#define ADC_CFG_PWREN_SHIFT (28U)
+#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
+
+#define ADC_CFG_PWREN_MASK (0x10000000U)
+#define ADC_CFG_PWREN_SHIFT (28U)
/*! PWREN - ADC Analog Pre-Enable
- * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog
- * startup delays. 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at
- * the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
+ * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
+ * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
+ * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
* is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
* After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
* executed.
*/
-#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
+#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */
/*! @name PAUSE - ADC Pause Register */
/*! @{ */
-#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
-#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
+
+#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
+#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
/*! PAUSEDLY - Pause Delay
*/
-#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
-#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
-#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
+#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
+
+#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
+#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
/*! PAUSEEN - PAUSE Option Enable
* 0b0..Pause operation disabled
* 0b1..Pause operation enabled
*/
-#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
+#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */
/*! @name SWTRIG - Software Trigger Register */
/*! @{ */
-#define ADC_SWTRIG_SWT0_MASK (0x1U)
-#define ADC_SWTRIG_SWT0_SHIFT (0U)
+
+#define ADC_SWTRIG_SWT0_MASK (0x1U)
+#define ADC_SWTRIG_SWT0_SHIFT (0U)
/*! SWT0 - Software trigger 0 event
* 0b0..No trigger 0 event generated.
* 0b1..Trigger 0 event generated.
*/
-#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
-#define ADC_SWTRIG_SWT1_MASK (0x2U)
-#define ADC_SWTRIG_SWT1_SHIFT (1U)
+#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
+
+#define ADC_SWTRIG_SWT1_MASK (0x2U)
+#define ADC_SWTRIG_SWT1_SHIFT (1U)
/*! SWT1 - Software trigger 1 event
* 0b0..No trigger 1 event generated.
* 0b1..Trigger 1 event generated.
*/
-#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
-#define ADC_SWTRIG_SWT2_MASK (0x4U)
-#define ADC_SWTRIG_SWT2_SHIFT (2U)
+#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
+
+#define ADC_SWTRIG_SWT2_MASK (0x4U)
+#define ADC_SWTRIG_SWT2_SHIFT (2U)
/*! SWT2 - Software trigger 2 event
* 0b0..No trigger 2 event generated.
* 0b1..Trigger 2 event generated.
*/
-#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
-#define ADC_SWTRIG_SWT3_MASK (0x8U)
-#define ADC_SWTRIG_SWT3_SHIFT (3U)
+#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
+
+#define ADC_SWTRIG_SWT3_MASK (0x8U)
+#define ADC_SWTRIG_SWT3_SHIFT (3U)
/*! SWT3 - Software trigger 3 event
* 0b0..No trigger 3 event generated.
* 0b1..Trigger 3 event generated.
*/
-#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
-#define ADC_SWTRIG_SWT4_MASK (0x10U)
-#define ADC_SWTRIG_SWT4_SHIFT (4U)
+#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
+
+#define ADC_SWTRIG_SWT4_MASK (0x10U)
+#define ADC_SWTRIG_SWT4_SHIFT (4U)
/*! SWT4 - Software trigger 4 event
* 0b0..No trigger 4 event generated.
* 0b1..Trigger 4 event generated.
*/
-#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
-#define ADC_SWTRIG_SWT5_MASK (0x20U)
-#define ADC_SWTRIG_SWT5_SHIFT (5U)
+#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
+
+#define ADC_SWTRIG_SWT5_MASK (0x20U)
+#define ADC_SWTRIG_SWT5_SHIFT (5U)
/*! SWT5 - Software trigger 5 event
* 0b0..No trigger 5 event generated.
* 0b1..Trigger 5 event generated.
*/
-#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
-#define ADC_SWTRIG_SWT6_MASK (0x40U)
-#define ADC_SWTRIG_SWT6_SHIFT (6U)
+#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
+
+#define ADC_SWTRIG_SWT6_MASK (0x40U)
+#define ADC_SWTRIG_SWT6_SHIFT (6U)
/*! SWT6 - Software trigger 6 event
* 0b0..No trigger 6 event generated.
* 0b1..Trigger 6 event generated.
*/
-#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
-#define ADC_SWTRIG_SWT7_MASK (0x80U)
-#define ADC_SWTRIG_SWT7_SHIFT (7U)
+#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
+
+#define ADC_SWTRIG_SWT7_MASK (0x80U)
+#define ADC_SWTRIG_SWT7_SHIFT (7U)
/*! SWT7 - Software trigger 7 event
* 0b0..No trigger 7 event generated.
* 0b1..Trigger 7 event generated.
*/
-#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
-#define ADC_SWTRIG_SWT8_MASK (0x100U)
-#define ADC_SWTRIG_SWT8_SHIFT (8U)
+#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
+
+#define ADC_SWTRIG_SWT8_MASK (0x100U)
+#define ADC_SWTRIG_SWT8_SHIFT (8U)
/*! SWT8 - Software trigger 8 event
* 0b0..No trigger 8 event generated.
* 0b1..Trigger 8 event generated.
*/
-#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
-#define ADC_SWTRIG_SWT9_MASK (0x200U)
-#define ADC_SWTRIG_SWT9_SHIFT (9U)
+#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
+
+#define ADC_SWTRIG_SWT9_MASK (0x200U)
+#define ADC_SWTRIG_SWT9_SHIFT (9U)
/*! SWT9 - Software trigger 9 event
* 0b0..No trigger 9 event generated.
* 0b1..Trigger 9 event generated.
*/
-#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
-#define ADC_SWTRIG_SWT10_MASK (0x400U)
-#define ADC_SWTRIG_SWT10_SHIFT (10U)
+#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
+
+#define ADC_SWTRIG_SWT10_MASK (0x400U)
+#define ADC_SWTRIG_SWT10_SHIFT (10U)
/*! SWT10 - Software trigger 10 event
* 0b0..No trigger 10 event generated.
* 0b1..Trigger 10 event generated.
*/
-#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
-#define ADC_SWTRIG_SWT11_MASK (0x800U)
-#define ADC_SWTRIG_SWT11_SHIFT (11U)
+#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
+
+#define ADC_SWTRIG_SWT11_MASK (0x800U)
+#define ADC_SWTRIG_SWT11_SHIFT (11U)
/*! SWT11 - Software trigger 11 event
* 0b0..No trigger 11 event generated.
* 0b1..Trigger 11 event generated.
*/
-#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
-#define ADC_SWTRIG_SWT12_MASK (0x1000U)
-#define ADC_SWTRIG_SWT12_SHIFT (12U)
+#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
+
+#define ADC_SWTRIG_SWT12_MASK (0x1000U)
+#define ADC_SWTRIG_SWT12_SHIFT (12U)
/*! SWT12 - Software trigger 12 event
* 0b0..No trigger 12 event generated.
* 0b1..Trigger 12 event generated.
*/
-#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
-#define ADC_SWTRIG_SWT13_MASK (0x2000U)
-#define ADC_SWTRIG_SWT13_SHIFT (13U)
+#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
+
+#define ADC_SWTRIG_SWT13_MASK (0x2000U)
+#define ADC_SWTRIG_SWT13_SHIFT (13U)
/*! SWT13 - Software trigger 13 event
* 0b0..No trigger 13 event generated.
* 0b1..Trigger 13 event generated.
*/
-#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
-#define ADC_SWTRIG_SWT14_MASK (0x4000U)
-#define ADC_SWTRIG_SWT14_SHIFT (14U)
+#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
+
+#define ADC_SWTRIG_SWT14_MASK (0x4000U)
+#define ADC_SWTRIG_SWT14_SHIFT (14U)
/*! SWT14 - Software trigger 14 event
* 0b0..No trigger 14 event generated.
* 0b1..Trigger 14 event generated.
*/
-#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
-#define ADC_SWTRIG_SWT15_MASK (0x8000U)
-#define ADC_SWTRIG_SWT15_SHIFT (15U)
+#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
+
+#define ADC_SWTRIG_SWT15_MASK (0x8000U)
+#define ADC_SWTRIG_SWT15_SHIFT (15U)
/*! SWT15 - Software trigger 15 event
* 0b0..No trigger 15 event generated.
* 0b1..Trigger 15 event generated.
*/
-#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
+#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
/*! @} */
/*! @name TSTAT - Trigger Status Register */
/*! @{ */
-#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
-#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
+
+#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)
+#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)
/*! TEXC_NUM - Trigger Exception Number
* 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
* 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
@@ -865,153 +934,164 @@ typedef struct
* 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
* 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
*/
-#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
-#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
-#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
+#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
+
+#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)
+#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)
/*! TCOMP_FLAG - Trigger Completion Flag
* 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
* 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
* 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
- * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion
- * interrupts. 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion
- * interrupts.
+ * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
+ * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
*/
-#define ADC_TSTAT_TCOMP_FLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
+#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
/*! @} */
/*! @name OFSTRIM - ADC Offset Trim Register */
/*! @{ */
-#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)
-#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)
+
+#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)
+#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)
/*! OFSTRIM_A - Trim for offset
*/
-#define ADC_OFSTRIM_OFSTRIM_A(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
-#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)
-#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)
+#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)
+
+#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)
+#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)
/*! OFSTRIM_B - Trim for offset
*/
-#define ADC_OFSTRIM_OFSTRIM_B(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
+#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)
/*! @} */
/*! @name TCTRL - Trigger Control Register */
/*! @{ */
-#define ADC_TCTRL_HTEN_MASK (0x1U)
-#define ADC_TCTRL_HTEN_SHIFT (0U)
+
+#define ADC_TCTRL_HTEN_MASK (0x1U)
+#define ADC_TCTRL_HTEN_SHIFT (0U)
/*! HTEN - Trigger enable
* 0b0..Hardware trigger source disabled
* 0b1..Hardware trigger source enabled
*/
-#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
-#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
-#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
+#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
+
+#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)
+#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)
/*! FIFO_SEL_A - SAR Result Destination For Channel A
* 0b0..Result written to FIFO 0
* 0b1..Result written to FIFO 1
*/
-#define ADC_TCTRL_FIFO_SEL_A(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
-#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)
-#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)
+#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
+
+#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)
+#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)
/*! FIFO_SEL_B - SAR Result Destination For Channel B
* 0b0..Result written to FIFO 0
* 0b1..Result written to FIFO 1
*/
-#define ADC_TCTRL_FIFO_SEL_B(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
-#define ADC_TCTRL_TPRI_MASK (0xF00U)
-#define ADC_TCTRL_TPRI_SHIFT (8U)
+#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)
+
+#define ADC_TCTRL_TPRI_MASK (0xF00U)
+#define ADC_TCTRL_TPRI_SHIFT (8U)
/*! TPRI - Trigger priority setting
* 0b0000..Set to highest priority, Level 1
* 0b0001-0b1110..Set to corresponding priority level
* 0b1111..Set to lowest priority, Level 16
*/
-#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
-#define ADC_TCTRL_RSYNC_MASK (0x8000U)
-#define ADC_TCTRL_RSYNC_SHIFT (15U)
+#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
+
+#define ADC_TCTRL_RSYNC_MASK (0x8000U)
+#define ADC_TCTRL_RSYNC_SHIFT (15U)
/*! RSYNC - Trigger Resync
*/
-#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
-#define ADC_TCTRL_TDLY_MASK (0xF0000U)
-#define ADC_TCTRL_TDLY_SHIFT (16U)
+#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
+
+#define ADC_TCTRL_TDLY_MASK (0xF0000U)
+#define ADC_TCTRL_TDLY_SHIFT (16U)
/*! TDLY - Trigger delay select
*/
-#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
-#define ADC_TCTRL_TCMD_MASK (0xF000000U)
-#define ADC_TCTRL_TCMD_SHIFT (24U)
+#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
+
+#define ADC_TCTRL_TCMD_MASK (0xF000000U)
+#define ADC_TCTRL_TCMD_SHIFT (24U)
/*! TCMD - Trigger command select
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..CMD1 is executed
* 0b0010-0b1110..Corresponding CMD is executed
* 0b1111..CMD15 is executed
*/
-#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
+#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */
/* The count of ADC_TCTRL */
-#define ADC_TCTRL_COUNT (16U)
+#define ADC_TCTRL_COUNT (16U)
/*! @name FCTRL - FIFO Control Register */
/*! @{ */
-#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
-#define ADC_FCTRL_FCOUNT_SHIFT (0U)
+
+#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
+#define ADC_FCTRL_FCOUNT_SHIFT (0U)
/*! FCOUNT - Result FIFO counter
*/
-#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
-#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
-#define ADC_FCTRL_FWMARK_SHIFT (16U)
+#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
+
+#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
+#define ADC_FCTRL_FWMARK_SHIFT (16U)
/*! FWMARK - Watermark level selection
*/
-#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
+#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */
/* The count of ADC_FCTRL */
-#define ADC_FCTRL_COUNT (2U)
+#define ADC_FCTRL_COUNT (2U)
/*! @name GCC - Gain Calibration Control */
/*! @{ */
-#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
-#define ADC_GCC_GAIN_CAL_SHIFT (0U)
+
+#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)
+#define ADC_GCC_GAIN_CAL_SHIFT (0U)
/*! GAIN_CAL - Gain Calibration Value
*/
-#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
-#define ADC_GCC_RDY_MASK (0x1000000U)
-#define ADC_GCC_RDY_SHIFT (24U)
+#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)
+
+#define ADC_GCC_RDY_MASK (0x1000000U)
+#define ADC_GCC_RDY_SHIFT (24U)
/*! RDY - Gain Calibration Value Valid
* 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.
* 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.
*/
-#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
+#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)
/*! @} */
/* The count of ADC_GCC */
-#define ADC_GCC_COUNT (2U)
+#define ADC_GCC_COUNT (2U)
/*! @name GCR - Gain Calculation Result */
/*! @{ */
-#define ADC_GCR_GCALR_MASK (0xFFFFU)
-#define ADC_GCR_GCALR_SHIFT (0U)
+
+#define ADC_GCR_GCALR_MASK (0xFFFFU)
+#define ADC_GCR_GCALR_SHIFT (0U)
/*! GCALR - Gain Calculation Result
*/
-#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
-#define ADC_GCR_RDY_MASK (0x1000000U)
-#define ADC_GCR_RDY_SHIFT (24U)
+#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)
+
+#define ADC_GCR_RDY_MASK (0x1000000U)
+#define ADC_GCR_RDY_SHIFT (24U)
/*! RDY - Gain Calculation Ready
* 0b0..The gain offset calculation value is invalid.
* 0b1..The gain calibration value is valid.
*/
-#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
+#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)
/*! @} */
/* The count of ADC_GCR */
-#define ADC_GCR_COUNT (2U)
+#define ADC_GCR_COUNT (2U)
/*! @name CMDL - ADC Command Low Buffer Register */
/*! @{ */
-#define ADC_CMDL_ADCH_MASK (0x1FU)
-#define ADC_CMDL_ADCH_SHIFT (0U)
+
+#define ADC_CMDL_ADCH_MASK (0x1FU)
+#define ADC_CMDL_ADCH_SHIFT (0U)
/*! ADCH - Input channel select
* 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
* 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
@@ -1021,55 +1101,61 @@ typedef struct
* 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
* 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
*/
-#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
-#define ADC_CMDL_CTYPE_MASK (0x60U)
-#define ADC_CMDL_CTYPE_SHIFT (5U)
+#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
+
+#define ADC_CMDL_CTYPE_MASK (0x60U)
+#define ADC_CMDL_CTYPE_SHIFT (5U)
/*! CTYPE - Conversion Type
* 0b00..Single-Ended Mode. Only A side channel is converted.
* 0b01..Single-Ended Mode. Only B side channel is converted.
* 0b10..Differential Mode. A-B.
* 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.
*/
-#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
-#define ADC_CMDL_MODE_MASK (0x80U)
-#define ADC_CMDL_MODE_SHIFT (7U)
+#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)
+
+#define ADC_CMDL_MODE_MASK (0x80U)
+#define ADC_CMDL_MODE_SHIFT (7U)
/*! MODE - Select resolution of conversions
* 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.
* 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.
*/
-#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
+#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)
/*! @} */
/* The count of ADC_CMDL */
-#define ADC_CMDL_COUNT (15U)
+#define ADC_CMDL_COUNT (15U)
/*! @name CMDH - ADC Command High Buffer Register */
/*! @{ */
-#define ADC_CMDH_CMPEN_MASK (0x3U)
-#define ADC_CMDH_CMPEN_SHIFT (0U)
+
+#define ADC_CMDH_CMPEN_MASK (0x3U)
+#define ADC_CMDH_CMPEN_SHIFT (0U)
/*! CMPEN - Compare Function Enable
* 0b00..Compare disabled.
* 0b01..Reserved
* 0b10..Compare enabled. Store on true.
* 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
*/
-#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
-#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
-#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
+#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
+
+#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)
+#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)
/*! WAIT_TRIG - Wait for trigger assertion before execution.
* 0b0..This command will be automatically executed.
* 0b1..The active trigger must be asserted again before executing this command.
*/
-#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
-#define ADC_CMDH_LWI_MASK (0x80U)
-#define ADC_CMDH_LWI_SHIFT (7U)
+#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
+
+#define ADC_CMDH_LWI_MASK (0x80U)
+#define ADC_CMDH_LWI_SHIFT (7U)
/*! LWI - Loop with Increment
* 0b0..Auto channel increment disabled
* 0b1..Auto channel increment enabled
*/
-#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
-#define ADC_CMDH_STS_MASK (0x700U)
-#define ADC_CMDH_STS_SHIFT (8U)
+#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
+
+#define ADC_CMDH_STS_MASK (0x700U)
+#define ADC_CMDH_STS_SHIFT (8U)
/*! STS - Sample Time Select
* 0b000..Minimum sample time of 3 ADCK cycles.
* 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
@@ -1080,9 +1166,10 @@ typedef struct
* 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
* 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
*/
-#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
-#define ADC_CMDH_AVGS_MASK (0x7000U)
-#define ADC_CMDH_AVGS_SHIFT (12U)
+#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
+
+#define ADC_CMDH_AVGS_MASK (0x7000U)
+#define ADC_CMDH_AVGS_SHIFT (12U)
/*! AVGS - Hardware Average Select
* 0b000..Single conversion.
* 0b001..2 conversions averaged.
@@ -1093,9 +1180,10 @@ typedef struct
* 0b110..64 conversions averaged.
* 0b111..128 conversions averaged.
*/
-#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
-#define ADC_CMDH_LOOP_MASK (0xF0000U)
-#define ADC_CMDH_LOOP_SHIFT (16U)
+#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
+
+#define ADC_CMDH_LOOP_MASK (0xF0000U)
+#define ADC_CMDH_LOOP_SHIFT (16U)
/*! LOOP - Loop Count Select
* 0b0000..Looping not enabled. Command executes 1 time.
* 0b0001..Loop 1 time. Command executes 2 times.
@@ -1103,9 +1191,10 @@ typedef struct
* 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
* 0b1111..Loop 15 times. Command executes 16 times.
*/
-#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
-#define ADC_CMDH_NEXT_MASK (0xF000000U)
-#define ADC_CMDH_NEXT_SHIFT (24U)
+#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
+
+#define ADC_CMDH_NEXT_MASK (0xF000000U)
+#define ADC_CMDH_NEXT_SHIFT (24U)
/*! NEXT - Next Command Select
* 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
* trigger pending, begin command associated with lower priority trigger.
@@ -1113,56 +1202,62 @@ typedef struct
* 0b0010-0b1110..Select corresponding CMD command buffer register as next command
* 0b1111..Select CMD15 command buffer register as next command.
*/
-#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
+#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */
/* The count of ADC_CMDH */
-#define ADC_CMDH_COUNT (15U)
+#define ADC_CMDH_COUNT (15U)
/*! @name CV - Compare Value Register */
/*! @{ */
-#define ADC_CV_CVL_MASK (0xFFFFU)
-#define ADC_CV_CVL_SHIFT (0U)
+
+#define ADC_CV_CVL_MASK (0xFFFFU)
+#define ADC_CV_CVL_SHIFT (0U)
/*! CVL - Compare Value Low.
*/
-#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
-#define ADC_CV_CVH_MASK (0xFFFF0000U)
-#define ADC_CV_CVH_SHIFT (16U)
+#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
+
+#define ADC_CV_CVH_MASK (0xFFFF0000U)
+#define ADC_CV_CVH_SHIFT (16U)
/*! CVH - Compare Value High.
*/
-#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
+#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */
/* The count of ADC_CV */
-#define ADC_CV_COUNT (4U)
+#define ADC_CV_COUNT (4U)
/*! @name RESFIFO - ADC Data Result FIFO Register */
/*! @{ */
-#define ADC_RESFIFO_D_MASK (0xFFFFU)
-#define ADC_RESFIFO_D_SHIFT (0U)
+
+#define ADC_RESFIFO_D_MASK (0xFFFFU)
+#define ADC_RESFIFO_D_SHIFT (0U)
/*! D - Data result
*/
-#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
-#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
-#define ADC_RESFIFO_TSRC_SHIFT (16U)
+#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
+
+#define ADC_RESFIFO_TSRC_MASK (0xF0000U)
+#define ADC_RESFIFO_TSRC_SHIFT (16U)
/*! TSRC - Trigger Source
* 0b0000..Trigger source 0 initiated this conversion.
* 0b0001..Trigger source 1 initiated this conversion.
* 0b0010-0b1110..Corresponding trigger source initiated this conversion.
* 0b1111..Trigger source 15 initiated this conversion.
*/
-#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
-#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
-#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
+#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
+
+#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
+#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
/*! LOOPCNT - Loop count value
* 0b0000..Result is from initial conversion in command.
* 0b0001..Result is from second conversion in command.
* 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
* 0b1111..Result is from 16th conversion in command.
*/
-#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
-#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
-#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
+#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
+
+#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
+#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
/*! CMDSRC - Command Buffer Source
* 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
* prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
@@ -1170,151 +1265,140 @@ typedef struct
* 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
* 0b1111..CMD15 buffer used as control settings for this conversion.
*/
-#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
-#define ADC_RESFIFO_VALID_MASK (0x80000000U)
-#define ADC_RESFIFO_VALID_SHIFT (31U)
+#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
+
+#define ADC_RESFIFO_VALID_MASK (0x80000000U)
+#define ADC_RESFIFO_VALID_SHIFT (31U)
/*! VALID - FIFO entry is valid
* 0b0..FIFO is empty. Discard any read from RESFIFO.
* 0b1..FIFO record read from RESFIFO is valid.
*/
-#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
+#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */
/* The count of ADC_RESFIFO */
-#define ADC_RESFIFO_COUNT (2U)
+#define ADC_RESFIFO_COUNT (2U)
/*! @name CAL_GAR - Calibration General A-Side Registers */
/*! @{ */
-#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)
-#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)
+
+#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)
+#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)
/*! CAL_GAR_VAL - Calibration General A Side Register Element
*/
-#define ADC_CAL_GAR_CAL_GAR_VAL(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
+#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)
/*! @} */
/* The count of ADC_CAL_GAR */
-#define ADC_CAL_GAR_COUNT (33U)
+#define ADC_CAL_GAR_COUNT (33U)
/*! @name CAL_GBR - Calibration General B-Side Registers */
/*! @{ */
-#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)
-#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)
+
+#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)
+#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)
/*! CAL_GBR_VAL - Calibration General B Side Register Element
*/
-#define ADC_CAL_GBR_CAL_GBR_VAL(x) \
- (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
+#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)
/*! @} */
/* The count of ADC_CAL_GBR */
-#define ADC_CAL_GBR_COUNT (33U)
+#define ADC_CAL_GBR_COUNT (33U)
/*! @name TST - ADC Test Register */
/*! @{ */
-#define ADC_TST_CST_LONG_MASK (0x1U)
-#define ADC_TST_CST_LONG_SHIFT (0U)
+
+#define ADC_TST_CST_LONG_MASK (0x1U)
+#define ADC_TST_CST_LONG_SHIFT (0U)
/*! CST_LONG - Calibration Sample Time Long
* 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles.
* 0b1..Increased sample time. 67 ADCK cycles total sample time.
*/
-#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)
-#define ADC_TST_FOFFM_MASK (0x100U)
-#define ADC_TST_FOFFM_SHIFT (8U)
+#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)
+
+#define ADC_TST_FOFFM_MASK (0x100U)
+#define ADC_TST_FOFFM_SHIFT (8U)
/*! FOFFM - Force M-side positive offset
* 0b0..Normal operation. No forced offset.
* 0b1..Test configuration. Forced positive offset on MDAC.
*/
-#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
-#define ADC_TST_FOFFP_MASK (0x200U)
-#define ADC_TST_FOFFP_SHIFT (9U)
+#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)
+
+#define ADC_TST_FOFFP_MASK (0x200U)
+#define ADC_TST_FOFFP_SHIFT (9U)
/*! FOFFP - Force P-side positive offset
* 0b0..Normal operation. No forced offset.
* 0b1..Test configuration. Forced positive offset on PDAC.
*/
-#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
-#define ADC_TST_FOFFM2_MASK (0x400U)
-#define ADC_TST_FOFFM2_SHIFT (10U)
+#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)
+
+#define ADC_TST_FOFFM2_MASK (0x400U)
+#define ADC_TST_FOFFM2_SHIFT (10U)
/*! FOFFM2 - Force M-side negative offset
* 0b0..Normal operation. No forced offset.
* 0b1..Test configuration. Forced negative offset on MDAC.
*/
-#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)
-#define ADC_TST_FOFFP2_MASK (0x800U)
-#define ADC_TST_FOFFP2_SHIFT (11U)
+#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)
+
+#define ADC_TST_FOFFP2_MASK (0x800U)
+#define ADC_TST_FOFFP2_SHIFT (11U)
/*! FOFFP2 - Force P-side negative offset
* 0b0..Normal operation. No forced offset.
* 0b1..Test configuration. Forced negative offset on PDAC.
*/
-#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)
-#define ADC_TST_TESTEN_MASK (0x800000U)
-#define ADC_TST_TESTEN_SHIFT (23U)
+#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)
+
+#define ADC_TST_TESTEN_MASK (0x800000U)
+#define ADC_TST_TESTEN_SHIFT (23U)
/*! TESTEN - Enable test configuration
* 0b0..Normal operation. Test configuration not enabled.
* 0b1..Hardware BIST Test in progress.
*/
-#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
+#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group ADC_Register_Masks */
+
/* ADC - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x500A0000u)
-/** Peripheral ADC0 base address */
-#define ADC0_BASE_NS (0x400A0000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-/** Peripheral ADC0 base pointer */
-#define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
-/** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS \
- { \
- ADC0_BASE \
- }
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS \
- { \
- ADC0 \
- }
-/** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS_NS \
- { \
- ADC0_BASE_NS \
- }
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS_NS \
- { \
- ADC0_NS \
- }
+ /** Peripheral ADC0 base address */
+ #define ADC0_BASE (0x500A0000u)
+ /** Peripheral ADC0 base address */
+ #define ADC0_BASE_NS (0x400A0000u)
+ /** Peripheral ADC0 base pointer */
+ #define ADC0 ((ADC_Type *)ADC0_BASE)
+ /** Peripheral ADC0 base pointer */
+ #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)
+ /** Array initializer of ADC peripheral base addresses */
+ #define ADC_BASE_ADDRS { ADC0_BASE }
+ /** Array initializer of ADC peripheral base pointers */
+ #define ADC_BASE_PTRS { ADC0 }
+ /** Array initializer of ADC peripheral base addresses */
+ #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }
+ /** Array initializer of ADC peripheral base pointers */
+ #define ADC_BASE_PTRS_NS { ADC0_NS }
#else
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x400A0000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-/** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS \
- { \
- ADC0_BASE \
- }
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS \
- { \
- ADC0 \
- }
+ /** Peripheral ADC0 base address */
+ #define ADC0_BASE (0x400A0000u)
+ /** Peripheral ADC0 base pointer */
+ #define ADC0 ((ADC_Type *)ADC0_BASE)
+ /** Array initializer of ADC peripheral base addresses */
+ #define ADC_BASE_ADDRS { ADC0_BASE }
+ /** Array initializer of ADC peripheral base pointers */
+ #define ADC_BASE_PTRS { ADC0 }
#endif
/** Interrupt vectors for the ADC peripheral type */
-#define ADC_IRQS \
- { \
- ADC0_IRQn \
- }
+#define ADC_IRQS { ADC0_IRQn }
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- AHB_SECURE_CTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -1325,148 +1409,103 @@ typedef struct
*/
/** AHB_SECURE_CTRL - Register Layout Typedef */
-typedef struct
-{
- struct
- { /* offset: 0x0, array step: 0x30 */
- __IO uint32_t
- SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
- uint8_t RESERVED_0[12];
- __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash
- sector is 32 Kbytes. There are 20 FLASH sectors in total., array
- offset: 0x10, array step: index*0x30, index2*0x4 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM
- sector is 4 Kbytes. There are 32 ROM sectors in total., array offset:
- 0x20, array step: index*0x30, index2*0x4 */
- } SEC_CTRL_FLASH_ROM[1];
- struct
- { /* offset: 0x30, array step: 0x14 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step:
- index*0x14, index2*0x4 */
- } SEC_CTRL_RAMX[1];
- uint8_t RESERVED_0[12];
- struct
- { /* offset: 0x50, array step: 0x18 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step:
- index*0x18, index2*0x4 */
- } SEC_CTRL_RAM0[1];
- uint8_t RESERVED_1[8];
- struct
- { /* offset: 0x70, array step: 0x18 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step:
- index*0x18, index2*0x4 */
- } SEC_CTRL_RAM1[1];
- uint8_t RESERVED_2[8];
- struct
- { /* offset: 0x90, array step: 0x18 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step:
- index*0x18, index2*0x4 */
- } SEC_CTRL_RAM2[1];
- uint8_t RESERVED_3[8];
- struct
- { /* offset: 0xB0, array step: 0x18 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step:
- index*0x18, index2*0x4 */
- } SEC_CTRL_RAM3[1];
- uint8_t RESERVED_4[8];
- struct
- { /* offset: 0xD0, array step: 0x14 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step:
- index*0x14, index2*0x4 */
- } SEC_CTRL_RAM4[1];
- uint8_t RESERVED_5[12];
- struct
- { /* offset: 0xF0, array step: 0x30 */
- __IO uint32_t
- SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */
- uint8_t RESERVED_0[12];
- __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in
- total., array offset: 0x100, array step: 0x30 */
- __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in
- total., array offset: 0x104, array step: 0x30 */
- __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in
- total., array offset: 0x108, array step: 0x30 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in
- total., array offset: 0x110, array step: 0x30 */
- __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in
- total., array offset: 0x114, array step: 0x30 */
- __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in
- total., array offset: 0x118, array step: 0x30 */
- __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB
- bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in
- total., array offset: 0x11C, array step: 0x30 */
- } SEC_CTRL_APB_BRIDGE[1];
- __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */
- __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */
- uint8_t RESERVED_6[8];
- __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */
- __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */
- uint8_t RESERVED_7[8];
- struct
- { /* offset: 0x140, array step: 0x14 */
- __IO uint32_t
- SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */
- __IO uint32_t
- SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */
- uint8_t RESERVED_0[8];
- __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset:
- 0x150, array step: index*0x14, index2*0x4 */
- } SEC_CTRL_AHB_PORT10[1];
- uint8_t RESERVED_8[12];
- struct
- { /* offset: 0x160, array step: 0x14 */
- __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array
- step: 0x14 */
- uint8_t RESERVED_0[12];
- __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step:
- index*0x14, index2*0x4 */
- } SEC_CTRL_USB_HS[1];
- uint8_t RESERVED_9[3212];
- __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00,
- array step: 0x4 */
- uint8_t RESERVED_10[80];
- __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n,
- array offset: 0xE80, array step: 0x4 */
- uint8_t RESERVED_11[80];
- __IO uint32_t
- SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */
- uint8_t RESERVED_12[124];
- __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
- __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
- uint8_t RESERVED_13[8];
- __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */
- __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */
- uint8_t RESERVED_14[36];
- __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */
- uint8_t RESERVED_15[16];
- __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */
- __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */
- uint8_t RESERVED_16[20];
- __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
- __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */
- uint8_t RESERVED_17[4];
- __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */
- __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x30 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */
+ } SEC_CTRL_FLASH_ROM[1];
+ struct { /* offset: 0x30, array step: 0x14 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */
+ } SEC_CTRL_RAMX[1];
+ uint8_t RESERVED_0[12];
+ struct { /* offset: 0x50, array step: 0x18 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */
+ } SEC_CTRL_RAM0[1];
+ uint8_t RESERVED_1[8];
+ struct { /* offset: 0x70, array step: 0x18 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */
+ } SEC_CTRL_RAM1[1];
+ uint8_t RESERVED_2[8];
+ struct { /* offset: 0x90, array step: 0x18 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */
+ } SEC_CTRL_RAM2[1];
+ uint8_t RESERVED_3[8];
+ struct { /* offset: 0xB0, array step: 0x18 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */
+ } SEC_CTRL_RAM3[1];
+ uint8_t RESERVED_4[8];
+ struct { /* offset: 0xD0, array step: 0x14 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */
+ } SEC_CTRL_RAM4[1];
+ uint8_t RESERVED_5[12];
+ struct { /* offset: 0xF0, array step: 0x30 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */
+ } SEC_CTRL_APB_BRIDGE[1];
+ __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */
+ __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */
+ uint8_t RESERVED_6[8];
+ __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */
+ __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */
+ uint8_t RESERVED_7[8];
+ struct { /* offset: 0x140, array step: 0x14 */
+ __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */
+ __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */
+ } SEC_CTRL_AHB_PORT10[1];
+ uint8_t RESERVED_8[12];
+ struct { /* offset: 0x160, array step: 0x14 */
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */
+ } SEC_CTRL_USB_HS[1];
+ uint8_t RESERVED_9[3212];
+ __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */
+ uint8_t RESERVED_10[80];
+ __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */
+ uint8_t RESERVED_11[80];
+ __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */
+ uint8_t RESERVED_12[124];
+ __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */
+ __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */
+ uint8_t RESERVED_13[8];
+ __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */
+ __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */
+ uint8_t RESERVED_14[36];
+ __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */
+ uint8_t RESERVED_15[16];
+ __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */
+ __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */
+ uint8_t RESERVED_16[20];
+ __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */
+ __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */
+ uint8_t RESERVED_17[4];
+ __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */
+ __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */
} AHB_SECURE_CTRL_Type;
/* ----------------------------------------------------------------------------
@@ -1480,6 +1519,7 @@ typedef struct
/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)
/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF
@@ -1488,9 +1528,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)
/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF
@@ -1499,17 +1538,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)
-/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32
- * Kbytes. There are 20 FLASH sectors in total. */
+/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -1518,9 +1555,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -1529,9 +1565,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -1540,9 +1575,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -1551,9 +1585,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -1562,9 +1595,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -1573,9 +1605,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -1584,9 +1615,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -1595,9 +1625,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
@@ -1606,9 +1634,9 @@ typedef struct
/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */
#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U)
-/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes.
- * There are 32 ROM sectors in total. */
+/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -1617,9 +1645,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -1628,9 +1655,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -1639,9 +1665,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -1650,9 +1675,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -1661,9 +1685,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -1672,9 +1695,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -1683,9 +1705,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -1694,9 +1715,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */
@@ -1707,6 +1726,7 @@ typedef struct
/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)
/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF
@@ -1715,9 +1735,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */
@@ -1725,6 +1743,7 @@ typedef struct
/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -1733,9 +1752,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -1744,9 +1762,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -1755,9 +1772,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -1766,9 +1782,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -1777,9 +1792,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -1788,9 +1802,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -1799,9 +1812,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -1810,9 +1822,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */
@@ -1823,6 +1833,7 @@ typedef struct
/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)
/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF
@@ -1831,9 +1842,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */
@@ -1841,6 +1850,7 @@ typedef struct
/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -1849,9 +1859,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -1860,9 +1869,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -1871,9 +1879,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -1882,9 +1889,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -1893,9 +1899,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -1904,9 +1909,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -1915,9 +1919,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -1926,9 +1929,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */
@@ -1939,6 +1940,7 @@ typedef struct
/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U)
/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0
@@ -1947,9 +1949,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */
@@ -1957,6 +1957,7 @@ typedef struct
/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -1965,9 +1966,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -1976,9 +1976,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -1987,9 +1986,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -1998,9 +1996,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -2009,9 +2006,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -2020,9 +2016,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -2031,9 +2026,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -2042,9 +2036,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */
@@ -2055,6 +2047,7 @@ typedef struct
/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)
/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF
@@ -2063,9 +2056,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */
@@ -2073,6 +2064,7 @@ typedef struct
/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -2081,9 +2073,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -2092,9 +2083,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -2103,9 +2093,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -2114,9 +2103,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -2125,9 +2113,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -2136,9 +2123,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -2147,9 +2133,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -2158,9 +2143,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */
@@ -2171,6 +2154,7 @@ typedef struct
/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U)
/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF
@@ -2179,9 +2163,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */
@@ -2189,6 +2171,7 @@ typedef struct
/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -2197,9 +2180,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -2208,9 +2190,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -2219,9 +2200,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -2230,9 +2210,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U)
/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'
@@ -2241,9 +2220,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U)
/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'
@@ -2252,9 +2230,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U)
/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'
@@ -2263,9 +2240,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U)
/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'
@@ -2274,9 +2250,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */
@@ -2287,6 +2261,7 @@ typedef struct
/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U)
/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF
@@ -2295,9 +2270,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */
@@ -2305,6 +2278,7 @@ typedef struct
/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U)
/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'
@@ -2313,9 +2287,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U)
/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'
@@ -2324,9 +2297,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U)
/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'
@@ -2335,9 +2307,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U)
/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'
@@ -2346,9 +2317,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */
@@ -2359,6 +2328,7 @@ typedef struct
/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)
/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0
@@ -2367,9 +2337,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)
/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1
@@ -2378,17 +2347,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)
/*! SYSCON_RULE - System Configuration
@@ -2397,9 +2364,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)
/*! IOCON_RULE - I/O Configuration
@@ -2408,9 +2374,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)
/*! GINT0_RULE - GPIO input Interrupt 0
@@ -2419,9 +2384,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)
/*! GINT1_RULE - GPIO input Interrupt 1
@@ -2430,9 +2394,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)
/*! PINT_RULE - Pin Interrupt and Pattern match
@@ -2441,9 +2404,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)
/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match
@@ -2452,9 +2414,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U)
/*! INPUTMUX_RULE - Peripheral input multiplexing
@@ -2463,17 +2424,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)
/*! CTIMER0_RULE - Standard counter/Timer 0
@@ -2482,9 +2441,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)
/*! CTIMER1_RULE - Standard counter/Timer 1
@@ -2493,9 +2451,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)
/*! WWDT_RULE - Windiwed wtachdog Timer
@@ -2504,9 +2461,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)
/*! MRT_RULE - Multi-rate Timer
@@ -2515,9 +2471,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)
/*! UTICK_RULE - Micro-Timer
@@ -2526,17 +2481,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)
/*! ANACTRL_RULE - Analog Modules controller
@@ -2545,17 +2498,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)
/*! PMC_RULE - Power Management Controller
@@ -2564,9 +2515,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)
/*! SYSCTRL_RULE - System Controller
@@ -2575,17 +2525,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)
/*! CTIMER2_RULE - Standard counter/Timer 2
@@ -2594,9 +2542,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)
/*! CTIMER3_RULE - Standard counter/Timer 3
@@ -2605,9 +2552,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)
/*! CTIMER4_RULE - Standard counter/Timer 4
@@ -2616,9 +2562,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)
/*! RTC_RULE - Real Time Counter
@@ -2627,9 +2572,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)
/*! OSEVENT_RULE - OS Event Timer
@@ -2638,17 +2582,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)
/*! FLASH_CTRL_RULE - Flash Controller
@@ -2657,9 +2599,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)
/*! PRINCE_RULE - Prince
@@ -2668,17 +2609,15 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)
-/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is
- * 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
+/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)
/*! USBHPHY_RULE - USB High Speed Phy controller
@@ -2687,9 +2626,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)
/*! RNG_RULE - True Random Number Generator
@@ -2698,9 +2636,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U)
/*! PUF_RULE - PUF
@@ -2709,9 +2646,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)
/*! PLU_RULE - Programmable Look-Up logic
@@ -2720,9 +2656,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */
@@ -2730,6 +2664,7 @@ typedef struct
/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U)
/*! DMA0_RULE - DMA Controller
@@ -2738,9 +2673,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U)
/*! FS_USB_DEV_RULE - USB Full-speed device
@@ -2749,9 +2683,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U)
/*! SCT_RULE - SCTimer
@@ -2760,9 +2693,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U)
/*! FLEXCOMM0_RULE - Flexcomm interface 0
@@ -2771,9 +2703,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U)
/*! FLEXCOMM1_RULE - Flexcomm interface 1
@@ -2782,13 +2713,12 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK)
/*! @} */
/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U)
/*! FLEXCOMM2_RULE - Flexcomm interface 2
@@ -2797,9 +2727,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U)
/*! FLEXCOMM3_RULE - Flexcomm interface 3
@@ -2808,9 +2737,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U)
/*! FLEXCOMM4_RULE - Flexcomm interface 4
@@ -2819,9 +2747,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U)
/*! MAILBOX_RULE - Inter CPU communication Mailbox
@@ -2830,9 +2757,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U)
/*! GPIO0_RULE - High Speed GPIO
@@ -2841,13 +2767,12 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK)
/*! @} */
/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U)
/*! USB_HS_DEV_RULE - USB high Speed device registers
@@ -2856,9 +2781,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U)
/*! CRC_RULE - CRC engine
@@ -2867,9 +2791,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U)
/*! FLEXCOMM5_RULE - Flexcomm interface 5
@@ -2878,9 +2801,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U)
/*! FLEXCOMM6_RULE - Flexcomm interface 6
@@ -2889,13 +2811,12 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK)
/*! @} */
/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U)
/*! FLEXCOMM7_RULE - Flexcomm interface 7
@@ -2904,9 +2825,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U)
/*! SDIO_RULE - SDMMC card interface
@@ -2915,9 +2835,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U)
/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)
@@ -2926,9 +2845,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U)
/*! HS_LSPI_RULE - High Speed SPI
@@ -2937,13 +2855,12 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK)
/*! @} */
/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U)
/*! ADC_RULE - ADC
@@ -2952,9 +2869,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U)
/*! USB_FS_HOST_RULE - USB Full Speed Host registers.
@@ -2963,9 +2879,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U)
/*! USB_HS_HOST_RULE - USB High speed host registers
@@ -2974,9 +2889,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U)
/*! HASH_RULE - SHA-2 crypto registers
@@ -2985,9 +2899,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U)
/*! CASPER_RULE - RSA/ECC crypto accelerator
@@ -2996,9 +2909,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U)
/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator)
@@ -3007,9 +2919,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U)
/*! DMA1_RULE - DMA Controller (Secure)
@@ -3018,9 +2929,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */
@@ -3028,6 +2937,7 @@ typedef struct
/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U)
/*! GPIO1_RULE - Secure High Speed GPIO
@@ -3036,9 +2946,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)
/*! AHB_SEC_CTRL_RULE - AHB Secure Controller
@@ -3047,9 +2956,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */
@@ -3057,6 +2964,7 @@ typedef struct
/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)
/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF
@@ -3065,9 +2973,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)
/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF
@@ -3076,9 +2983,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)
/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF
@@ -3087,9 +2993,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)
/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF
@@ -3098,9 +3003,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */
@@ -3111,6 +3014,7 @@ typedef struct
/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)
/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF
@@ -3119,9 +3023,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */
@@ -3129,6 +3031,7 @@ typedef struct
/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)
/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF
@@ -3137,9 +3040,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)
/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF
@@ -3148,9 +3050,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)
/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF
@@ -3159,9 +3060,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK)
+
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)
#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)
/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF
@@ -3170,9 +3070,7 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */
@@ -3183,46 +3081,42 @@ typedef struct
/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)
#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)
/*! SEC_VIO_ADDR - security violation address for AHB port
*/
-#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */
-#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U)
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U)
/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)
/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator.
* 0b0..Read access.
* 0b1..Write access.
*/
-#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)
/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator.
* 0b0..Code access.
* 0b1..Data access.
*/
-#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)
-/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master
- * sec level and privilege level
+/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level
*/
-#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)
#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)
/*! SEC_VIO_INFO_MASTER - security violation master number
@@ -3238,1300 +3132,1159 @@ typedef struct
* 0b1011..USB-FS Host.
* 0b1100..SDMA1.
*/
-#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)
/*! @} */
/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */
-#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U)
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U)
/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)
/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)
/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)
/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)
/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)
/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)
/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)
/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)
/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)
/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)
/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)
/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)
+
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)
#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)
/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear.
* 0b0..Not valid.
* 0b1..Valid (violation occurred).
*/
-#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)
/*! @} */
/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)
/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)
/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)
/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)
/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)
/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)
/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)
/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)
/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)
/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)
/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)
/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)
/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)
/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)
/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)
/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)
/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)
/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)
/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)
/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)
/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)
/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)
/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)
/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)
/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)
/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)
/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)
/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)
/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)
/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)
/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)
/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)
/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)
/*! @} */
/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)
/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)
/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)
/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)
/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)
/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)
/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)
/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)
/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)
/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)
/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)
/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)
/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)
/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)
/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)
/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)
/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)
/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)
/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)
/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)
/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)
/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)
/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)
/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)
/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)
/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)
/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)
/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)
/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)
/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)
/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)
/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)
+
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)
#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)
/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31
* 0b1..Pin state is readable by non-secure world.
* 0b0..Pin state is blocked to non-secure world.
*/
-#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)
/*! @} */
/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)
/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)
/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)
/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)
/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)
/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)
/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)
/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)
/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)
/*! UTICK_IRQ - Micro Tick Timer interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)
/*! MRT_IRQ - Multi-Rate Timer interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)
/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)
/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)
/*! SCT_IRQ - SCTimer/PWM interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)
/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)
/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)
/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)
/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)
/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)
/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)
/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)
/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)
/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)
/*! ADC_IRQ - General Purpose ADC interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)
/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U)
/*! ACMP_IRQ - Analog Comparator interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)
/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)
/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)
/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)
/*! USB0_IRQ - USB Full Speed Controller interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)
/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U)
/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)
/*! MAILBOX_IRQ - Mailbox interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)
/*! @} */
/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)
/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)
/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)
/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)
/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)
/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)
/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)
/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)
/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)
/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)
/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)
/*! SDIO_IRQ - SDIO Controller interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)
/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)
/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)
/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U)
/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)
/*! USB1_IRQ - USB High Speed Controller interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)
/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)
/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)
/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)
/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)
/*! PLU_IRQ - Programmable Look-Up Controller interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)
/*! SEC_VIO_IRQ - Security Violation interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)
/*! SHA_IRQ - HASH-AES interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)
/*! CASPER_IRQ - CASPER interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U)
/*! PUFKEY_IRQ - PUF interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)
/*! PQ_IRQ - Power Quad interrupt.
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)
/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)
+
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)
#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)
/*! LSPI_HS_IRQ - High Speed SPI interrupt
* 0b0..
* 0b1..
*/
-#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)
/*! @} */
/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */
/*! @{ */
+
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)
/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)
+
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)
/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)
+
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U)
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U)
/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)
+
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U)
#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U)
/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)
/*! @} */
/*! @name MASTER_SEC_LEVEL - master secure level register */
/*! @{ */
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U)
/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus.
@@ -4540,9 +4293,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U)
/*! CPU1S - Micro-Cortex M33 (CPU1) System bus.
@@ -4551,9 +4303,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)
/*! USBFSD - USB Full Speed Device.
@@ -4562,9 +4313,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)
/*! SDMA0 - System DMA 0.
@@ -4573,9 +4323,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)
/*! SDIO - SDIO.
@@ -4584,9 +4333,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U)
/*! PQ - Power Quad.
@@ -4595,9 +4343,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)
/*! HASH - Hash.
@@ -4606,9 +4353,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)
/*! USBFSH - USB Full speed Host.
@@ -4617,9 +4363,8 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)
/*! SDMA1 - System DMA 1 security level.
@@ -4628,22 +4373,20 @@ typedef struct
* 0b10..Secure and Non-priviledge user access allowed.
* 0b11..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)
#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)
/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)
/*! @} */
/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */
/*! @{ */
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U)
/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C)
@@ -4652,9 +4395,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U)
/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S)
@@ -4663,9 +4405,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)
/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD)
@@ -4674,9 +4415,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)
/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0)
@@ -4685,9 +4425,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U)
/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO)
@@ -4696,9 +4435,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U)
/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ)
@@ -4707,9 +4445,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)
/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH)
@@ -4718,9 +4455,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)
/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH)
@@ -4729,9 +4465,8 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)
/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1)
@@ -4740,316 +4475,273 @@ typedef struct
* 0b01..Secure and Non-priviledge user access allowed.
* 0b00..Secure and Priviledge user access allowed.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)
+
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)
#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)
/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)
/*! @} */
/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */
/*! @{ */
+
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & \
- AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
+#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK)
+
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & \
- AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
+#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK)
+
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)
/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & \
- AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
+#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK)
+
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U)
/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & \
- AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
+#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK)
+
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U)
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U)
/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & \
- AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
+#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK)
+
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U)
#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U)
/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
+#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK)
/*! @} */
/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */
/*! @{ */
+
#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)
#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)
/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & \
- AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
+#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK)
+
#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)
#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)
/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & \
- AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
+#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK)
+
#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U)
#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U)
/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock.
* 0b10..Writable.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK)
+#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK)
/*! @} */
/*! @name MISC_CTRL_DP_REG - secure control duplicate register */
/*! @{ */
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)
/*! WRITE_LOCK - Write lock.
* 0b10..Secure control registers can be written.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
* 0b10..Disable check.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
* 0b10..Disable check.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
* 0b10..Disable check.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
* 0b10..Enable abort fort secure checker.
* 0b01..Disable abort fort secure checker.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
* 0b10..Simple master in strict mode.
* 0b01..Simple master in tier mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
* 0b10..Smart master in strict mode.
* 0b01..Smart master in tier mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)
#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)
/*! IDAU_ALL_NS - Disable IDAU.
* 0b10..IDAU is enabled.
* 0b01..IDAU is disable.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)
/*! @} */
/*! @name MISC_CTRL_REG - secure control register */
/*! @{ */
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)
/*! WRITE_LOCK - Write lock.
* 0b10..Secure control registers can be written.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)
/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix.
* 0b10..Disable check.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)
/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix.
* 0b10..Disable check.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)
/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix.
* 0b10..Disable check.
* 0b01..Restricted mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)
/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort.
* 0b10..Enable abort fort secure checker.
* 0b01..Disable abort fort secure checker.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)
/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode.
* 0b10..Simple master in strict mode.
* 0b01..Simple master in tier mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)
/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode.
* 0b10..Smart master in strict mode.
* 0b01..Smart master in tier mode.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)
+
#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)
#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)
/*! IDAU_ALL_NS - Disable IDAU.
* 0b10..IDAU is enabled.
* 0b01..IDAU is disable.
*/
-#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) \
- (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & \
- AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group AHB_SECURE_CTRL_Register_Masks */
+
/* AHB_SECURE_CTRL - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral AHB_SECURE_CTRL base address */
-#define AHB_SECURE_CTRL_BASE (0x500AC000u)
-/** Peripheral AHB_SECURE_CTRL base address */
-#define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)
-/** Peripheral AHB_SECURE_CTRL base pointer */
-#define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
-/** Peripheral AHB_SECURE_CTRL base pointer */
-#define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
-/** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
-#define AHB_SECURE_CTRL_BASE_ADDRS \
- { \
- AHB_SECURE_CTRL_BASE \
- }
-/** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
-#define AHB_SECURE_CTRL_BASE_PTRS \
- { \
- AHB_SECURE_CTRL \
- }
-/** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
-#define AHB_SECURE_CTRL_BASE_ADDRS_NS \
- { \
- AHB_SECURE_CTRL_BASE_NS \
- }
-/** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
-#define AHB_SECURE_CTRL_BASE_PTRS_NS \
- { \
- AHB_SECURE_CTRL_NS \
- }
+ /** Peripheral AHB_SECURE_CTRL base address */
+ #define AHB_SECURE_CTRL_BASE (0x500AC000u)
+ /** Peripheral AHB_SECURE_CTRL base address */
+ #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)
+ /** Peripheral AHB_SECURE_CTRL base pointer */
+ #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
+ /** Peripheral AHB_SECURE_CTRL base pointer */
+ #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+ #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+ #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+ #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+ #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }
#else
-/** Peripheral AHB_SECURE_CTRL base address */
-#define AHB_SECURE_CTRL_BASE (0x400AC000u)
-/** Peripheral AHB_SECURE_CTRL base pointer */
-#define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
-/** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
-#define AHB_SECURE_CTRL_BASE_ADDRS \
- { \
- AHB_SECURE_CTRL_BASE \
- }
-/** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
-#define AHB_SECURE_CTRL_BASE_PTRS \
- { \
- AHB_SECURE_CTRL \
- }
+ /** Peripheral AHB_SECURE_CTRL base address */
+ #define AHB_SECURE_CTRL_BASE (0x400AC000u)
+ /** Peripheral AHB_SECURE_CTRL base pointer */
+ #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */
+ #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */
+ #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }
#endif
/*!
* @}
*/ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- ANACTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -5060,27 +4752,25 @@ typedef struct
*/
/** ANACTRL - Register Layout Typedef */
-typedef struct
-{
- uint8_t RESERVED_0[4];
- __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
- uint8_t RESERVED_1[4];
- __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */
- __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
- __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
- uint8_t RESERVED_2[8];
- __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */
- __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */
- uint8_t RESERVED_3[8];
- __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register,
- offset: 0x30 */
- __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */
- uint8_t RESERVED_4[8];
- __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */
- __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */
- __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */
- uint8_t RESERVED_5[180];
- __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */
+typedef struct {
+ uint8_t RESERVED_0[4];
+ __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */
+ __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */
+ __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */
+ __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */
+ uint8_t RESERVED_3[8];
+ __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */
+ __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */
+ uint8_t RESERVED_4[8];
+ __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */
+ __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */
+ __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */
+ uint8_t RESERVED_5[180];
+ __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */
} ANACTRL_Type;
/* ----------------------------------------------------------------------------
@@ -5094,664 +4784,622 @@ typedef struct
/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */
/*! @{ */
+
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)
/*! FLASH_PWRDWN - Flash Power Down status.
* 0b0..Flash is not in power down mode.
* 0b1..Flash is in power down mode.
*/
-#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & \
- ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)
+
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)
#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)
/*! FLASH_INIT_ERROR - Flash initialization error status.
* 0b0..No error.
* 0b1..At least one error occured during flash initialization..
*/
-#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & \
- ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)
/*! @} */
/*! @name FREQ_ME_CTRL - Frequency Measure function control register */
/*! @{ */
-#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)
-#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)
+
+#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)
+#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)
/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale
*/
-#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
-#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)
-#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)
+#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)
+
+#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)
+#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)
/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit
* when the measurement cycle has completed and there is valid capture data in the CAPVAL field
* (bits 30:0).
*/
-#define ANACTRL_FREQ_ME_CTRL_PROG(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
+#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)
/*! @} */
/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */
/*! @{ */
-#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)
-#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)
+
+#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)
+#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)
/*! ENA_12MHZCLK - 12 MHz clock control.
* 0b0..12 MHz clock is disabled.
* 0b1..12 MHz clock is enabled.
*/
-#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
-#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U)
-#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U)
+#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)
+
+#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U)
+#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U)
/*! ENA_48MHZCLK - 48 MHz clock control.
* 0b0..Reserved.
* 0b1..48 MHz clock is enabled.
*/
-#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)
-#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)
-#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)
+#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)
+
+#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)
+#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)
/*! DAC_TRIM - Frequency trim.
*/
-#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
-#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)
-#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)
+#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)
+
+#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)
+#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)
/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode,
* the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF
* packets.
*/
-#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)
-#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U)
-#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U)
+#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)
+
+#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U)
+#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U)
/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0.
*/
-#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)
-#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U)
-#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U)
+#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)
+
+#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U)
+#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U)
/*! ENA_96MHZCLK - 96 MHz clock control.
* 0b0..96 MHz clock is disabled.
* 0b1..96 MHz clock is enabled.
*/
-#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)
+#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)
/*! @} */
/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */
/*! @{ */
-#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U)
-#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U)
+
+#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U)
+#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U)
/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled.
* 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).
* 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by
* FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).
*/
-#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)
-#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U)
-#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U)
+#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)
+
+#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U)
+#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U)
/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses
* the threshold voltage of a SLVT transistor, this output signal will go high. It is also
* possible to observe the clk_valid signal.
*/
-#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
+#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)
/*! @} */
/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */
/*! @{ */
+
#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)
#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)
/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.
* 0b0..XO AC buffer bypass is disabled.
* 0b1..XO AC buffer bypass is enabled.
*/
-#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & \
- ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)
+#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)
+
#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U)
#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U)
/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL.
* 0b0..High speed Crystal oscillator output to USB HS PLL is disabled.
* 0b1..High speed Crystal oscillator output to USB HS PLL is enabled.
*/
-#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & \
- ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)
+#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)
+
#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)
#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)
/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system.
* 0b0..High speed Crystal oscillator output to CPU system is disabled.
* 0b1..High speed Crystal oscillator output to CPU system is enabled.
*/
-#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & \
- ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
+#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)
/*! @} */
/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */
/*! @{ */
-#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U)
-#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U)
+
+#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U)
+#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U)
/*! XO_READY - Indicates XO out frequency statibilty.
* 0b0..XO output frequency is not yet stable.
* 0b1..XO output frequency is stable.
*/
-#define ANACTRL_XO32M_STATUS_XO_READY(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
+#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)
/*! @} */
/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */
/*! @{ */
+
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U)
/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control.
* 0b0..BOD VBAT interrupt is disabled.
* 0b1..BOD VBAT interrupt is enabled.
*/
-#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)
+
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U)
/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.
*/
-#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)
+
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)
/*! BODCORE_INT_ENABLE - BOD CORE interrupt control.
* 0b0..BOD CORE interrupt is disabled.
* 0b1..BOD CORE interrupt is enabled.
*/
-#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)
+
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)
#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)
/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.
*/
-#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)
+
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)
/*! DCDC_INT_ENABLE - DCDC interrupt control.
* 0b0..DCDC interrupt is disabled.
* 0b1..DCDC interrupt is enabled.
*/
-#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)
+
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)
#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)
/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.
*/
-#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)
/*! @} */
/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */
/*! @{ */
+
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U)
/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable.
* 0b0..No interrupt pending..
* 0b1..Interrupt pending..
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U)
/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable.
* 0b0..No interrupt pending..
* 0b1..Interrupt pending..
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U)
/*! BODVBAT_VAL - Current value of BOD VBAT power status output.
* 0b0..VBAT voltage level is below the threshold.
* 0b1..VBAT voltage level is above the threshold.
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)
/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.
* 0b0..No interrupt pending..
* 0b1..Interrupt pending..
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)
/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.
* 0b0..No interrupt pending..
* 0b1..Interrupt pending..
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)
#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)
/*! BODCORE_VAL - Current value of BOD CORE power status output.
* 0b0..CORE voltage level is below the threshold.
* 0b1..CORE voltage level is above the threshold.
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)
/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.
* 0b0..No interrupt pending..
* 0b1..Interrupt pending..
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)
/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.
* 0b0..No interrupt pending..
* 0b1..Interrupt pending..
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)
+
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)
#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)
/*! DCDC_VAL - Current value of DCDC power status output.
* 0b0..DCDC output Voltage is below the targeted regulation level.
* 0b1..DCDC output Voltage is above the targeted regulation level.
*/
-#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & \
- ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)
/*! @} */
/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */
/*! @{ */
-#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U)
-#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U)
+
+#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U)
+#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U)
/*! SL - Select short or long ringo (for all ringos types).
* 0b0..Select short ringo (few elements).
* 0b1..Select long ringo (many elements).
*/
-#define ANACTRL_RINGO0_CTRL_SL(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK)
-#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U)
-#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U)
+#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK)
+
+#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U)
+#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U)
/*! FS - Ringo frequency output divider.
* 0b0..High frequency output (frequency lower than 100 MHz).
* 0b1..Low frequency output (frequency lower than 10 MHz).
*/
-#define ANACTRL_RINGO0_CTRL_FS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK)
-#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU)
-#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U)
+#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK)
+
+#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU)
+#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U)
/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control.
* 0b00..Normal mode.
* 0b01..P-Monitor mode. Measure with weak P transistor.
* 0b10..P-Monitor mode. Measure with weak N transistor.
* 0b11..Don't use.
*/
-#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK)
-#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U)
-#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U)
+#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK)
+
+#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U)
+#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U)
/*! PD - Ringo module Power control.
* 0b0..The Ringo module is enabled.
* 0b1..The Ringo module is disabled.
*/
-#define ANACTRL_RINGO0_CTRL_PD(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK)
-#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U)
-#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U)
+#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U)
+#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U)
/*! E_ND0 - First NAND2-based ringo control.
* 0b0..First NAND2-based ringo is disabled.
* 0b1..First NAND2-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_ND0(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK)
-#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U)
-#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U)
+#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U)
+#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U)
/*! E_ND1 - Second NAND2-based ringo control.
* 0b0..Second NAND2-based ringo is disabled.
* 0b1..Second NAND2-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_ND1(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK)
-#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U)
-#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U)
+#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U)
+#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U)
/*! E_NR0 - First NOR2-based ringo control.
* 0b0..First NOR2-based ringo is disabled.
* 0b1..First NOR2-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_NR0(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK)
-#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U)
-#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U)
+#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U)
+#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U)
/*! E_NR1 - Second NOR2-based ringo control.
* 0b0..Second NORD2-based ringo is disabled.
* 0b1..Second NORD2-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_NR1(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK)
-#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U)
-#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U)
+#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U)
+#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U)
/*! E_IV0 - First Inverter-based ringo control.
* 0b0..First INV-based ringo is disabled.
* 0b1..First INV-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_IV0(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK)
-#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U)
-#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U)
+#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U)
+#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U)
/*! E_IV1 - Second Inverter-based ringo control.
* 0b0..Second INV-based ringo is disabled.
* 0b1..Second INV-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_IV1(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK)
-#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U)
-#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U)
+#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U)
+#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U)
/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control.
* 0b0..First PN-based ringo is disabled.
* 0b1..First PN-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_PN0(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK)
-#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U)
-#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U)
+#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK)
+
+#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U)
+#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U)
/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control.
* 0b0..Second PN-based ringo is disabled.
* 0b1..Second PN-based ringo is enabled.
*/
-#define ANACTRL_RINGO0_CTRL_E_PN1(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK)
-#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U)
-#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U)
-/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency
- * input / 16)
+#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK)
+
+#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U)
+#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U)
+/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
*/
-#define ANACTRL_RINGO0_CTRL_DIVISOR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK)
-#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
+#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK)
+
+#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
* value, cleared when the change is complete.
*/
-#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & \
- ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK)
+#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK)
/*! @} */
/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */
/*! @{ */
-#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U)
-#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U)
+
+#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U)
+#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U)
/*! S - Select short or long ringo (for all ringos types).
* 0b0..Select short ringo (few elements).
* 0b1..Select long ringo (many elements).
*/
-#define ANACTRL_RINGO1_CTRL_S(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK)
-#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U)
-#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U)
+#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK)
+
+#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U)
+#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U)
/*! FS - Ringo frequency output divider.
* 0b0..High frequency output (frequency lower than 100 MHz).
* 0b1..Low frequency output (frequency lower than 10 MHz).
*/
-#define ANACTRL_RINGO1_CTRL_FS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK)
-#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U)
-#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U)
+#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK)
+
+#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U)
+#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U)
/*! PD - Ringo module Power control.
* 0b0..The Ringo module is enabled.
* 0b1..The Ringo module is disabled.
*/
-#define ANACTRL_RINGO1_CTRL_PD(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK)
-#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U)
-#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U)
+#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK)
+
+#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U)
+#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U)
/*! E_R24 - .
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO1_CTRL_E_R24(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK)
-#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U)
-#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U)
+#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK)
+
+#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U)
+#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U)
/*! E_R35 - .
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO1_CTRL_E_R35(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK)
-#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U)
-#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U)
+#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK)
+
+#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U)
+#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U)
/*! E_M2 - Metal 2 (M2) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO1_CTRL_E_M2(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK)
-#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U)
-#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U)
+#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK)
+
+#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U)
+#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U)
/*! E_M3 - Metal 3 (M3) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO1_CTRL_E_M3(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK)
-#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U)
-#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U)
+#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK)
+
+#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U)
+#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U)
/*! E_M4 - Metal 4 (M4) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO1_CTRL_E_M4(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK)
-#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U)
-#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U)
+#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK)
+
+#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U)
+#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U)
/*! E_M5 - Metal 5 (M5) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO1_CTRL_E_M5(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK)
-#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U)
-#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U)
-/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency
- * input / 16)
+#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK)
+
+#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U)
+#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U)
+/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
*/
-#define ANACTRL_RINGO1_CTRL_DIVISOR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK)
-#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
+#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK)
+
+#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
* value, cleared when the change is complete.
*/
-#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & \
- ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK)
+#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK)
/*! @} */
/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */
/*! @{ */
-#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U)
-#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U)
+
+#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U)
+#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U)
/*! S - Select short or long ringo (for all ringos types).
* 0b0..Select short ringo (few elements).
* 0b1..Select long ringo (many elements).
*/
-#define ANACTRL_RINGO2_CTRL_S(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK)
-#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U)
-#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U)
+#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK)
+
+#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U)
+#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U)
/*! FS - Ringo frequency output divider.
* 0b0..High frequency output (frequency lower than 100 MHz).
* 0b1..Low frequency output (frequency lower than 10 MHz).
*/
-#define ANACTRL_RINGO2_CTRL_FS(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK)
-#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U)
-#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U)
+#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK)
+
+#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U)
+#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U)
/*! PD - Ringo module Power control.
* 0b0..The Ringo module is enabled.
* 0b1..The Ringo module is disabled.
*/
-#define ANACTRL_RINGO2_CTRL_PD(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK)
-#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U)
-#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U)
+#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK)
+
+#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U)
+#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U)
/*! E_R24 - .
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO2_CTRL_E_R24(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK)
-#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U)
-#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U)
+#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK)
+
+#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U)
+#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U)
/*! E_R35 - .
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO2_CTRL_E_R35(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK)
-#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U)
-#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U)
+#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK)
+
+#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U)
+#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U)
/*! E_M2 - Metal 2 (M2) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO2_CTRL_E_M2(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK)
-#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U)
-#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U)
+#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK)
+
+#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U)
+#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U)
/*! E_M3 - Metal 3 (M3) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO2_CTRL_E_M3(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK)
-#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U)
-#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U)
+#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK)
+
+#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U)
+#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U)
/*! E_M4 - Metal 4 (M4) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO2_CTRL_E_M4(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK)
-#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U)
-#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U)
+#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK)
+
+#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U)
+#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U)
/*! E_M5 - Metal 5 (M5) monitor control.
* 0b0..Ringo is disabled.
* 0b1..Ringo is enabled.
*/
-#define ANACTRL_RINGO2_CTRL_E_M5(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK)
-#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U)
-#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U)
-/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency
- * input / 16)
+#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK)
+
+#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U)
+#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U)
+/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)
*/
-#define ANACTRL_RINGO2_CTRL_DIVISOR(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK)
-#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
+#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK)
+
+#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)
#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U)
/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider
* value, cleared when the change is complete.
*/
-#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & \
- ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)
+#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)
/*! @} */
/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */
/*! @{ */
+
#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U)
#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U)
/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors.
*/
-#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & \
- ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK)
-#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U)
-#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U)
+#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK)
+
+#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U)
+#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U)
/*! usb_id_ext - Override value for ID if using external detectors.
*/
-#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) \
- (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)
+#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group ANACTRL_Register_Masks */
+
/* ANACTRL - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral ANACTRL base address */
-#define ANACTRL_BASE (0x50013000u)
-/** Peripheral ANACTRL base address */
-#define ANACTRL_BASE_NS (0x40013000u)
-/** Peripheral ANACTRL base pointer */
-#define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
-/** Peripheral ANACTRL base pointer */
-#define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS)
-/** Array initializer of ANACTRL peripheral base addresses */
-#define ANACTRL_BASE_ADDRS \
- { \
- ANACTRL_BASE \
- }
-/** Array initializer of ANACTRL peripheral base pointers */
-#define ANACTRL_BASE_PTRS \
- { \
- ANACTRL \
- }
-/** Array initializer of ANACTRL peripheral base addresses */
-#define ANACTRL_BASE_ADDRS_NS \
- { \
- ANACTRL_BASE_NS \
- }
-/** Array initializer of ANACTRL peripheral base pointers */
-#define ANACTRL_BASE_PTRS_NS \
- { \
- ANACTRL_NS \
- }
+ /** Peripheral ANACTRL base address */
+ #define ANACTRL_BASE (0x50013000u)
+ /** Peripheral ANACTRL base address */
+ #define ANACTRL_BASE_NS (0x40013000u)
+ /** Peripheral ANACTRL base pointer */
+ #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
+ /** Peripheral ANACTRL base pointer */
+ #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS)
+ /** Array initializer of ANACTRL peripheral base addresses */
+ #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
+ /** Array initializer of ANACTRL peripheral base pointers */
+ #define ANACTRL_BASE_PTRS { ANACTRL }
+ /** Array initializer of ANACTRL peripheral base addresses */
+ #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS }
+ /** Array initializer of ANACTRL peripheral base pointers */
+ #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS }
#else
-/** Peripheral ANACTRL base address */
-#define ANACTRL_BASE (0x40013000u)
-/** Peripheral ANACTRL base pointer */
-#define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
-/** Array initializer of ANACTRL peripheral base addresses */
-#define ANACTRL_BASE_ADDRS \
- { \
- ANACTRL_BASE \
- }
-/** Array initializer of ANACTRL peripheral base pointers */
-#define ANACTRL_BASE_PTRS \
- { \
- ANACTRL \
- }
+ /** Peripheral ANACTRL base address */
+ #define ANACTRL_BASE (0x40013000u)
+ /** Peripheral ANACTRL base pointer */
+ #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)
+ /** Array initializer of ANACTRL peripheral base addresses */
+ #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }
+ /** Array initializer of ANACTRL peripheral base pointers */
+ #define ANACTRL_BASE_PTRS { ANACTRL }
#endif
/*!
* @}
*/ /* end of group ANACTRL_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- CASPER Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -5762,32 +5410,28 @@ typedef struct
*/
/** CASPER - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */
- __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches
- the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR.,
- offset: 0x4 */
- __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of
- operations., offset: 0x8 */
- __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */
- __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */
- __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */
- __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */
- uint8_t RESERVED_0[4];
- __IO uint32_t AREG; /**< A register, offset: 0x20 */
- __IO uint32_t BREG; /**< B register, offset: 0x24 */
- __IO uint32_t CREG; /**< C register, offset: 0x28 */
- __IO uint32_t DREG; /**< D register, offset: 0x2C */
- __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */
- __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */
- __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */
- __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */
- uint8_t RESERVED_1[32];
- __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */
- __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */
- uint8_t RESERVED_2[24];
- __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */
+typedef struct {
+ __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */
+ __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */
+ __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */
+ __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */
+ __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */
+ __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t AREG; /**< A register, offset: 0x20 */
+ __IO uint32_t BREG; /**< B register, offset: 0x24 */
+ __IO uint32_t CREG; /**< C register, offset: 0x28 */
+ __IO uint32_t DREG; /**< D register, offset: 0x2C */
+ __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */
+ __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */
+ __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */
+ __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */
+ uint8_t RESERVED_1[32];
+ __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */
+ __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */
} CASPER_Type;
/* ----------------------------------------------------------------------------
@@ -5801,337 +5445,341 @@ typedef struct
/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */
/*! @{ */
-#define CASPER_CTRL0_ABBPAIR_MASK (0x1U)
-#define CASPER_CTRL0_ABBPAIR_SHIFT (0U)
+
+#define CASPER_CTRL0_ABBPAIR_MASK (0x1U)
+#define CASPER_CTRL0_ABBPAIR_SHIFT (0U)
/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up
* 0b0..Bank-pair 0 (1st)
* 0b1..Bank-pair 1 (2nd)
*/
-#define CASPER_CTRL0_ABBPAIR(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)
-#define CASPER_CTRL0_ABOFF_MASK (0x4U)
-#define CASPER_CTRL0_ABOFF_SHIFT (2U)
+#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)
+
+#define CASPER_CTRL0_ABOFF_MASK (0x4U)
+#define CASPER_CTRL0_ABOFF_SHIFT (2U)
/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code
* sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed
* if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up
*/
-#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)
-#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U)
-#define CASPER_CTRL0_CDBPAIR_SHIFT (16U)
+#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)
+
+#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U)
+#define CASPER_CTRL0_CDBPAIR_SHIFT (16U)
/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up
* 0b0..Bank-pair 0 (1st)
* 0b1..Bank-pair 1 (2nd)
*/
-#define CASPER_CTRL0_CDBPAIR(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)
-#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U)
-#define CASPER_CTRL0_CDOFF_SHIFT (18U)
+#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)
+
+#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U)
+#define CASPER_CTRL0_CDOFF_SHIFT (18U)
/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees
* (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32
* bit operation. Ideally not in the same RAM as the AB values
*/
-#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
+#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
/*! @} */
-/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the
- * accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */
+/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */
/*! @{ */
-#define CASPER_CTRL1_ITER_MASK (0xFFU)
-#define CASPER_CTRL1_ITER_SHIFT (0U)
+
+#define CASPER_CTRL1_ITER_MASK (0xFFU)
+#define CASPER_CTRL1_ITER_SHIFT (0U)
/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate.
*/
-#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)
-#define CASPER_CTRL1_MODE_MASK (0xFF00U)
-#define CASPER_CTRL1_MODE_SHIFT (8U)
+#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)
+
+#define CASPER_CTRL1_MODE_MASK (0xFF00U)
+#define CASPER_CTRL1_MODE_SHIFT (8U)
/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active.
*/
-#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
-#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U)
-#define CASPER_CTRL1_RESBPAIR_SHIFT (16U)
+#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
+
+#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U)
+#define CASPER_CTRL1_RESBPAIR_SHIFT (16U)
/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally
* this is not the same bank as ABBPAIR (when 4-up supported)
* 0b0..Bank-pair 0 (1st)
* 0b1..Bank-pair 1 (2nd)
*/
-#define CASPER_CTRL1_RESBPAIR(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)
-#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U)
-#define CASPER_CTRL1_RESOFF_SHIFT (18U)
+#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)
+
+#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U)
+#define CASPER_CTRL1_RESOFF_SHIFT (18U)
/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally
* not in the same RAM as the AB and CD values
*/
-#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)
-#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U)
-#define CASPER_CTRL1_CSKIP_SHIFT (30U)
-/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation)
- * if not 0: 0b00..No Skip 0b01..Skip if Carry is 1 0b10..Skip if Carry is 0 0b11..Set CTRLOFF to CDOFF and Skip
+#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)
+
+#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U)
+#define CASPER_CTRL1_CSKIP_SHIFT (30U)
+/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0:
+ * 0b00..No Skip
+ * 0b01..Skip if Carry is 1
+ * 0b10..Skip if Carry is 0
+ * 0b11..Set CTRLOFF to CDOFF and Skip
*/
-#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
+#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
/*! @} */
/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */
/*! @{ */
-#define CASPER_LOADER_COUNT_MASK (0xFFU)
-#define CASPER_LOADER_COUNT_SHIFT (0U)
+
+#define CASPER_LOADER_COUNT_MASK (0xFFU)
+#define CASPER_LOADER_COUNT_SHIFT (0U)
/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one
* op - does not iterate, write N means N control pairs to load
*/
-#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK)
-#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U)
-#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U)
+#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK)
+
+#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U)
+#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U)
/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not
* matter which bank is used as this is loaded when not performing an operation.
* 0b0..Bank-pair 0 (1st)
* 0b1..Bank-pair 1 (2nd)
*/
-#define CASPER_LOADER_CTRLBPAIR(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK)
-#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U)
-#define CASPER_LOADER_CTRLOFF_SHIFT (18U)
+#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK)
+
+#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U)
+#define CASPER_LOADER_CTRLOFF_SHIFT (18U)
/*! CTRLOFF - DWord Offset of CTRL pair to load next.
*/
-#define CASPER_LOADER_CTRLOFF(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK)
+#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK)
/*! @} */
/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */
/*! @{ */
-#define CASPER_STATUS_DONE_MASK (0x1U)
-#define CASPER_STATUS_DONE_SHIFT (0U)
+
+#define CASPER_STATUS_DONE_MASK (0x1U)
+#define CASPER_STATUS_DONE_SHIFT (0U)
/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear.
* 0b0..Busy or just cleared
* 0b1..Completed last operation
*/
-#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)
-#define CASPER_STATUS_CARRY_MASK (0x10U)
-#define CASPER_STATUS_CARRY_SHIFT (4U)
+#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)
+
+#define CASPER_STATUS_CARRY_MASK (0x10U)
+#define CASPER_STATUS_CARRY_SHIFT (4U)
/*! CARRY - Last carry value if operation produced a carry bit
* 0b0..Carry was 0 or no carry
* 0b1..Carry was 1
*/
-#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)
-#define CASPER_STATUS_BUSY_MASK (0x20U)
-#define CASPER_STATUS_BUSY_SHIFT (5U)
+#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)
+
+#define CASPER_STATUS_BUSY_MASK (0x20U)
+#define CASPER_STATUS_BUSY_SHIFT (5U)
/*! BUSY - Indicates if the accelerator is busy performing an operation
* 0b0..Not busy - is idle
* 0b1..Is busy
*/
-#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
+#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
/*! @} */
/*! @name INTENSET - Sets interrupts */
/*! @{ */
-#define CASPER_INTENSET_DONE_MASK (0x1U)
-#define CASPER_INTENSET_DONE_SHIFT (0U)
+
+#define CASPER_INTENSET_DONE_MASK (0x1U)
+#define CASPER_INTENSET_DONE_SHIFT (0U)
/*! DONE - Set if the accelerator should interrupt when done.
* 0b0..Do not interrupt when done
* 0b1..Interrupt when done
*/
-#define CASPER_INTENSET_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
+#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
/*! @} */
/*! @name INTENCLR - Clears interrupts */
/*! @{ */
-#define CASPER_INTENCLR_DONE_MASK (0x1U)
-#define CASPER_INTENCLR_DONE_SHIFT (0U)
+
+#define CASPER_INTENCLR_DONE_MASK (0x1U)
+#define CASPER_INTENCLR_DONE_SHIFT (0U)
/*! DONE - Written to clear an interrupt set with INTENSET.
* 0b0..If written 0, ignored
* 0b1..If written 1, do not Interrupt when done
*/
-#define CASPER_INTENCLR_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
+#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
/*! @} */
/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */
/*! @{ */
-#define CASPER_INTSTAT_DONE_MASK (0x1U)
-#define CASPER_INTSTAT_DONE_SHIFT (0U)
+
+#define CASPER_INTSTAT_DONE_MASK (0x1U)
+#define CASPER_INTSTAT_DONE_SHIFT (0U)
/*! DONE - If set, interrupt is caused by accelerator being done.
* 0b0..Not caused by accelerator being done
* 0b1..Caused by accelerator being done
*/
-#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
+#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
/*! @} */
/*! @name AREG - A register */
/*! @{ */
-#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_AREG_REG_VALUE_SHIFT (0U)
+
+#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_AREG_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
* but is available when accelerator not busy.
*/
-#define CASPER_AREG_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
+#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
/*! @} */
/*! @name BREG - B register */
/*! @{ */
-#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_BREG_REG_VALUE_SHIFT (0U)
+
+#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_BREG_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
* but is available when accelerator not busy.
*/
-#define CASPER_BREG_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
+#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
/*! @} */
/*! @name CREG - C register */
/*! @{ */
-#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_CREG_REG_VALUE_SHIFT (0U)
+
+#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_CREG_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
* but is available when accelerator not busy.
*/
-#define CASPER_CREG_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
+#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
/*! @} */
/*! @name DREG - D register */
/*! @{ */
-#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_DREG_REG_VALUE_SHIFT (0U)
+
+#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_DREG_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application,
* but is available when accelerator not busy.
*/
-#define CASPER_DREG_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
+#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
/*! @} */
/*! @name RES0 - Result register 0 */
/*! @{ */
-#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_RES0_REG_VALUE_SHIFT (0U)
+
+#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES0_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
* written or read by application, but is available when accelerator not busy.
*/
-#define CASPER_RES0_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
+#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
/*! @} */
/*! @name RES1 - Result register 1 */
/*! @{ */
-#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_RES1_REG_VALUE_SHIFT (0U)
+
+#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES1_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
* written or read by application, but is available when accelerator not busy.
*/
-#define CASPER_RES1_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
+#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
/*! @} */
/*! @name RES2 - Result register 2 */
/*! @{ */
-#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_RES2_REG_VALUE_SHIFT (0U)
+
+#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES2_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
* written or read by application, but is available when accelerator not busy.
*/
-#define CASPER_RES2_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
+#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
/*! @} */
/*! @name RES3 - Result register 3 */
/*! @{ */
-#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU)
-#define CASPER_RES3_REG_VALUE_SHIFT (0U)
+
+#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU)
+#define CASPER_RES3_REG_VALUE_SHIFT (0U)
/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally
* written or read by application, but is available when accelerator not busy.
*/
-#define CASPER_RES3_REG_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
+#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
/*! @} */
/*! @name MASK - Optional mask register */
/*! @{ */
-#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU)
-#define CASPER_MASK_MASK_SHIFT (0U)
+
+#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU)
+#define CASPER_MASK_MASK_SHIFT (0U)
/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values
*/
-#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
+#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
/*! @} */
/*! @name REMASK - Optional re-mask register */
/*! @{ */
-#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU)
-#define CASPER_REMASK_MASK_SHIFT (0U)
+
+#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU)
+#define CASPER_REMASK_MASK_SHIFT (0U)
/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values
*/
-#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
+#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
/*! @} */
/*! @name LOCK - Security lock register */
/*! @{ */
-#define CASPER_LOCK_LOCK_MASK (0x1U)
-#define CASPER_LOCK_LOCK_SHIFT (0U)
+
+#define CASPER_LOCK_LOCK_MASK (0x1U)
+#define CASPER_LOCK_LOCK_SHIFT (0U)
/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock.
* 0b0..unlock
* 0b1..Lock to current security level
*/
-#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)
-#define CASPER_LOCK_KEY_MASK (0x1FFF0U)
-#define CASPER_LOCK_KEY_SHIFT (4U)
+#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)
+
+#define CASPER_LOCK_KEY_MASK (0x1FFF0U)
+#define CASPER_LOCK_KEY_SHIFT (4U)
/*! KEY - Must be written as 0x73D to change the register.
* 0b0011100111101..If set during write, will allow lock or unlock
*/
-#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
+#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group CASPER_Register_Masks */
+
/* CASPER - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral CASPER base address */
-#define CASPER_BASE (0x500A5000u)
-/** Peripheral CASPER base address */
-#define CASPER_BASE_NS (0x400A5000u)
-/** Peripheral CASPER base pointer */
-#define CASPER ((CASPER_Type *)CASPER_BASE)
-/** Peripheral CASPER base pointer */
-#define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS)
-/** Array initializer of CASPER peripheral base addresses */
-#define CASPER_BASE_ADDRS \
- { \
- CASPER_BASE \
- }
-/** Array initializer of CASPER peripheral base pointers */
-#define CASPER_BASE_PTRS \
- { \
- CASPER \
- }
-/** Array initializer of CASPER peripheral base addresses */
-#define CASPER_BASE_ADDRS_NS \
- { \
- CASPER_BASE_NS \
- }
-/** Array initializer of CASPER peripheral base pointers */
-#define CASPER_BASE_PTRS_NS \
- { \
- CASPER_NS \
- }
+ /** Peripheral CASPER base address */
+ #define CASPER_BASE (0x500A5000u)
+ /** Peripheral CASPER base address */
+ #define CASPER_BASE_NS (0x400A5000u)
+ /** Peripheral CASPER base pointer */
+ #define CASPER ((CASPER_Type *)CASPER_BASE)
+ /** Peripheral CASPER base pointer */
+ #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS)
+ /** Array initializer of CASPER peripheral base addresses */
+ #define CASPER_BASE_ADDRS { CASPER_BASE }
+ /** Array initializer of CASPER peripheral base pointers */
+ #define CASPER_BASE_PTRS { CASPER }
+ /** Array initializer of CASPER peripheral base addresses */
+ #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS }
+ /** Array initializer of CASPER peripheral base pointers */
+ #define CASPER_BASE_PTRS_NS { CASPER_NS }
#else
-/** Peripheral CASPER base address */
-#define CASPER_BASE (0x400A5000u)
-/** Peripheral CASPER base pointer */
-#define CASPER ((CASPER_Type *)CASPER_BASE)
-/** Array initializer of CASPER peripheral base addresses */
-#define CASPER_BASE_ADDRS \
- { \
- CASPER_BASE \
- }
-/** Array initializer of CASPER peripheral base pointers */
-#define CASPER_BASE_PTRS \
- { \
- CASPER \
- }
+ /** Peripheral CASPER base address */
+ #define CASPER_BASE (0x400A5000u)
+ /** Peripheral CASPER base pointer */
+ #define CASPER ((CASPER_Type *)CASPER_BASE)
+ /** Array initializer of CASPER peripheral base addresses */
+ #define CASPER_BASE_ADDRS { CASPER_BASE }
+ /** Array initializer of CASPER peripheral base pointers */
+ #define CASPER_BASE_PTRS { CASPER }
#endif
+/** Interrupt vectors for the CASPER peripheral type */
+#define CASPER_IRQS { CASER_IRQn }
/*!
* @}
*/ /* end of group CASPER_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -6142,15 +5790,13 @@ typedef struct
*/
/** CRC - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
- __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
- union
- { /* offset: 0x8 */
- __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
- __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
- };
+typedef struct {
+ __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
+ __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
+ union { /* offset: 0x8 */
+ __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
+ __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
+ };
} CRC_Type;
/* ----------------------------------------------------------------------------
@@ -6164,123 +5810,112 @@ typedef struct
/*! @name MODE - CRC mode register */
/*! @{ */
-#define CRC_MODE_CRC_POLY_MASK (0x3U)
-#define CRC_MODE_CRC_POLY_SHIFT (0U)
+
+#define CRC_MODE_CRC_POLY_MASK (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT (0U)
/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
*/
-#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
-#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
-#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
-/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for
- * CRC_WR_DATA (per byte)
+#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+
+#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
+/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
*/
-#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
-#define CRC_MODE_CMPL_WR_MASK (0x8U)
-#define CRC_MODE_CMPL_WR_SHIFT (3U)
+#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+
+#define CRC_MODE_CMPL_WR_MASK (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT (3U)
/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
*/
-#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
-#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
-#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
+#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+
+#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
*/
-#define CRC_MODE_BIT_RVS_SUM(x) \
- (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
-#define CRC_MODE_CMPL_SUM_MASK (0x20U)
-#define CRC_MODE_CMPL_SUM_SHIFT (5U)
+#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+
+#define CRC_MODE_CMPL_SUM_MASK (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT (5U)
/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
*/
-#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
/*! @} */
/*! @name SEED - CRC seed register */
/*! @{ */
-#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
-#define CRC_SEED_CRC_SEED_SHIFT (0U)
+
+#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT (0U)
/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
* selected bit order and 1's complement pre-processes. A write access to this register will
* overrule the CRC calculation in progresses.
*/
-#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
/*! @} */
/*! @name SUM - CRC checksum register */
/*! @{ */
-#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
-#define CRC_SUM_CRC_SUM_SHIFT (0U)
-/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement
- * post-processes.
+
+#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT (0U)
+/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
*/
-#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
/*! @} */
/*! @name WR_DATA - CRC data register */
/*! @{ */
-#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
-#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
+
+#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
* selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
* accept back-to-back transactions.
*/
-#define CRC_WR_DATA_CRC_WR_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group CRC_Register_Masks */
+
/* CRC - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral CRC_ENGINE base address */
-#define CRC_ENGINE_BASE (0x50095000u)
-/** Peripheral CRC_ENGINE base address */
-#define CRC_ENGINE_BASE_NS (0x40095000u)
-/** Peripheral CRC_ENGINE base pointer */
-#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
-/** Peripheral CRC_ENGINE base pointer */
-#define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS)
-/** Array initializer of CRC peripheral base addresses */
-#define CRC_BASE_ADDRS \
- { \
- CRC_ENGINE_BASE \
- }
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASE_PTRS \
- { \
- CRC_ENGINE \
- }
-/** Array initializer of CRC peripheral base addresses */
-#define CRC_BASE_ADDRS_NS \
- { \
- CRC_ENGINE_BASE_NS \
- }
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASE_PTRS_NS \
- { \
- CRC_ENGINE_NS \
- }
+ /** Peripheral CRC_ENGINE base address */
+ #define CRC_ENGINE_BASE (0x50095000u)
+ /** Peripheral CRC_ENGINE base address */
+ #define CRC_ENGINE_BASE_NS (0x40095000u)
+ /** Peripheral CRC_ENGINE base pointer */
+ #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
+ /** Peripheral CRC_ENGINE base pointer */
+ #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS)
+ /** Array initializer of CRC peripheral base addresses */
+ #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
+ /** Array initializer of CRC peripheral base pointers */
+ #define CRC_BASE_PTRS { CRC_ENGINE }
+ /** Array initializer of CRC peripheral base addresses */
+ #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS }
+ /** Array initializer of CRC peripheral base pointers */
+ #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS }
#else
-/** Peripheral CRC_ENGINE base address */
-#define CRC_ENGINE_BASE (0x40095000u)
-/** Peripheral CRC_ENGINE base pointer */
-#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
-/** Array initializer of CRC peripheral base addresses */
-#define CRC_BASE_ADDRS \
- { \
- CRC_ENGINE_BASE \
- }
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASE_PTRS \
- { \
- CRC_ENGINE \
- }
+ /** Peripheral CRC_ENGINE base address */
+ #define CRC_ENGINE_BASE (0x40095000u)
+ /** Peripheral CRC_ENGINE base pointer */
+ #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
+ /** Array initializer of CRC peripheral base addresses */
+ #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
+ /** Array initializer of CRC peripheral base pointers */
+ #define CRC_BASE_PTRS { CRC_ENGINE }
#endif
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- CTIMER Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -6291,32 +5926,21 @@ typedef struct
*/
/** CTIMER - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify
- which of eight possible interrupt sources are pending., offset: 0x0 */
- __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer
- Counter can be disabled or reset through the TCR., offset: 0x4 */
- __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
- __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
- __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
- __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
- __IO uint32_t
- MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or
- generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
- __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to
- load the Capture Registers and whether or not an interrupt is generated when a capture takes
- place., offset: 0x28 */
- __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn.
- input., array offset: 0x2C, array step: 0x4 */
- __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins.,
- offset: 0x3C */
- uint8_t RESERVED_0[48];
- __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter
- mode selects the signal and edge(s) for counting., offset: 0x70 */
- __IO uint32_t
- PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */
- __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+typedef struct {
+ __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+ __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
+ __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
+ __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
+ __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
+ __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+ __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+ __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+ __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+ uint8_t RESERVED_0[48];
+ __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+ __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */
+ __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
} CTIMER_Type;
/* ----------------------------------------------------------------------------
@@ -6328,361 +5952,408 @@ typedef struct
* @{
*/
-/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of
- * eight possible interrupt sources are pending. */
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
/*! @{ */
-#define CTIMER_IR_MR0INT_MASK (0x1U)
-#define CTIMER_IR_MR0INT_SHIFT (0U)
+
+#define CTIMER_IR_MR0INT_MASK (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT (0U)
/*! MR0INT - Interrupt flag for match channel 0.
*/
-#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
-#define CTIMER_IR_MR1INT_MASK (0x2U)
-#define CTIMER_IR_MR1INT_SHIFT (1U)
+#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+
+#define CTIMER_IR_MR1INT_MASK (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT (1U)
/*! MR1INT - Interrupt flag for match channel 1.
*/
-#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
-#define CTIMER_IR_MR2INT_MASK (0x4U)
-#define CTIMER_IR_MR2INT_SHIFT (2U)
+#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+
+#define CTIMER_IR_MR2INT_MASK (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT (2U)
/*! MR2INT - Interrupt flag for match channel 2.
*/
-#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
-#define CTIMER_IR_MR3INT_MASK (0x8U)
-#define CTIMER_IR_MR3INT_SHIFT (3U)
+#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+
+#define CTIMER_IR_MR3INT_MASK (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT (3U)
/*! MR3INT - Interrupt flag for match channel 3.
*/
-#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
-#define CTIMER_IR_CR0INT_MASK (0x10U)
-#define CTIMER_IR_CR0INT_SHIFT (4U)
+#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+
+#define CTIMER_IR_CR0INT_MASK (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT (4U)
/*! CR0INT - Interrupt flag for capture channel 0 event.
*/
-#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
-#define CTIMER_IR_CR1INT_MASK (0x20U)
-#define CTIMER_IR_CR1INT_SHIFT (5U)
+#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+
+#define CTIMER_IR_CR1INT_MASK (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT (5U)
/*! CR1INT - Interrupt flag for capture channel 1 event.
*/
-#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
-#define CTIMER_IR_CR2INT_MASK (0x40U)
-#define CTIMER_IR_CR2INT_SHIFT (6U)
+#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+
+#define CTIMER_IR_CR2INT_MASK (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT (6U)
/*! CR2INT - Interrupt flag for capture channel 2 event.
*/
-#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
-#define CTIMER_IR_CR3INT_MASK (0x80U)
-#define CTIMER_IR_CR3INT_SHIFT (7U)
+#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+
+#define CTIMER_IR_CR3INT_MASK (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT (7U)
/*! CR3INT - Interrupt flag for capture channel 3 event.
*/
-#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
/*! @} */
-/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be
- * disabled or reset through the TCR. */
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
/*! @{ */
-#define CTIMER_TCR_CEN_MASK (0x1U)
-#define CTIMER_TCR_CEN_SHIFT (0U)
+
+#define CTIMER_TCR_CEN_MASK (0x1U)
+#define CTIMER_TCR_CEN_SHIFT (0U)
/*! CEN - Counter enable.
* 0b0..Disabled.The counters are disabled.
* 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
*/
-#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
-#define CTIMER_TCR_CRST_MASK (0x2U)
-#define CTIMER_TCR_CRST_SHIFT (1U)
+#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+
+#define CTIMER_TCR_CRST_MASK (0x2U)
+#define CTIMER_TCR_CRST_SHIFT (1U)
/*! CRST - Counter reset.
* 0b0..Disabled. Do nothing.
* 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of
* the APB bus clock. The counters remain reset until TCR[1] is returned to zero.
*/
-#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
/*! @} */
/*! @name TC - Timer Counter */
/*! @{ */
-#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
-#define CTIMER_TC_TCVAL_SHIFT (0U)
+
+#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT (0U)
/*! TCVAL - Timer counter value.
*/
-#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
/*! @} */
/*! @name PR - Prescale Register */
/*! @{ */
-#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
-#define CTIMER_PR_PRVAL_SHIFT (0U)
+
+#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT (0U)
/*! PRVAL - Prescale counter value.
*/
-#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
/*! @} */
/*! @name PC - Prescale Counter */
/*! @{ */
-#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
-#define CTIMER_PC_PCVAL_SHIFT (0U)
+
+#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT (0U)
/*! PCVAL - Prescale counter value.
*/
-#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
/*! @} */
/*! @name MCR - Match Control Register */
/*! @{ */
-#define CTIMER_MCR_MR0I_MASK (0x1U)
-#define CTIMER_MCR_MR0I_SHIFT (0U)
+
+#define CTIMER_MCR_MR0I_MASK (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT (0U)
/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
*/
-#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
-#define CTIMER_MCR_MR0R_MASK (0x2U)
-#define CTIMER_MCR_MR0R_SHIFT (1U)
+#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+
+#define CTIMER_MCR_MR0R_MASK (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT (1U)
/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it.
*/
-#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
-#define CTIMER_MCR_MR0S_MASK (0x4U)
-#define CTIMER_MCR_MR0S_SHIFT (2U)
+#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+
+#define CTIMER_MCR_MR0S_MASK (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT (2U)
/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
*/
-#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
-#define CTIMER_MCR_MR1I_MASK (0x8U)
-#define CTIMER_MCR_MR1I_SHIFT (3U)
+#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+
+#define CTIMER_MCR_MR1I_MASK (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT (3U)
/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
*/
-#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
-#define CTIMER_MCR_MR1R_MASK (0x10U)
-#define CTIMER_MCR_MR1R_SHIFT (4U)
+#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+
+#define CTIMER_MCR_MR1R_MASK (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT (4U)
/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it.
*/
-#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
-#define CTIMER_MCR_MR1S_MASK (0x20U)
-#define CTIMER_MCR_MR1S_SHIFT (5U)
+#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+
+#define CTIMER_MCR_MR1S_MASK (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT (5U)
/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
*/
-#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
-#define CTIMER_MCR_MR2I_MASK (0x40U)
-#define CTIMER_MCR_MR2I_SHIFT (6U)
+#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+
+#define CTIMER_MCR_MR2I_MASK (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT (6U)
/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
*/
-#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
-#define CTIMER_MCR_MR2R_MASK (0x80U)
-#define CTIMER_MCR_MR2R_SHIFT (7U)
+#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+
+#define CTIMER_MCR_MR2R_MASK (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT (7U)
/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it.
*/
-#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
-#define CTIMER_MCR_MR2S_MASK (0x100U)
-#define CTIMER_MCR_MR2S_SHIFT (8U)
+#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+
+#define CTIMER_MCR_MR2S_MASK (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT (8U)
/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.
*/
-#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
-#define CTIMER_MCR_MR3I_MASK (0x200U)
-#define CTIMER_MCR_MR3I_SHIFT (9U)
+#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+
+#define CTIMER_MCR_MR3I_MASK (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT (9U)
/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
*/
-#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
-#define CTIMER_MCR_MR3R_MASK (0x400U)
-#define CTIMER_MCR_MR3R_SHIFT (10U)
+#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+
+#define CTIMER_MCR_MR3R_MASK (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT (10U)
/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it.
*/
-#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
-#define CTIMER_MCR_MR3S_MASK (0x800U)
-#define CTIMER_MCR_MR3S_SHIFT (11U)
+#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+
+#define CTIMER_MCR_MR3S_MASK (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT (11U)
/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
*/
-#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
-#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
-#define CTIMER_MCR_MR0RL_SHIFT (24U)
+#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+
+#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT (24U)
/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
* (either via a match event or a write to bit 1 of the TCR).
*/
-#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
-#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
-#define CTIMER_MCR_MR1RL_SHIFT (25U)
+#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+
+#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT (25U)
/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
* (either via a match event or a write to bit 1 of the TCR).
*/
-#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
-#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
-#define CTIMER_MCR_MR2RL_SHIFT (26U)
+#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+
+#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT (26U)
/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
* (either via a match event or a write to bit 1 of the TCR).
*/
-#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
-#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
-#define CTIMER_MCR_MR3RL_SHIFT (27U)
+#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+
+#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT (27U)
/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
* (either via a match event or a write to bit 1 of the TCR).
*/
-#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
/*! @} */
-/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or
- * generate an interrupt every time MR matches the TC. */
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
/*! @{ */
-#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
-#define CTIMER_MR_MATCH_SHIFT (0U)
+
+#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT (0U)
/*! MATCH - Timer counter match value.
*/
-#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
/*! @} */
/* The count of CTIMER_MR */
-#define CTIMER_MR_COUNT (4U)
+#define CTIMER_MR_COUNT (4U)
-/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the
- * Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
/*! @{ */
-#define CTIMER_CCR_CAP0RE_MASK (0x1U)
-#define CTIMER_CCR_CAP0RE_SHIFT (0U)
+
+#define CTIMER_CCR_CAP0RE_MASK (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT (0U)
/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
-#define CTIMER_CCR_CAP0FE_MASK (0x2U)
-#define CTIMER_CCR_CAP0FE_SHIFT (1U)
+#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+
+#define CTIMER_CCR_CAP0FE_MASK (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT (1U)
/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
-#define CTIMER_CCR_CAP0I_MASK (0x4U)
-#define CTIMER_CCR_CAP0I_SHIFT (2U)
+#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+
+#define CTIMER_CCR_CAP0I_MASK (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT (2U)
/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
*/
-#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
-#define CTIMER_CCR_CAP1RE_MASK (0x8U)
-#define CTIMER_CCR_CAP1RE_SHIFT (3U)
+#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+
+#define CTIMER_CCR_CAP1RE_MASK (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT (3U)
/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
-#define CTIMER_CCR_CAP1FE_MASK (0x10U)
-#define CTIMER_CCR_CAP1FE_SHIFT (4U)
+#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+
+#define CTIMER_CCR_CAP1FE_MASK (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT (4U)
/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
-#define CTIMER_CCR_CAP1I_MASK (0x20U)
-#define CTIMER_CCR_CAP1I_SHIFT (5U)
+#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+
+#define CTIMER_CCR_CAP1I_MASK (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT (5U)
/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
*/
-#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
-#define CTIMER_CCR_CAP2RE_MASK (0x40U)
-#define CTIMER_CCR_CAP2RE_SHIFT (6U)
+#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+
+#define CTIMER_CCR_CAP2RE_MASK (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT (6U)
/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
-#define CTIMER_CCR_CAP2FE_MASK (0x80U)
-#define CTIMER_CCR_CAP2FE_SHIFT (7U)
+#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+
+#define CTIMER_CCR_CAP2FE_MASK (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT (7U)
/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
-#define CTIMER_CCR_CAP2I_MASK (0x100U)
-#define CTIMER_CCR_CAP2I_SHIFT (8U)
+#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+
+#define CTIMER_CCR_CAP2I_MASK (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT (8U)
/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
*/
-#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
-#define CTIMER_CCR_CAP3RE_MASK (0x200U)
-#define CTIMER_CCR_CAP3RE_SHIFT (9U)
+#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+
+#define CTIMER_CCR_CAP3RE_MASK (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT (9U)
/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
-#define CTIMER_CCR_CAP3FE_MASK (0x400U)
-#define CTIMER_CCR_CAP3FE_SHIFT (10U)
+#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+
+#define CTIMER_CCR_CAP3FE_MASK (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT (10U)
/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with
* the contents of TC. 0 = disabled. 1 = enabled.
*/
-#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
-#define CTIMER_CCR_CAP3I_MASK (0x800U)
-#define CTIMER_CCR_CAP3I_SHIFT (11U)
+#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+
+#define CTIMER_CCR_CAP3I_MASK (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT (11U)
/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
*/
-#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
/*! @} */
/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
/*! @{ */
-#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
-#define CTIMER_CR_CAP_SHIFT (0U)
+
+#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT (0U)
/*! CAP - Timer counter capture value.
*/
-#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
/*! @} */
/* The count of CTIMER_CR */
-#define CTIMER_CR_COUNT (4U)
+#define CTIMER_CR_COUNT (4U)
/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
/*! @{ */
-#define CTIMER_EMR_EM0_MASK (0x1U)
-#define CTIMER_EMR_EM0_SHIFT (0U)
+
+#define CTIMER_EMR_EM0_MASK (0x1U)
+#define CTIMER_EMR_EM0_SHIFT (0U)
/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output
* is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle,
* go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if
* the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
*/
-#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
-#define CTIMER_EMR_EM1_MASK (0x2U)
-#define CTIMER_EMR_EM1_SHIFT (1U)
+#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+
+#define CTIMER_EMR_EM1_MASK (0x2U)
+#define CTIMER_EMR_EM1_SHIFT (1U)
/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output
* is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle,
* go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if
* the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
*/
-#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
-#define CTIMER_EMR_EM2_MASK (0x4U)
-#define CTIMER_EMR_EM2_SHIFT (2U)
+#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+
+#define CTIMER_EMR_EM2_MASK (0x4U)
+#define CTIMER_EMR_EM2_SHIFT (2U)
/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output
* is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle,
* go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if
* the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
*/
-#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
-#define CTIMER_EMR_EM3_MASK (0x8U)
-#define CTIMER_EMR_EM3_SHIFT (3U)
+#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+
+#define CTIMER_EMR_EM3_MASK (0x8U)
+#define CTIMER_EMR_EM3_SHIFT (3U)
/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output
* is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle,
* go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins
* if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
*/
-#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
-#define CTIMER_EMR_EMC0_MASK (0x30U)
-#define CTIMER_EMR_EMC0_SHIFT (4U)
+#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+
+#define CTIMER_EMR_EMC0_MASK (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT (4U)
/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.
* 0b00..Do Nothing.
* 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
* 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
* 0b11..Toggle. Toggle the corresponding External Match bit/output.
*/
-#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
-#define CTIMER_EMR_EMC1_MASK (0xC0U)
-#define CTIMER_EMR_EMC1_SHIFT (6U)
+#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+
+#define CTIMER_EMR_EMC1_MASK (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT (6U)
/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.
* 0b00..Do Nothing.
* 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
* 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
* 0b11..Toggle. Toggle the corresponding External Match bit/output.
*/
-#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
-#define CTIMER_EMR_EMC2_MASK (0x300U)
-#define CTIMER_EMR_EMC2_SHIFT (8U)
+#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+
+#define CTIMER_EMR_EMC2_MASK (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT (8U)
/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.
* 0b00..Do Nothing.
* 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
* 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
* 0b11..Toggle. Toggle the corresponding External Match bit/output.
*/
-#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
-#define CTIMER_EMR_EMC3_MASK (0xC00U)
-#define CTIMER_EMR_EMC3_SHIFT (10U)
+#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+
+#define CTIMER_EMR_EMC3_MASK (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT (10U)
/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.
* 0b00..Do Nothing.
* 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
* 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
* 0b11..Toggle. Toggle the corresponding External Match bit/output.
*/
-#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
/*! @} */
-/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects
- * the signal and edge(s) for counting. */
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
/*! @{ */
-#define CTIMER_CTCR_CTMODE_MASK (0x3U)
-#define CTIMER_CTCR_CTMODE_SHIFT (0U)
+
+#define CTIMER_CTCR_CTMODE_MASK (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT (0U)
/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment
* Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC
* is incremented when the Prescale Counter matches the Prescale Register.
@@ -6691,9 +6362,10 @@ typedef struct
* 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.
* 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.
*/
-#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
-#define CTIMER_CTCR_CINSEL_MASK (0xCU)
-#define CTIMER_CTCR_CINSEL_SHIFT (2U)
+#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+
+#define CTIMER_CTCR_CINSEL_MASK (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT (2U)
/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which
* CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input
* in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be
@@ -6704,15 +6376,17 @@ typedef struct
* 0b10..Channel 2. CAPn.2 for CTIMERn
* 0b11..Channel 3. CAPn.3 for CTIMERn
*/
-#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
-#define CTIMER_CTCR_ENCC_MASK (0x10U)
-#define CTIMER_CTCR_ENCC_SHIFT (4U)
+#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+
+#define CTIMER_CTCR_ENCC_MASK (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT (4U)
/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the
* capture-edge event specified in bits 7:5 occurs.
*/
-#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
-#define CTIMER_CTCR_SELCC_MASK (0xE0U)
-#define CTIMER_CTCR_SELCC_SHIFT (5U)
+#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+
+#define CTIMER_CTCR_SELCC_MASK (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT (5U)
/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the
* timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to
* 0x3 and 0x6 to 0x7 are reserved.
@@ -6723,161 +6397,148 @@ typedef struct
* 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
* 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
*/
-#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
/*! @} */
/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */
/*! @{ */
-#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
-#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
+
+#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
/*! PWMEN0 - PWM mode enable for channel0.
* 0b0..Match. CTIMERn_MAT0 is controlled by EM0.
* 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
*/
-#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
-#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
-#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
+#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+
+#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
/*! PWMEN1 - PWM mode enable for channel1.
* 0b0..Match. CTIMERn_MAT01 is controlled by EM1.
* 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
*/
-#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
-#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
-#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
+#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+
+#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
/*! PWMEN2 - PWM mode enable for channel2.
* 0b0..Match. CTIMERn_MAT2 is controlled by EM2.
* 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
*/
-#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
-#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
-#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
+#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+
+#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
* 0b0..Match. CTIMERn_MAT3 is controlled by EM3.
* 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
*/
-#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
/*! @} */
/*! @name MSR - Match Shadow Register */
/*! @{ */
-#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU)
-#define CTIMER_MSR_SHADOW_SHIFT (0U)
+
+#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOW_SHIFT (0U)
/*! SHADOW - Timer counter match shadow value.
*/
-#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK)
+#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK)
/*! @} */
/* The count of CTIMER_MSR */
-#define CTIMER_MSR_COUNT (4U)
+#define CTIMER_MSR_COUNT (4U)
+
/*!
* @}
*/ /* end of group CTIMER_Register_Masks */
+
/* CTIMER - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral CTIMER0 base address */
-#define CTIMER0_BASE (0x50008000u)
-/** Peripheral CTIMER0 base address */
-#define CTIMER0_BASE_NS (0x40008000u)
-/** Peripheral CTIMER0 base pointer */
-#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
-/** Peripheral CTIMER0 base pointer */
-#define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS)
-/** Peripheral CTIMER1 base address */
-#define CTIMER1_BASE (0x50009000u)
-/** Peripheral CTIMER1 base address */
-#define CTIMER1_BASE_NS (0x40009000u)
-/** Peripheral CTIMER1 base pointer */
-#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
-/** Peripheral CTIMER1 base pointer */
-#define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS)
-/** Peripheral CTIMER2 base address */
-#define CTIMER2_BASE (0x50028000u)
-/** Peripheral CTIMER2 base address */
-#define CTIMER2_BASE_NS (0x40028000u)
-/** Peripheral CTIMER2 base pointer */
-#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
-/** Peripheral CTIMER2 base pointer */
-#define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS)
-/** Peripheral CTIMER3 base address */
-#define CTIMER3_BASE (0x50029000u)
-/** Peripheral CTIMER3 base address */
-#define CTIMER3_BASE_NS (0x40029000u)
-/** Peripheral CTIMER3 base pointer */
-#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
-/** Peripheral CTIMER3 base pointer */
-#define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS)
-/** Peripheral CTIMER4 base address */
-#define CTIMER4_BASE (0x5002A000u)
-/** Peripheral CTIMER4 base address */
-#define CTIMER4_BASE_NS (0x4002A000u)
-/** Peripheral CTIMER4 base pointer */
-#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
-/** Peripheral CTIMER4 base pointer */
-#define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS)
-/** Array initializer of CTIMER peripheral base addresses */
-#define CTIMER_BASE_ADDRS \
- { \
- CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE \
- }
-/** Array initializer of CTIMER peripheral base pointers */
-#define CTIMER_BASE_PTRS \
- { \
- CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 \
- }
-/** Array initializer of CTIMER peripheral base addresses */
-#define CTIMER_BASE_ADDRS_NS \
- { \
- CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS \
- }
-/** Array initializer of CTIMER peripheral base pointers */
-#define CTIMER_BASE_PTRS_NS \
- { \
- CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS \
- }
+ /** Peripheral CTIMER0 base address */
+ #define CTIMER0_BASE (0x50008000u)
+ /** Peripheral CTIMER0 base address */
+ #define CTIMER0_BASE_NS (0x40008000u)
+ /** Peripheral CTIMER0 base pointer */
+ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
+ /** Peripheral CTIMER0 base pointer */
+ #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS)
+ /** Peripheral CTIMER1 base address */
+ #define CTIMER1_BASE (0x50009000u)
+ /** Peripheral CTIMER1 base address */
+ #define CTIMER1_BASE_NS (0x40009000u)
+ /** Peripheral CTIMER1 base pointer */
+ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
+ /** Peripheral CTIMER1 base pointer */
+ #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS)
+ /** Peripheral CTIMER2 base address */
+ #define CTIMER2_BASE (0x50028000u)
+ /** Peripheral CTIMER2 base address */
+ #define CTIMER2_BASE_NS (0x40028000u)
+ /** Peripheral CTIMER2 base pointer */
+ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
+ /** Peripheral CTIMER2 base pointer */
+ #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS)
+ /** Peripheral CTIMER3 base address */
+ #define CTIMER3_BASE (0x50029000u)
+ /** Peripheral CTIMER3 base address */
+ #define CTIMER3_BASE_NS (0x40029000u)
+ /** Peripheral CTIMER3 base pointer */
+ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
+ /** Peripheral CTIMER3 base pointer */
+ #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS)
+ /** Peripheral CTIMER4 base address */
+ #define CTIMER4_BASE (0x5002A000u)
+ /** Peripheral CTIMER4 base address */
+ #define CTIMER4_BASE_NS (0x4002A000u)
+ /** Peripheral CTIMER4 base pointer */
+ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
+ /** Peripheral CTIMER4 base pointer */
+ #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS)
+ /** Array initializer of CTIMER peripheral base addresses */
+ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+ /** Array initializer of CTIMER peripheral base pointers */
+ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+ /** Array initializer of CTIMER peripheral base addresses */
+ #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }
+ /** Array initializer of CTIMER peripheral base pointers */
+ #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }
#else
-/** Peripheral CTIMER0 base address */
-#define CTIMER0_BASE (0x40008000u)
-/** Peripheral CTIMER0 base pointer */
-#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
-/** Peripheral CTIMER1 base address */
-#define CTIMER1_BASE (0x40009000u)
-/** Peripheral CTIMER1 base pointer */
-#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
-/** Peripheral CTIMER2 base address */
-#define CTIMER2_BASE (0x40028000u)
-/** Peripheral CTIMER2 base pointer */
-#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
-/** Peripheral CTIMER3 base address */
-#define CTIMER3_BASE (0x40029000u)
-/** Peripheral CTIMER3 base pointer */
-#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
-/** Peripheral CTIMER4 base address */
-#define CTIMER4_BASE (0x4002A000u)
-/** Peripheral CTIMER4 base pointer */
-#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
-/** Array initializer of CTIMER peripheral base addresses */
-#define CTIMER_BASE_ADDRS \
- { \
- CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE \
- }
-/** Array initializer of CTIMER peripheral base pointers */
-#define CTIMER_BASE_PTRS \
- { \
- CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 \
- }
+ /** Peripheral CTIMER0 base address */
+ #define CTIMER0_BASE (0x40008000u)
+ /** Peripheral CTIMER0 base pointer */
+ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
+ /** Peripheral CTIMER1 base address */
+ #define CTIMER1_BASE (0x40009000u)
+ /** Peripheral CTIMER1 base pointer */
+ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
+ /** Peripheral CTIMER2 base address */
+ #define CTIMER2_BASE (0x40028000u)
+ /** Peripheral CTIMER2 base pointer */
+ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
+ /** Peripheral CTIMER3 base address */
+ #define CTIMER3_BASE (0x40029000u)
+ /** Peripheral CTIMER3 base pointer */
+ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
+ /** Peripheral CTIMER4 base address */
+ #define CTIMER4_BASE (0x4002A000u)
+ /** Peripheral CTIMER4 base pointer */
+ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
+ /** Array initializer of CTIMER peripheral base addresses */
+ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+ /** Array initializer of CTIMER peripheral base pointers */
+ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
#endif
/** Interrupt vectors for the CTIMER peripheral type */
-#define CTIMER_IRQS \
- { \
- CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn \
- }
+#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
/*!
* @}
*/ /* end of group CTIMER_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- DBGMAILBOX Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -6888,13 +6549,12 @@ typedef struct
*/
/** DBGMAILBOX - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */
- __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */
- __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */
- uint8_t RESERVED_0[240];
- __I uint32_t ID; /**< Identification register, offset: 0xFC */
+typedef struct {
+ __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */
+ __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */
+ __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */
+ uint8_t RESERVED_0[240];
+ __I uint32_t ID; /**< Identification register, offset: 0xFC */
} DBGMAILBOX_Type;
/* ----------------------------------------------------------------------------
@@ -6908,130 +6568,116 @@ typedef struct
/*! @name CSW - CRC mode register */
/*! @{ */
-#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U)
-#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U)
+
+#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U)
+#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U)
/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation
*/
-#define DBGMAILBOX_CSW_RESYNCH_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK)
-#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U)
-#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U)
+#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK)
+
+#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U)
+#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U)
/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST)
*/
-#define DBGMAILBOX_CSW_REQ_PENDING(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK)
-#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U)
-#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U)
+#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK)
+
+#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U)
+#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U)
/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)
*/
-#define DBGMAILBOX_CSW_DBG_OR_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
-#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U)
-#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U)
+#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
+
+#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U)
+#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U)
/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM)
*/
-#define DBGMAILBOX_CSW_AHB_OR_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
-#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U)
-#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U)
+#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
+
+#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U)
+#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U)
/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to
* this bit will cause a soft reset for DM.
*/
-#define DBGMAILBOX_CSW_SOFT_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK)
-#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
-#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
+#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK)
+
+#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
+#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is
* not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)
*/
-#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
+#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK)
/*! @} */
/*! @name REQUEST - CRC seed register */
/*! @{ */
-#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU)
-#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U)
+
+#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU)
+#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U)
/*! REQ - Request Value
*/
-#define DBGMAILBOX_REQUEST_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK)
+#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK)
/*! @} */
/*! @name RETURN - Return value from ROM. */
/*! @{ */
-#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU)
-#define DBGMAILBOX_RETURN_RET_SHIFT (0U)
+
+#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU)
+#define DBGMAILBOX_RETURN_RET_SHIFT (0U)
/*! RET - The Return value from ROM.
*/
-#define DBGMAILBOX_RETURN_RET(x) \
- (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK)
+#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK)
/*! @} */
/*! @name ID - Identification register */
/*! @{ */
-#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU)
-#define DBGMAILBOX_ID_ID_SHIFT (0U)
+
+#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU)
+#define DBGMAILBOX_ID_ID_SHIFT (0U)
/*! ID - Identification value.
*/
-#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK)
+#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group DBGMAILBOX_Register_Masks */
+
/* DBGMAILBOX - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral DBGMAILBOX base address */
-#define DBGMAILBOX_BASE (0x5009C000u)
-/** Peripheral DBGMAILBOX base address */
-#define DBGMAILBOX_BASE_NS (0x4009C000u)
-/** Peripheral DBGMAILBOX base pointer */
-#define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
-/** Peripheral DBGMAILBOX base pointer */
-#define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS)
-/** Array initializer of DBGMAILBOX peripheral base addresses */
-#define DBGMAILBOX_BASE_ADDRS \
- { \
- DBGMAILBOX_BASE \
- }
-/** Array initializer of DBGMAILBOX peripheral base pointers */
-#define DBGMAILBOX_BASE_PTRS \
- { \
- DBGMAILBOX \
- }
-/** Array initializer of DBGMAILBOX peripheral base addresses */
-#define DBGMAILBOX_BASE_ADDRS_NS \
- { \
- DBGMAILBOX_BASE_NS \
- }
-/** Array initializer of DBGMAILBOX peripheral base pointers */
-#define DBGMAILBOX_BASE_PTRS_NS \
- { \
- DBGMAILBOX_NS \
- }
+ /** Peripheral DBGMAILBOX base address */
+ #define DBGMAILBOX_BASE (0x5009C000u)
+ /** Peripheral DBGMAILBOX base address */
+ #define DBGMAILBOX_BASE_NS (0x4009C000u)
+ /** Peripheral DBGMAILBOX base pointer */
+ #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
+ /** Peripheral DBGMAILBOX base pointer */
+ #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS)
+ /** Array initializer of DBGMAILBOX peripheral base addresses */
+ #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE }
+ /** Array initializer of DBGMAILBOX peripheral base pointers */
+ #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX }
+ /** Array initializer of DBGMAILBOX peripheral base addresses */
+ #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS }
+ /** Array initializer of DBGMAILBOX peripheral base pointers */
+ #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS }
#else
-/** Peripheral DBGMAILBOX base address */
-#define DBGMAILBOX_BASE (0x4009C000u)
-/** Peripheral DBGMAILBOX base pointer */
-#define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
-/** Array initializer of DBGMAILBOX peripheral base addresses */
-#define DBGMAILBOX_BASE_ADDRS \
- { \
- DBGMAILBOX_BASE \
- }
-/** Array initializer of DBGMAILBOX peripheral base pointers */
-#define DBGMAILBOX_BASE_PTRS \
- { \
- DBGMAILBOX \
- }
+ /** Peripheral DBGMAILBOX base address */
+ #define DBGMAILBOX_BASE (0x4009C000u)
+ /** Peripheral DBGMAILBOX base pointer */
+ #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE)
+ /** Array initializer of DBGMAILBOX peripheral base addresses */
+ #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE }
+ /** Array initializer of DBGMAILBOX peripheral base pointers */
+ #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX }
#endif
/*!
* @}
*/ /* end of group DBGMAILBOX_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -7042,53 +6688,43 @@ typedef struct
*/
/** DMA - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
- __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
- __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
- uint8_t RESERVED_0[20];
- struct
- { /* offset: 0x20, array step: 0x5C */
- __IO uint32_t
- ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
- uint8_t RESERVED_0[4];
- __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
- uint8_t RESERVED_1[4];
- __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
- uint8_t RESERVED_2[4];
- __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
- uint8_t RESERVED_3[4];
- __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
- uint8_t RESERVED_4[4];
- __IO uint32_t
- INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
- uint8_t RESERVED_5[4];
- __O uint32_t
- INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
- uint8_t RESERVED_6[4];
- __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
- uint8_t RESERVED_7[4];
- __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
- uint8_t RESERVED_8[4];
- __O uint32_t
- SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
- uint8_t RESERVED_9[4];
- __O uint32_t
- SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
- uint8_t RESERVED_10[4];
- __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
- } COMMON[1];
- uint8_t RESERVED_1[900];
- struct
- { /* offset: 0x400, array step: 0x10 */
- __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
- __I uint32_t
- CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
- __IO uint32_t
- XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
- uint8_t RESERVED_0[4];
- } CHANNEL[23];
+typedef struct {
+ __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
+ __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
+ __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ struct { /* offset: 0x20, array step: 0x5C */
+ __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+ uint8_t RESERVED_0[4];
+ __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+ uint8_t RESERVED_1[4];
+ __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+ uint8_t RESERVED_2[4];
+ __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+ uint8_t RESERVED_5[4];
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+ uint8_t RESERVED_7[4];
+ __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+ uint8_t RESERVED_8[4];
+ __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+ uint8_t RESERVED_9[4];
+ __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+ uint8_t RESERVED_10[4];
+ __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+ } COMMON[1];
+ uint8_t RESERVED_1[900];
+ struct { /* offset: 0x400, array step: 0x10 */
+ __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+ __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } CHANNEL[23];
} DMA_Type;
/* ----------------------------------------------------------------------------
@@ -7102,261 +6738,267 @@ typedef struct
/*! @name CTRL - DMA control. */
/*! @{ */
-#define DMA_CTRL_ENABLE_MASK (0x1U)
-#define DMA_CTRL_ENABLE_SHIFT (0U)
+
+#define DMA_CTRL_ENABLE_MASK (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT (0U)
/*! ENABLE - DMA controller master enable.
* 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
* disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
* 0b1..Enabled. The DMA controller is enabled.
*/
-#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
/*! @} */
/*! @name INTSTAT - Interrupt status. */
/*! @{ */
-#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
-#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
+
+#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
* 0b0..Not pending. No enabled interrupts are pending.
* 0b1..Pending. At least one enabled interrupt is pending.
*/
-#define DMA_INTSTAT_ACTIVEINT(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
-#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
-#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
+#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+
+#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
* 0b0..Not pending. No error interrupts are pending.
* 0b1..Pending. At least one error interrupt is pending.
*/
-#define DMA_INTSTAT_ACTIVEERRINT(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
/*! @} */
/*! @name SRAMBASE - SRAM address of the channel configuration table. */
/*! @{ */
-#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
-#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
+
+#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
* table must begin on a 512 byte boundary.
*/
-#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
/*! @} */
/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
+
+#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
* number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
*/
-#define DMA_COMMON_ENABLESET_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
/*! @} */
/* The count of DMA_COMMON_ENABLESET */
-#define DMA_COMMON_ENABLESET_COUNT (1U)
+#define DMA_COMMON_ENABLESET_COUNT (1U)
/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
+
+#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
* the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
* are reserved.
*/
-#define DMA_COMMON_ENABLECLR_CLR(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
/*! @} */
/* The count of DMA_COMMON_ENABLECLR */
-#define DMA_COMMON_ENABLECLR_COUNT (1U)
+#define DMA_COMMON_ENABLECLR_COUNT (1U)
/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
+
+#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
* number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
*/
-#define DMA_COMMON_ACTIVE_ACT(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
/*! @} */
/* The count of DMA_COMMON_ACTIVE */
-#define DMA_COMMON_ACTIVE_COUNT (1U)
+#define DMA_COMMON_ACTIVE_COUNT (1U)
/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
+
+#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
* number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
*/
-#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
/*! @} */
/* The count of DMA_COMMON_BUSY */
-#define DMA_COMMON_BUSY_COUNT (1U)
+#define DMA_COMMON_BUSY_COUNT (1U)
/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
+
+#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
* bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
* not active. 1 = error interrupt is active.
*/
-#define DMA_COMMON_ERRINT_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
/*! @} */
/* The count of DMA_COMMON_ERRINT */
-#define DMA_COMMON_ERRINT_COUNT (1U)
+#define DMA_COMMON_ERRINT_COUNT (1U)
/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
+
+#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
* number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
* interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
*/
-#define DMA_COMMON_INTENSET_INTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
/*! @} */
/* The count of DMA_COMMON_INTENSET */
-#define DMA_COMMON_INTENSET_COUNT (1U)
+#define DMA_COMMON_INTENSET_COUNT (1U)
/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
+
+#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
* corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
* reserved.
*/
-#define DMA_COMMON_INTENCLR_CLR(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
/*! @} */
/* The count of DMA_COMMON_INTENCLR */
-#define DMA_COMMON_INTENCLR_COUNT (1U)
+#define DMA_COMMON_INTENCLR_COUNT (1U)
/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTA_IA_SHIFT (0U)
+
+#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT (0U)
/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
* bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
* interrupt A is not active. 1 = the DMA channel interrupt A is active.
*/
-#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
/*! @} */
/* The count of DMA_COMMON_INTA */
-#define DMA_COMMON_INTA_COUNT (1U)
+#define DMA_COMMON_INTA_COUNT (1U)
/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTB_IB_SHIFT (0U)
+
+#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT (0U)
/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
* bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
* interrupt B is not active. 1 = the DMA channel interrupt B is active.
*/
-#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
/*! @} */
/* The count of DMA_COMMON_INTB */
-#define DMA_COMMON_INTB_COUNT (1U)
+#define DMA_COMMON_INTB_COUNT (1U)
/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
+
+#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
* = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
* VALIDPENDING control bit for DMA channel n
*/
-#define DMA_COMMON_SETVALID_SV(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
/*! @} */
/* The count of DMA_COMMON_SETVALID */
-#define DMA_COMMON_SETVALID_COUNT (1U)
+#define DMA_COMMON_SETVALID_COUNT (1U)
/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
+
+#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
* of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
* sets the TRIG bit for DMA channel n.
*/
-#define DMA_COMMON_SETTRIG_TRIG(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
/*! @} */
/* The count of DMA_COMMON_SETTRIG */
-#define DMA_COMMON_SETTRIG_COUNT (1U)
+#define DMA_COMMON_SETTRIG_COUNT (1U)
/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
/*! @{ */
-#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
+
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
* 1 = aborts DMA operations on channel n.
*/
-#define DMA_COMMON_ABORT_ABORTCTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
/*! @} */
/* The count of DMA_COMMON_ABORT */
-#define DMA_COMMON_ABORT_COUNT (1U)
+#define DMA_COMMON_ABORT_COUNT (1U)
/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
/*! @{ */
-#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
-#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
+
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
* move, any peripheral DMA request associated with that channel can be disabled to prevent any
* interaction between the peripheral and the DMA controller.
* 0b0..Disabled. Peripheral DMA requests are disabled.
* 0b1..Enabled. Peripheral DMA requests are enabled.
*/
-#define DMA_CHANNEL_CFG_PERIPHREQEN(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
-#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
-#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
/*! HWTRIGEN - Hardware Triggering Enable for this channel.
* 0b0..Disabled. Hardware triggering is not used.
* 0b1..Enabled. Use hardware triggering.
*/
-#define DMA_CHANNEL_CFG_HWTRIGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
-#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
-#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
+#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
* 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
* 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
*/
-#define DMA_CHANNEL_CFG_TRIGPOL(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
-#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
-#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
+#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
- * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single
- * trigger. 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
+ * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
+ * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
* 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
* trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
* is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
* current BURSTPOWER length are completed.
*/
-#define DMA_CHANNEL_CFG_TRIGTYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
-#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
-#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
+#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
* 0b0..Single transfer. Hardware trigger causes a single transfer.
* 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
@@ -7364,10 +7006,10 @@ typedef struct
* hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
* complete.
*/
-#define DMA_CHANNEL_CFG_TRIGBURST(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
-#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
-#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
+#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
* SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
* When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
@@ -7378,10 +7020,10 @@ typedef struct
* total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
* multiple of the burst size.
*/
-#define DMA_CHANNEL_CFG_BURSTPOWER(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
+#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
* 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
* could be used to read several sequential registers from a peripheral for each DMA burst,
@@ -7389,10 +7031,10 @@ typedef struct
* 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
* 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
*/
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
* 'wrapped', meaning that the destination address range for each burst will be the same. As an
* example, this could be used to write several sequential registers to a peripheral for each DMA
@@ -7400,126 +7042,126 @@ typedef struct
* 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
* 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
*/
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
-#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
-#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
* levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
*/
-#define DMA_CHANNEL_CFG_CHPRIORITY(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
/*! @} */
/* The count of DMA_CHANNEL_CFG */
-#define DMA_CHANNEL_CFG_COUNT (23U)
+#define DMA_CHANNEL_CFG_COUNT (23U)
/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
/*! @{ */
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
+
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
* corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
* 0b0..No effect. No effect on DMA operation.
* 0b1..Valid pending.
*/
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
-#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
-#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
* cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
* 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
* 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
*/
-#define DMA_CHANNEL_CTLSTAT_TRIG(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
/*! @} */
/* The count of DMA_CHANNEL_CTLSTAT */
-#define DMA_CHANNEL_CTLSTAT_COUNT (23U)
+#define DMA_CHANNEL_CTLSTAT_COUNT (23U)
/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
/*! @{ */
-#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
-#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
+
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
* is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
* 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
* 0b1..Valid. The current channel descriptor is considered valid.
*/
-#define DMA_CHANNEL_XFERCFG_CFGVALID(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
-#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
-#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
* descriptor is exhausted. Reloading allows ping-pong and linked transfers.
* 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
* 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
*/
-#define DMA_CHANNEL_XFERCFG_RELOAD(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
-#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
-#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
/*! SWTRIG - Software Trigger.
* 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
* the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
* 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
* be used with level triggering when TRIGBURST = 0.
*/
-#define DMA_CHANNEL_XFERCFG_SWTRIG(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
/*! CLRTRIG - Clear Trigger.
- * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next
- * descriptor will be started. 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
+ * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
+ * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
*/
-#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
-#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
-#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
* interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
* convention, interrupt A may be used when only one interrupt flag is needed.
* 0b0..No effect.
* 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
*/
-#define DMA_CHANNEL_XFERCFG_SETINTA(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
-#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
-#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
+#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
* interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
* convention, interrupt A may be used when only one interrupt flag is needed.
* 0b0..No effect.
* 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
*/
-#define DMA_CHANNEL_XFERCFG_SETINTB(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
-#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
-#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
+#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
/*! WIDTH - Transfer width used for this DMA channel.
* 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
* 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
* 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
* 0b11..Reserved. Reserved setting, do not use.
*/
-#define DMA_CHANNEL_XFERCFG_WIDTH(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
-#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
-#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
+#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
- * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source
- * is a peripheral device. 0b01..1 x width. The source address is incremented by the amount specified by Width for each
- * transfer. This is the usual case when the source is memory. 0b10..2 x width. The source address is incremented by 2
- * times the amount specified by Width for each transfer. 0b11..4 x width. The source address is incremented by 4 times
- * the amount specified by Width for each transfer.
- */
-#define DMA_CHANNEL_XFERCFG_SRCINC(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
-#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
-#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
+ * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
+ * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
+ * the usual case when the source is memory.
+ * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
+ * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
+ */
+#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
* 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
* the destination is a peripheral device.
@@ -7528,10 +7170,10 @@ typedef struct
* 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
* 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
*/
-#define DMA_CHANNEL_XFERCFG_DSTINC(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
+#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
* transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
* uses this bit field during transfer to count down. Hence, it cannot be used by software to read
@@ -7539,85 +7181,66 @@ typedef struct
* transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
* 1,024 transfers will be performed.
*/
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
/*! @} */
/* The count of DMA_CHANNEL_XFERCFG */
-#define DMA_CHANNEL_XFERCFG_COUNT (23U)
+#define DMA_CHANNEL_XFERCFG_COUNT (23U)
+
/*!
* @}
*/ /* end of group DMA_Register_Masks */
+
/* DMA - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral DMA0 base address */
-#define DMA0_BASE (0x50082000u)
-/** Peripheral DMA0 base address */
-#define DMA0_BASE_NS (0x40082000u)
-/** Peripheral DMA0 base pointer */
-#define DMA0 ((DMA_Type *)DMA0_BASE)
-/** Peripheral DMA0 base pointer */
-#define DMA0_NS ((DMA_Type *)DMA0_BASE_NS)
-/** Peripheral DMA1 base address */
-#define DMA1_BASE (0x500A7000u)
-/** Peripheral DMA1 base address */
-#define DMA1_BASE_NS (0x400A7000u)
-/** Peripheral DMA1 base pointer */
-#define DMA1 ((DMA_Type *)DMA1_BASE)
-/** Peripheral DMA1 base pointer */
-#define DMA1_NS ((DMA_Type *)DMA1_BASE_NS)
-/** Array initializer of DMA peripheral base addresses */
-#define DMA_BASE_ADDRS \
- { \
- DMA0_BASE, DMA1_BASE \
- }
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASE_PTRS \
- { \
- DMA0, DMA1 \
- }
-/** Array initializer of DMA peripheral base addresses */
-#define DMA_BASE_ADDRS_NS \
- { \
- DMA0_BASE_NS, DMA1_BASE_NS \
- }
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASE_PTRS_NS \
- { \
- DMA0_NS, DMA1_NS \
- }
+ /** Peripheral DMA0 base address */
+ #define DMA0_BASE (0x50082000u)
+ /** Peripheral DMA0 base address */
+ #define DMA0_BASE_NS (0x40082000u)
+ /** Peripheral DMA0 base pointer */
+ #define DMA0 ((DMA_Type *)DMA0_BASE)
+ /** Peripheral DMA0 base pointer */
+ #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS)
+ /** Peripheral DMA1 base address */
+ #define DMA1_BASE (0x500A7000u)
+ /** Peripheral DMA1 base address */
+ #define DMA1_BASE_NS (0x400A7000u)
+ /** Peripheral DMA1 base pointer */
+ #define DMA1 ((DMA_Type *)DMA1_BASE)
+ /** Peripheral DMA1 base pointer */
+ #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS)
+ /** Array initializer of DMA peripheral base addresses */
+ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
+ /** Array initializer of DMA peripheral base pointers */
+ #define DMA_BASE_PTRS { DMA0, DMA1 }
+ /** Array initializer of DMA peripheral base addresses */
+ #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS }
+ /** Array initializer of DMA peripheral base pointers */
+ #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS }
#else
-/** Peripheral DMA0 base address */
-#define DMA0_BASE (0x40082000u)
-/** Peripheral DMA0 base pointer */
-#define DMA0 ((DMA_Type *)DMA0_BASE)
-/** Peripheral DMA1 base address */
-#define DMA1_BASE (0x400A7000u)
-/** Peripheral DMA1 base pointer */
-#define DMA1 ((DMA_Type *)DMA1_BASE)
-/** Array initializer of DMA peripheral base addresses */
-#define DMA_BASE_ADDRS \
- { \
- DMA0_BASE, DMA1_BASE \
- }
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASE_PTRS \
- { \
- DMA0, DMA1 \
- }
+ /** Peripheral DMA0 base address */
+ #define DMA0_BASE (0x40082000u)
+ /** Peripheral DMA0 base pointer */
+ #define DMA0 ((DMA_Type *)DMA0_BASE)
+ /** Peripheral DMA1 base address */
+ #define DMA1_BASE (0x400A7000u)
+ /** Peripheral DMA1 base pointer */
+ #define DMA1 ((DMA_Type *)DMA1_BASE)
+ /** Array initializer of DMA peripheral base addresses */
+ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }
+ /** Array initializer of DMA peripheral base pointers */
+ #define DMA_BASE_PTRS { DMA0, DMA1 }
#endif
/** Interrupt vectors for the DMA peripheral type */
-#define DMA_IRQS \
- { \
- DMA0_IRQn, DMA1_IRQn \
- }
+#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn }
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- FLASH Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -7628,25 +7251,23 @@ typedef struct
*/
/** FLASH - Register Layout Typedef */
-typedef struct
-{
- __O uint32_t CMD; /**< command register, offset: 0x0 */
- __O uint32_t EVENT; /**< event register, offset: 0x4 */
- uint8_t RESERVED_0[8];
- __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */
- __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */
- uint8_t RESERVED_1[104];
- __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array
- offset: 0x80, array step: 0x4 */
- uint8_t RESERVED_2[3912];
- __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */
- __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */
- __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */
- __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */
- __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */
- __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */
- uint8_t RESERVED_3[12];
- __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */
+typedef struct {
+ __O uint32_t CMD; /**< command register, offset: 0x0 */
+ __O uint32_t EVENT; /**< event register, offset: 0x4 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */
+ __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */
+ uint8_t RESERVED_1[104];
+ __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_2[3912];
+ __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */
+ __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */
+ __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */
+ __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */
+ __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */
+ __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */
+ uint8_t RESERVED_3[12];
+ __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */
} FLASH_Type;
/* ----------------------------------------------------------------------------
@@ -7660,317 +7281,306 @@ typedef struct
/*! @name CMD - command register */
/*! @{ */
-#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU)
-#define FLASH_CMD_CMD_SHIFT (0U)
+
+#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU)
+#define FLASH_CMD_CMD_SHIFT (0U)
/*! CMD - command register.
*/
-#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK)
+#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK)
/*! @} */
/*! @name EVENT - event register */
/*! @{ */
-#define FLASH_EVENT_RST_MASK (0x1U)
-#define FLASH_EVENT_RST_SHIFT (0U)
+
+#define FLASH_EVENT_RST_MASK (0x1U)
+#define FLASH_EVENT_RST_SHIFT (0U)
/*! RST - When bit is set, the controller and flash are reset.
*/
-#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK)
-#define FLASH_EVENT_WAKEUP_MASK (0x2U)
-#define FLASH_EVENT_WAKEUP_SHIFT (1U)
+#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK)
+
+#define FLASH_EVENT_WAKEUP_MASK (0x2U)
+#define FLASH_EVENT_WAKEUP_SHIFT (1U)
/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active.
*/
-#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK)
-#define FLASH_EVENT_ABORT_MASK (0x4U)
-#define FLASH_EVENT_ABORT_SHIFT (2U)
+#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK)
+
+#define FLASH_EVENT_ABORT_MASK (0x4U)
+#define FLASH_EVENT_ABORT_SHIFT (2U)
/*! ABORT - When bit is set, a running program/erase command is aborted.
*/
-#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK)
+#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK)
/*! @} */
/*! @name STARTA - start (or only) address for next flash command */
/*! @{ */
-#define FLASH_STARTA_STARTA_MASK (0x3FFFFU)
-#define FLASH_STARTA_STARTA_SHIFT (0U)
+
+#define FLASH_STARTA_STARTA_MASK (0x3FFFFU)
+#define FLASH_STARTA_STARTA_SHIFT (0U)
/*! STARTA - Address / Start address for commands that take an address (range) as a parameter.
*/
-#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK)
+#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK)
/*! @} */
/*! @name STOPA - end address for next flash command, if command operates on address ranges */
/*! @{ */
-#define FLASH_STOPA_STOPA_MASK (0x3FFFFU)
-#define FLASH_STOPA_STOPA_SHIFT (0U)
+
+#define FLASH_STOPA_STOPA_MASK (0x3FFFFU)
+#define FLASH_STOPA_STOPA_SHIFT (0U)
/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified
* by STOPA is included in the address range).
*/
-#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
+#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)
/*! @} */
/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */
/*! @{ */
-#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU)
-#define FLASH_DATAW_DATAW_SHIFT (0U)
-#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
+
+#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU)
+#define FLASH_DATAW_DATAW_SHIFT (0U)
+#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)
/*! @} */
/* The count of FLASH_DATAW */
-#define FLASH_DATAW_COUNT (4U)
+#define FLASH_DATAW_COUNT (4U)
/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */
/*! @{ */
-#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U)
-#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U)
+
+#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U)
+#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U)
/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
*/
-#define FLASH_INT_CLR_ENABLE_FAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK)
-#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U)
-#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U)
+#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK)
+
+#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U)
+#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U)
/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
*/
-#define FLASH_INT_CLR_ENABLE_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK)
-#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U)
-#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U)
+#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK)
+
+#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U)
+#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U)
/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
*/
-#define FLASH_INT_CLR_ENABLE_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK)
-#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U)
-#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U)
+#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK)
+
+#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U)
+#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U)
/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared.
*/
-#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK)
+#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK)
/*! @} */
/*! @name INT_SET_ENABLE - Set interrupt enable bits */
/*! @{ */
-#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U)
-#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U)
+
+#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U)
+#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U)
/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
*/
-#define FLASH_INT_SET_ENABLE_FAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK)
-#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U)
-#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U)
+#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK)
+
+#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U)
+#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U)
/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
*/
-#define FLASH_INT_SET_ENABLE_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK)
-#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U)
-#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U)
+#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK)
+
+#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U)
+#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U)
/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
*/
-#define FLASH_INT_SET_ENABLE_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK)
-#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U)
-#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U)
+#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK)
+
+#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U)
+#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U)
/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set.
*/
-#define FLASH_INT_SET_ENABLE_ECC_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK)
+#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt status bits */
/*! @{ */
-#define FLASH_INT_STATUS_FAIL_MASK (0x1U)
-#define FLASH_INT_STATUS_FAIL_SHIFT (0U)
+
+#define FLASH_INT_STATUS_FAIL_MASK (0x1U)
+#define FLASH_INT_STATUS_FAIL_SHIFT (0U)
/*! FAIL - This status bit is set if execution of a (legal) command failed.
*/
-#define FLASH_INT_STATUS_FAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK)
-#define FLASH_INT_STATUS_ERR_MASK (0x2U)
-#define FLASH_INT_STATUS_ERR_SHIFT (1U)
+#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK)
+
+#define FLASH_INT_STATUS_ERR_MASK (0x2U)
+#define FLASH_INT_STATUS_ERR_SHIFT (1U)
/*! ERR - This status bit is set if execution of an illegal command is detected.
*/
-#define FLASH_INT_STATUS_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK)
-#define FLASH_INT_STATUS_DONE_MASK (0x4U)
-#define FLASH_INT_STATUS_DONE_SHIFT (2U)
+#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK)
+
+#define FLASH_INT_STATUS_DONE_MASK (0x4U)
+#define FLASH_INT_STATUS_DONE_SHIFT (2U)
/*! DONE - This status bit is set at the end of command execution.
*/
-#define FLASH_INT_STATUS_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK)
-#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U)
-#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U)
+#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK)
+
+#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U)
+#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U)
/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested
* read, or a speculative read, or reads performed by a controller command), a correctable or
* uncorrectable error is detected by ECC decoding logic.
*/
-#define FLASH_INT_STATUS_ECC_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK)
+#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK)
/*! @} */
/*! @name INT_ENABLE - Interrupt enable bits */
/*! @{ */
-#define FLASH_INT_ENABLE_FAIL_MASK (0x1U)
-#define FLASH_INT_ENABLE_FAIL_SHIFT (0U)
-/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is
- * high.
+
+#define FLASH_INT_ENABLE_FAIL_MASK (0x1U)
+#define FLASH_INT_ENABLE_FAIL_SHIFT (0U)
+/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
*/
-#define FLASH_INT_ENABLE_FAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK)
-#define FLASH_INT_ENABLE_ERR_MASK (0x2U)
-#define FLASH_INT_ENABLE_ERR_SHIFT (1U)
-/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is
- * high.
+#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK)
+
+#define FLASH_INT_ENABLE_ERR_MASK (0x2U)
+#define FLASH_INT_ENABLE_ERR_SHIFT (1U)
+/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
*/
-#define FLASH_INT_ENABLE_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK)
-#define FLASH_INT_ENABLE_DONE_MASK (0x4U)
-#define FLASH_INT_ENABLE_DONE_SHIFT (2U)
-/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is
- * high.
+#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK)
+
+#define FLASH_INT_ENABLE_DONE_MASK (0x4U)
+#define FLASH_INT_ENABLE_DONE_SHIFT (2U)
+/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
*/
-#define FLASH_INT_ENABLE_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK)
-#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U)
-#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U)
-/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is
- * high.
+#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK)
+
+#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U)
+#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U)
+/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high.
*/
-#define FLASH_INT_ENABLE_ECC_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK)
+#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK)
/*! @} */
/*! @name INT_CLR_STATUS - Clear interrupt status bits */
/*! @{ */
-#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U)
-#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U)
+
+#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U)
+#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U)
/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
*/
-#define FLASH_INT_CLR_STATUS_FAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK)
-#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U)
-#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U)
+#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK)
+
+#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U)
+#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U)
/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
*/
-#define FLASH_INT_CLR_STATUS_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK)
-#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U)
-#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U)
+#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK)
+
+#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U)
+#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U)
/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
*/
-#define FLASH_INT_CLR_STATUS_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK)
-#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U)
-#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U)
+#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK)
+
+#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U)
+#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U)
/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared.
*/
-#define FLASH_INT_CLR_STATUS_ECC_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK)
+#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK)
/*! @} */
/*! @name INT_SET_STATUS - Set interrupt status bits */
/*! @{ */
-#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U)
-#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U)
+
+#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U)
+#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U)
/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
*/
-#define FLASH_INT_SET_STATUS_FAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK)
-#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U)
-#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U)
+#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK)
+
+#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U)
+#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U)
/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
*/
-#define FLASH_INT_SET_STATUS_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK)
-#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U)
-#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U)
+#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK)
+
+#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U)
+#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U)
/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
*/
-#define FLASH_INT_SET_STATUS_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK)
-#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U)
-#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U)
+#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK)
+
+#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U)
+#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U)
/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set.
*/
-#define FLASH_INT_SET_STATUS_ECC_ERR(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK)
+#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK)
/*! @} */
/*! @name MODULE_ID - Controller+Memory module identification */
/*! @{ */
-#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU)
-#define FLASH_MODULE_ID_APERTURE_SHIFT (0U)
+
+#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU)
+#define FLASH_MODULE_ID_APERTURE_SHIFT (0U)
/*! APERTURE - Aperture i.
*/
-#define FLASH_MODULE_ID_APERTURE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK)
-#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U)
-#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U)
+#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK)
+
+#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U)
+#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U)
/*! MINOR_REV - Minor revision i.
*/
-#define FLASH_MODULE_ID_MINOR_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK)
-#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U)
-#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U)
+#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK)
+
+#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U)
+#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U)
/*! MAJOR_REV - Major revision i.
*/
-#define FLASH_MODULE_ID_MAJOR_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK)
-#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U)
-#define FLASH_MODULE_ID_ID_SHIFT (16U)
+#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK)
+
+#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U)
+#define FLASH_MODULE_ID_ID_SHIFT (16U)
/*! ID - Identifier.
*/
-#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK)
+#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group FLASH_Register_Masks */
+
/* FLASH - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral FLASH base address */
-#define FLASH_BASE (0x50034000u)
-/** Peripheral FLASH base address */
-#define FLASH_BASE_NS (0x40034000u)
-/** Peripheral FLASH base pointer */
-#define FLASH ((FLASH_Type *)FLASH_BASE)
-/** Peripheral FLASH base pointer */
-#define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS)
-/** Array initializer of FLASH peripheral base addresses */
-#define FLASH_BASE_ADDRS \
- { \
- FLASH_BASE \
- }
-/** Array initializer of FLASH peripheral base pointers */
-#define FLASH_BASE_PTRS \
- { \
- FLASH \
- }
-/** Array initializer of FLASH peripheral base addresses */
-#define FLASH_BASE_ADDRS_NS \
- { \
- FLASH_BASE_NS \
- }
-/** Array initializer of FLASH peripheral base pointers */
-#define FLASH_BASE_PTRS_NS \
- { \
- FLASH_NS \
- }
+ /** Peripheral FLASH base address */
+ #define FLASH_BASE (0x50034000u)
+ /** Peripheral FLASH base address */
+ #define FLASH_BASE_NS (0x40034000u)
+ /** Peripheral FLASH base pointer */
+ #define FLASH ((FLASH_Type *)FLASH_BASE)
+ /** Peripheral FLASH base pointer */
+ #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS)
+ /** Array initializer of FLASH peripheral base addresses */
+ #define FLASH_BASE_ADDRS { FLASH_BASE }
+ /** Array initializer of FLASH peripheral base pointers */
+ #define FLASH_BASE_PTRS { FLASH }
+ /** Array initializer of FLASH peripheral base addresses */
+ #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS }
+ /** Array initializer of FLASH peripheral base pointers */
+ #define FLASH_BASE_PTRS_NS { FLASH_NS }
#else
-/** Peripheral FLASH base address */
-#define FLASH_BASE (0x40034000u)
-/** Peripheral FLASH base pointer */
-#define FLASH ((FLASH_Type *)FLASH_BASE)
-/** Array initializer of FLASH peripheral base addresses */
-#define FLASH_BASE_ADDRS \
- { \
- FLASH_BASE \
- }
-/** Array initializer of FLASH peripheral base pointers */
-#define FLASH_BASE_PTRS \
- { \
- FLASH \
- }
+ /** Peripheral FLASH base address */
+ #define FLASH_BASE (0x40034000u)
+ /** Peripheral FLASH base pointer */
+ #define FLASH ((FLASH_Type *)FLASH_BASE)
+ /** Array initializer of FLASH peripheral base addresses */
+ #define FLASH_BASE_ADDRS { FLASH_BASE }
+ /** Array initializer of FLASH peripheral base pointers */
+ #define FLASH_BASE_PTRS { FLASH }
#endif
/*!
* @}
*/ /* end of group FLASH_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- FLASH_CFPA Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -7981,71 +7591,46 @@ typedef struct
*/
/** FLASH_CFPA - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t HEADER; /**< ., offset: 0x0 */
- __IO uint32_t VERSION; /**< ., offset: 0x4 */
- __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */
- __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */
- __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */
- uint8_t RESERVED_0[4];
- __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */
- __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */
- __IO uint32_t
- DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2
- customers who develops non-secure code only. - In this scenario, or easy of development,
- Level-I customer releases the part to always allow non-secure debug. - To allow level-2
- customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to
- further restrict the debug access., offset: 0x20 */
- __IO uint32_t
- DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2
- customers who develops non-secure code only. - In this scenario, or easy of development,
- Level-I customer releases the part to always allow non-secure debug. - To allow level-2
- customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to
- further restrict the debug access., offset: 0x24 */
- __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to
- indicate boot ROM to enter FA mode., offset: 0x28 */
- __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in
- the active CFPA page each time CMPA page programming is going on. It shall
- always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */
- union
- { /* offset: 0x30 */
- __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */
- struct
- { /* offset: 0x30 */
- __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */
- __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */
- __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */
- } PRINCE_REGION0_IV_CODE_CORE;
- };
- union
- { /* offset: 0x68 */
- __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */
- struct
- { /* offset: 0x68 */
- __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */
- __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */
- __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */
- } PRINCE_REGION1_IV_CODE_CORE;
- };
- union
- { /* offset: 0xA0 */
- __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */
- struct
- { /* offset: 0xA0 */
- __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */
- __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */
- __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */
- } PRINCE_REGION2_IV_CODE_CORE;
- };
- uint8_t RESERVED_1[40];
- __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array
- step: 0x4 */
- __IO uint32_t
- SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for
- DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128]
- SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for
- DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
+typedef struct {
+ __IO uint32_t HEADER; /**< ., offset: 0x0 */
+ __IO uint32_t VERSION; /**< ., offset: 0x4 */
+ __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */
+ __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */
+ __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */
+ __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */
+ __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */
+ __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */
+ __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */
+ __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */
+ union { /* offset: 0x30 */
+ __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */
+ struct { /* offset: 0x30 */
+ __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */
+ __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */
+ __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */
+ } PRINCE_REGION0_IV_CODE_CORE;
+ };
+ union { /* offset: 0x68 */
+ __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */
+ struct { /* offset: 0x68 */
+ __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */
+ __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */
+ __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */
+ } PRINCE_REGION1_IV_CODE_CORE;
+ };
+ union { /* offset: 0xA0 */
+ __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */
+ struct { /* offset: 0xA0 */
+ __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */
+ __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */
+ __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */
+ } PRINCE_REGION2_IV_CODE_CORE;
+ };
+ uint8_t RESERVED_1[40];
+ __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */
+ __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
} FLASH_CFPA_Type;
/* ----------------------------------------------------------------------------
@@ -8059,629 +7644,568 @@ typedef struct
/*! @name HEADER - . */
/*! @{ */
-#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_HEADER_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK)
+#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK)
/*! @} */
/*! @name VERSION - . */
/*! @{ */
-#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_VERSION_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK)
+#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK)
/*! @} */
/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */
/*! @{ */
-#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_S_FW_VERSION_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK)
+#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK)
/*! @} */
/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */
/*! @{ */
-#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK)
+#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK)
/*! @} */
/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */
/*! @{ */
-#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK)
+#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK)
/*! @} */
/*! @name ROTKH_REVOKE - . */
/*! @{ */
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U)
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U)
+
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U)
/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
*/
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK)
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU)
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK)
+
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U)
/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
*/
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK)
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U)
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK)
+
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U)
/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
*/
-#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK)
+
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U)
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U)
+/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked
+ */
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK)
/*! @} */
/*! @name VENDOR_USAGE - . */
/*! @{ */
+
#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU)
#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U)
/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE.
*/
-#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & \
- FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK)
+#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK)
+
#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U)
#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U)
/*! INVERSE_VALUE - inverse value of bits [15:0]
*/
-#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & \
- FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK)
+#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK)
/*! @} */
-/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2
- * customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases
- * the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is
- * used. - ROM will use this word to further restrict the debug access. */
+/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */
/*! @{ */
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U)
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U)
/*! NIDEN - Non Secure non-invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK)
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U)
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U)
/*! DBGEN - Non Secure debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)
/*! SPNIDEN - Secure non-invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK)
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U)
/*! SPIDEN - Secure invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK)
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U)
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U)
/*! TAPEN - JTAG TAP enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U)
/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)
/*! ISP_CMD_EN - ISP Boot Command enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)
/*! FA_CMD_EN - FA Command enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)
/*! ME_CMD_EN - Flash Mass Erase Command enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U)
/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)
/*! UUID_CHECK - Enforce UUID match during Debug authentication.
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)
#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)
/*! INVERSE_VALUE - inverse value of bits [15:0]
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK)
/*! @} */
-/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2
- * customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases
- * the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is
- * used. - ROM will use this word to further restrict the debug access. */
+/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */
/*! @{ */
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U)
/*! NIDEN - Non Secure non-invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK)
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U)
/*! DBGEN - Non Secure debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)
/*! SPNIDEN - Secure non-invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)
/*! SPIDEN - Secure invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK)
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK)
+
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U)
/*! TAPEN - JTAG TAP fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U)
/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)
/*! ISP_CMD_EN - ISP Boot Command fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)
/*! FA_CMD_EN - FA Command fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)
/*! ME_CMD_EN - Flash Mass Erase Command fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U)
/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
+
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)
#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)
/*! INVERSE_VALUE - inverse value of bits [15:0]
*/
-#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & \
- FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
/*! @} */
-/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM
- * to enter FA mode. */
+/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */
/*! @{ */
-#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK)
+#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK)
/*! @} */
-/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active
- * CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.
- */
+/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */
/*! @{ */
+
#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & \
- FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK)
+#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION0_IV_CODE - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */
-#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U)
+#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U)
/*! @name PRINCE_REGION0_IV_HEADER0 - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION0_IV_HEADER1 - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U)
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK)
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK)
+
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK)
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK)
+
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK)
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK)
/*! @} */
/*! @name PRINCE_REGION0_IV_BODY - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */
-#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U)
+#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U)
/*! @name PRINCE_REGION1_IV_CODE - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */
-#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U)
+#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U)
/*! @name PRINCE_REGION1_IV_HEADER0 - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION1_IV_HEADER1 - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U)
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK)
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK)
+
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK)
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK)
+
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK)
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK)
/*! @} */
/*! @name PRINCE_REGION1_IV_BODY - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */
-#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U)
+#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U)
/*! @name PRINCE_REGION2_IV_CODE - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */
-#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U)
+#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U)
/*! @name PRINCE_REGION2_IV_HEADER0 - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION2_IV_HEADER1 - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U)
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK)
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK)
+
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK)
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK)
+
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK)
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK)
/*! @} */
/*! @name PRINCE_REGION2_IV_BODY - . */
/*! @{ */
+
#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & \
- FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK)
+#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */
-#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U)
+#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U)
/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */
/*! @{ */
-#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK)
+#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_CUSTOMER_DEFINED */
-#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U)
+#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U)
-/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for
- * DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160]
- * SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */
+/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */
/*! @{ */
-#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U)
+
+#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK)
+#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK)
/*! @} */
/* The count of FLASH_CFPA_SHA256_DIGEST */
-#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U)
+#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U)
+
/*!
* @}
*/ /* end of group FLASH_CFPA_Register_Masks */
+
/* FLASH_CFPA - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral FLASH_CFPA0 base address */
-#define FLASH_CFPA0_BASE (0x1009E000u)
-/** Peripheral FLASH_CFPA0 base address */
-#define FLASH_CFPA0_BASE_NS (0x9E000u)
-/** Peripheral FLASH_CFPA0 base pointer */
-#define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
-/** Peripheral FLASH_CFPA0 base pointer */
-#define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS)
-/** Peripheral FLASH_CFPA1 base address */
-#define FLASH_CFPA1_BASE (0x1009E200u)
-/** Peripheral FLASH_CFPA1 base address */
-#define FLASH_CFPA1_BASE_NS (0x9E200u)
-/** Peripheral FLASH_CFPA1 base pointer */
-#define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
-/** Peripheral FLASH_CFPA1 base pointer */
-#define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS)
-/** Peripheral FLASH_CFPA_SCRATCH base address */
-#define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u)
-/** Peripheral FLASH_CFPA_SCRATCH base address */
-#define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u)
-/** Peripheral FLASH_CFPA_SCRATCH base pointer */
-#define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
-/** Peripheral FLASH_CFPA_SCRATCH base pointer */
-#define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS)
-/** Array initializer of FLASH_CFPA peripheral base addresses */
-#define FLASH_CFPA_BASE_ADDRS \
- { \
- FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE \
- }
-/** Array initializer of FLASH_CFPA peripheral base pointers */
-#define FLASH_CFPA_BASE_PTRS \
- { \
- FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH \
- }
-/** Array initializer of FLASH_CFPA peripheral base addresses */
-#define FLASH_CFPA_BASE_ADDRS_NS \
- { \
- FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS \
- }
-/** Array initializer of FLASH_CFPA peripheral base pointers */
-#define FLASH_CFPA_BASE_PTRS_NS \
- { \
- FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS \
- }
+ /** Peripheral FLASH_CFPA0 base address */
+ #define FLASH_CFPA0_BASE (0x1009E000u)
+ /** Peripheral FLASH_CFPA0 base address */
+ #define FLASH_CFPA0_BASE_NS (0x9E000u)
+ /** Peripheral FLASH_CFPA0 base pointer */
+ #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
+ /** Peripheral FLASH_CFPA0 base pointer */
+ #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS)
+ /** Peripheral FLASH_CFPA1 base address */
+ #define FLASH_CFPA1_BASE (0x1009E200u)
+ /** Peripheral FLASH_CFPA1 base address */
+ #define FLASH_CFPA1_BASE_NS (0x9E200u)
+ /** Peripheral FLASH_CFPA1 base pointer */
+ #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
+ /** Peripheral FLASH_CFPA1 base pointer */
+ #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS)
+ /** Peripheral FLASH_CFPA_SCRATCH base address */
+ #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u)
+ /** Peripheral FLASH_CFPA_SCRATCH base address */
+ #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u)
+ /** Peripheral FLASH_CFPA_SCRATCH base pointer */
+ #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
+ /** Peripheral FLASH_CFPA_SCRATCH base pointer */
+ #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS)
+ /** Array initializer of FLASH_CFPA peripheral base addresses */
+ #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }
+ /** Array initializer of FLASH_CFPA peripheral base pointers */
+ #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }
+ /** Array initializer of FLASH_CFPA peripheral base addresses */
+ #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS }
+ /** Array initializer of FLASH_CFPA peripheral base pointers */
+ #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS }
#else
-/** Peripheral FLASH_CFPA0 base address */
-#define FLASH_CFPA0_BASE (0x9E000u)
-/** Peripheral FLASH_CFPA0 base pointer */
-#define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
-/** Peripheral FLASH_CFPA1 base address */
-#define FLASH_CFPA1_BASE (0x9E200u)
-/** Peripheral FLASH_CFPA1 base pointer */
-#define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
-/** Peripheral FLASH_CFPA_SCRATCH base address */
-#define FLASH_CFPA_SCRATCH_BASE (0x9DE00u)
-/** Peripheral FLASH_CFPA_SCRATCH base pointer */
-#define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
-/** Array initializer of FLASH_CFPA peripheral base addresses */
-#define FLASH_CFPA_BASE_ADDRS \
- { \
- FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE \
- }
-/** Array initializer of FLASH_CFPA peripheral base pointers */
-#define FLASH_CFPA_BASE_PTRS \
- { \
- FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH \
- }
+ /** Peripheral FLASH_CFPA0 base address */
+ #define FLASH_CFPA0_BASE (0x9E000u)
+ /** Peripheral FLASH_CFPA0 base pointer */
+ #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)
+ /** Peripheral FLASH_CFPA1 base address */
+ #define FLASH_CFPA1_BASE (0x9E200u)
+ /** Peripheral FLASH_CFPA1 base pointer */
+ #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)
+ /** Peripheral FLASH_CFPA_SCRATCH base address */
+ #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u)
+ /** Peripheral FLASH_CFPA_SCRATCH base pointer */
+ #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)
+ /** Array initializer of FLASH_CFPA peripheral base addresses */
+ #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }
+ /** Array initializer of FLASH_CFPA peripheral base pointers */
+ #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }
#endif
/*!
* @}
*/ /* end of group FLASH_CFPA_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- FLASH_CMPA Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -8692,36 +8216,26 @@ typedef struct
*/
/** FLASH_CMPA - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */
- __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */
- __IO uint32_t USB_ID; /**< ., offset: 0x8 */
- __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */
- __IO uint32_t CC_SOCU_PIN; /**< ., offset: 0x10 */
- __IO uint32_t CC_SOCU_DFLT; /**< ., offset: 0x14 */
- __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x18 */
- __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */
- __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */
- __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */
- __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */
- __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */
- __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */
- __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table
- hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust
- Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root
- of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7
- for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */
- uint8_t RESERVED_1[144];
- __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array
- step: 0x4 */
- __IO uint32_t
- SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for
- DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128]
- SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for
- DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
+typedef struct {
+ __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */
+ __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */
+ __IO uint32_t USB_ID; /**< ., offset: 0x8 */
+ __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */
+ __IO uint32_t CC_SOCU_PIN; /**< ., offset: 0x10 */
+ __IO uint32_t CC_SOCU_DFLT; /**< ., offset: 0x14 */
+ __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x18 */
+ __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */
+ __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */
+ __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */
+ __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */
+ __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */
+ __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */
+ __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */
+ uint8_t RESERVED_1[144];
+ __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */
+ __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */
} FLASH_CMPA_Type;
/* ----------------------------------------------------------------------------
@@ -8735,6 +8249,7 @@ typedef struct
/*! @name BOOT_CFG - . */
/*! @{ */
+
#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U)
#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U)
/*! DEFAULT_ISP_MODE - Default ISP mode:
@@ -8744,601 +8259,544 @@ typedef struct
* 0b011..I2C Slave ISP
* 0b111..Disable ISP fall through
*/
-#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & \
- FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK)
-#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U)
-#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U)
+#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK)
+
+#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U)
+#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U)
/*! BOOT_SPEED - Core clock:
* 0b00..Defined by NMPA.SYSTEM_SPEED_CODE
- * 0b01..48MHz FRO
- * 0b10..96MHz FRO
+ * 0b01..96MHz FRO
+ * 0b10..48MHz FRO
*/
-#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK)
+#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK)
+
#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U)
#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U)
/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle
* rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO
* pin
*/
-#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & \
- FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK)
+#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK)
/*! @} */
/*! @name SPI_FLASH_CFG - . */
/*! @{ */
+
#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU)
#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U)
/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field.
*/
-#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & \
- FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK)
+#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK)
/*! @} */
/*! @name USB_ID - . */
/*! @{ */
-#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU)
-#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U)
+
+#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU)
+#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U)
/*! USB_VENDOR_ID - .
*/
-#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK)
-#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U)
-#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U)
+#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK)
+
+#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U)
+#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U)
/*! USB_PRODUCT_ID - .
*/
-#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK)
+#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK)
/*! @} */
/*! @name SDIO_CFG - . */
/*! @{ */
-#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_SDIO_CFG_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK)
+#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK)
/*! @} */
/*! @name CC_SOCU_PIN - . */
/*! @{ */
-#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U)
-#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U)
+
+#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U)
+#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U)
/*! NIDEN - Non Secure non-invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U)
-#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U)
+#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U)
+#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U)
/*! DBGEN - Non Secure debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)
-#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)
+#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)
+#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)
/*! SPNIDEN - Secure non-invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U)
-#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U)
+#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U)
+#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U)
/*! SPIDEN - Secure invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U)
-#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U)
+#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U)
+#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U)
/*! TAPEN - JTAG TAP enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U)
-#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U)
+#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U)
+#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U)
/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)
-#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)
+#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)
+#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)
/*! ISP_CMD_EN - ISP Boot Command enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)
-#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)
+#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)
+#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)
/*! FA_CMD_EN - FA Command enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)
-#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)
+#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)
+#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)
/*! ME_CMD_EN - Flash Mass Erase Command enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U)
-#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U)
+#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U)
+#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U)
/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable
* 0b0..Use DAP to enable
* 0b1..Fixed state
*/
-#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)
-#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)
+#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)
+#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)
/*! UUID_CHECK - Enforce UUID match during Debug authentication.
*/
-#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK)
+#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK)
+
#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)
#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)
/*! INVERSE_VALUE - inverse value of bits [15:0]
*/
-#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & \
- FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK)
+#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK)
/*! @} */
/*! @name CC_SOCU_DFLT - . */
/*! @{ */
-#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U)
-#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U)
+#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U)
/*! NIDEN - Non Secure non-invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U)
-#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U)
+#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U)
+#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U)
/*! DBGEN - Non Secure debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)
-#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)
+#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)
+#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)
/*! SPNIDEN - Secure non-invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)
-#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)
+#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)
+#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)
/*! SPIDEN - Secure invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U)
-#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U)
+#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U)
+#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U)
/*! TAPEN - JTAG TAP fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U)
+#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U)
#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U)
/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & \
- FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)
+#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)
#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)
/*! ISP_CMD_EN - ISP Boot Command fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & \
- FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)
-#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)
+#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)
+#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)
/*! FA_CMD_EN - FA Command fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)
-#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)
+#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)
+#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)
/*! ME_CMD_EN - Flash Mass Erase Command fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK)
-#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U)
+#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK)
+
+#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U)
#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U)
/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state
* 0b0..Disable
* 0b1..Enable
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & \
- FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
+#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK)
+
#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)
#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)
/*! INVERSE_VALUE - inverse value of bits [15:0]
*/
-#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & \
- FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
+#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK)
/*! @} */
/*! @name VENDOR_USAGE - . */
/*! @{ */
+
#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U)
#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U)
/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area.
*/
-#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & \
- FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK)
+#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK)
/*! @} */
/*! @name SECURE_BOOT_CFG - . */
/*! @{ */
-#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U)
-#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U)
+
+#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U)
+#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U)
/*! RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU)
#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U)
/*! DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U)
#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U)
-/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 -
- * included
+/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U)
#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U)
/*! SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U)
#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U)
/*! TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to
* NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header.
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U)
#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U)
-/*! BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code
- * generation
+/*! BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U)
#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U)
/*! BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U)
#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U)
/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK)
+
#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U)
#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U)
/*! SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10,
* 11 - Boot signed images. (internal flash, RSA signed)
*/
-#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & \
- FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK)
+#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK)
/*! @} */
/*! @name PRINCE_BASE_ADDR - . */
/*! @{ */
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU)
#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U)
/*! ADDR0_PRG - Programmable portion of the base address of region 0.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U)
/*! ADDR1_PRG - Programmable portion of the base address of region 1.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U)
/*! ADDR2_PRG - Programmable portion of the base address of region 2.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U)
/*! LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U)
/*! LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U)
/*! LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U)
/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased
* together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U)
/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased
* together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK)
+
#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U)
#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U)
/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased
* together. 00 - Check is disabled. 01, 10, 11 - Check is enabled.
*/
-#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & \
- FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK)
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK)
/*! @} */
/*! @name PRINCE_SR_0 - Region 0, sub-region enable */
/*! @{ */
-#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK)
+#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_SR_1 - Region 1, sub-region enable */
/*! @{ */
-#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK)
+#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK)
/*! @} */
/*! @name PRINCE_SR_2 - Region 2, sub-region enable */
/*! @{ */
-#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK)
+#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK)
/*! @} */
/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */
/*! @{ */
+
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)
/*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.
*/
-#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & \
- FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
+#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
+
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU)
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U)
/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600.
*/
-#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & \
- FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
+#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
+
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U)
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U)
/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.
*/
-#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & \
- FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
+#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
+
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U)
#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U)
/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.
*/
-#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & \
- FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
+#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
/*! @} */
/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */
/*! @{ */
+
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U)
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U)
/*! TRIM_VALID - 0 : Capa Bank trimmings not valid. Default trimmings value are used. 1 : Capa Bank trimmings valid.
*/
-#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & \
- FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
+#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK)
+
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU)
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U)
/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600.
*/
-#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & \
- FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
+#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK)
+
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U)
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U)
/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600.
*/
-#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & \
- FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
+#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK)
+
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U)
#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U)
/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600.
*/
-#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & \
- FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
+#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK)
/*! @} */
-/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192]
- * ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root
- * of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table
- * hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */
+/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */
/*! @{ */
-#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_ROTKH_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK)
+#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK)
/*! @} */
/* The count of FLASH_CMPA_ROTKH */
-#define FLASH_CMPA_ROTKH_COUNT (8U)
+#define FLASH_CMPA_ROTKH_COUNT (8U)
/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */
/*! @{ */
-#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK)
+#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK)
/*! @} */
/* The count of FLASH_CMPA_CUSTOMER_DEFINED */
-#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U)
+#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U)
-/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for
- * DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160]
- * SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */
+/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */
/*! @{ */
-#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U)
+
+#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK)
+#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK)
/*! @} */
/* The count of FLASH_CMPA_SHA256_DIGEST */
-#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U)
+#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U)
+
/*!
* @}
*/ /* end of group FLASH_CMPA_Register_Masks */
+
/* FLASH_CMPA - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral FLASH_CMPA base address */
-#define FLASH_CMPA_BASE (0x1009E400u)
-/** Peripheral FLASH_CMPA base address */
-#define FLASH_CMPA_BASE_NS (0x9E400u)
-/** Peripheral FLASH_CMPA base pointer */
-#define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
-/** Peripheral FLASH_CMPA base pointer */
-#define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS)
-/** Array initializer of FLASH_CMPA peripheral base addresses */
-#define FLASH_CMPA_BASE_ADDRS \
- { \
- FLASH_CMPA_BASE \
- }
-/** Array initializer of FLASH_CMPA peripheral base pointers */
-#define FLASH_CMPA_BASE_PTRS \
- { \
- FLASH_CMPA \
- }
-/** Array initializer of FLASH_CMPA peripheral base addresses */
-#define FLASH_CMPA_BASE_ADDRS_NS \
- { \
- FLASH_CMPA_BASE_NS \
- }
-/** Array initializer of FLASH_CMPA peripheral base pointers */
-#define FLASH_CMPA_BASE_PTRS_NS \
- { \
- FLASH_CMPA_NS \
- }
+ /** Peripheral FLASH_CMPA base address */
+ #define FLASH_CMPA_BASE (0x1009E400u)
+ /** Peripheral FLASH_CMPA base address */
+ #define FLASH_CMPA_BASE_NS (0x9E400u)
+ /** Peripheral FLASH_CMPA base pointer */
+ #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
+ /** Peripheral FLASH_CMPA base pointer */
+ #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS)
+ /** Array initializer of FLASH_CMPA peripheral base addresses */
+ #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE }
+ /** Array initializer of FLASH_CMPA peripheral base pointers */
+ #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA }
+ /** Array initializer of FLASH_CMPA peripheral base addresses */
+ #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS }
+ /** Array initializer of FLASH_CMPA peripheral base pointers */
+ #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS }
#else
-/** Peripheral FLASH_CMPA base address */
-#define FLASH_CMPA_BASE (0x9E400u)
-/** Peripheral FLASH_CMPA base pointer */
-#define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
-/** Array initializer of FLASH_CMPA peripheral base addresses */
-#define FLASH_CMPA_BASE_ADDRS \
- { \
- FLASH_CMPA_BASE \
- }
-/** Array initializer of FLASH_CMPA peripheral base pointers */
-#define FLASH_CMPA_BASE_PTRS \
- { \
- FLASH_CMPA \
- }
+ /** Peripheral FLASH_CMPA base address */
+ #define FLASH_CMPA_BASE (0x9E400u)
+ /** Peripheral FLASH_CMPA base pointer */
+ #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)
+ /** Array initializer of FLASH_CMPA peripheral base addresses */
+ #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE }
+ /** Array initializer of FLASH_CMPA peripheral base pointers */
+ #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA }
#endif
/*!
* @}
*/ /* end of group FLASH_CMPA_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- FLASH_KEY_STORE Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -9349,74 +8807,60 @@ typedef struct
*/
/** FLASH_KEY_STORE - Register Layout Typedef */
-typedef struct
-{
- struct
- { /* offset: 0x0 */
- __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */
- __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */
- } KEY_STORE_HEADER;
- __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */
- union
- { /* offset: 0x4B0 */
- __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */
- struct
- { /* offset: 0x4B0 */
- __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */
- __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */
- __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */
- } SBKEY_KEY_CODE_CORE;
- };
- union
- { /* offset: 0x4E8 */
- __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */
- struct
- { /* offset: 0x4E8 */
- __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */
- __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */
- __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */
- } USER_KEK_KEY_CODE_CORE;
- };
- union
- { /* offset: 0x520 */
- __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */
- struct
- { /* offset: 0x520 */
- __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */
- __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */
- __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */
- } UDS_KEY_CODE_CORE;
- };
- union
- { /* offset: 0x558 */
- __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */
- struct
- { /* offset: 0x558 */
- __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */
- __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */
- __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */
- } PRINCE_REGION0_KEY_CODE_CORE;
- };
- union
- { /* offset: 0x590 */
- __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */
- struct
- { /* offset: 0x590 */
- __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */
- __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */
- __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */
- } PRINCE_REGION1_KEY_CODE_CORE;
- };
- union
- { /* offset: 0x5C8 */
- __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */
- struct
- { /* offset: 0x5C8 */
- __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */
- __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */
- __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */
- } PRINCE_REGION2_KEY_CODE_CORE;
- };
+typedef struct {
+ struct { /* offset: 0x0 */
+ __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */
+ __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */
+ } KEY_STORE_HEADER;
+ __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */
+ union { /* offset: 0x4B0 */
+ __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */
+ struct { /* offset: 0x4B0 */
+ __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */
+ __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */
+ __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */
+ } SBKEY_KEY_CODE_CORE;
+ };
+ union { /* offset: 0x4E8 */
+ __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */
+ struct { /* offset: 0x4E8 */
+ __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */
+ __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */
+ __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */
+ } USER_KEK_KEY_CODE_CORE;
+ };
+ union { /* offset: 0x520 */
+ __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */
+ struct { /* offset: 0x520 */
+ __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */
+ __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */
+ __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */
+ } UDS_KEY_CODE_CORE;
+ };
+ union { /* offset: 0x558 */
+ __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */
+ struct { /* offset: 0x558 */
+ __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */
+ __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */
+ __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */
+ } PRINCE_REGION0_KEY_CODE_CORE;
+ };
+ union { /* offset: 0x590 */
+ __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */
+ struct { /* offset: 0x590 */
+ __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */
+ __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */
+ __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */
+ } PRINCE_REGION1_KEY_CODE_CORE;
+ };
+ union { /* offset: 0x5C8 */
+ __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */
+ struct { /* offset: 0x5C8 */
+ __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */
+ __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */
+ __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */
+ } PRINCE_REGION2_KEY_CODE_CORE;
+ };
} FLASH_KEY_STORE_Type;
/* ----------------------------------------------------------------------------
@@ -9430,234 +8874,219 @@ typedef struct
/*! @name HEADER - Valid Key Sore Header : 0x95959595 */
/*! @{ */
-#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U)
+
+#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_HEADER_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK)
+#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK)
/*! @} */
/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */
/*! @{ */
+
#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK)
+#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK)
/*! @} */
/*! @name ACTIVATION_CODE - . */
/*! @{ */
+
#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */
-#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U)
+#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U)
/*! @name SBKEY_KEY_CODE - . */
/*! @{ */
+
#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */
-#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U)
+#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U)
/*! @name SBKEY_HEADER0 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK)
+#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK)
/*! @} */
/*! @name SBKEY_HEADER1 - . */
/*! @{ */
-#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U)
+
+#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U)
#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & \
- FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK)
+#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK)
+
#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & \
- FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK)
-#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U)
+#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK)
+
+#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & \
- FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK)
+#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK)
/*! @} */
/*! @name SBKEY_BODY - . */
/*! @{ */
-#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U)
+
+#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK)
+#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_SBKEY_BODY */
-#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U)
+#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U)
/*! @name USER_KEK_KEY_CODE - . */
/*! @{ */
+
#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */
-#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U)
+#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U)
/*! @name USER_KEK_HEADER0 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK)
+#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK)
/*! @} */
/*! @name USER_KEK_HEADER1 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U)
#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & \
- FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK)
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK)
+
#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & \
- FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK)
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK)
+
#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & \
- FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK)
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK)
/*! @} */
/*! @name USER_KEK_BODY - . */
/*! @{ */
+
#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK)
+#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_USER_KEK_BODY */
-#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U)
+#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U)
/*! @name UDS_KEY_CODE - . */
/*! @{ */
-#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
+
+#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */
-#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U)
+#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U)
/*! @name UDS_HEADER0 - . */
/*! @{ */
-#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U)
+
+#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK)
+#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK)
/*! @} */
/*! @name UDS_HEADER1 - . */
/*! @{ */
-#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U)
-#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U)
+
+#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U)
+#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK)
-#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U)
-#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U)
+#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK)
+
+#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U)
+#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK)
-#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U)
-#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U)
+#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK)
+
+#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U)
+#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK)
+#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK)
/*! @} */
/*! @name UDS_BODY - . */
/*! @{ */
-#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU)
-#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U)
+
+#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU)
+#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK)
+#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_UDS_BODY */
-#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U)
+#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U)
/*! @name PRINCE_REGION0_KEY_CODE - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */
@@ -9665,49 +9094,44 @@ typedef struct
/*! @name PRINCE_REGION0_HEADER0 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION0_HEADER1 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U)
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK)
+
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK)
+
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK)
/*! @} */
/*! @name PRINCE_REGION0_BODY - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */
@@ -9715,13 +9139,12 @@ typedef struct
/*! @name PRINCE_REGION1_KEY_CODE - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */
@@ -9729,49 +9152,44 @@ typedef struct
/*! @name PRINCE_REGION1_HEADER0 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION1_HEADER1 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U)
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK)
+
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK)
+
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK)
/*! @} */
/*! @name PRINCE_REGION1_BODY - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */
@@ -9779,13 +9197,12 @@ typedef struct
/*! @name PRINCE_REGION2_KEY_CODE - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */
@@ -9793,109 +9210,89 @@ typedef struct
/*! @name PRINCE_REGION2_HEADER0 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK)
/*! @} */
/*! @name PRINCE_REGION2_HEADER1 - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U)
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U)
/*! TYPE - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK)
+
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U)
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U)
/*! INDEX - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK)
+
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U)
#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U)
/*! SIZE - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK)
/*! @} */
/*! @name PRINCE_REGION2_BODY - . */
/*! @{ */
+
#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU)
#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U)
/*! FIELD - .
*/
-#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) \
- (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & \
- FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK)
+#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK)
/*! @} */
/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */
#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U)
+
/*!
* @}
*/ /* end of group FLASH_KEY_STORE_Register_Masks */
+
/* FLASH_KEY_STORE - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral FLASH_KEY_STORE base address */
-#define FLASH_KEY_STORE_BASE (0x1009E600u)
-/** Peripheral FLASH_KEY_STORE base address */
-#define FLASH_KEY_STORE_BASE_NS (0x9E600u)
-/** Peripheral FLASH_KEY_STORE base pointer */
-#define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
-/** Peripheral FLASH_KEY_STORE base pointer */
-#define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS)
-/** Array initializer of FLASH_KEY_STORE peripheral base addresses */
-#define FLASH_KEY_STORE_BASE_ADDRS \
- { \
- FLASH_KEY_STORE_BASE \
- }
-/** Array initializer of FLASH_KEY_STORE peripheral base pointers */
-#define FLASH_KEY_STORE_BASE_PTRS \
- { \
- FLASH_KEY_STORE \
- }
-/** Array initializer of FLASH_KEY_STORE peripheral base addresses */
-#define FLASH_KEY_STORE_BASE_ADDRS_NS \
- { \
- FLASH_KEY_STORE_BASE_NS \
- }
-/** Array initializer of FLASH_KEY_STORE peripheral base pointers */
-#define FLASH_KEY_STORE_BASE_PTRS_NS \
- { \
- FLASH_KEY_STORE_NS \
- }
+ /** Peripheral FLASH_KEY_STORE base address */
+ #define FLASH_KEY_STORE_BASE (0x1009E600u)
+ /** Peripheral FLASH_KEY_STORE base address */
+ #define FLASH_KEY_STORE_BASE_NS (0x9E600u)
+ /** Peripheral FLASH_KEY_STORE base pointer */
+ #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
+ /** Peripheral FLASH_KEY_STORE base pointer */
+ #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS)
+ /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
+ #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE }
+ /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
+ #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE }
+ /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
+ #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS }
+ /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
+ #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS }
#else
-/** Peripheral FLASH_KEY_STORE base address */
-#define FLASH_KEY_STORE_BASE (0x9E600u)
-/** Peripheral FLASH_KEY_STORE base pointer */
-#define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
-/** Array initializer of FLASH_KEY_STORE peripheral base addresses */
-#define FLASH_KEY_STORE_BASE_ADDRS \
- { \
- FLASH_KEY_STORE_BASE \
- }
-/** Array initializer of FLASH_KEY_STORE peripheral base pointers */
-#define FLASH_KEY_STORE_BASE_PTRS \
- { \
- FLASH_KEY_STORE \
- }
+ /** Peripheral FLASH_KEY_STORE base address */
+ #define FLASH_KEY_STORE_BASE (0x9E600u)
+ /** Peripheral FLASH_KEY_STORE base pointer */
+ #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)
+ /** Array initializer of FLASH_KEY_STORE peripheral base addresses */
+ #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE }
+ /** Array initializer of FLASH_KEY_STORE peripheral base pointers */
+ #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE }
#endif
/*!
* @}
*/ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- FLEXCOMM Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -9906,11 +9303,10 @@ typedef struct
*/
/** FLEXCOMM - Register Layout Typedef */
-typedef struct
-{
- uint8_t RESERVED_0[4088];
- __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
- __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
+typedef struct {
+ uint8_t RESERVED_0[4088];
+ __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+ __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
} FLEXCOMM_Type;
/* ----------------------------------------------------------------------------
@@ -9924,8 +9320,9 @@ typedef struct
/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
/*! @{ */
-#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
-#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
+
+#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
/*! PERSEL - Peripheral Select. This field is writable by software.
* 0b000..No peripheral selected.
* 0b001..USART function selected.
@@ -9936,243 +9333,221 @@ typedef struct
* 0b110..Reserved
* 0b111..Reserved
*/
-#define FLEXCOMM_PSELID_PERSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
-#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
-#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
+#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+
+#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
/*! LOCK - Lock the peripheral select. This field is writable by software.
* 0b0..Peripheral select can be changed by software.
* 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.
*/
-#define FLEXCOMM_PSELID_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
-#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
-#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
+#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
/*! USARTPRESENT - USART present indicator. This field is Read-only.
* 0b0..This Flexcomm does not include the USART function.
* 0b1..This Flexcomm includes the USART function.
*/
-#define FLEXCOMM_PSELID_USARTPRESENT(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
-#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
-#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
+#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
/*! SPIPRESENT - SPI present indicator. This field is Read-only.
* 0b0..This Flexcomm does not include the SPI function.
* 0b1..This Flexcomm includes the SPI function.
*/
-#define FLEXCOMM_PSELID_SPIPRESENT(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
-#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
-#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
+#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
/*! I2CPRESENT - I2C present indicator. This field is Read-only.
* 0b0..This Flexcomm does not include the I2C function.
* 0b1..This Flexcomm includes the I2C function.
*/
-#define FLEXCOMM_PSELID_I2CPRESENT(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
-#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
-#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
+#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
/*! I2SPRESENT - I 2S present indicator. This field is Read-only.
* 0b0..This Flexcomm does not include the I2S function.
* 0b1..This Flexcomm includes the I2S function.
*/
-#define FLEXCOMM_PSELID_I2SPRESENT(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
-#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
-#define FLEXCOMM_PSELID_ID_SHIFT (12U)
+#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+
+#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT (12U)
/*! ID - Flexcomm ID.
*/
-#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
/*! @} */
/*! @name PID - Peripheral identification register. */
/*! @{ */
-#define FLEXCOMM_PID_APERTURE_MASK (0xFFU)
-#define FLEXCOMM_PID_APERTURE_SHIFT (0U)
+
+#define FLEXCOMM_PID_APERTURE_MASK (0xFFU)
+#define FLEXCOMM_PID_APERTURE_SHIFT (0U)
/*! APERTURE - size aperture for the register port on the bus (APB or AHB).
*/
-#define FLEXCOMM_PID_APERTURE(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK)
-#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U)
-#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U)
+#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK)
+
+#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U)
+#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U)
/*! MINOR_REV - Minor revision of module implementation.
*/
-#define FLEXCOMM_PID_MINOR_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK)
-#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U)
-#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U)
+#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK)
+
+#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U)
+#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U)
/*! MAJOR_REV - Major revision of module implementation.
*/
-#define FLEXCOMM_PID_MAJOR_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK)
-#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
-#define FLEXCOMM_PID_ID_SHIFT (16U)
+#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK)
+
+#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT (16U)
/*! ID - Module identifier for the selected function.
*/
-#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group FLEXCOMM_Register_Masks */
+
/* FLEXCOMM - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral FLEXCOMM0 base address */
-#define FLEXCOMM0_BASE (0x50086000u)
-/** Peripheral FLEXCOMM0 base address */
-#define FLEXCOMM0_BASE_NS (0x40086000u)
-/** Peripheral FLEXCOMM0 base pointer */
-#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
-/** Peripheral FLEXCOMM0 base pointer */
-#define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)
-/** Peripheral FLEXCOMM1 base address */
-#define FLEXCOMM1_BASE (0x50087000u)
-/** Peripheral FLEXCOMM1 base address */
-#define FLEXCOMM1_BASE_NS (0x40087000u)
-/** Peripheral FLEXCOMM1 base pointer */
-#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
-/** Peripheral FLEXCOMM1 base pointer */
-#define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)
-/** Peripheral FLEXCOMM2 base address */
-#define FLEXCOMM2_BASE (0x50088000u)
-/** Peripheral FLEXCOMM2 base address */
-#define FLEXCOMM2_BASE_NS (0x40088000u)
-/** Peripheral FLEXCOMM2 base pointer */
-#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
-/** Peripheral FLEXCOMM2 base pointer */
-#define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)
-/** Peripheral FLEXCOMM3 base address */
-#define FLEXCOMM3_BASE (0x50089000u)
-/** Peripheral FLEXCOMM3 base address */
-#define FLEXCOMM3_BASE_NS (0x40089000u)
-/** Peripheral FLEXCOMM3 base pointer */
-#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
-/** Peripheral FLEXCOMM3 base pointer */
-#define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)
-/** Peripheral FLEXCOMM4 base address */
-#define FLEXCOMM4_BASE (0x5008A000u)
-/** Peripheral FLEXCOMM4 base address */
-#define FLEXCOMM4_BASE_NS (0x4008A000u)
-/** Peripheral FLEXCOMM4 base pointer */
-#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
-/** Peripheral FLEXCOMM4 base pointer */
-#define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS)
-/** Peripheral FLEXCOMM5 base address */
-#define FLEXCOMM5_BASE (0x50096000u)
-/** Peripheral FLEXCOMM5 base address */
-#define FLEXCOMM5_BASE_NS (0x40096000u)
-/** Peripheral FLEXCOMM5 base pointer */
-#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
-/** Peripheral FLEXCOMM5 base pointer */
-#define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS)
-/** Peripheral FLEXCOMM6 base address */
-#define FLEXCOMM6_BASE (0x50097000u)
-/** Peripheral FLEXCOMM6 base address */
-#define FLEXCOMM6_BASE_NS (0x40097000u)
-/** Peripheral FLEXCOMM6 base pointer */
-#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
-/** Peripheral FLEXCOMM6 base pointer */
-#define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS)
-/** Peripheral FLEXCOMM7 base address */
-#define FLEXCOMM7_BASE (0x50098000u)
-/** Peripheral FLEXCOMM7 base address */
-#define FLEXCOMM7_BASE_NS (0x40098000u)
-/** Peripheral FLEXCOMM7 base pointer */
-#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
-/** Peripheral FLEXCOMM7 base pointer */
-#define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS)
-/** Peripheral FLEXCOMM8 base address */
-#define FLEXCOMM8_BASE (0x5009F000u)
-/** Peripheral FLEXCOMM8 base address */
-#define FLEXCOMM8_BASE_NS (0x4009F000u)
-/** Peripheral FLEXCOMM8 base pointer */
-#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
-/** Peripheral FLEXCOMM8 base pointer */
-#define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS)
-/** Array initializer of FLEXCOMM peripheral base addresses */
-#define FLEXCOMM_BASE_ADDRS \
- { \
- FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, \
- FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE \
- }
-/** Array initializer of FLEXCOMM peripheral base pointers */
-#define FLEXCOMM_BASE_PTRS \
- { \
- FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 \
- }
-/** Array initializer of FLEXCOMM peripheral base addresses */
-#define FLEXCOMM_BASE_ADDRS_NS \
- { \
- FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, \
- FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS \
- }
-/** Array initializer of FLEXCOMM peripheral base pointers */
-#define FLEXCOMM_BASE_PTRS_NS \
- { \
- FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, \
- FLEXCOMM7_NS, FLEXCOMM8_NS \
- }
+ /** Peripheral FLEXCOMM0 base address */
+ #define FLEXCOMM0_BASE (0x50086000u)
+ /** Peripheral FLEXCOMM0 base address */
+ #define FLEXCOMM0_BASE_NS (0x40086000u)
+ /** Peripheral FLEXCOMM0 base pointer */
+ #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+ /** Peripheral FLEXCOMM0 base pointer */
+ #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)
+ /** Peripheral FLEXCOMM1 base address */
+ #define FLEXCOMM1_BASE (0x50087000u)
+ /** Peripheral FLEXCOMM1 base address */
+ #define FLEXCOMM1_BASE_NS (0x40087000u)
+ /** Peripheral FLEXCOMM1 base pointer */
+ #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+ /** Peripheral FLEXCOMM1 base pointer */
+ #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)
+ /** Peripheral FLEXCOMM2 base address */
+ #define FLEXCOMM2_BASE (0x50088000u)
+ /** Peripheral FLEXCOMM2 base address */
+ #define FLEXCOMM2_BASE_NS (0x40088000u)
+ /** Peripheral FLEXCOMM2 base pointer */
+ #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+ /** Peripheral FLEXCOMM2 base pointer */
+ #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)
+ /** Peripheral FLEXCOMM3 base address */
+ #define FLEXCOMM3_BASE (0x50089000u)
+ /** Peripheral FLEXCOMM3 base address */
+ #define FLEXCOMM3_BASE_NS (0x40089000u)
+ /** Peripheral FLEXCOMM3 base pointer */
+ #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+ /** Peripheral FLEXCOMM3 base pointer */
+ #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)
+ /** Peripheral FLEXCOMM4 base address */
+ #define FLEXCOMM4_BASE (0x5008A000u)
+ /** Peripheral FLEXCOMM4 base address */
+ #define FLEXCOMM4_BASE_NS (0x4008A000u)
+ /** Peripheral FLEXCOMM4 base pointer */
+ #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+ /** Peripheral FLEXCOMM4 base pointer */
+ #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS)
+ /** Peripheral FLEXCOMM5 base address */
+ #define FLEXCOMM5_BASE (0x50096000u)
+ /** Peripheral FLEXCOMM5 base address */
+ #define FLEXCOMM5_BASE_NS (0x40096000u)
+ /** Peripheral FLEXCOMM5 base pointer */
+ #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+ /** Peripheral FLEXCOMM5 base pointer */
+ #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS)
+ /** Peripheral FLEXCOMM6 base address */
+ #define FLEXCOMM6_BASE (0x50097000u)
+ /** Peripheral FLEXCOMM6 base address */
+ #define FLEXCOMM6_BASE_NS (0x40097000u)
+ /** Peripheral FLEXCOMM6 base pointer */
+ #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+ /** Peripheral FLEXCOMM6 base pointer */
+ #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS)
+ /** Peripheral FLEXCOMM7 base address */
+ #define FLEXCOMM7_BASE (0x50098000u)
+ /** Peripheral FLEXCOMM7 base address */
+ #define FLEXCOMM7_BASE_NS (0x40098000u)
+ /** Peripheral FLEXCOMM7 base pointer */
+ #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+ /** Peripheral FLEXCOMM7 base pointer */
+ #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS)
+ /** Peripheral FLEXCOMM8 base address */
+ #define FLEXCOMM8_BASE (0x5009F000u)
+ /** Peripheral FLEXCOMM8 base address */
+ #define FLEXCOMM8_BASE_NS (0x4009F000u)
+ /** Peripheral FLEXCOMM8 base pointer */
+ #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+ /** Peripheral FLEXCOMM8 base pointer */
+ #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS)
+ /** Array initializer of FLEXCOMM peripheral base addresses */
+ #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }
+ /** Array initializer of FLEXCOMM peripheral base pointers */
+ #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }
+ /** Array initializer of FLEXCOMM peripheral base addresses */
+ #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS }
+ /** Array initializer of FLEXCOMM peripheral base pointers */
+ #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS }
#else
-/** Peripheral FLEXCOMM0 base address */
-#define FLEXCOMM0_BASE (0x40086000u)
-/** Peripheral FLEXCOMM0 base pointer */
-#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
-/** Peripheral FLEXCOMM1 base address */
-#define FLEXCOMM1_BASE (0x40087000u)
-/** Peripheral FLEXCOMM1 base pointer */
-#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
-/** Peripheral FLEXCOMM2 base address */
-#define FLEXCOMM2_BASE (0x40088000u)
-/** Peripheral FLEXCOMM2 base pointer */
-#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
-/** Peripheral FLEXCOMM3 base address */
-#define FLEXCOMM3_BASE (0x40089000u)
-/** Peripheral FLEXCOMM3 base pointer */
-#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
-/** Peripheral FLEXCOMM4 base address */
-#define FLEXCOMM4_BASE (0x4008A000u)
-/** Peripheral FLEXCOMM4 base pointer */
-#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
-/** Peripheral FLEXCOMM5 base address */
-#define FLEXCOMM5_BASE (0x40096000u)
-/** Peripheral FLEXCOMM5 base pointer */
-#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
-/** Peripheral FLEXCOMM6 base address */
-#define FLEXCOMM6_BASE (0x40097000u)
-/** Peripheral FLEXCOMM6 base pointer */
-#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
-/** Peripheral FLEXCOMM7 base address */
-#define FLEXCOMM7_BASE (0x40098000u)
-/** Peripheral FLEXCOMM7 base pointer */
-#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
-/** Peripheral FLEXCOMM8 base address */
-#define FLEXCOMM8_BASE (0x4009F000u)
-/** Peripheral FLEXCOMM8 base pointer */
-#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
-/** Array initializer of FLEXCOMM peripheral base addresses */
-#define FLEXCOMM_BASE_ADDRS \
- { \
- FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, \
- FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE \
- }
-/** Array initializer of FLEXCOMM peripheral base pointers */
-#define FLEXCOMM_BASE_PTRS \
- { \
- FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 \
- }
+ /** Peripheral FLEXCOMM0 base address */
+ #define FLEXCOMM0_BASE (0x40086000u)
+ /** Peripheral FLEXCOMM0 base pointer */
+ #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+ /** Peripheral FLEXCOMM1 base address */
+ #define FLEXCOMM1_BASE (0x40087000u)
+ /** Peripheral FLEXCOMM1 base pointer */
+ #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+ /** Peripheral FLEXCOMM2 base address */
+ #define FLEXCOMM2_BASE (0x40088000u)
+ /** Peripheral FLEXCOMM2 base pointer */
+ #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+ /** Peripheral FLEXCOMM3 base address */
+ #define FLEXCOMM3_BASE (0x40089000u)
+ /** Peripheral FLEXCOMM3 base pointer */
+ #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+ /** Peripheral FLEXCOMM4 base address */
+ #define FLEXCOMM4_BASE (0x4008A000u)
+ /** Peripheral FLEXCOMM4 base pointer */
+ #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+ /** Peripheral FLEXCOMM5 base address */
+ #define FLEXCOMM5_BASE (0x40096000u)
+ /** Peripheral FLEXCOMM5 base pointer */
+ #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+ /** Peripheral FLEXCOMM6 base address */
+ #define FLEXCOMM6_BASE (0x40097000u)
+ /** Peripheral FLEXCOMM6 base pointer */
+ #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+ /** Peripheral FLEXCOMM7 base address */
+ #define FLEXCOMM7_BASE (0x40098000u)
+ /** Peripheral FLEXCOMM7 base pointer */
+ #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+ /** Peripheral FLEXCOMM8 base address */
+ #define FLEXCOMM8_BASE (0x4009F000u)
+ /** Peripheral FLEXCOMM8 base pointer */
+ #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+ /** Array initializer of FLEXCOMM peripheral base addresses */
+ #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }
+ /** Array initializer of FLEXCOMM peripheral base pointers */
+ #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }
#endif
/** Interrupt vectors for the FLEXCOMM peripheral type */
-#define FLEXCOMM_IRQS \
- { \
- FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, \
- FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn \
- }
+#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn }
/*!
* @}
*/ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- GINT Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -10183,15 +9558,12 @@ typedef struct
*/
/** GINT - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
- uint8_t RESERVED_0[28];
- __IO uint32_t
- PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[24];
- __IO uint32_t
- PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+typedef struct {
+ __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
} GINT_Type;
/* ----------------------------------------------------------------------------
@@ -10205,131 +9577,117 @@ typedef struct
/*! @name CTRL - GPIO grouped interrupt control register */
/*! @{ */
-#define GINT_CTRL_INT_MASK (0x1U)
-#define GINT_CTRL_INT_SHIFT (0U)
+
+#define GINT_CTRL_INT_MASK (0x1U)
+#define GINT_CTRL_INT_SHIFT (0U)
/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
* 0b0..No request. No interrupt request is pending.
* 0b1..Request active. Interrupt request is active.
*/
-#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
-#define GINT_CTRL_COMB_MASK (0x2U)
-#define GINT_CTRL_COMB_SHIFT (1U)
+#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+
+#define GINT_CTRL_COMB_MASK (0x2U)
+#define GINT_CTRL_COMB_SHIFT (1U)
/*! COMB - Combine enabled inputs for group interrupt
- * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on
- * its programmed polarity). 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active
- * (based on their programmed polarity).
+ * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).
+ * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).
*/
-#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
-#define GINT_CTRL_TRIG_MASK (0x4U)
-#define GINT_CTRL_TRIG_SHIFT (2U)
+#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+
+#define GINT_CTRL_TRIG_MASK (0x4U)
+#define GINT_CTRL_TRIG_SHIFT (2U)
/*! TRIG - Group interrupt trigger
* 0b0..Edge-triggered.
* 0b1..Level-triggered.
*/
-#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
/*! @} */
/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
/*! @{ */
-#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
-#define GINT_PORT_POL_POL_SHIFT (0U)
+
+#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT (0U)
/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n
* of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to
* the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin
* contributes to the group interrupt.
*/
-#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
/*! @} */
/* The count of GINT_PORT_POL */
-#define GINT_PORT_POL_COUNT (2U)
+#define GINT_PORT_POL_COUNT (2U)
/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
/*! @{ */
-#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
-#define GINT_PORT_ENA_ENA_SHIFT (0U)
+
+#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT (0U)
/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the
* port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is
* enabled and contributes to the grouped interrupt.
*/
-#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
/*! @} */
/* The count of GINT_PORT_ENA */
-#define GINT_PORT_ENA_COUNT (2U)
+#define GINT_PORT_ENA_COUNT (2U)
+
/*!
* @}
*/ /* end of group GINT_Register_Masks */
+
/* GINT - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral GINT0 base address */
-#define GINT0_BASE (0x50002000u)
-/** Peripheral GINT0 base address */
-#define GINT0_BASE_NS (0x40002000u)
-/** Peripheral GINT0 base pointer */
-#define GINT0 ((GINT_Type *)GINT0_BASE)
-/** Peripheral GINT0 base pointer */
-#define GINT0_NS ((GINT_Type *)GINT0_BASE_NS)
-/** Peripheral GINT1 base address */
-#define GINT1_BASE (0x50003000u)
-/** Peripheral GINT1 base address */
-#define GINT1_BASE_NS (0x40003000u)
-/** Peripheral GINT1 base pointer */
-#define GINT1 ((GINT_Type *)GINT1_BASE)
-/** Peripheral GINT1 base pointer */
-#define GINT1_NS ((GINT_Type *)GINT1_BASE_NS)
-/** Array initializer of GINT peripheral base addresses */
-#define GINT_BASE_ADDRS \
- { \
- GINT0_BASE, GINT1_BASE \
- }
-/** Array initializer of GINT peripheral base pointers */
-#define GINT_BASE_PTRS \
- { \
- GINT0, GINT1 \
- }
-/** Array initializer of GINT peripheral base addresses */
-#define GINT_BASE_ADDRS_NS \
- { \
- GINT0_BASE_NS, GINT1_BASE_NS \
- }
-/** Array initializer of GINT peripheral base pointers */
-#define GINT_BASE_PTRS_NS \
- { \
- GINT0_NS, GINT1_NS \
- }
+ /** Peripheral GINT0 base address */
+ #define GINT0_BASE (0x50002000u)
+ /** Peripheral GINT0 base address */
+ #define GINT0_BASE_NS (0x40002000u)
+ /** Peripheral GINT0 base pointer */
+ #define GINT0 ((GINT_Type *)GINT0_BASE)
+ /** Peripheral GINT0 base pointer */
+ #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS)
+ /** Peripheral GINT1 base address */
+ #define GINT1_BASE (0x50003000u)
+ /** Peripheral GINT1 base address */
+ #define GINT1_BASE_NS (0x40003000u)
+ /** Peripheral GINT1 base pointer */
+ #define GINT1 ((GINT_Type *)GINT1_BASE)
+ /** Peripheral GINT1 base pointer */
+ #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS)
+ /** Array initializer of GINT peripheral base addresses */
+ #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
+ /** Array initializer of GINT peripheral base pointers */
+ #define GINT_BASE_PTRS { GINT0, GINT1 }
+ /** Array initializer of GINT peripheral base addresses */
+ #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS }
+ /** Array initializer of GINT peripheral base pointers */
+ #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS }
#else
-/** Peripheral GINT0 base address */
-#define GINT0_BASE (0x40002000u)
-/** Peripheral GINT0 base pointer */
-#define GINT0 ((GINT_Type *)GINT0_BASE)
-/** Peripheral GINT1 base address */
-#define GINT1_BASE (0x40003000u)
-/** Peripheral GINT1 base pointer */
-#define GINT1 ((GINT_Type *)GINT1_BASE)
-/** Array initializer of GINT peripheral base addresses */
-#define GINT_BASE_ADDRS \
- { \
- GINT0_BASE, GINT1_BASE \
- }
-/** Array initializer of GINT peripheral base pointers */
-#define GINT_BASE_PTRS \
- { \
- GINT0, GINT1 \
- }
+ /** Peripheral GINT0 base address */
+ #define GINT0_BASE (0x40002000u)
+ /** Peripheral GINT0 base pointer */
+ #define GINT0 ((GINT_Type *)GINT0_BASE)
+ /** Peripheral GINT1 base address */
+ #define GINT1_BASE (0x40003000u)
+ /** Peripheral GINT1 base pointer */
+ #define GINT1 ((GINT_Type *)GINT1_BASE)
+ /** Array initializer of GINT peripheral base addresses */
+ #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
+ /** Array initializer of GINT peripheral base pointers */
+ #define GINT_BASE_PTRS { GINT0, GINT1 }
#endif
/** Interrupt vectors for the GINT peripheral type */
-#define GINT_IRQS \
- { \
- GINT0_IRQn, GINT1_IRQn \
- }
+#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
/*!
* @}
*/ /* end of group GINT_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -10340,34 +9698,30 @@ typedef struct
*/
/** GPIO - Register Layout Typedef */
-typedef struct
-{
- __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20,
- index2*0x1 */
- uint8_t RESERVED_0[4032];
- __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step:
- index*0x80, index2*0x4 */
- uint8_t RESERVED_1[3840];
- __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */
- uint8_t RESERVED_2[120];
- __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */
- uint8_t RESERVED_3[120];
- __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */
- uint8_t RESERVED_4[120];
- __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */
- uint8_t RESERVED_5[120];
- __IO uint32_t
- SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */
- uint8_t RESERVED_6[120];
- __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */
- uint8_t RESERVED_7[120];
- __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */
- uint8_t RESERVED_8[120];
- __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
- uint8_t RESERVED_9[120];
- __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
- uint8_t RESERVED_10[120];
- __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+typedef struct {
+ __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+ uint8_t RESERVED_0[4032];
+ __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+ uint8_t RESERVED_1[3840];
+ __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */
+ uint8_t RESERVED_2[120];
+ __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */
+ uint8_t RESERVED_3[120];
+ __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */
+ uint8_t RESERVED_4[120];
+ __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */
+ uint8_t RESERVED_5[120];
+ __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+ uint8_t RESERVED_6[120];
+ __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */
+ uint8_t RESERVED_7[120];
+ __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */
+ uint8_t RESERVED_8[120];
+ __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+ uint8_t RESERVED_9[120];
+ __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+ uint8_t RESERVED_10[120];
+ __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
} GPIO_Type;
/* ----------------------------------------------------------------------------
@@ -10381,244 +9735,241 @@ typedef struct
/*! @name B - Byte pin registers for all port GPIO pins */
/*! @{ */
-#define GPIO_B_PBYTE_MASK (0x1U)
-#define GPIO_B_PBYTE_SHIFT (0U)
+
+#define GPIO_B_PBYTE_MASK (0x1U)
+#define GPIO_B_PBYTE_SHIFT (0U)
/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
* except that pins configured as analog I/O always read as 0. One register for each port pin.
* Supported pins depends on the specific device and package. Write: loads the pin's output bit.
* One register for each port pin. Supported pins depends on the specific device and package.
*/
-#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
/*! @} */
/* The count of GPIO_B */
-#define GPIO_B_COUNT (2U)
+#define GPIO_B_COUNT (2U)
/* The count of GPIO_B */
-#define GPIO_B_COUNT2 (32U)
+#define GPIO_B_COUNT2 (32U)
/*! @name W - Word pin registers for all port GPIO pins */
/*! @{ */
-#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
-#define GPIO_W_PWORD_SHIFT (0U)
+
+#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT (0U)
/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
* HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
* read. Writing any value other than 0 will set the output bit. One register for each port pin.
* Supported pins depends on the specific device and package.
*/
-#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
/*! @} */
/* The count of GPIO_W */
-#define GPIO_W_COUNT (2U)
+#define GPIO_W_COUNT (2U)
/* The count of GPIO_W */
-#define GPIO_W_COUNT2 (32U)
+#define GPIO_W_COUNT2 (32U)
/*! @name DIR - Direction registers for all port GPIO pins */
/*! @{ */
-#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
-#define GPIO_DIR_DIRP_SHIFT (0U)
+
+#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT (0U)
/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
* pins depends on the specific device and package. 0 = input. 1 = output.
*/
-#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
/*! @} */
/* The count of GPIO_DIR */
-#define GPIO_DIR_COUNT (2U)
+#define GPIO_DIR_COUNT (2U)
/*! @name MASK - Mask register for all port GPIO pins */
/*! @{ */
-#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
-#define GPIO_MASK_MASKP_SHIFT (0U)
+
+#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT (0U)
/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
* PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 =
* Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
* not affected.
*/
-#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
/*! @} */
/* The count of GPIO_MASK */
-#define GPIO_MASK_COUNT (2U)
+#define GPIO_MASK_COUNT (2U)
/*! @name PIN - Port pin register for all port GPIO pins */
/*! @{ */
-#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
-#define GPIO_PIN_PORT_SHIFT (0U)
+
+#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT (0U)
/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
* pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
* 1 = Read: pin is high; write: set output bit.
*/
-#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
/*! @} */
/* The count of GPIO_PIN */
-#define GPIO_PIN_COUNT (2U)
+#define GPIO_PIN_COUNT (2U)
/*! @name MPIN - Masked port register for all port GPIO pins */
/*! @{ */
-#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
-#define GPIO_MPIN_MPORTP_SHIFT (0U)
+
+#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT (0U)
/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
* the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
* register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
* = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
* if the corresponding bit in the MASK register is 0.
*/
-#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
/*! @} */
/* The count of GPIO_MPIN */
-#define GPIO_MPIN_COUNT (2U)
+#define GPIO_MPIN_COUNT (2U)
/*! @name SET - Write: Set register for port. Read: output bits for port */
/*! @{ */
-#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
-#define GPIO_SET_SETP_SHIFT (0U)
+
+#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT (0U)
/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
* the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
* bit; write: set output bit.
*/
-#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
/*! @} */
/* The count of GPIO_SET */
-#define GPIO_SET_COUNT (2U)
+#define GPIO_SET_COUNT (2U)
/*! @name CLR - Clear port for all port GPIO pins */
/*! @{ */
-#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
-#define GPIO_CLR_CLRP_SHIFT (0U)
+
+#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT (0U)
/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
* specific device and package. 0 = No operation. 1 = Clear output bit.
*/
-#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
/*! @} */
/* The count of GPIO_CLR */
-#define GPIO_CLR_COUNT (2U)
+#define GPIO_CLR_COUNT (2U)
/*! @name NOT - Toggle port for all port GPIO pins */
/*! @{ */
-#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
-#define GPIO_NOT_NOTP_SHIFT (0U)
+
+#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT (0U)
/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
* specific device and package. 0 = no operation. 1 = Toggle output bit.
*/
-#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
/*! @} */
/* The count of GPIO_NOT */
-#define GPIO_NOT_COUNT (2U)
+#define GPIO_NOT_COUNT (2U)
/*! @name DIRSET - Set pin direction bits for port */
/*! @{ */
-#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU)
-#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
+
+#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
* the specific device and package. 0 = No operation. 1 = Set direction bit.
*/
-#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
/*! @} */
/* The count of GPIO_DIRSET */
-#define GPIO_DIRSET_COUNT (2U)
+#define GPIO_DIRSET_COUNT (2U)
/*! @name DIRCLR - Clear pin direction bits for port */
/*! @{ */
-#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU)
-#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
+
+#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
* the specific device and package. 0 = No operation. 1 = Clear direction bit.
*/
-#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
/*! @} */
/* The count of GPIO_DIRCLR */
-#define GPIO_DIRCLR_COUNT (2U)
+#define GPIO_DIRCLR_COUNT (2U)
/*! @name DIRNOT - Toggle pin direction bits for port */
/*! @{ */
-#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU)
-#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
+
+#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
* on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
*/
-#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
/*! @} */
/* The count of GPIO_DIRNOT */
-#define GPIO_DIRNOT_COUNT (2U)
+#define GPIO_DIRNOT_COUNT (2U)
+
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
+
/* GPIO - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral GPIO base address */
-#define GPIO_BASE (0x5008C000u)
-/** Peripheral GPIO base address */
-#define GPIO_BASE_NS (0x4008C000u)
-/** Peripheral GPIO base pointer */
-#define GPIO ((GPIO_Type *)GPIO_BASE)
-/** Peripheral GPIO base pointer */
-#define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS)
-/** Peripheral SECGPIO base address */
-#define SECGPIO_BASE (0x500A8000u)
-/** Peripheral SECGPIO base address */
-#define SECGPIO_BASE_NS (0x400A8000u)
-/** Peripheral SECGPIO base pointer */
-#define SECGPIO ((GPIO_Type *)SECGPIO_BASE)
-/** Peripheral SECGPIO base pointer */
-#define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS)
-/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS \
- { \
- GPIO_BASE, SECGPIO_BASE \
- }
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS \
- { \
- GPIO, SECGPIO \
- }
-/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS_NS \
- { \
- GPIO_BASE_NS, SECGPIO_BASE_NS \
- }
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS_NS \
- { \
- GPIO_NS, SECGPIO_NS \
- }
+ /** Peripheral GPIO base address */
+ #define GPIO_BASE (0x5008C000u)
+ /** Peripheral GPIO base address */
+ #define GPIO_BASE_NS (0x4008C000u)
+ /** Peripheral GPIO base pointer */
+ #define GPIO ((GPIO_Type *)GPIO_BASE)
+ /** Peripheral GPIO base pointer */
+ #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS)
+ /** Peripheral SECGPIO base address */
+ #define SECGPIO_BASE (0x500A8000u)
+ /** Peripheral SECGPIO base address */
+ #define SECGPIO_BASE_NS (0x400A8000u)
+ /** Peripheral SECGPIO base pointer */
+ #define SECGPIO ((GPIO_Type *)SECGPIO_BASE)
+ /** Peripheral SECGPIO base pointer */
+ #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS)
+ /** Array initializer of GPIO peripheral base addresses */
+ #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE }
+ /** Array initializer of GPIO peripheral base pointers */
+ #define GPIO_BASE_PTRS { GPIO, SECGPIO }
+ /** Array initializer of GPIO peripheral base addresses */
+ #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS }
+ /** Array initializer of GPIO peripheral base pointers */
+ #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS }
#else
-/** Peripheral GPIO base address */
-#define GPIO_BASE (0x4008C000u)
-/** Peripheral GPIO base pointer */
-#define GPIO ((GPIO_Type *)GPIO_BASE)
-/** Peripheral SECGPIO base address */
-#define SECGPIO_BASE (0x400A8000u)
-/** Peripheral SECGPIO base pointer */
-#define SECGPIO ((GPIO_Type *)SECGPIO_BASE)
-/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS \
- { \
- GPIO_BASE, SECGPIO_BASE \
- }
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS \
- { \
- GPIO, SECGPIO \
- }
+ /** Peripheral GPIO base address */
+ #define GPIO_BASE (0x4008C000u)
+ /** Peripheral GPIO base pointer */
+ #define GPIO ((GPIO_Type *)GPIO_BASE)
+ /** Peripheral SECGPIO base address */
+ #define SECGPIO_BASE (0x400A8000u)
+ /** Peripheral SECGPIO base pointer */
+ #define SECGPIO ((GPIO_Type *)SECGPIO_BASE)
+ /** Array initializer of GPIO peripheral base addresses */
+ #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE }
+ /** Array initializer of GPIO peripheral base pointers */
+ #define GPIO_BASE_PTRS { GPIO, SECGPIO }
#endif
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- HASHCRYPT Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -10629,26 +9980,23 @@ typedef struct
*/
/** HASHCRYPT - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */
- __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */
- __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */
- __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */
- __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */
- __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */
- uint8_t RESERVED_0[8];
- __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */
- __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */
- __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_1[32];
- __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */
- __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are
- available., offset: 0x84 */
- uint8_t RESERVED_2[4];
- __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding
- level., offset: 0x8C */
- __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */
+ __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */
+ __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */
+ __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */
+ __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */
+ __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */
+ __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */
+ __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_1[32];
+ __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */
+ __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */
+ __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */
} HASHCRYPT_Type;
/* ----------------------------------------------------------------------------
@@ -10662,8 +10010,9 @@ typedef struct
/*! @name CTRL - Control register to enable and operate Hash and Crypto */
/*! @{ */
-#define HASHCRYPT_CTRL_MODE_MASK (0x7U)
-#define HASHCRYPT_CTRL_MODE_SHIFT (0U)
+
+#define HASHCRYPT_CTRL_MODE_MASK (0x7U)
+#define HASHCRYPT_CTRL_MODE_SHIFT (0U)
/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if
* specific modes beyond SHA1 and SHA2-256 are available.
* 0b000..Disabled
@@ -10672,59 +10021,60 @@ typedef struct
* 0b100..AES if available (see also CRYPTCFG register for more controls)
* 0b101..ICB-AES if available (see also CRYPTCFG register for more controls)
*/
-#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK)
-#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U)
-#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U)
+#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK)
+
+#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U)
+#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U)
/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING
* Status bit will clear for a cycle during the initialization from New=1.
* 0b1..Starts a new Hash/Crypto and initializes the Digest/Result.
*/
-#define HASHCRYPT_CTRL_NEW_HASH(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK)
-#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U)
-#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U)
+#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK)
+
+#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U)
+#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U)
/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words
* and then will process the Hash. If Cryptographic, it will load as many words as needed,
* including key if not already loaded. It will then request again. Normal model is that the DMA
* interrupts the processor when its length expires. Note that if the processor will write the key and
* optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be
* expected to load those for the 1st block (when needed).
- * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is
- * used. 0b1..DMA will push in the data.
+ * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used.
+ * 0b1..DMA will push in the data.
*/
-#define HASHCRYPT_CTRL_DMA_I(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK)
-#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U)
-#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U)
+#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK)
+
+#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U)
+#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U)
/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the
* DMA has to know to switch direction and the locations. This can be used for crypto uses.
* 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt.
*/
-#define HASHCRYPT_CTRL_DMA_O(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK)
-#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U)
-#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U)
+#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK)
+
+#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U)
+#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U)
/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB
* is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For
* cryptographic swapping, see the CRYPTCFG register.
*/
-#define HASHCRYPT_CTRL_HASHSWPB(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK)
+#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK)
/*! @} */
/*! @name STATUS - Indicates status of Hash peripheral. */
/*! @{ */
-#define HASHCRYPT_STATUS_WAITING_MASK (0x1U)
-#define HASHCRYPT_STATUS_WAITING_SHIFT (0U)
+
+#define HASHCRYPT_STATUS_WAITING_MASK (0x1U)
+#define HASHCRYPT_STATUS_WAITING_SHIFT (0U)
/*! WAITING - If 1, the block is waiting for more data to process.
* 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set
* if IsLast is set nor will it set until at least 1 word is read of the output.
* 0b1..Waiting for data to be written in (16 words)
*/
-#define HASHCRYPT_STATUS_WAITING(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK)
-#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U)
-#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U)
+#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK)
+
+#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U)
+#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U)
/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block
* already started. For Cryptographic uses, this will be set for each block processed, indicating
* OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared
@@ -10733,106 +10083,106 @@ typedef struct
* 0b0..No Digest is ready
* 0b1..Digest is ready. Application may read it or may write more data
*/
-#define HASHCRYPT_STATUS_DIGEST(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK)
-#define HASHCRYPT_STATUS_ERROR_MASK (0x4U)
-#define HASHCRYPT_STATUS_ERROR_SHIFT (2U)
+#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK)
+
+#define HASHCRYPT_STATUS_ERROR_MASK (0x4U)
+#define HASHCRYPT_STATUS_ERROR_SHIFT (2U)
/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA
* was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT
* field will indicate which block it was on.
* 0b0..No error.
* 0b1..An error occurred since last cleared (written 1 to clear).
*/
-#define HASHCRYPT_STATUS_ERROR(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK)
-#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U)
-#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U)
+#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK)
+
+#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U)
+#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U)
/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING)
* 0b0..No Key is needed and writes will not be treated as Key
* 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING.
*/
-#define HASHCRYPT_STATUS_NEEDKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK)
-#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U)
-#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U)
+#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK)
+
+#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U)
+#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U)
/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING)
* 0b0..No IV/Nonce is needed, either because written already or because not needed.
* 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING.
*/
-#define HASHCRYPT_STATUS_NEEDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK)
-#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U)
-#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U)
+#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK)
+
+#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U)
+#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U)
/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from
* CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0,
* it has to compute the full ICB, quicker when not 0.
*/
-#define HASHCRYPT_STATUS_ICBIDX(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK)
+#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK)
/*! @} */
/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */
/*! @{ */
-#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U)
-#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U)
+
+#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U)
+#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U)
/*! WAITING - Indicates if should interrupt when waiting for data input.
* 0b0..Will not interrupt when waiting.
* 0b1..Will interrupt when waiting
*/
-#define HASHCRYPT_INTENSET_WAITING(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK)
-#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U)
-#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U)
-/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a
- * full sequence). 0b0..Will not interrupt when Digest is ready 0b1..Will interrupt when Digest is ready. Interrupt
- * cleared by writing more data, starting a new Hash, or disabling (done).
- */
-#define HASHCRYPT_INTENSET_DIGEST(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK)
-#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U)
-#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U)
+#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK)
+
+#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U)
+#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U)
+/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence).
+ * 0b0..Will not interrupt when Digest is ready
+ * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done).
+ */
+#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK)
+
+#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U)
+#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U)
/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status)
* 0b0..Will not interrupt on Error.
* 0b1..Will interrupt on Error (until cleared).
*/
-#define HASHCRYPT_INTENSET_ERROR(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK)
+#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK)
/*! @} */
/*! @name INTENCLR - Write 1 to clear interrupts. */
/*! @{ */
-#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U)
-#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U)
+
+#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U)
+#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U)
/*! WAITING - Write 1 to clear mask.
*/
-#define HASHCRYPT_INTENCLR_WAITING(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK)
-#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U)
-#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U)
+#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK)
+
+#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U)
+#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U)
/*! DIGEST - Write 1 to clear mask.
*/
-#define HASHCRYPT_INTENCLR_DIGEST(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK)
-#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U)
-#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U)
+#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK)
+
+#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U)
+#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U)
/*! ERROR - Write 1 to clear mask.
*/
-#define HASHCRYPT_INTENCLR_ERROR(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK)
+#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK)
/*! @} */
/*! @name MEMCTRL - Setup Master to access memory (if available) */
/*! @{ */
-#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U)
-#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U)
+
+#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U)
+#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U)
/*! MASTER - Enables mastering.
* 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA.
* 0b1..Mastering is enabled and DMA and INDATA should not be used.
*/
-#define HASHCRYPT_MEMCTRL_MASTER(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK)
-#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U)
-#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U)
+#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK)
+
+#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U)
+#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U)
/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks
* to copy starting at MEMADDR. This register will decrement after each block is copied, ending
* in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA
@@ -10840,148 +10190,147 @@ typedef struct
* to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit)
* blocks to hash.
*/
-#define HASHCRYPT_MEMCTRL_COUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK)
+#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK)
/*! @} */
/*! @name MEMADDR - Address to start memory access from (if available). */
/*! @{ */
-#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU)
-#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U)
+
+#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U)
/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will
* advance as it processes the words. If it fails with a bus error, the register will contain
* the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be
* able to address SPIFI.
*/
-#define HASHCRYPT_MEMADDR_BASE(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK)
+#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK)
/*! @} */
/*! @name INDATA - Input of 16 words at a time to load up buffer. */
/*! @{ */
-#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU)
-#define HASHCRYPT_INDATA_DATA_SHIFT (0U)
+
+#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_INDATA_DATA_SHIFT (0U)
/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this
* block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as
* bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block
* will swap the word to restore into big endian.
*/
-#define HASHCRYPT_INDATA_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK)
+#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK)
/*! @} */
/*! @name ALIAS - */
/*! @{ */
-#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU)
-#define HASHCRYPT_ALIAS_DATA_SHIFT (0U)
+
+#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_ALIAS_DATA_SHIFT (0U)
/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this
* block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as
* bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block
* will swap the word to restore into big endian.
*/
-#define HASHCRYPT_ALIAS_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK)
+#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK)
/*! @} */
/* The count of HASHCRYPT_ALIAS */
-#define HASHCRYPT_ALIAS_COUNT (7U)
+#define HASHCRYPT_ALIAS_COUNT (7U)
/*! @name DIGEST0 - */
/*! @{ */
-#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU)
-#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U)
-/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for
- * SHA1.
+
+#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U)
+/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1.
*/
-#define HASHCRYPT_DIGEST0_DIGEST(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK)
+#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK)
/*! @} */
/* The count of HASHCRYPT_DIGEST0 */
-#define HASHCRYPT_DIGEST0_COUNT (8U)
+#define HASHCRYPT_DIGEST0_COUNT (8U)
/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */
/*! @{ */
-#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U)
-#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U)
+
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U)
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U)
/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read
* in normal little endian - Least significant word 1st. Note: only if allowed by configuration.
*/
-#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK)
-#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U)
-#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U)
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK)
+
+#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U)
+#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U)
/*! SWAPKEY - If 1, will Swap the key input (bytes in each word).
*/
-#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK)
-#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U)
-#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U)
+#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK)
+
+#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U)
+#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U)
/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word).
*/
-#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK)
-#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U)
-#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U)
+#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK)
+
+#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U)
+#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U)
/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian.
* Note: only if allowed by configuration.
*/
-#define HASHCRYPT_CRYPTCFG_MSW1ST(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK)
-#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U)
-#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U)
+#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK)
+
+#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U)
+#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U)
/*! AESMODE - AES Cipher mode to use if plain AES
* 0b00..ECB - used as is
* 0b01..CBC mode (see details on IV/nonce)
* 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS.
* 0b11..reserved
*/
-#define HASHCRYPT_CRYPTCFG_AESMODE(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK)
-#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U)
-#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U)
+#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK)
+
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U)
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U)
/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB
* 0b0..Encrypt
* 0b1..Decrypt
*/
-#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK)
-#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U)
-#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U)
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK)
+
+#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U)
+#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U)
/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are
* used, only the highest level is permitted to select this.
* 0b0..User key provided in normal way
* 0b1..Secret key provided in hidden way by HW
*/
-#define HASHCRYPT_CRYPTCFG_AESSECRET(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK)
-#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U)
-#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U)
+#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK)
+
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U)
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U)
/*! AESKEYSZ - Sets the AES key size
* 0b00..128 bit key
* 0b01..192 bit key
* 0b10..256 bit key
* 0b11..reserved
*/
-#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK)
-#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U)
-#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U)
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK)
+
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U)
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U)
/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for
* Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if
* using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other
* use CTR should use ECB directly and do its own XOR and so on.
*/
-#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK)
-#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U)
-#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U)
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK)
+
+#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U)
+#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U)
/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash".
*/
-#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK)
-#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U)
-#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U)
+#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK)
+
+#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U)
+#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U)
/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the
* counter is assumed to occupy the low order bits of the IV.
* 0b00..32 bits of the IV/ctr are used (from 127:96)
@@ -10989,10 +10338,10 @@ typedef struct
* 0b10..96 bits of the IV/ctr are used (from 127:32)
* 0b11..All 128 bits of the IV/ctr are used
*/
-#define HASHCRYPT_CRYPTCFG_ICBSZ(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK)
-#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U)
-#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U)
+#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK)
+
+#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U)
+#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U)
/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new
* IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st.
* 0b00..8 blocks
@@ -11000,60 +10349,60 @@ typedef struct
* 0b10..32 blocks
* 0b11..64 blocks
*/
-#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK)
+#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK)
/*! @} */
/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */
/*! @{ */
-#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U)
-#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U)
+
+#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U)
+#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U)
/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit
*/
-#define HASHCRYPT_CONFIG_DUAL(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK)
-#define HASHCRYPT_CONFIG_DMA_MASK (0x2U)
-#define HASHCRYPT_CONFIG_DMA_SHIFT (1U)
+#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK)
+
+#define HASHCRYPT_CONFIG_DMA_MASK (0x2U)
+#define HASHCRYPT_CONFIG_DMA_SHIFT (1U)
/*! DMA - 1 if DMA is connected
*/
-#define HASHCRYPT_CONFIG_DMA(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK)
-#define HASHCRYPT_CONFIG_AHB_MASK (0x8U)
-#define HASHCRYPT_CONFIG_AHB_SHIFT (3U)
+#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK)
+
+#define HASHCRYPT_CONFIG_AHB_MASK (0x8U)
+#define HASHCRYPT_CONFIG_AHB_SHIFT (3U)
/*! AHB - 1 if AHB Master is enabled
*/
-#define HASHCRYPT_CONFIG_AHB(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK)
-#define HASHCRYPT_CONFIG_AES_MASK (0x40U)
-#define HASHCRYPT_CONFIG_AES_SHIFT (6U)
+#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK)
+
+#define HASHCRYPT_CONFIG_AES_MASK (0x40U)
+#define HASHCRYPT_CONFIG_AES_SHIFT (6U)
/*! AES - 1 if AES 128 included
*/
-#define HASHCRYPT_CONFIG_AES(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK)
-#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U)
-#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U)
+#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK)
+
+#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U)
+#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U)
/*! AESKEY - 1 if AES 192 and 256 also included
*/
-#define HASHCRYPT_CONFIG_AESKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK)
-#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U)
-#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U)
+#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK)
+
+#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U)
+#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U)
/*! SECRET - 1 if AES Secret key available
*/
-#define HASHCRYPT_CONFIG_SECRET(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK)
-#define HASHCRYPT_CONFIG_ICB_MASK (0x800U)
-#define HASHCRYPT_CONFIG_ICB_SHIFT (11U)
+#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK)
+
+#define HASHCRYPT_CONFIG_ICB_MASK (0x800U)
+#define HASHCRYPT_CONFIG_ICB_SHIFT (11U)
/*! ICB - 1 if ICB over AES included
*/
-#define HASHCRYPT_CONFIG_ICB(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK)
+#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK)
/*! @} */
/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */
/*! @{ */
-#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U)
-#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U)
+
+#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U)
+#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U)
/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock.
* If locked already, may only write if at same or higher security level as lock. Reads as: 0 if
* unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the
@@ -11061,83 +10410,68 @@ typedef struct
* 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests.
* 0b01..Locks to the current security level. AHB Master will issue requests at this level.
*/
-#define HASHCRYPT_LOCK_SECLOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK)
-#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U)
-#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U)
+#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK)
+
+#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U)
+#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U)
/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0
*/
-#define HASHCRYPT_LOCK_PATTERN(x) \
- (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK)
+#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK)
/*! @} */
/*! @name MASK - */
/*! @{ */
-#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU)
-#define HASHCRYPT_MASK_MASK_SHIFT (0U)
+
+#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU)
+#define HASHCRYPT_MASK_MASK_SHIFT (0U)
/*! MASK - A random word.
*/
-#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK)
+#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK)
/*! @} */
/* The count of HASHCRYPT_MASK */
-#define HASHCRYPT_MASK_COUNT (4U)
+#define HASHCRYPT_MASK_COUNT (4U)
+
/*!
* @}
*/ /* end of group HASHCRYPT_Register_Masks */
+
/* HASHCRYPT - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral HASHCRYPT base address */
-#define HASHCRYPT_BASE (0x500A4000u)
-/** Peripheral HASHCRYPT base address */
-#define HASHCRYPT_BASE_NS (0x400A4000u)
-/** Peripheral HASHCRYPT base pointer */
-#define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)
-/** Peripheral HASHCRYPT base pointer */
-#define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS)
-/** Array initializer of HASHCRYPT peripheral base addresses */
-#define HASHCRYPT_BASE_ADDRS \
- { \
- HASHCRYPT_BASE \
- }
-/** Array initializer of HASHCRYPT peripheral base pointers */
-#define HASHCRYPT_BASE_PTRS \
- { \
- HASHCRYPT \
- }
-/** Array initializer of HASHCRYPT peripheral base addresses */
-#define HASHCRYPT_BASE_ADDRS_NS \
- { \
- HASHCRYPT_BASE_NS \
- }
-/** Array initializer of HASHCRYPT peripheral base pointers */
-#define HASHCRYPT_BASE_PTRS_NS \
- { \
- HASHCRYPT_NS \
- }
+ /** Peripheral HASHCRYPT base address */
+ #define HASHCRYPT_BASE (0x500A4000u)
+ /** Peripheral HASHCRYPT base address */
+ #define HASHCRYPT_BASE_NS (0x400A4000u)
+ /** Peripheral HASHCRYPT base pointer */
+ #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)
+ /** Peripheral HASHCRYPT base pointer */
+ #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS)
+ /** Array initializer of HASHCRYPT peripheral base addresses */
+ #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE }
+ /** Array initializer of HASHCRYPT peripheral base pointers */
+ #define HASHCRYPT_BASE_PTRS { HASHCRYPT }
+ /** Array initializer of HASHCRYPT peripheral base addresses */
+ #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS }
+ /** Array initializer of HASHCRYPT peripheral base pointers */
+ #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS }
#else
-/** Peripheral HASHCRYPT base address */
-#define HASHCRYPT_BASE (0x400A4000u)
-/** Peripheral HASHCRYPT base pointer */
-#define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)
-/** Array initializer of HASHCRYPT peripheral base addresses */
-#define HASHCRYPT_BASE_ADDRS \
- { \
- HASHCRYPT_BASE \
- }
-/** Array initializer of HASHCRYPT peripheral base pointers */
-#define HASHCRYPT_BASE_PTRS \
- { \
- HASHCRYPT \
- }
+ /** Peripheral HASHCRYPT base address */
+ #define HASHCRYPT_BASE (0x400A4000u)
+ /** Peripheral HASHCRYPT base pointer */
+ #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)
+ /** Array initializer of HASHCRYPT peripheral base addresses */
+ #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE }
+ /** Array initializer of HASHCRYPT peripheral base pointers */
+ #define HASHCRYPT_BASE_PTRS { HASHCRYPT }
#endif
/*!
* @}
*/ /* end of group HASHCRYPT_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- I2C Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -11148,31 +10482,28 @@ typedef struct
*/
/** I2C - Register Layout Typedef */
-typedef struct
-{
- uint8_t RESERVED_0[2048];
- __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
- __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
- __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
- __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
- __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
- __IO uint32_t
- CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for
- the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
- __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
- uint8_t RESERVED_1[4];
- __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
- __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
- __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
- uint8_t RESERVED_2[20];
- __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
- __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
- __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
- __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
- uint8_t RESERVED_3[36];
- __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
- uint8_t RESERVED_4[1912];
- __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+typedef struct {
+ uint8_t RESERVED_0[2048];
+ __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
+ __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
+ __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
+ __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+ __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
+ __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
+ __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+ uint8_t RESERVED_2[20];
+ __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
+ __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+ __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
+ __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
+ uint8_t RESERVED_3[36];
+ __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
+ uint8_t RESERVED_4[1912];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
} I2C_Type;
/* ----------------------------------------------------------------------------
@@ -11186,40 +10517,45 @@ typedef struct
/*! @name CFG - Configuration for shared functions. */
/*! @{ */
-#define I2C_CFG_MSTEN_MASK (0x1U)
-#define I2C_CFG_MSTEN_SHIFT (0U)
+
+#define I2C_CFG_MSTEN_MASK (0x1U)
+#define I2C_CFG_MSTEN_SHIFT (0U)
/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
* changed, but the Master function is internally reset.
* 0b0..Disabled. The I2C Master function is disabled.
* 0b1..Enabled. The I2C Master function is enabled.
*/
-#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
-#define I2C_CFG_SLVEN_MASK (0x2U)
-#define I2C_CFG_SLVEN_SHIFT (1U)
+#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+
+#define I2C_CFG_SLVEN_MASK (0x2U)
+#define I2C_CFG_SLVEN_SHIFT (1U)
/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
* changed, but the Slave function is internally reset.
* 0b0..Disabled. The I2C slave function is disabled.
* 0b1..Enabled. The I2C slave function is enabled.
*/
-#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
-#define I2C_CFG_MONEN_MASK (0x4U)
-#define I2C_CFG_MONEN_SHIFT (2U)
+#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+
+#define I2C_CFG_MONEN_MASK (0x4U)
+#define I2C_CFG_MONEN_SHIFT (2U)
/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
* changed, but the Monitor function is internally reset.
* 0b0..Disabled. The I2C Monitor function is disabled.
* 0b1..Enabled. The I2C Monitor function is enabled.
*/
-#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
-#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
-#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
+#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+
+#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
* 0b0..Disabled. Time-out function is disabled.
* 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
* interrupts if they are enabled. Typically, only one time-out will be used in a system.
*/
-#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
-#define I2C_CFG_MONCLKSTR_MASK (0x10U)
-#define I2C_CFG_MONCLKSTR_SHIFT (4U)
+#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+
+#define I2C_CFG_MONCLKSTR_MASK (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT (4U)
/*! MONCLKSTR - Monitor function Clock Stretching.
* 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
* to read data provided by the Monitor function before it is overwritten. This mode may be used when
@@ -11227,9 +10563,10 @@ typedef struct
* 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
* read all incoming data supplied by the Monitor function.
*/
-#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
-#define I2C_CFG_HSCAPABLE_MASK (0x20U)
-#define I2C_CFG_HSCAPABLE_SHIFT (5U)
+#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+
+#define I2C_CFG_HSCAPABLE_MASK (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT (5U)
/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive
* and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies
* to all functions: Master, Slave, and Monitor.
@@ -11241,39 +10578,42 @@ typedef struct
* High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more
* information.
*/
-#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
/*! @} */
/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
/*! @{ */
-#define I2C_STAT_MSTPENDING_MASK (0x1U)
-#define I2C_STAT_MSTPENDING_SHIFT (0U)
+
+#define I2C_STAT_MSTPENDING_MASK (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT (0U)
/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
* the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
* type of software service if any the master expects. This flag will cause an interrupt when set
* if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
* an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
* state, and no communication is needed, mask this interrupt.
- * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a
- * command. 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in
- * the idle state, it is waiting to receive or transmit data or the NACK bit.
+ * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
+ * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
+ * idle state, it is waiting to receive or transmit data or the NACK bit.
*/
-#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
-#define I2C_STAT_MSTSTATE_MASK (0xEU)
-#define I2C_STAT_MSTSTATE_SHIFT (1U)
+#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+
+#define I2C_STAT_MSTSTATE_MASK (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT (1U)
/*! MSTSTATE - Master State code. The master state code reflects the master state when the
* MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
* indicates a specific required service for the Master function. All other values are reserved. See
* Table 400 for details of state values and appropriate responses.
* 0b000..Idle. The Master function is available to be used for a new transaction.
- * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and
- * Acknowledged by slave. 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write
- * was previously sent and Acknowledged by slave. 0b011..NACK Address. Slave NACKed address. 0b100..NACK Data. Slave
- * NACKed transmitted data.
- */
-#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
-#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
-#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
+ * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
+ * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
+ * 0b011..NACK Address. Slave NACKed address.
+ * 0b100..NACK Data. Slave NACKed transmitted data.
+ */
+#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+
+#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
* this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
* 0b0..No Arbitration Loss has occurred.
@@ -11281,9 +10621,10 @@ typedef struct
* function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
* or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
*/
-#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
-#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
-#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
+#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+
+#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
* this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
* 0b0..No Start/Stop Error has occurred.
@@ -11292,10 +10633,10 @@ typedef struct
* idle state, no action is required. A request for a Start could be made, or software could attempt to insure
* that the bus has not stalled.
*/
-#define I2C_STAT_MSTSTSTPERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
-#define I2C_STAT_SLVPENDING_MASK (0x100U)
-#define I2C_STAT_SLVPENDING_SHIFT (8U)
+#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+
+#define I2C_STAT_SLVPENDING_MASK (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT (8U)
/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
* communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
* enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
@@ -11307,33 +10648,35 @@ typedef struct
* also be detected automatically, since the address must be acknowledged before the clock can be
* stretched.
* 0b0..In progress. The Slave function does not currently need service.
- * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE
- * field.
+ * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
*/
-#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
-#define I2C_STAT_SLVSTATE_MASK (0x600U)
-#define I2C_STAT_SLVSTATE_SHIFT (9U)
+#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+
+#define I2C_STAT_SLVSTATE_MASK (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT (9U)
/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
* the Slave function. All other values are reserved. See Table 401 for state values and actions.
* note that the occurrence of some states and how they are handled are affected by DMA mode and
* Automatic Operation modes.
- * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by
- * hardware. 0b01..Slave receive. Received data is available (Slave Receiver mode). 0b10..Slave transmit. Data can be
- * transmitted (Slave Transmitter mode).
+ * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
+ * 0b01..Slave receive. Received data is available (Slave Receiver mode).
+ * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
*/
-#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
-#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
-#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
+#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+
+#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
* This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
* operation. This read-only flag reflects the slave function status in real time.
- * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot
- * be entered at this time. 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock.
- * Deep-sleep or Power-down mode could be entered at this time.
+ * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
+ * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
+ * Power-down mode could be entered at this time.
*/
-#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
-#define I2C_STAT_SLVIDX_MASK (0x3000U)
-#define I2C_STAT_SLVIDX_SHIFT (12U)
+#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+
+#define I2C_STAT_SLVIDX_MASK (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT (12U)
/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
* selected by receiving an address that matches one of the slave addresses defined by any enabled
* slave address registers, and provides an identification of the address that was matched. It is
@@ -11343,9 +10686,10 @@ typedef struct
* 0b10..Address 2. Slave address 2 was matched.
* 0b11..Address 3. Slave address 3 was matched.
*/
-#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
-#define I2C_STAT_SLVSEL_MASK (0x4000U)
-#define I2C_STAT_SLVSEL_SHIFT (14U)
+#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+
+#define I2C_STAT_SLVSEL_MASK (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT (14U)
/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
* function to acknowledge the address, or when the address has been automatically acknowledged.
* It is cleared when another address cycle presents an address that does not match an enabled
@@ -11355,9 +10699,10 @@ typedef struct
* 0b0..Not selected. The Slave function is not currently selected.
* 0b1..Selected. The Slave function is currently selected.
*/
-#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
-#define I2C_STAT_SLVDESEL_MASK (0x8000U)
-#define I2C_STAT_SLVDESEL_SHIFT (15U)
+#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+
+#define I2C_STAT_SLVDESEL_MASK (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT (15U)
/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
* INTENSET. This flag can be cleared by writing a 1 to this bit.
* 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
@@ -11365,33 +10710,37 @@ typedef struct
* 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
* changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
*/
-#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
-#define I2C_STAT_MONRDY_MASK (0x10000U)
-#define I2C_STAT_MONRDY_SHIFT (16U)
+#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+
+#define I2C_STAT_MONRDY_MASK (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT (16U)
/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
* 0b0..No data. The Monitor function does not currently have data available.
* 0b1..Data waiting. The Monitor function has data waiting to be read.
*/
-#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
-#define I2C_STAT_MONOV_MASK (0x20000U)
-#define I2C_STAT_MONOV_SHIFT (17U)
+#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+
+#define I2C_STAT_MONOV_MASK (0x20000U)
+#define I2C_STAT_MONOV_SHIFT (17U)
/*! MONOV - Monitor Overflow flag.
* 0b0..No overrun. Monitor data has not overrun.
* 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
* enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
*/
-#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
-#define I2C_STAT_MONACTIVE_MASK (0x40000U)
-#define I2C_STAT_MONACTIVE_SHIFT (18U)
+#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+
+#define I2C_STAT_MONACTIVE_MASK (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT (18U)
/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
* be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
* more recently than a bus Stop.
* 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
* 0b1..Active. The Monitor function considers the I2C bus to be active.
*/
-#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
-#define I2C_STAT_MONIDLE_MASK (0x80000U)
-#define I2C_STAT_MONIDLE_SHIFT (19U)
+#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+
+#define I2C_STAT_MONIDLE_MASK (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT (19U)
/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
* from active to inactive. This can be used by software to decide when to process data
* accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
@@ -11399,202 +10748,204 @@ typedef struct
* 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
* 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
*/
-#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
-#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
-#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
+#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+
+#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
* longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
* edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
* is idle.
* 0b0..No time-out. I2C bus events have not caused a time-out.
- * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT
- * register.
+ * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
*/
-#define I2C_STAT_EVENTTIMEOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
-#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
-#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
+#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+
+#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
* time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
* 0b0..No time-out. SCL low time has not caused a time-out.
* 0b1..Time-out. SCL low time has caused a time-out.
*/
-#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
/*! @} */
/*! @name INTENSET - Interrupt Enable Set and read register. */
/*! @{ */
-#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
-#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
+
+#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
/*! MSTPENDINGEN - Master Pending interrupt Enable.
* 0b0..Disabled. The MstPending interrupt is disabled.
* 0b1..Enabled. The MstPending interrupt is enabled.
*/
-#define I2C_INTENSET_MSTPENDINGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
-#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
-#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
+#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+
+#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
* 0b0..Disabled. The MstArbLoss interrupt is disabled.
* 0b1..Enabled. The MstArbLoss interrupt is enabled.
*/
-#define I2C_INTENSET_MSTARBLOSSEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
-#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
-#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
+#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+
+#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
* 0b0..Disabled. The MstStStpErr interrupt is disabled.
* 0b1..Enabled. The MstStStpErr interrupt is enabled.
*/
-#define I2C_INTENSET_MSTSTSTPERREN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
-#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
-#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
+#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+
+#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
/*! SLVPENDINGEN - Slave Pending interrupt Enable.
* 0b0..Disabled. The SlvPending interrupt is disabled.
* 0b1..Enabled. The SlvPending interrupt is enabled.
*/
-#define I2C_INTENSET_SLVPENDINGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
-#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
-#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
+#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+
+#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
* 0b0..Disabled. The SlvNotStr interrupt is disabled.
* 0b1..Enabled. The SlvNotStr interrupt is enabled.
*/
-#define I2C_INTENSET_SLVNOTSTREN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
-#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
-#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
+#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+
+#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
/*! SLVDESELEN - Slave Deselect interrupt Enable.
* 0b0..Disabled. The SlvDeSel interrupt is disabled.
* 0b1..Enabled. The SlvDeSel interrupt is enabled.
*/
-#define I2C_INTENSET_SLVDESELEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
-#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
-#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
+#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+
+#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
/*! MONRDYEN - Monitor data Ready interrupt Enable.
* 0b0..Disabled. The MonRdy interrupt is disabled.
* 0b1..Enabled. The MonRdy interrupt is enabled.
*/
-#define I2C_INTENSET_MONRDYEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
-#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
-#define I2C_INTENSET_MONOVEN_SHIFT (17U)
+#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+
+#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT (17U)
/*! MONOVEN - Monitor Overrun interrupt Enable.
* 0b0..Disabled. The MonOv interrupt is disabled.
* 0b1..Enabled. The MonOv interrupt is enabled.
*/
-#define I2C_INTENSET_MONOVEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
-#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
-#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
+#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+
+#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
/*! MONIDLEEN - Monitor Idle interrupt Enable.
* 0b0..Disabled. The MonIdle interrupt is disabled.
* 0b1..Enabled. The MonIdle interrupt is enabled.
*/
-#define I2C_INTENSET_MONIDLEEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
-#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
-#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
+#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
* 0b0..Disabled. The Event time-out interrupt is disabled.
* 0b1..Enabled. The Event time-out interrupt is enabled.
*/
-#define I2C_INTENSET_EVENTTIMEOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
-#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
-#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
+#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
* 0b0..Disabled. The SCL time-out interrupt is disabled.
* 0b1..Enabled. The SCL time-out interrupt is enabled.
*/
-#define I2C_INTENSET_SCLTIMEOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
/*! @} */
/*! @name INTENCLR - Interrupt Enable Clear register. */
/*! @{ */
-#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
-#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
+
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
* bit in the INTENSET register if implemented.
*/
-#define I2C_INTENCLR_MSTPENDINGCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
-#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
-#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
+#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
*/
-#define I2C_INTENCLR_MSTARBLOSSCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
-#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
-#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
+#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
*/
-#define I2C_INTENCLR_MSTSTSTPERRCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
-#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
-#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
/*! SLVPENDINGCLR - Slave Pending interrupt clear.
*/
-#define I2C_INTENCLR_SLVPENDINGCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
-#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
-#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
+#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
*/
-#define I2C_INTENCLR_SLVNOTSTRCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
-#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
-#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
+#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+
+#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
/*! SLVDESELCLR - Slave Deselect interrupt clear.
*/
-#define I2C_INTENCLR_SLVDESELCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
-#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
-#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
+#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+
+#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
/*! MONRDYCLR - Monitor data Ready interrupt clear.
*/
-#define I2C_INTENCLR_MONRDYCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
-#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
-#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
+#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+
+#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
/*! MONOVCLR - Monitor Overrun interrupt clear.
*/
-#define I2C_INTENCLR_MONOVCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
-#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
-#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
+#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+
+#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
/*! MONIDLECLR - Monitor Idle interrupt clear.
*/
-#define I2C_INTENCLR_MONIDLECLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
+#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
*/
-#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
-#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
-#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
*/
-#define I2C_INTENCLR_SCLTIMEOUTCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
/*! @} */
/*! @name TIMEOUT - Time-out value register. */
/*! @{ */
-#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
-#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
+
+#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
* time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
*/
-#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
-#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
-#define I2C_TIMEOUT_TO_SHIFT (4U)
+#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+
+#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT (4U)
/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
* function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
* disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
@@ -11602,117 +10953,123 @@ typedef struct
* 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
* I2C function clock.
*/
-#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
/*! @} */
-/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the
- * MSTTIME register, and controls some timing of the Slave function. */
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
/*! @{ */
-#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
-#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
+
+#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
* need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
* FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
* divided by 65,536 before use.
*/
-#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
/*! @} */
/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
/*! @{ */
-#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
-#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
+
+#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
/*! MSTPENDING - Master Pending.
*/
-#define I2C_INTSTAT_MSTPENDING(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
-#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
-#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
+#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+
+#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
/*! MSTARBLOSS - Master Arbitration Loss flag.
*/
-#define I2C_INTSTAT_MSTARBLOSS(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
-#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
-#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
+#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+
+#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
/*! MSTSTSTPERR - Master Start/Stop Error flag.
*/
-#define I2C_INTSTAT_MSTSTSTPERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
-#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
-#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
+#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+
+#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
/*! SLVPENDING - Slave Pending.
*/
-#define I2C_INTSTAT_SLVPENDING(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
-#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
-#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
+#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+
+#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
/*! SLVNOTSTR - Slave Not Stretching status.
*/
-#define I2C_INTSTAT_SLVNOTSTR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
-#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
-#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
+#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+
+#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
/*! SLVDESEL - Slave Deselected flag.
*/
-#define I2C_INTSTAT_SLVDESEL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
-#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
-#define I2C_INTSTAT_MONRDY_SHIFT (16U)
+#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+
+#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT (16U)
/*! MONRDY - Monitor Ready.
*/
-#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
-#define I2C_INTSTAT_MONOV_MASK (0x20000U)
-#define I2C_INTSTAT_MONOV_SHIFT (17U)
+#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+
+#define I2C_INTSTAT_MONOV_MASK (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT (17U)
/*! MONOV - Monitor Overflow flag.
*/
-#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
-#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
-#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
+#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+
+#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
/*! MONIDLE - Monitor Idle flag.
*/
-#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
-#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
-#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
+#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
/*! EVENTTIMEOUT - Event time-out Interrupt flag.
*/
-#define I2C_INTSTAT_EVENTTIMEOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
-#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
-#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
+#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+
+#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
/*! SCLTIMEOUT - SCL time-out Interrupt flag.
*/
-#define I2C_INTSTAT_SCLTIMEOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
/*! @} */
/*! @name MSTCTL - Master control register. */
/*! @{ */
-#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
-#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
+
+#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
/*! MSTCONTINUE - Master Continue. This bit is write-only.
* 0b0..No effect.
* 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing
* transmit data, reading received data, or any other housekeeping related to the next bus operation.
*/
-#define I2C_MSTCTL_MSTCONTINUE(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
-#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
-#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
+#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+
+#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
/*! MSTSTART - Master Start control. This bit is write-only.
* 0b0..No effect.
* 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
*/
-#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
-#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
-#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
+#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+
+#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
/*! MSTSTOP - Master Stop control. This bit is write-only.
* 0b0..No effect.
* 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
* if the master is receiving data from the slave (Master Receiver mode).
*/
-#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
-#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
-#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
+#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+
+#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
* operations such as Start, address, Stop, and address match must always be done with software,
* typically via an interrupt. Address acknowledgement must also be done by software except when
@@ -11724,13 +11081,14 @@ typedef struct
* 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
* Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
*/
-#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
/*! @} */
/*! @name MSTTIME - Master timing configuration. */
/*! @{ */
-#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
-#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
+
+#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
* master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
* corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
@@ -11744,10 +11102,10 @@ typedef struct
* 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
* 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
*/
-#define I2C_MSTTIME_MSTSCLLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
-#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
-#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
+#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+
+#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
* master on SCL. Other masters in a multi-master system could shorten this time. This
* corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
@@ -11761,24 +11119,25 @@ typedef struct
* 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
* 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
*/
-#define I2C_MSTTIME_MSTSCLHIGH(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
/*! @} */
/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
/*! @{ */
-#define I2C_MSTDAT_DATA_MASK (0xFFU)
-#define I2C_MSTDAT_DATA_SHIFT (0U)
+
+#define I2C_MSTDAT_DATA_MASK (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT (0U)
/*! DATA - Master function data register. Read: read the most recently received data for the Master
* function. Write: transmit data using the Master function.
*/
-#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
/*! @} */
/*! @name SLVCTL - Slave control register. */
/*! @{ */
-#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
-#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
+
+#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
/*! SLVCONTINUE - Slave Continue.
* 0b0..No effect.
* 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag
@@ -11786,25 +11145,26 @@ typedef struct
* housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE
* should not be set unless SLVPENDING = 1.
*/
-#define I2C_SLVCTL_SLVCONTINUE(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
-#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
-#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
+#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+
+#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
/*! SLVNACK - Slave NACK.
* 0b0..No effect.
- * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave
- * Receiver mode).
+ * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
*/
-#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
-#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
-#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
+#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+
+#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
/*! SLVDMA - Slave DMA enable.
* 0b0..Disabled. No DMA requests are issued for Slave mode operation.
* 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
*/
-#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
-#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
-#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
+#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+
+#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches
* SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA
* to allow processing of the data without intervention. If this bit is clear and a header
@@ -11817,9 +11177,10 @@ typedef struct
* not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK
* is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.
*/
-#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
-#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
-#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
+#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write
* request on the next header with an address matching SLVADR0. Since DMA needs to be configured to
* match the transfer direction, the direction needs to be specified. This bit allows a direction to
@@ -11827,61 +11188,64 @@ typedef struct
* 0b0..The expected next operation in Automatic Mode is an I2C write.
* 0b1..The expected next operation in Automatic Mode is an I2C read.
*/
-#define I2C_SLVCTL_AUTOMATCHREAD(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
/*! @} */
/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
/*! @{ */
-#define I2C_SLVDAT_DATA_MASK (0xFFU)
-#define I2C_SLVDAT_DATA_SHIFT (0U)
+
+#define I2C_SLVDAT_DATA_MASK (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT (0U)
/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
* function. Write: transmit data using the Slave function.
*/
-#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
/*! @} */
/*! @name SLVADR - Slave address register. */
/*! @{ */
-#define I2C_SLVADR_SADISABLE_MASK (0x1U)
-#define I2C_SLVADR_SADISABLE_SHIFT (0U)
+
+#define I2C_SLVADR_SADISABLE_MASK (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT (0U)
/*! SADISABLE - Slave Address n Disable.
* 0b0..Enabled. Slave Address n is enabled.
* 0b1..Ignored Slave Address n is ignored.
*/
-#define I2C_SLVADR_SADISABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
-#define I2C_SLVADR_SLVADR_MASK (0xFEU)
-#define I2C_SLVADR_SLVADR_SHIFT (1U)
+#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+
+#define I2C_SLVADR_SLVADR_MASK (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT (1U)
/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
*/
-#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
-#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
-#define I2C_SLVADR_AUTONACK_SHIFT (15U)
+#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+
+#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT (15U)
/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows
* software to ignore I2C traffic while handling previous I2C data or other operations.
* 0b0..Normal operation, matching I2C addresses are not ignored.
* 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches
* SLVADRn, and AUTOMATCHREAD matches the direction.
*/
-#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
/*! @} */
/* The count of I2C_SLVADR */
-#define I2C_SLVADR_COUNT (4U)
+#define I2C_SLVADR_COUNT (4U)
/*! @name SLVQUAL0 - Slave Qualification for address 0. */
/*! @{ */
-#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
-#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
+
+#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
/*! QUALMODE0 - Qualify mode for slave address 0.
* 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
* 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
*/
-#define I2C_SLVQUAL0_QUALMODE0(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
-#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
-#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
+#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+
+#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
* be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
* set to 1 will cause an automatic match of the corresponding bit of the received address when it
@@ -11889,214 +11253,197 @@ typedef struct
* address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
* (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
*/
-#define I2C_SLVQUAL0_SLVQUAL0(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
/*! @} */
/*! @name MONRXDAT - Monitor receiver data register. */
/*! @{ */
-#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
-#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
+
+#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
*/
-#define I2C_MONRXDAT_MONRXDAT(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
-#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
-#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
+#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+
+#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
/*! MONSTART - Monitor Received Start.
* 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
* 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
*/
-#define I2C_MONRXDAT_MONSTART(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
-#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
-#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
+#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+
+#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
/*! MONRESTART - Monitor Received Repeated Start.
* 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
* 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
*/
-#define I2C_MONRXDAT_MONRESTART(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
-#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
-#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
+#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+
+#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
/*! MONNACK - Monitor Received NACK.
- * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master
- * or slave receiver. 0b1..Not acknowledged. The data currently being provided by the Monitor function was not
- * acknowledged by any receiver.
+ * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
+ * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
*/
-#define I2C_MONRXDAT_MONNACK(x) \
- (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
/*! @} */
/*! @name ID - Peripheral identification register. */
/*! @{ */
-#define I2C_ID_APERTURE_MASK (0xFFU)
-#define I2C_ID_APERTURE_SHIFT (0U)
+
+#define I2C_ID_APERTURE_MASK (0xFFU)
+#define I2C_ID_APERTURE_SHIFT (0U)
/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
*/
-#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
-#define I2C_ID_MINOR_REV_MASK (0xF00U)
-#define I2C_ID_MINOR_REV_SHIFT (8U)
+#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+
+#define I2C_ID_MINOR_REV_MASK (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT (8U)
/*! MINOR_REV - Minor revision of module implementation.
*/
-#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
-#define I2C_ID_MAJOR_REV_MASK (0xF000U)
-#define I2C_ID_MAJOR_REV_SHIFT (12U)
+#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+
+#define I2C_ID_MAJOR_REV_MASK (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT (12U)
/*! MAJOR_REV - Major revision of module implementation.
*/
-#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
-#define I2C_ID_ID_MASK (0xFFFF0000U)
-#define I2C_ID_ID_SHIFT (16U)
+#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+
+#define I2C_ID_ID_MASK (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT (16U)
/*! ID - Module identifier for the selected function.
*/
-#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group I2C_Register_Masks */
+
/* I2C - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x50086000u)
-/** Peripheral I2C0 base address */
-#define I2C0_BASE_NS (0x40086000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-/** Peripheral I2C0 base pointer */
-#define I2C0_NS ((I2C_Type *)I2C0_BASE_NS)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE (0x50087000u)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE_NS (0x40087000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-/** Peripheral I2C1 base pointer */
-#define I2C1_NS ((I2C_Type *)I2C1_BASE_NS)
-/** Peripheral I2C2 base address */
-#define I2C2_BASE (0x50088000u)
-/** Peripheral I2C2 base address */
-#define I2C2_BASE_NS (0x40088000u)
-/** Peripheral I2C2 base pointer */
-#define I2C2 ((I2C_Type *)I2C2_BASE)
-/** Peripheral I2C2 base pointer */
-#define I2C2_NS ((I2C_Type *)I2C2_BASE_NS)
-/** Peripheral I2C3 base address */
-#define I2C3_BASE (0x50089000u)
-/** Peripheral I2C3 base address */
-#define I2C3_BASE_NS (0x40089000u)
-/** Peripheral I2C3 base pointer */
-#define I2C3 ((I2C_Type *)I2C3_BASE)
-/** Peripheral I2C3 base pointer */
-#define I2C3_NS ((I2C_Type *)I2C3_BASE_NS)
-/** Peripheral I2C4 base address */
-#define I2C4_BASE (0x5008A000u)
-/** Peripheral I2C4 base address */
-#define I2C4_BASE_NS (0x4008A000u)
-/** Peripheral I2C4 base pointer */
-#define I2C4 ((I2C_Type *)I2C4_BASE)
-/** Peripheral I2C4 base pointer */
-#define I2C4_NS ((I2C_Type *)I2C4_BASE_NS)
-/** Peripheral I2C5 base address */
-#define I2C5_BASE (0x50096000u)
-/** Peripheral I2C5 base address */
-#define I2C5_BASE_NS (0x40096000u)
-/** Peripheral I2C5 base pointer */
-#define I2C5 ((I2C_Type *)I2C5_BASE)
-/** Peripheral I2C5 base pointer */
-#define I2C5_NS ((I2C_Type *)I2C5_BASE_NS)
-/** Peripheral I2C6 base address */
-#define I2C6_BASE (0x50097000u)
-/** Peripheral I2C6 base address */
-#define I2C6_BASE_NS (0x40097000u)
-/** Peripheral I2C6 base pointer */
-#define I2C6 ((I2C_Type *)I2C6_BASE)
-/** Peripheral I2C6 base pointer */
-#define I2C6_NS ((I2C_Type *)I2C6_BASE_NS)
-/** Peripheral I2C7 base address */
-#define I2C7_BASE (0x50098000u)
-/** Peripheral I2C7 base address */
-#define I2C7_BASE_NS (0x40098000u)
-/** Peripheral I2C7 base pointer */
-#define I2C7 ((I2C_Type *)I2C7_BASE)
-/** Peripheral I2C7 base pointer */
-#define I2C7_NS ((I2C_Type *)I2C7_BASE_NS)
-/** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS \
- { \
- I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE \
- }
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS \
- { \
- I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 \
- }
-/** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS_NS \
- { \
- I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS \
- }
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS_NS \
- { \
- I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS \
- }
+ /** Peripheral I2C0 base address */
+ #define I2C0_BASE (0x50086000u)
+ /** Peripheral I2C0 base address */
+ #define I2C0_BASE_NS (0x40086000u)
+ /** Peripheral I2C0 base pointer */
+ #define I2C0 ((I2C_Type *)I2C0_BASE)
+ /** Peripheral I2C0 base pointer */
+ #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS)
+ /** Peripheral I2C1 base address */
+ #define I2C1_BASE (0x50087000u)
+ /** Peripheral I2C1 base address */
+ #define I2C1_BASE_NS (0x40087000u)
+ /** Peripheral I2C1 base pointer */
+ #define I2C1 ((I2C_Type *)I2C1_BASE)
+ /** Peripheral I2C1 base pointer */
+ #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS)
+ /** Peripheral I2C2 base address */
+ #define I2C2_BASE (0x50088000u)
+ /** Peripheral I2C2 base address */
+ #define I2C2_BASE_NS (0x40088000u)
+ /** Peripheral I2C2 base pointer */
+ #define I2C2 ((I2C_Type *)I2C2_BASE)
+ /** Peripheral I2C2 base pointer */
+ #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS)
+ /** Peripheral I2C3 base address */
+ #define I2C3_BASE (0x50089000u)
+ /** Peripheral I2C3 base address */
+ #define I2C3_BASE_NS (0x40089000u)
+ /** Peripheral I2C3 base pointer */
+ #define I2C3 ((I2C_Type *)I2C3_BASE)
+ /** Peripheral I2C3 base pointer */
+ #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS)
+ /** Peripheral I2C4 base address */
+ #define I2C4_BASE (0x5008A000u)
+ /** Peripheral I2C4 base address */
+ #define I2C4_BASE_NS (0x4008A000u)
+ /** Peripheral I2C4 base pointer */
+ #define I2C4 ((I2C_Type *)I2C4_BASE)
+ /** Peripheral I2C4 base pointer */
+ #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS)
+ /** Peripheral I2C5 base address */
+ #define I2C5_BASE (0x50096000u)
+ /** Peripheral I2C5 base address */
+ #define I2C5_BASE_NS (0x40096000u)
+ /** Peripheral I2C5 base pointer */
+ #define I2C5 ((I2C_Type *)I2C5_BASE)
+ /** Peripheral I2C5 base pointer */
+ #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS)
+ /** Peripheral I2C6 base address */
+ #define I2C6_BASE (0x50097000u)
+ /** Peripheral I2C6 base address */
+ #define I2C6_BASE_NS (0x40097000u)
+ /** Peripheral I2C6 base pointer */
+ #define I2C6 ((I2C_Type *)I2C6_BASE)
+ /** Peripheral I2C6 base pointer */
+ #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS)
+ /** Peripheral I2C7 base address */
+ #define I2C7_BASE (0x50098000u)
+ /** Peripheral I2C7 base address */
+ #define I2C7_BASE_NS (0x40098000u)
+ /** Peripheral I2C7 base pointer */
+ #define I2C7 ((I2C_Type *)I2C7_BASE)
+ /** Peripheral I2C7 base pointer */
+ #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS)
+ /** Array initializer of I2C peripheral base addresses */
+ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
+ /** Array initializer of I2C peripheral base pointers */
+ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
+ /** Array initializer of I2C peripheral base addresses */
+ #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS }
+ /** Array initializer of I2C peripheral base pointers */
+ #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS }
#else
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40086000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE (0x40087000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-/** Peripheral I2C2 base address */
-#define I2C2_BASE (0x40088000u)
-/** Peripheral I2C2 base pointer */
-#define I2C2 ((I2C_Type *)I2C2_BASE)
-/** Peripheral I2C3 base address */
-#define I2C3_BASE (0x40089000u)
-/** Peripheral I2C3 base pointer */
-#define I2C3 ((I2C_Type *)I2C3_BASE)
-/** Peripheral I2C4 base address */
-#define I2C4_BASE (0x4008A000u)
-/** Peripheral I2C4 base pointer */
-#define I2C4 ((I2C_Type *)I2C4_BASE)
-/** Peripheral I2C5 base address */
-#define I2C5_BASE (0x40096000u)
-/** Peripheral I2C5 base pointer */
-#define I2C5 ((I2C_Type *)I2C5_BASE)
-/** Peripheral I2C6 base address */
-#define I2C6_BASE (0x40097000u)
-/** Peripheral I2C6 base pointer */
-#define I2C6 ((I2C_Type *)I2C6_BASE)
-/** Peripheral I2C7 base address */
-#define I2C7_BASE (0x40098000u)
-/** Peripheral I2C7 base pointer */
-#define I2C7 ((I2C_Type *)I2C7_BASE)
-/** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS \
- { \
- I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE \
- }
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS \
- { \
- I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 \
- }
+ /** Peripheral I2C0 base address */
+ #define I2C0_BASE (0x40086000u)
+ /** Peripheral I2C0 base pointer */
+ #define I2C0 ((I2C_Type *)I2C0_BASE)
+ /** Peripheral I2C1 base address */
+ #define I2C1_BASE (0x40087000u)
+ /** Peripheral I2C1 base pointer */
+ #define I2C1 ((I2C_Type *)I2C1_BASE)
+ /** Peripheral I2C2 base address */
+ #define I2C2_BASE (0x40088000u)
+ /** Peripheral I2C2 base pointer */
+ #define I2C2 ((I2C_Type *)I2C2_BASE)
+ /** Peripheral I2C3 base address */
+ #define I2C3_BASE (0x40089000u)
+ /** Peripheral I2C3 base pointer */
+ #define I2C3 ((I2C_Type *)I2C3_BASE)
+ /** Peripheral I2C4 base address */
+ #define I2C4_BASE (0x4008A000u)
+ /** Peripheral I2C4 base pointer */
+ #define I2C4 ((I2C_Type *)I2C4_BASE)
+ /** Peripheral I2C5 base address */
+ #define I2C5_BASE (0x40096000u)
+ /** Peripheral I2C5 base pointer */
+ #define I2C5 ((I2C_Type *)I2C5_BASE)
+ /** Peripheral I2C6 base address */
+ #define I2C6_BASE (0x40097000u)
+ /** Peripheral I2C6 base pointer */
+ #define I2C6 ((I2C_Type *)I2C6_BASE)
+ /** Peripheral I2C7 base address */
+ #define I2C7_BASE (0x40098000u)
+ /** Peripheral I2C7 base pointer */
+ #define I2C7 ((I2C_Type *)I2C7_BASE)
+ /** Array initializer of I2C peripheral base addresses */
+ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }
+ /** Array initializer of I2C peripheral base pointers */
+ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }
#endif
/** Interrupt vectors for the I2C peripheral type */
-#define I2C_IRQS \
- { \
- FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, \
- FLEXCOMM6_IRQn, FLEXCOMM7_IRQn \
- }
+#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -12107,36 +11454,32 @@ typedef struct
*/
/** I2S - Register Layout Typedef */
-typedef struct
-{
- uint8_t RESERVED_0[3072];
- __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
- __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
- __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
- uint8_t RESERVED_1[16];
- __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
- uint8_t RESERVED_2[480];
- __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
- __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
- __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
- uint8_t RESERVED_3[4];
- __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
- __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
- __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
- uint8_t RESERVED_4[4];
- __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
- __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x
- 24-bit data and not using DMA., offset: 0xE24 */
- uint8_t RESERVED_5[8];
- __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
- __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x
- 24-bit data and not using DMA., offset: 0xE34 */
- uint8_t RESERVED_6[8];
- __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
- __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S
- is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
- uint8_t RESERVED_7[436];
- __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */
+typedef struct {
+ uint8_t RESERVED_0[3072];
+ __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+ __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+ __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+ uint8_t RESERVED_2[480];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+ uint8_t RESERVED_6[8];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+ uint8_t RESERVED_7[436];
+ __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */
} I2S_Type;
/* ----------------------------------------------------------------------------
@@ -12150,17 +11493,18 @@ typedef struct
/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
/*! @{ */
-#define I2S_CFG1_MAINENABLE_MASK (0x1U)
-#define I2S_CFG1_MAINENABLE_SHIFT (0U)
+
+#define I2S_CFG1_MAINENABLE_MASK (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT (0U)
/*! MAINENABLE - Main enable for I 2S function in this Flexcomm
* 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags
* are reset. No other channel pairs can be enabled.
- * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual
- * PAIRENABLE bits.
+ * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
*/
-#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
-#define I2S_CFG1_DATAPAUSE_MASK (0x2U)
-#define I2S_CFG1_DATAPAUSE_SHIFT (1U)
+#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+
+#define I2S_CFG1_DATAPAUSE_MASK (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT (1U)
/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer
* and the FIFO. This could be done in order to change streams, or while restarting after a data
* underflow or overflow. When paused, FIFO operations can be done without corrupting data that is
@@ -12172,9 +11516,10 @@ typedef struct
* 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.
* 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.
*/
-#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
-#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
-#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
+#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+
+#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field
* whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this
* Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs
@@ -12184,19 +11529,21 @@ typedef struct
* 0b10..3 I2S channel pairs in this flexcomm
* 0b11..4 I2S channel pairs in this flexcomm
*/
-#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
-#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
-#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
-/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this
- * Flexcomm. 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or
- * receive data. 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation
- * of SCK, when divided from the Flexcomm function clock. 0b10..Master using an existing SCK. SCK is received and used
- * directly to generate WS, as well as transmitting or receiving data. 0b11..Normal master mode. SCK and WS are
- * generated so they can be sent to one or more slave devices.
- */
-#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
-#define I2S_CFG1_MODE_MASK (0xC0U)
-#define I2S_CFG1_MODE_SHIFT (6U)
+#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+
+#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
+/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.
+ * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.
+ * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of
+ * SCK, when divided from the Flexcomm function clock.
+ * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.
+ * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.
+ */
+#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+
+#define I2S_CFG1_MODE_MASK (0xC0U)
+#define I2S_CFG1_MODE_SHIFT (6U)
/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all
* supported cases. See Formats and modes for examples.
* 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece
@@ -12208,9 +11555,10 @@ typedef struct
* 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.
* 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.
*/
-#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
-#define I2S_CFG1_RIGHTLOW_MASK (0x100U)
-#define I2S_CFG1_RIGHTLOW_SHIFT (8U)
+#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+
+#define I2S_CFG1_RIGHTLOW_MASK (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT (8U)
/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left
* and right channel data as it is transferred to or from the FIFO. This bit is not used if the
* data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10
@@ -12222,9 +11570,10 @@ typedef struct
* 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO
* bits 15:0 are used for the right channel.
*/
-#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
-#define I2S_CFG1_LEFTJUST_MASK (0x200U)
-#define I2S_CFG1_LEFTJUST_SHIFT (9U)
+#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+
+#define I2S_CFG1_LEFTJUST_MASK (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT (9U)
/*! LEFTJUST - Left Justify data.
* 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting
* from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data
@@ -12233,9 +11582,10 @@ typedef struct
* from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would
* correspond to left justified data in the stream on the data bus.
*/
-#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
-#define I2S_CFG1_ONECHANNEL_MASK (0x400U)
-#define I2S_CFG1_ONECHANNEL_SHIFT (10U)
+#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+
+#define I2S_CFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT (10U)
/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit
* applies only to the first I2S channel pair. Other channel pairs may select this mode
* independently in their separate CFG1 registers.
@@ -12247,24 +11597,26 @@ typedef struct
* (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data
* for the single channel of data is placed at the clock defined by POSITION.
*/
-#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
-#define I2S_CFG1_SCK_POL_MASK (0x1000U)
-#define I2S_CFG1_SCK_POL_SHIFT (12U)
+#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+
+#define I2S_CFG1_SCK_POL_MASK (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT (12U)
/*! SCK_POL - SCK polarity.
* 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).
* 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.
*/
-#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
-#define I2S_CFG1_WS_POL_MASK (0x2000U)
-#define I2S_CFG1_WS_POL_SHIFT (13U)
+#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+
+#define I2S_CFG1_WS_POL_MASK (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT (13U)
/*! WS_POL - WS polarity.
* 0b0..Data frames begin at a falling edge of WS (standard for classic I2S).
- * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic'
- * variations of I2S).
+ * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).
*/
-#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
-#define I2S_CFG1_DATALEN_MASK (0x1F0000U)
-#define I2S_CFG1_DATALEN_SHIFT (16U)
+#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+
+#define I2S_CFG1_DATALEN_MASK (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT (16U)
/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or
* received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received
* from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the
@@ -12275,13 +11627,14 @@ typedef struct
* 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F =
* data is 32 bits in length
*/
-#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
/*! @} */
/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
/*! @{ */
-#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
-#define I2S_CFG2_FRAMELEN_SHIFT (0U)
+
+#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT (0U)
/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the
* frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported
* 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is
@@ -12289,9 +11642,10 @@ typedef struct
* mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger
* than DATALEN in order for the WS pulse to be generated correctly.
*/
-#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
-#define I2S_CFG2_POSITION_MASK (0x1FF0000U)
-#define I2S_CFG2_POSITION_SHIFT (16U)
+#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+
+#define I2S_CFG2_POSITION_MASK (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT (16U)
/*! POSITION - Data Position. Defines the location within the frame of the data for this channel
* pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION
* defines the location of data in both the left phase and right phase, starting one clock after
@@ -12302,119 +11656,126 @@ typedef struct
* position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS
* phase. 0x002 = data begins at bit position 2 within the frame or WS phase.
*/
-#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
/*! @} */
/*! @name STAT - Status register for the primary channel pair. */
/*! @{ */
-#define I2S_STAT_BUSY_MASK (0x1U)
-#define I2S_STAT_BUSY_SHIFT (0U)
-/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel
- * pair. 0b0..The transmitter/receiver for channel pair is currently idle. 0b1..The transmitter/receiver for channel
- * pair is currently processing data.
+
+#define I2S_STAT_BUSY_MASK (0x1U)
+#define I2S_STAT_BUSY_SHIFT (0U)
+/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.
+ * 0b0..The transmitter/receiver for channel pair is currently idle.
+ * 0b1..The transmitter/receiver for channel pair is currently processing data.
*/
-#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
-#define I2S_STAT_SLVFRMERR_MASK (0x2U)
-#define I2S_STAT_SLVFRMERR_SHIFT (1U)
+#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+
+#define I2S_STAT_SLVFRMERR_MASK (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT (1U)
/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as
* a slave. An error indicates that the incoming WS signal did not transition as expected due to
* a mismatch between FRAMELEN and the actual incoming I2S stream.
* 0b0..No error has been recorded.
- * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a
- * 1 to this bit position.
+ * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.
*/
-#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
-#define I2S_STAT_LR_MASK (0x4U)
-#define I2S_STAT_LR_SHIFT (2U)
+#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+
+#define I2S_STAT_LR_MASK (0x4U)
+#define I2S_STAT_LR_SHIFT (2U)
/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to
* be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data
* being processed for the currently busy channel pair.
* 0b0..Left channel.
* 0b1..Right channel.
*/
-#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
-#define I2S_STAT_DATAPAUSED_MASK (0x8U)
-#define I2S_STAT_DATAPAUSED_SHIFT (3U)
+#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+
+#define I2S_STAT_DATAPAUSED_MASK (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT (3U)
/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels
* 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for
* an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.
* 0b1..A data pause has been requested and is now in force.
*/
-#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
/*! @} */
/*! @name DIV - Clock divider, used by all channel pairs. */
/*! @{ */
-#define I2S_DIV_DIV_MASK (0xFFFU)
-#define I2S_DIV_DIV_SHIFT (0U)
+
+#define I2S_DIV_DIV_MASK (0xFFFU)
+#define I2S_DIV_DIV_SHIFT (0U)
/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The
* Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2.
* 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is
* divided by 4,096.
*/
-#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
/*! @} */
/*! @name FIFOCFG - FIFO configuration and enable register. */
/*! @{ */
-#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
-#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
+
+#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
/*! ENABLETX - Enable the transmit FIFO.
* 0b0..The transmit FIFO is not enabled.
* 0b1..The transmit FIFO is enabled.
*/
-#define I2S_FIFOCFG_ENABLETX(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
-#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
-#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
+#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+
+#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
/*! ENABLERX - Enable the receive FIFO.
* 0b0..The receive FIFO is not enabled.
* 0b1..The receive FIFO is enabled.
*/
-#define I2S_FIFOCFG_ENABLERX(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
-#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
-#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX
* FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is
* cleared, new data is provided, and the I2S is un-paused.
* 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24
* bits or less, or when MONO = 1 for this channel pair.
- * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is
- * preferred.
- */
-#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
-#define I2S_FIFOCFG_PACK48_MASK (0x8U)
-#define I2S_FIFOCFG_PACK48_SHIFT (3U)
-/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software
- * or DMA. 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. 0b1..48-bit I2S FIFO entries are handled as
- * alternating 32-bit and 16-bit values.
- */
-#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
-#define I2S_FIFOCFG_SIZE_MASK (0x30U)
-#define I2S_FIFOCFG_SIZE_SHIFT (4U)
+ * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
+ */
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
+ * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values.
+ * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
+ */
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+
+#define I2S_FIFOCFG_SIZE_MASK (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT (4U)
/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
* entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
*/
-#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
-#define I2S_FIFOCFG_DMATX_MASK (0x1000U)
-#define I2S_FIFOCFG_DMATX_SHIFT (12U)
+#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+
+#define I2S_FIFOCFG_DMATX_MASK (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT (12U)
/*! DMATX - DMA configuration for transmit.
* 0b0..DMA is not used for the transmit function.
- * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if
- * DMA is enabled.
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
*/
-#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
-#define I2S_FIFOCFG_DMARX_MASK (0x2000U)
-#define I2S_FIFOCFG_DMARX_SHIFT (13U)
+#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+
+#define I2S_FIFOCFG_DMARX_MASK (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT (13U)
/*! DMARX - DMA configuration for receive.
* 0b0..DMA is not used for the receive function.
- * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if
- * DMA is enabled.
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
*/
-#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
-#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
-#define I2S_FIFOCFG_WAKETX_SHIFT (14U)
+#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+
+#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT (14U)
/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
* modes (up to power-down, as long as the peripheral function works in that power mode) without
* enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
@@ -12424,9 +11785,10 @@ typedef struct
* 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
* FIFOTRIG, even when the TXLVL interrupt is not enabled.
*/
-#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
-#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
-#define I2S_FIFOCFG_WAKERX_SHIFT (15U)
+#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+
+#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT (15U)
/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
* modes (up to power-down, as long as the peripheral function works in that power mode) without
* enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
@@ -12436,118 +11798,124 @@ typedef struct
* 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
* FIFOTRIG, even when the RXLVL interrupt is not enabled.
*/
-#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
-#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
-#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
+#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+
+#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
*/
-#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
-#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
-#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
+#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+
+#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
*/
-#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
/*! @} */
/*! @name FIFOSTAT - FIFO status register. */
/*! @{ */
-#define I2S_FIFOSTAT_TXERR_MASK (0x1U)
-#define I2S_FIFOSTAT_TXERR_SHIFT (0U)
+
+#define I2S_FIFOSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT (0U)
/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
* caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
* needed. Cleared by writing a 1 to this bit.
*/
-#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
-#define I2S_FIFOSTAT_RXERR_MASK (0x2U)
-#define I2S_FIFOSTAT_RXERR_SHIFT (1U)
+#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+
+#define I2S_FIFOSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT (1U)
/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
* not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
*/
-#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
-#define I2S_FIFOSTAT_PERINT_MASK (0x8U)
-#define I2S_FIFOSTAT_PERINT_SHIFT (3U)
+#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+
+#define I2S_FIFOSTAT_PERINT_MASK (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT (3U)
/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
* an interrupt. The details can be found by reading the peripheral's STAT register.
*/
-#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
-#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
-#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
-/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last
- * piece of data.
+#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+
+#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
*/
-#define I2S_FIFOSTAT_TXEMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
-#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
-#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+
+#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
* written. When 0, the transmit FIFO is full and another write would cause it to overflow.
*/
-#define I2S_FIFOSTAT_TXNOTFULL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
-#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
-#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
-/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive
- * FIFO is empty.
- */
-#define I2S_FIFOSTAT_RXNOTEMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
-#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
-#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
+#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+
+#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
* prevent the peripheral from causing an overflow.
*/
-#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
-#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
-#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
+#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+
+#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
* and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
* the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
* 0.
*/
-#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
-#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
-#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
+#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+
+#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
* RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
* point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
* 1.
*/
-#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
/*! @} */
/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
/*! @{ */
-#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
-#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
+
+#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
* in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
* 0b0..Transmit FIFO level does not generate a FIFO level trigger.
- * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this
- * register.
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
*/
-#define I2S_FIFOTRIG_TXLVLENA(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
-#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
-#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
+#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+
+#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
* in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
* 0b0..Receive FIFO level does not generate a FIFO level trigger.
- * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this
- * register.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
*/
-#define I2S_FIFOTRIG_RXLVLENA(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
-#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
-#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
+#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+
+#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
* to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
* the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
* becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
* FIFO level decreases to 15 entries (is no longer full).
*/
-#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
-#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
-#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
+#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+
+#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
* is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
* can wake up the device just enough to perform DMA, then return to the reduced power mode. See
@@ -12555,344 +11923,325 @@ typedef struct
* longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
* FIFO has received 16 entries (has become full).
*/
-#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
/*! @{ */
-#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
-#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
-/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT
- * register. 0b0..No interrupt will be generated for a transmit error. 0b1..An interrupt will be generated when a
- * transmit error occurs.
- */
-#define I2S_FIFOINTENSET_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
-#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
-#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
-/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT
- * register. 0b0..No interrupt will be generated for a receive error. 0b1..An interrupt will be generated when a receive
- * error occurs.
- */
-#define I2S_FIFOINTENSET_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
-#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
-#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
+
+#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+
+#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+
+#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
* specified by the TXLVL field in the FIFOTRIG register.
* 0b0..No interrupt will be generated based on the TX FIFO level.
* 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
* to the level specified by TXLVL in the FIFOTRIG register.
*/
-#define I2S_FIFOINTENSET_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
-#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
-#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
+#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+
+#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
* specified by the TXLVL field in the FIFOTRIG register.
* 0b0..No interrupt will be generated based on the RX FIFO level.
* 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
* increases to the level specified by RXLVL in the FIFOTRIG register.
*/
-#define I2S_FIFOINTENSET_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
/*! @{ */
-#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
-#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
+
+#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define I2S_FIFOINTENCLR_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
-#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
-#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
+#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+
+#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define I2S_FIFOINTENCLR_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
-#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
-#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
+#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+
+#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define I2S_FIFOINTENCLR_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
-#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
-#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
+#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+
+#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define I2S_FIFOINTENCLR_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTSTAT - FIFO interrupt status register. */
/*! @{ */
-#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
-#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
+
+#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
/*! TXERR - TX FIFO error.
*/
-#define I2S_FIFOINTSTAT_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
-#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
-#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
+#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+
+#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
/*! RXERR - RX FIFO error.
*/
-#define I2S_FIFOINTSTAT_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
-#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
-#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
+#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+
+#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
/*! TXLVL - Transmit FIFO level interrupt.
*/
-#define I2S_FIFOINTSTAT_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
-#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
-#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
+#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+
+#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
/*! RXLVL - Receive FIFO level interrupt.
*/
-#define I2S_FIFOINTSTAT_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
-#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
-#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
+#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+
+#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
/*! PERINT - Peripheral interrupt.
*/
-#define I2S_FIFOINTSTAT_PERINT(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
/*! @} */
/*! @name FIFOWR - FIFO write data. */
/*! @{ */
-#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
-#define I2S_FIFOWR_TXDATA_SHIFT (0U)
+
+#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT (0U)
/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details.
*/
-#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
/*! @} */
-/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data
- * and not using DMA. */
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
/*! @{ */
-#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
-#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
-/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on
- * configuration details.
+
+#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
+/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details.
*/
-#define I2S_FIFOWR48H_TXDATA(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
/*! @} */
/*! @name FIFORD - FIFO read data. */
/*! @{ */
-#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
-#define I2S_FIFORD_RXDATA_SHIFT (0U)
+
+#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT (0U)
/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details.
*/
-#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
/*! @} */
-/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data
- * and not using DMA. */
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
/*! @{ */
-#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
-#define I2S_FIFORD48H_RXDATA_SHIFT (0U)
-/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on
- * configuration details.
+
+#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
*/
-#define I2S_FIFORD48H_RXDATA(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
/*! @} */
/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
/*! @{ */
-#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
-#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
+
+#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
/*! RXDATA - Received data from the FIFO.
*/
-#define I2S_FIFORDNOPOP_RXDATA(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
/*! @} */
-/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is
- * configured for 2x 24-bit data and not using DMA. */
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
/*! @{ */
-#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
-#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
-/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on
- * configuration details.
+
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
+/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details.
*/
-#define I2S_FIFORD48HNOPOP_RXDATA(x) \
- (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
/*! @} */
/*! @name ID - I2S Module identification */
/*! @{ */
-#define I2S_ID_APERTURE_MASK (0xFFU)
-#define I2S_ID_APERTURE_SHIFT (0U)
+
+#define I2S_ID_APERTURE_MASK (0xFFU)
+#define I2S_ID_APERTURE_SHIFT (0U)
/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
*/
-#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)
-#define I2S_ID_MINOR_REV_MASK (0xF00U)
-#define I2S_ID_MINOR_REV_SHIFT (8U)
+#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)
+
+#define I2S_ID_MINOR_REV_MASK (0xF00U)
+#define I2S_ID_MINOR_REV_SHIFT (8U)
/*! MINOR_REV - Minor revision of module implementation, starting at 0.
*/
-#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)
-#define I2S_ID_MAJOR_REV_MASK (0xF000U)
-#define I2S_ID_MAJOR_REV_SHIFT (12U)
+#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)
+
+#define I2S_ID_MAJOR_REV_MASK (0xF000U)
+#define I2S_ID_MAJOR_REV_SHIFT (12U)
/*! MAJOR_REV - Major revision of module implementation, starting at 0.
*/
-#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)
-#define I2S_ID_ID_MASK (0xFFFF0000U)
-#define I2S_ID_ID_SHIFT (16U)
+#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)
+
+#define I2S_ID_ID_MASK (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT (16U)
/*! ID - Unique module identifier for this IP block.
*/
-#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group I2S_Register_Masks */
+
/* I2S - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x50086000u)
-/** Peripheral I2S0 base address */
-#define I2S0_BASE_NS (0x40086000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-/** Peripheral I2S0 base pointer */
-#define I2S0_NS ((I2S_Type *)I2S0_BASE_NS)
-/** Peripheral I2S1 base address */
-#define I2S1_BASE (0x50087000u)
-/** Peripheral I2S1 base address */
-#define I2S1_BASE_NS (0x40087000u)
-/** Peripheral I2S1 base pointer */
-#define I2S1 ((I2S_Type *)I2S1_BASE)
-/** Peripheral I2S1 base pointer */
-#define I2S1_NS ((I2S_Type *)I2S1_BASE_NS)
-/** Peripheral I2S2 base address */
-#define I2S2_BASE (0x50088000u)
-/** Peripheral I2S2 base address */
-#define I2S2_BASE_NS (0x40088000u)
-/** Peripheral I2S2 base pointer */
-#define I2S2 ((I2S_Type *)I2S2_BASE)
-/** Peripheral I2S2 base pointer */
-#define I2S2_NS ((I2S_Type *)I2S2_BASE_NS)
-/** Peripheral I2S3 base address */
-#define I2S3_BASE (0x50089000u)
-/** Peripheral I2S3 base address */
-#define I2S3_BASE_NS (0x40089000u)
-/** Peripheral I2S3 base pointer */
-#define I2S3 ((I2S_Type *)I2S3_BASE)
-/** Peripheral I2S3 base pointer */
-#define I2S3_NS ((I2S_Type *)I2S3_BASE_NS)
-/** Peripheral I2S4 base address */
-#define I2S4_BASE (0x5008A000u)
-/** Peripheral I2S4 base address */
-#define I2S4_BASE_NS (0x4008A000u)
-/** Peripheral I2S4 base pointer */
-#define I2S4 ((I2S_Type *)I2S4_BASE)
-/** Peripheral I2S4 base pointer */
-#define I2S4_NS ((I2S_Type *)I2S4_BASE_NS)
-/** Peripheral I2S5 base address */
-#define I2S5_BASE (0x50096000u)
-/** Peripheral I2S5 base address */
-#define I2S5_BASE_NS (0x40096000u)
-/** Peripheral I2S5 base pointer */
-#define I2S5 ((I2S_Type *)I2S5_BASE)
-/** Peripheral I2S5 base pointer */
-#define I2S5_NS ((I2S_Type *)I2S5_BASE_NS)
-/** Peripheral I2S6 base address */
-#define I2S6_BASE (0x50097000u)
-/** Peripheral I2S6 base address */
-#define I2S6_BASE_NS (0x40097000u)
-/** Peripheral I2S6 base pointer */
-#define I2S6 ((I2S_Type *)I2S6_BASE)
-/** Peripheral I2S6 base pointer */
-#define I2S6_NS ((I2S_Type *)I2S6_BASE_NS)
-/** Peripheral I2S7 base address */
-#define I2S7_BASE (0x50098000u)
-/** Peripheral I2S7 base address */
-#define I2S7_BASE_NS (0x40098000u)
-/** Peripheral I2S7 base pointer */
-#define I2S7 ((I2S_Type *)I2S7_BASE)
-/** Peripheral I2S7 base pointer */
-#define I2S7_NS ((I2S_Type *)I2S7_BASE_NS)
-/** Array initializer of I2S peripheral base addresses */
-#define I2S_BASE_ADDRS \
- { \
- I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE \
- }
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASE_PTRS \
- { \
- I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 \
- }
-/** Array initializer of I2S peripheral base addresses */
-#define I2S_BASE_ADDRS_NS \
- { \
- I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS \
- }
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASE_PTRS_NS \
- { \
- I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS \
- }
+ /** Peripheral I2S0 base address */
+ #define I2S0_BASE (0x50086000u)
+ /** Peripheral I2S0 base address */
+ #define I2S0_BASE_NS (0x40086000u)
+ /** Peripheral I2S0 base pointer */
+ #define I2S0 ((I2S_Type *)I2S0_BASE)
+ /** Peripheral I2S0 base pointer */
+ #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS)
+ /** Peripheral I2S1 base address */
+ #define I2S1_BASE (0x50087000u)
+ /** Peripheral I2S1 base address */
+ #define I2S1_BASE_NS (0x40087000u)
+ /** Peripheral I2S1 base pointer */
+ #define I2S1 ((I2S_Type *)I2S1_BASE)
+ /** Peripheral I2S1 base pointer */
+ #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS)
+ /** Peripheral I2S2 base address */
+ #define I2S2_BASE (0x50088000u)
+ /** Peripheral I2S2 base address */
+ #define I2S2_BASE_NS (0x40088000u)
+ /** Peripheral I2S2 base pointer */
+ #define I2S2 ((I2S_Type *)I2S2_BASE)
+ /** Peripheral I2S2 base pointer */
+ #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS)
+ /** Peripheral I2S3 base address */
+ #define I2S3_BASE (0x50089000u)
+ /** Peripheral I2S3 base address */
+ #define I2S3_BASE_NS (0x40089000u)
+ /** Peripheral I2S3 base pointer */
+ #define I2S3 ((I2S_Type *)I2S3_BASE)
+ /** Peripheral I2S3 base pointer */
+ #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS)
+ /** Peripheral I2S4 base address */
+ #define I2S4_BASE (0x5008A000u)
+ /** Peripheral I2S4 base address */
+ #define I2S4_BASE_NS (0x4008A000u)
+ /** Peripheral I2S4 base pointer */
+ #define I2S4 ((I2S_Type *)I2S4_BASE)
+ /** Peripheral I2S4 base pointer */
+ #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS)
+ /** Peripheral I2S5 base address */
+ #define I2S5_BASE (0x50096000u)
+ /** Peripheral I2S5 base address */
+ #define I2S5_BASE_NS (0x40096000u)
+ /** Peripheral I2S5 base pointer */
+ #define I2S5 ((I2S_Type *)I2S5_BASE)
+ /** Peripheral I2S5 base pointer */
+ #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS)
+ /** Peripheral I2S6 base address */
+ #define I2S6_BASE (0x50097000u)
+ /** Peripheral I2S6 base address */
+ #define I2S6_BASE_NS (0x40097000u)
+ /** Peripheral I2S6 base pointer */
+ #define I2S6 ((I2S_Type *)I2S6_BASE)
+ /** Peripheral I2S6 base pointer */
+ #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS)
+ /** Peripheral I2S7 base address */
+ #define I2S7_BASE (0x50098000u)
+ /** Peripheral I2S7 base address */
+ #define I2S7_BASE_NS (0x40098000u)
+ /** Peripheral I2S7 base pointer */
+ #define I2S7 ((I2S_Type *)I2S7_BASE)
+ /** Peripheral I2S7 base pointer */
+ #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS)
+ /** Array initializer of I2S peripheral base addresses */
+ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }
+ /** Array initializer of I2S peripheral base pointers */
+ #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }
+ /** Array initializer of I2S peripheral base addresses */
+ #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS }
+ /** Array initializer of I2S peripheral base pointers */
+ #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS }
#else
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x40086000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-/** Peripheral I2S1 base address */
-#define I2S1_BASE (0x40087000u)
-/** Peripheral I2S1 base pointer */
-#define I2S1 ((I2S_Type *)I2S1_BASE)
-/** Peripheral I2S2 base address */
-#define I2S2_BASE (0x40088000u)
-/** Peripheral I2S2 base pointer */
-#define I2S2 ((I2S_Type *)I2S2_BASE)
-/** Peripheral I2S3 base address */
-#define I2S3_BASE (0x40089000u)
-/** Peripheral I2S3 base pointer */
-#define I2S3 ((I2S_Type *)I2S3_BASE)
-/** Peripheral I2S4 base address */
-#define I2S4_BASE (0x4008A000u)
-/** Peripheral I2S4 base pointer */
-#define I2S4 ((I2S_Type *)I2S4_BASE)
-/** Peripheral I2S5 base address */
-#define I2S5_BASE (0x40096000u)
-/** Peripheral I2S5 base pointer */
-#define I2S5 ((I2S_Type *)I2S5_BASE)
-/** Peripheral I2S6 base address */
-#define I2S6_BASE (0x40097000u)
-/** Peripheral I2S6 base pointer */
-#define I2S6 ((I2S_Type *)I2S6_BASE)
-/** Peripheral I2S7 base address */
-#define I2S7_BASE (0x40098000u)
-/** Peripheral I2S7 base pointer */
-#define I2S7 ((I2S_Type *)I2S7_BASE)
-/** Array initializer of I2S peripheral base addresses */
-#define I2S_BASE_ADDRS \
- { \
- I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE \
- }
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASE_PTRS \
- { \
- I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 \
- }
+ /** Peripheral I2S0 base address */
+ #define I2S0_BASE (0x40086000u)
+ /** Peripheral I2S0 base pointer */
+ #define I2S0 ((I2S_Type *)I2S0_BASE)
+ /** Peripheral I2S1 base address */
+ #define I2S1_BASE (0x40087000u)
+ /** Peripheral I2S1 base pointer */
+ #define I2S1 ((I2S_Type *)I2S1_BASE)
+ /** Peripheral I2S2 base address */
+ #define I2S2_BASE (0x40088000u)
+ /** Peripheral I2S2 base pointer */
+ #define I2S2 ((I2S_Type *)I2S2_BASE)
+ /** Peripheral I2S3 base address */
+ #define I2S3_BASE (0x40089000u)
+ /** Peripheral I2S3 base pointer */
+ #define I2S3 ((I2S_Type *)I2S3_BASE)
+ /** Peripheral I2S4 base address */
+ #define I2S4_BASE (0x4008A000u)
+ /** Peripheral I2S4 base pointer */
+ #define I2S4 ((I2S_Type *)I2S4_BASE)
+ /** Peripheral I2S5 base address */
+ #define I2S5_BASE (0x40096000u)
+ /** Peripheral I2S5 base pointer */
+ #define I2S5 ((I2S_Type *)I2S5_BASE)
+ /** Peripheral I2S6 base address */
+ #define I2S6_BASE (0x40097000u)
+ /** Peripheral I2S6 base pointer */
+ #define I2S6 ((I2S_Type *)I2S6_BASE)
+ /** Peripheral I2S7 base address */
+ #define I2S7_BASE (0x40098000u)
+ /** Peripheral I2S7 base pointer */
+ #define I2S7 ((I2S_Type *)I2S7_BASE)
+ /** Array initializer of I2S peripheral base addresses */
+ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }
+ /** Array initializer of I2S peripheral base pointers */
+ #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }
#endif
/** Interrupt vectors for the I2S peripheral type */
-#define I2S_IRQS \
- { \
- FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, \
- FLEXCOMM6_IRQn, FLEXCOMM7_IRQn \
- }
+#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- INPUTMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -12903,66 +12252,56 @@ typedef struct
*/
/** INPUTMUX - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */
- uint8_t RESERVED_0[4];
- __IO uint32_t
- TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[16];
- __IO uint32_t
- TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_2[16];
- __IO uint32_t
- TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */
- uint8_t RESERVED_3[80];
- __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
- __IO uint32_t
- DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */
- uint8_t RESERVED_4[36];
- __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160,
- array step: 0x4 */
- uint8_t RESERVED_5[16];
- __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
- __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
- uint8_t RESERVED_6[24];
- __IO uint32_t
- TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */
- uint8_t RESERVED_7[16];
- __IO uint32_t
- TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */
- uint8_t RESERVED_8[16];
- __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */
- uint8_t RESERVED_9[24];
- __IO uint32_t
- DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */
- uint8_t RESERVED_10[24];
- __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240,
- array step: 0x4 */
- uint8_t RESERVED_11[1264];
- __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */
- uint8_t RESERVED_12[4];
- __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */
- uint8_t RESERVED_13[4];
- __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */
- uint8_t RESERVED_14[12];
- __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */
- uint8_t RESERVED_15[4];
- __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */
- uint8_t RESERVED_16[4];
- __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */
- uint8_t RESERVED_17[12];
- __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */
- uint8_t RESERVED_18[4];
- __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */
- uint8_t RESERVED_19[4];
- __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */
- uint8_t RESERVED_20[12];
- __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */
- uint8_t RESERVED_21[4];
- __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */
- uint8_t RESERVED_22[4];
- __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */
+typedef struct {
+ __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */
+ uint8_t RESERVED_3[80];
+ __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+ __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */
+ uint8_t RESERVED_4[36];
+ __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */
+ uint8_t RESERVED_5[16];
+ __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
+ __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */
+ uint8_t RESERVED_7[16];
+ __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */
+ uint8_t RESERVED_8[16];
+ __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */
+ uint8_t RESERVED_9[24];
+ __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_10[24];
+ __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */
+ uint8_t RESERVED_11[1264];
+ __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */
+ uint8_t RESERVED_12[4];
+ __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */
+ uint8_t RESERVED_13[4];
+ __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */
+ uint8_t RESERVED_14[12];
+ __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */
+ uint8_t RESERVED_15[4];
+ __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */
+ uint8_t RESERVED_16[4];
+ __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */
+ uint8_t RESERVED_17[12];
+ __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */
+ uint8_t RESERVED_18[4];
+ __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */
+ uint8_t RESERVED_19[4];
+ __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */
+ uint8_t RESERVED_20[12];
+ __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */
+ uint8_t RESERVED_21[4];
+ __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */
+ uint8_t RESERVED_22[4];
+ __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */
} INPUTMUX_Type;
/* ----------------------------------------------------------------------------
@@ -12976,8 +12315,9 @@ typedef struct
/*! @name SCT0_INMUX - Input mux register for SCT0 input */
/*! @{ */
-#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)
-#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
+
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
/*! INP_N - Input number to SCT0 inputs 0 to 6..
* 0b00000..SCT_GPI0 function selected from IOCON register
* 0b00001..SCT_GPI1 function selected from IOCON register
@@ -13005,17 +12345,17 @@ typedef struct
* 0b10111..DEBUG_HALTED from cpu0 or cpu1
* 0b11000-0b11111..None
*/
-#define INPUTMUX_SCT0_INMUX_INP_N(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
+#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
/*! @} */
/* The count of INPUTMUX_SCT0_INMUX */
-#define INPUTMUX_SCT0_INMUX_COUNT (7U)
+#define INPUTMUX_SCT0_INMUX_COUNT (7U)
/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */
/*! @{ */
-#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU)
-#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U)
+
+#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU)
+#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U)
/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4
* 0b00000..CT_INP0 function selected from IOCON register
* 0b00001..CT_INP1 function selected from IOCON register
@@ -13044,17 +12384,17 @@ typedef struct
* 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
* 0b11001-0b11111..None
*/
-#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK)
+#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK)
/*! @} */
/* The count of INPUTMUX_TIMER0CAPTSEL */
-#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U)
+#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U)
/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */
/*! @{ */
-#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU)
-#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U)
+
+#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU)
+#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U)
/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4
* 0b00000..CT_INP0 function selected from IOCON register
* 0b00001..CT_INP1 function selected from IOCON register
@@ -13083,17 +12423,17 @@ typedef struct
* 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
* 0b11001-0b11111..None
*/
-#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK)
+#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK)
/*! @} */
/* The count of INPUTMUX_TIMER1CAPTSEL */
-#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U)
+#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U)
/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */
/*! @{ */
-#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU)
-#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U)
+
+#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU)
+#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U)
/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4
* 0b00000..CT_INP0 function selected from IOCON register
* 0b00001..CT_INP1 function selected from IOCON register
@@ -13122,31 +12462,31 @@ typedef struct
* 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
* 0b11001-0b11111..None
*/
-#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK)
+#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK)
/*! @} */
/* The count of INPUTMUX_TIMER2CAPTSEL */
-#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U)
+#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U)
/*! @name PINTSEL - Pin interrupt select register */
/*! @{ */
-#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU)
-#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
+
+#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN =
* (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63.
*/
-#define INPUTMUX_PINTSEL_INTPIN(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
/*! @} */
/* The count of INPUTMUX_PINTSEL */
-#define INPUTMUX_PINTSEL_COUNT (8U)
+#define INPUTMUX_PINTSEL_COUNT (8U)
/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */
/*! @{ */
-#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU)
-#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U)
+
+#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU)
+#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U)
/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22).
* 0b00000..Pin interrupt 0
* 0b00001..Pin interrupt 1
@@ -13172,54 +12512,54 @@ typedef struct
* 0b10101..HASH DMA RX trigger
* 0b10110-0b11111..None
*/
-#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK)
+#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK)
/*! @} */
/* The count of INPUTMUX_DMA0_ITRIG_INMUX */
-#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U)
+#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U)
/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */
/*! @{ */
-#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU)
-#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U)
+
+#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU)
+#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U)
/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).
*/
-#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK)
+#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK)
/*! @} */
/* The count of INPUTMUX_DMA0_OTRIG_INMUX */
-#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U)
+#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U)
/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
/*! @{ */
-#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
-#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
+
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
* CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
* (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
*/
-#define INPUTMUX_FREQMEAS_REF_CLKIN(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
/*! @} */
/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
/*! @{ */
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
+
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 =
* CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock
* (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4
*/
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
/*! @} */
/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */
/*! @{ */
-#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU)
-#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U)
+
+#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU)
+#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U)
/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4
* 0b00000..CT_INP0 function selected from IOCON register
* 0b00001..CT_INP1 function selected from IOCON register
@@ -13248,17 +12588,17 @@ typedef struct
* 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
* 0b11001-0b11111..None
*/
-#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK)
+#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK)
/*! @} */
/* The count of INPUTMUX_TIMER3CAPTSEL */
-#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U)
+#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U)
/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */
/*! @{ */
-#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU)
-#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U)
+
+#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU)
+#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U)
/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4
* 0b00000..CT_INP0 function selected from IOCON register
* 0b00001..CT_INP1 function selected from IOCON register
@@ -13287,31 +12627,31 @@ typedef struct
* 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing
* 0b11001-0b11111..None
*/
-#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK)
+#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK)
/*! @} */
/* The count of INPUTMUX_TIMER4CAPTSEL */
-#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U)
+#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U)
/*! @name PINTSECSEL - Pin interrupt secure select register */
/*! @{ */
-#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU)
-#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U)
+
+#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU)
+#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U)
/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x:
* INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31.
*/
-#define INPUTMUX_PINTSECSEL_INTPIN(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK)
+#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK)
/*! @} */
/* The count of INPUTMUX_PINTSECSEL */
-#define INPUTMUX_PINTSECSEL_COUNT (2U)
+#define INPUTMUX_PINTSECSEL_COUNT (2U)
/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */
/*! @{ */
-#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU)
-#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U)
+
+#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU)
+#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U)
/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9).
* 0b0000..Pin interrupt 0
* 0b0001..Pin interrupt 1
@@ -13330,209 +12670,189 @@ typedef struct
* 0b1110..HASH DMA RX trigger
* 0b1111..None
*/
-#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK)
+#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK)
/*! @} */
/* The count of INPUTMUX_DMA1_ITRIG_INMUX */
-#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U)
+#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U)
/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */
/*! @{ */
-#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU)
-#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U)
+
+#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU)
+#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U)
/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9).
*/
-#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK)
+#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK)
/*! @} */
/* The count of INPUTMUX_DMA1_OTRIG_INMUX */
-#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U)
+#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U)
/*! @name DMA0_REQ_ENA - Enable DMA0 requests */
/*! @{ */
-#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU)
-#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U)
+
+#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU)
+#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U)
/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled.
*/
-#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK)
+#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK)
/*! @} */
/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */
/*! @{ */
-#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU)
-#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U)
-/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA
- * register
+
+#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU)
+#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U)
+/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register
*/
-#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK)
+#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK)
/*! @} */
/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */
/*! @{ */
-#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU)
-#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U)
-/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in
- * DMA0_REQ_ENA register
+
+#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU)
+#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U)
+/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register
*/
-#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK)
+#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK)
/*! @} */
/*! @name DMA1_REQ_ENA - Enable DMA1 requests */
/*! @{ */
-#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU)
-#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U)
+
+#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU)
+#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U)
/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled.
*/
-#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK)
+#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK)
/*! @} */
/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */
/*! @{ */
-#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU)
-#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U)
-/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA
- * register
+
+#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU)
+#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U)
+/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register
*/
-#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK)
+#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK)
/*! @} */
/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */
/*! @{ */
-#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU)
-#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U)
-/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in
- * DMA1_REQ_ENA register
+
+#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU)
+#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U)
+/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register
*/
-#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK)
+#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK)
/*! @} */
/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */
/*! @{ */
-#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU)
-#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U)
+
+#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU)
+#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U)
/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled.
*/
-#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK)
+#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK)
/*! @} */
/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */
/*! @{ */
-#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU)
-#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U)
+
+#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU)
+#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U)
/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no
* change in DMA0_ITRIG_ENA register
*/
-#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK)
+#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK)
/*! @} */
/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */
/*! @{ */
-#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU)
-#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U)
+
+#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU)
+#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U)
/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no
* change in DMA0_ITRIG_ENA register
*/
-#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK)
+#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK)
/*! @} */
/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */
/*! @{ */
-#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU)
-#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U)
+
+#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU)
+#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U)
/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled.
*/
-#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK)
+#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK)
/*! @} */
/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */
/*! @{ */
-#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU)
-#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U)
+
+#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU)
+#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U)
/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no
* change in DMA1_ITRIG_ENA register
*/
-#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK)
+#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK)
/*! @} */
/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */
/*! @{ */
-#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU)
-#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U)
+
+#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU)
+#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U)
/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no
* change in DMA1_ITRIG_ENA register
*/
-#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) \
- (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK)
+#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group INPUTMUX_Register_Masks */
+
/* INPUTMUX - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral INPUTMUX base address */
-#define INPUTMUX_BASE (0x50006000u)
-/** Peripheral INPUTMUX base address */
-#define INPUTMUX_BASE_NS (0x40006000u)
-/** Peripheral INPUTMUX base pointer */
-#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
-/** Peripheral INPUTMUX base pointer */
-#define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS)
-/** Array initializer of INPUTMUX peripheral base addresses */
-#define INPUTMUX_BASE_ADDRS \
- { \
- INPUTMUX_BASE \
- }
-/** Array initializer of INPUTMUX peripheral base pointers */
-#define INPUTMUX_BASE_PTRS \
- { \
- INPUTMUX \
- }
-/** Array initializer of INPUTMUX peripheral base addresses */
-#define INPUTMUX_BASE_ADDRS_NS \
- { \
- INPUTMUX_BASE_NS \
- }
-/** Array initializer of INPUTMUX peripheral base pointers */
-#define INPUTMUX_BASE_PTRS_NS \
- { \
- INPUTMUX_NS \
- }
+ /** Peripheral INPUTMUX base address */
+ #define INPUTMUX_BASE (0x50006000u)
+ /** Peripheral INPUTMUX base address */
+ #define INPUTMUX_BASE_NS (0x40006000u)
+ /** Peripheral INPUTMUX base pointer */
+ #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
+ /** Peripheral INPUTMUX base pointer */
+ #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS)
+ /** Array initializer of INPUTMUX peripheral base addresses */
+ #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
+ /** Array initializer of INPUTMUX peripheral base pointers */
+ #define INPUTMUX_BASE_PTRS { INPUTMUX }
+ /** Array initializer of INPUTMUX peripheral base addresses */
+ #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS }
+ /** Array initializer of INPUTMUX peripheral base pointers */
+ #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS }
#else
-/** Peripheral INPUTMUX base address */
-#define INPUTMUX_BASE (0x40006000u)
-/** Peripheral INPUTMUX base pointer */
-#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
-/** Array initializer of INPUTMUX peripheral base addresses */
-#define INPUTMUX_BASE_ADDRS \
- { \
- INPUTMUX_BASE \
- }
-/** Array initializer of INPUTMUX peripheral base pointers */
-#define INPUTMUX_BASE_PTRS \
- { \
- INPUTMUX \
- }
+ /** Peripheral INPUTMUX base address */
+ #define INPUTMUX_BASE (0x40006000u)
+ /** Peripheral INPUTMUX base pointer */
+ #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
+ /** Array initializer of INPUTMUX peripheral base addresses */
+ #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
+ /** Array initializer of INPUTMUX peripheral base pointers */
+ #define INPUTMUX_BASE_PTRS { INPUTMUX }
#endif
/*!
* @}
*/ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- IOCON Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -13543,10 +12863,8 @@ typedef struct
*/
/** IOCON - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins
- PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+typedef struct {
+ __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
} IOCON_Type;
/* ----------------------------------------------------------------------------
@@ -13560,8 +12878,9 @@ typedef struct
/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */
/*! @{ */
-#define IOCON_PIO_FUNC_MASK (0xFU)
-#define IOCON_PIO_FUNC_SHIFT (0U)
+
+#define IOCON_PIO_FUNC_MASK (0xFU)
+#define IOCON_PIO_FUNC_SHIFT (0U)
/*! FUNC - Selects pin function.
* 0b0000..Alternative connection 0.
* 0b0001..Alternative connection 1.
@@ -13572,151 +12891,146 @@ typedef struct
* 0b0110..Alternative connection 6.
* 0b0111..Alternative connection 7.
*/
-#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
-#define IOCON_PIO_MODE_MASK (0x30U)
-#define IOCON_PIO_MODE_SHIFT (4U)
+#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+
+#define IOCON_PIO_MODE_MASK (0x30U)
+#define IOCON_PIO_MODE_SHIFT (4U)
/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
* 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
* 0b01..Pull-down. Pull-down resistor enabled.
* 0b10..Pull-up. Pull-up resistor enabled.
* 0b11..Repeater. Repeater mode.
*/
-#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
-#define IOCON_PIO_SLEW_MASK (0x40U)
-#define IOCON_PIO_SLEW_SHIFT (6U)
+#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+
+#define IOCON_PIO_SLEW_MASK (0x40U)
+#define IOCON_PIO_SLEW_SHIFT (6U)
/*! SLEW - Driver slew rate.
* 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously.
* 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details.
*/
-#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
-#define IOCON_PIO_INVERT_MASK (0x80U)
-#define IOCON_PIO_INVERT_SHIFT (7U)
+#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+
+#define IOCON_PIO_INVERT_MASK (0x80U)
+#define IOCON_PIO_INVERT_SHIFT (7U)
/*! INVERT - Input polarity.
* 0b0..Disabled. Input function is not inverted.
* 0b1..Enabled. Input is function inverted.
*/
-#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
-#define IOCON_PIO_DIGIMODE_MASK (0x100U)
-#define IOCON_PIO_DIGIMODE_SHIFT (8U)
+#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+
+#define IOCON_PIO_DIGIMODE_MASK (0x100U)
+#define IOCON_PIO_DIGIMODE_SHIFT (8U)
/*! DIGIMODE - Select Digital mode.
* 0b0..Disable digital mode. Digital input set to 0.
* 0b1..Enable Digital mode. Digital input is enabled.
*/
-#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
-#define IOCON_PIO_OD_MASK (0x200U)
-#define IOCON_PIO_OD_SHIFT (9U)
+#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+
+#define IOCON_PIO_OD_MASK (0x200U)
+#define IOCON_PIO_OD_SHIFT (9U)
/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0).
* 0b0..Normal. Normal push-pull output
* 0b1..Open-drain. Simulated open-drain output (high drive disabled).
*/
-#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
-#define IOCON_PIO_ASW_MASK (0x400U)
-#define IOCON_PIO_ASW_SHIFT (10U)
+#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+
+#define IOCON_PIO_ASW_MASK (0x400U)
+#define IOCON_PIO_ASW_SHIFT (10U)
/*! ASW - Analog switch input control.
* 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed
* (enabled). For the other pins, analog switch is open (disabled).
- * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is
- * closed (enabled)
+ * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled)
*/
-#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK)
-#define IOCON_PIO_SSEL_MASK (0x800U)
-#define IOCON_PIO_SSEL_SHIFT (11U)
+#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK)
+
+#define IOCON_PIO_SSEL_MASK (0x800U)
+#define IOCON_PIO_SSEL_SHIFT (11U)
/*! SSEL - Supply Selection bit.
* 0b0..3V3 Signaling in I2C Mode.
* 0b1..1V8 Signaling in I2C Mode.
*/
-#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)
-#define IOCON_PIO_FILTEROFF_MASK (0x1000U)
-#define IOCON_PIO_FILTEROFF_SHIFT (12U)
+#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)
+
+#define IOCON_PIO_FILTEROFF_MASK (0x1000U)
+#define IOCON_PIO_FILTEROFF_SHIFT (12U)
/*! FILTEROFF - Controls input glitch filter.
* 0b0..Filter enabled.
* 0b1..Filter disabled.
*/
-#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
-#define IOCON_PIO_ECS_MASK (0x2000U)
-#define IOCON_PIO_ECS_SHIFT (13U)
+#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+
+#define IOCON_PIO_ECS_MASK (0x2000U)
+#define IOCON_PIO_ECS_SHIFT (13U)
/*! ECS - Pull-up current source enable in I2C mode.
* 0b1..Enabled. Pull resistor is conencted.
* 0b0..Disabled. IO is in open drain cell.
*/
-#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK)
-#define IOCON_PIO_EGP_MASK (0x4000U)
-#define IOCON_PIO_EGP_SHIFT (14U)
+#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK)
+
+#define IOCON_PIO_EGP_MASK (0x4000U)
+#define IOCON_PIO_EGP_SHIFT (14U)
/*! EGP - Switch between GPIO mode and I2C mode.
* 0b0..I2C mode.
* 0b1..GPIO mode.
*/
-#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)
-#define IOCON_PIO_I2CFILTER_MASK (0x8000U)
-#define IOCON_PIO_I2CFILTER_SHIFT (15U)
-/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode
- * operation. 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C.
+#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)
+
+#define IOCON_PIO_I2CFILTER_MASK (0x8000U)
+#define IOCON_PIO_I2CFILTER_SHIFT (15U)
+/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation.
+ * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C.
* 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C.
*/
-#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
+#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
/*! @} */
/* The count of IOCON_PIO */
-#define IOCON_PIO_COUNT (2U)
+#define IOCON_PIO_COUNT (2U)
/* The count of IOCON_PIO */
-#define IOCON_PIO_COUNT2 (32U)
+#define IOCON_PIO_COUNT2 (32U)
+
/*!
* @}
*/ /* end of group IOCON_Register_Masks */
+
/* IOCON - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral IOCON base address */
-#define IOCON_BASE (0x50001000u)
-/** Peripheral IOCON base address */
-#define IOCON_BASE_NS (0x40001000u)
-/** Peripheral IOCON base pointer */
-#define IOCON ((IOCON_Type *)IOCON_BASE)
-/** Peripheral IOCON base pointer */
-#define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS)
-/** Array initializer of IOCON peripheral base addresses */
-#define IOCON_BASE_ADDRS \
- { \
- IOCON_BASE \
- }
-/** Array initializer of IOCON peripheral base pointers */
-#define IOCON_BASE_PTRS \
- { \
- IOCON \
- }
-/** Array initializer of IOCON peripheral base addresses */
-#define IOCON_BASE_ADDRS_NS \
- { \
- IOCON_BASE_NS \
- }
-/** Array initializer of IOCON peripheral base pointers */
-#define IOCON_BASE_PTRS_NS \
- { \
- IOCON_NS \
- }
+ /** Peripheral IOCON base address */
+ #define IOCON_BASE (0x50001000u)
+ /** Peripheral IOCON base address */
+ #define IOCON_BASE_NS (0x40001000u)
+ /** Peripheral IOCON base pointer */
+ #define IOCON ((IOCON_Type *)IOCON_BASE)
+ /** Peripheral IOCON base pointer */
+ #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS)
+ /** Array initializer of IOCON peripheral base addresses */
+ #define IOCON_BASE_ADDRS { IOCON_BASE }
+ /** Array initializer of IOCON peripheral base pointers */
+ #define IOCON_BASE_PTRS { IOCON }
+ /** Array initializer of IOCON peripheral base addresses */
+ #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS }
+ /** Array initializer of IOCON peripheral base pointers */
+ #define IOCON_BASE_PTRS_NS { IOCON_NS }
#else
-/** Peripheral IOCON base address */
-#define IOCON_BASE (0x40001000u)
-/** Peripheral IOCON base pointer */
-#define IOCON ((IOCON_Type *)IOCON_BASE)
-/** Array initializer of IOCON peripheral base addresses */
-#define IOCON_BASE_ADDRS \
- { \
- IOCON_BASE \
- }
-/** Array initializer of IOCON peripheral base pointers */
-#define IOCON_BASE_PTRS \
- { \
- IOCON \
- }
+ /** Peripheral IOCON base address */
+ #define IOCON_BASE (0x40001000u)
+ /** Peripheral IOCON base pointer */
+ #define IOCON ((IOCON_Type *)IOCON_BASE)
+ /** Array initializer of IOCON peripheral base addresses */
+ #define IOCON_BASE_ADDRS { IOCON_BASE }
+ /** Array initializer of IOCON peripheral base pointers */
+ #define IOCON_BASE_PTRS { IOCON }
#endif
/*!
* @}
*/ /* end of group IOCON_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- MAILBOX Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -13727,18 +13041,15 @@ typedef struct
*/
/** MAILBOX - Register Layout Typedef */
-typedef struct
-{
- struct
- { /* offset: 0x0, array step: 0x10 */
- __IO uint32_t
- IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */
- __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */
- __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */
- uint8_t RESERVED_0[4];
- } MBOXIRQ[2];
- uint8_t RESERVED_0[216];
- __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x10 */
+ __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */
+ __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */
+ __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } MBOXIRQ[2];
+ uint8_t RESERVED_0[216];
+ __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */
} MAILBOX_Type;
/* ----------------------------------------------------------------------------
@@ -13752,112 +13063,95 @@ typedef struct
/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */
/*! @{ */
-#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU)
-#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U)
+
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU)
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U)
/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller.
*/
-#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)
/*! @} */
/* The count of MAILBOX_MBOXIRQ_IRQ */
-#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U)
+#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U)
/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */
/*! @{ */
-#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU)
-#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U)
+
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU)
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U)
/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register.
*/
-#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) \
- (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)
/*! @} */
/* The count of MAILBOX_MBOXIRQ_IRQSET */
-#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U)
+#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U)
/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */
/*! @{ */
-#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU)
-#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U)
+
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU)
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U)
/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register.
*/
-#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)
/*! @} */
/* The count of MAILBOX_MBOXIRQ_IRQCLR */
-#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U)
+#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U)
/*! @name MUTEX - Mutual exclusion register[1] */
/*! @{ */
-#define MAILBOX_MUTEX_EX_MASK (0x1U)
-#define MAILBOX_MUTEX_EX_SHIFT (0U)
+
+#define MAILBOX_MUTEX_EX_MASK (0x1U)
+#define MAILBOX_MUTEX_EX_SHIFT (0U)
/*! EX - Cleared when read, set when written. See usage description above.
*/
-#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)
+#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group MAILBOX_Register_Masks */
+
/* MAILBOX - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral MAILBOX base address */
-#define MAILBOX_BASE (0x5008B000u)
-/** Peripheral MAILBOX base address */
-#define MAILBOX_BASE_NS (0x4008B000u)
-/** Peripheral MAILBOX base pointer */
-#define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)
-/** Peripheral MAILBOX base pointer */
-#define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS)
-/** Array initializer of MAILBOX peripheral base addresses */
-#define MAILBOX_BASE_ADDRS \
- { \
- MAILBOX_BASE \
- }
-/** Array initializer of MAILBOX peripheral base pointers */
-#define MAILBOX_BASE_PTRS \
- { \
- MAILBOX \
- }
-/** Array initializer of MAILBOX peripheral base addresses */
-#define MAILBOX_BASE_ADDRS_NS \
- { \
- MAILBOX_BASE_NS \
- }
-/** Array initializer of MAILBOX peripheral base pointers */
-#define MAILBOX_BASE_PTRS_NS \
- { \
- MAILBOX_NS \
- }
+ /** Peripheral MAILBOX base address */
+ #define MAILBOX_BASE (0x5008B000u)
+ /** Peripheral MAILBOX base address */
+ #define MAILBOX_BASE_NS (0x4008B000u)
+ /** Peripheral MAILBOX base pointer */
+ #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)
+ /** Peripheral MAILBOX base pointer */
+ #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS)
+ /** Array initializer of MAILBOX peripheral base addresses */
+ #define MAILBOX_BASE_ADDRS { MAILBOX_BASE }
+ /** Array initializer of MAILBOX peripheral base pointers */
+ #define MAILBOX_BASE_PTRS { MAILBOX }
+ /** Array initializer of MAILBOX peripheral base addresses */
+ #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS }
+ /** Array initializer of MAILBOX peripheral base pointers */
+ #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS }
#else
-/** Peripheral MAILBOX base address */
-#define MAILBOX_BASE (0x4008B000u)
-/** Peripheral MAILBOX base pointer */
-#define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)
-/** Array initializer of MAILBOX peripheral base addresses */
-#define MAILBOX_BASE_ADDRS \
- { \
- MAILBOX_BASE \
- }
-/** Array initializer of MAILBOX peripheral base pointers */
-#define MAILBOX_BASE_PTRS \
- { \
- MAILBOX \
- }
+ /** Peripheral MAILBOX base address */
+ #define MAILBOX_BASE (0x4008B000u)
+ /** Peripheral MAILBOX base pointer */
+ #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)
+ /** Array initializer of MAILBOX peripheral base addresses */
+ #define MAILBOX_BASE_ADDRS { MAILBOX_BASE }
+ /** Array initializer of MAILBOX peripheral base pointers */
+ #define MAILBOX_BASE_PTRS { MAILBOX }
#endif
/** Interrupt vectors for the MAILBOX peripheral type */
-#define MAILBOX_IRQS \
- { \
- MAILBOX_IRQn \
- }
+#define MAILBOX_IRQS { MAILBOX_IRQn }
/*!
* @}
*/ /* end of group MAILBOX_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- MRT Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -13868,25 +13162,17 @@ typedef struct
*/
/** MRT - Register Layout Typedef */
-typedef struct
-{
- struct
- { /* offset: 0x0, array step: 0x10 */
- __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register.,
- array offset: 0x0, array step: 0x10 */
- __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset:
- 0x4, array step: 0x10 */
- __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array
- step: 0x10 */
- __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
- } CHANNEL[4];
- uint8_t RESERVED_0[176];
- __IO uint32_t
- MODCFG; /**< Module Configuration register. This register provides information about this particular MRT
- instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
- __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel.,
- offset: 0xF4 */
- __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x10 */
+ __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+ __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+ __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+ __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+ } CHANNEL[4];
+ uint8_t RESERVED_0[176];
+ __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+ __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+ __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
} MRT_Type;
/* ----------------------------------------------------------------------------
@@ -13900,232 +13186,219 @@ typedef struct
/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
/*! @{ */
-#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
-#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
+
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
* channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
* this bit field starts the timer immediately. If the timer is running, writing a zero to this
* bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
* stops at the end of the time interval.
*/
-#define MRT_CHANNEL_INTVAL_IVALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
-#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
-#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
+#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+
+#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
* This bit is write-only. Reading this bit always returns 0.
* 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
* time interval if the repeat mode is selected.
- * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is
- * running.
+ * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
*/
-#define MRT_CHANNEL_INTVAL_LOAD(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
/*! @} */
/* The count of MRT_CHANNEL_INTVAL */
-#define MRT_CHANNEL_INTVAL_COUNT (4U)
+#define MRT_CHANNEL_INTVAL_COUNT (4U)
/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
/*! @{ */
-#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
-#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
+
+#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
* register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
* or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
* register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
* returns -1 (0x00FF FFFF).
*/
-#define MRT_CHANNEL_TIMER_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
/*! @} */
/* The count of MRT_CHANNEL_TIMER */
-#define MRT_CHANNEL_TIMER_COUNT (4U)
+#define MRT_CHANNEL_TIMER_COUNT (4U)
/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
/*! @{ */
-#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
-#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
+
+#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
/*! INTEN - Enable the TIMERn interrupt.
* 0b0..Disabled. TIMERn interrupt is disabled.
* 0b1..Enabled. TIMERn interrupt is enabled.
*/
-#define MRT_CHANNEL_CTRL_INTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
-#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
-#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
+#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+
+#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
/*! MODE - Selects timer mode.
* 0b00..Repeat interrupt mode.
* 0b01..One-shot interrupt mode.
* 0b10..One-shot stall mode.
* 0b11..Reserved.
*/
-#define MRT_CHANNEL_CTRL_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
/*! @} */
/* The count of MRT_CHANNEL_CTRL */
-#define MRT_CHANNEL_CTRL_COUNT (4U)
+#define MRT_CHANNEL_CTRL_COUNT (4U)
/*! @name CHANNEL_STAT - MRT Status register. */
/*! @{ */
-#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
-#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
+
+#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
/*! INTFLAG - Monitors the interrupt flag.
* 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
* 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
* the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
* are raised. Writing a 1 to this bit clears the interrupt request.
*/
-#define MRT_CHANNEL_STAT_INTFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
-#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
-#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
+#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+
+#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
/*! RUN - Indicates the state of TIMERn. This bit is read-only.
* 0b0..Idle state. TIMERn is stopped.
* 0b1..Running. TIMERn is running.
*/
-#define MRT_CHANNEL_STAT_RUN(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
-#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
-#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
+#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+
+#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG
* register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating
* modes.
* 0b0..This channel is not in use.
* 0b1..This channel is in use.
*/
-#define MRT_CHANNEL_STAT_INUSE(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
/*! @} */
/* The count of MRT_CHANNEL_STAT */
-#define MRT_CHANNEL_STAT_COUNT (4U)
+#define MRT_CHANNEL_STAT_COUNT (4U)
-/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance,
- * and allows choosing an overall mode for the idle channel feature. */
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
/*! @{ */
-#define MRT_MODCFG_NOC_MASK (0xFU)
-#define MRT_MODCFG_NOC_SHIFT (0U)
+
+#define MRT_MODCFG_NOC_MASK (0xFU)
+#define MRT_MODCFG_NOC_SHIFT (0U)
/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
*/
-#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
-#define MRT_MODCFG_NOB_MASK (0x1F0U)
-#define MRT_MODCFG_NOB_SHIFT (4U)
+#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+
+#define MRT_MODCFG_NOB_MASK (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT (4U)
/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.)
*/
-#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
-#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
-#define MRT_MODCFG_MULTITASK_SHIFT (31U)
+#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+
+#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT (31U)
/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
* 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
* 0b1..Multi-task mode.
*/
-#define MRT_MODCFG_MULTITASK(x) \
- (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
/*! @} */
/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
/*! @{ */
-#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
-#define MRT_IDLE_CH_CHAN_SHIFT (4U)
+
+#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT (4U)
/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
* positioned such that it can be used as an offset from the MRT base address in order to access
* the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
* text above for more details.
*/
-#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
/*! @} */
/*! @name IRQ_FLAG - Global interrupt flag register */
/*! @{ */
-#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
-#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
+
+#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
* 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
* 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
* the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
* interrupt are raised. Writing a 1 to this bit clears the interrupt request.
*/
-#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
-#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
-#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
+#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+
+#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
*/
-#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
-#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
-#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
+#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+
+#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
*/
-#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
-#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
-#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
+#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+
+#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
*/
-#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group MRT_Register_Masks */
+
/* MRT - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral MRT0 base address */
-#define MRT0_BASE (0x5000D000u)
-/** Peripheral MRT0 base address */
-#define MRT0_BASE_NS (0x4000D000u)
-/** Peripheral MRT0 base pointer */
-#define MRT0 ((MRT_Type *)MRT0_BASE)
-/** Peripheral MRT0 base pointer */
-#define MRT0_NS ((MRT_Type *)MRT0_BASE_NS)
-/** Array initializer of MRT peripheral base addresses */
-#define MRT_BASE_ADDRS \
- { \
- MRT0_BASE \
- }
-/** Array initializer of MRT peripheral base pointers */
-#define MRT_BASE_PTRS \
- { \
- MRT0 \
- }
-/** Array initializer of MRT peripheral base addresses */
-#define MRT_BASE_ADDRS_NS \
- { \
- MRT0_BASE_NS \
- }
-/** Array initializer of MRT peripheral base pointers */
-#define MRT_BASE_PTRS_NS \
- { \
- MRT0_NS \
- }
+ /** Peripheral MRT0 base address */
+ #define MRT0_BASE (0x5000D000u)
+ /** Peripheral MRT0 base address */
+ #define MRT0_BASE_NS (0x4000D000u)
+ /** Peripheral MRT0 base pointer */
+ #define MRT0 ((MRT_Type *)MRT0_BASE)
+ /** Peripheral MRT0 base pointer */
+ #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS)
+ /** Array initializer of MRT peripheral base addresses */
+ #define MRT_BASE_ADDRS { MRT0_BASE }
+ /** Array initializer of MRT peripheral base pointers */
+ #define MRT_BASE_PTRS { MRT0 }
+ /** Array initializer of MRT peripheral base addresses */
+ #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS }
+ /** Array initializer of MRT peripheral base pointers */
+ #define MRT_BASE_PTRS_NS { MRT0_NS }
#else
-/** Peripheral MRT0 base address */
-#define MRT0_BASE (0x4000D000u)
-/** Peripheral MRT0 base pointer */
-#define MRT0 ((MRT_Type *)MRT0_BASE)
-/** Array initializer of MRT peripheral base addresses */
-#define MRT_BASE_ADDRS \
- { \
- MRT0_BASE \
- }
-/** Array initializer of MRT peripheral base pointers */
-#define MRT_BASE_PTRS \
- { \
- MRT0 \
- }
+ /** Peripheral MRT0 base address */
+ #define MRT0_BASE (0x4000D000u)
+ /** Peripheral MRT0 base pointer */
+ #define MRT0 ((MRT_Type *)MRT0_BASE)
+ /** Array initializer of MRT peripheral base addresses */
+ #define MRT_BASE_ADDRS { MRT0_BASE }
+ /** Array initializer of MRT peripheral base pointers */
+ #define MRT_BASE_PTRS { MRT0 }
#endif
/** Interrupt vectors for the MRT peripheral type */
-#define MRT_IRQS \
- { \
- MRT0_IRQn \
- }
+#define MRT_IRQS { MRT0_IRQn }
/*!
* @}
*/ /* end of group MRT_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- OSTIMER Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -14136,16 +13409,15 @@ typedef struct
*/
/** OSTIMER - Register Layout Typedef */
-typedef struct
-{
- __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */
- __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */
- __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */
- __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */
- __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */
- __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */
- uint8_t RESERVED_0[4];
- __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */
+typedef struct {
+ __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */
+ __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */
+ __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */
+ __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */
+ __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */
+ __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */
} OSTIMER_Type;
/* ----------------------------------------------------------------------------
@@ -14159,162 +13431,140 @@ typedef struct
/*! @name EVTIMERL - EVTIMER Low Register */
/*! @{ */
+
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
-/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the EVTIMER.
- * Note there is physically only one EVTimer, readable from all domains.
+/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits
+ * EVTIMER. Note: There is only one EVTIMER, readable from all domains.
*/
-#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & \
- OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
/*! @} */
/*! @name EVTIMERH - EVTIMER High Register */
/*! @{ */
+
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU)
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
-/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 32 bits of the EVTIMER.
- * Note there is physically only one EVTimer, readable from all domains.
+/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits
+ * EVTIMER. Note there is only one EVTIMER, readable from all domains.
*/
-#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & \
- OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
/*! @} */
-/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */
+/*! @name CAPTURE_L - Capture Low Register */
/*! @{ */
-#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU)
-#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U)
-/*! CAPTUREn_VALUE - A read reflects the value of the lower 32 bits of the central EVTIMER at the
- * time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are
- * implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses.
+
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U)
+/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at
+ * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();").
*/
-#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK)
+#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK)
/*! @} */
-/*! @name CAPTUREN_H - Local Capture High Register for CPUn */
+/*! @name CAPTURE_H - Capture High Register */
/*! @{ */
-#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0x3FFU)
-#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U)
-/*! CAPTUREn_VALUE - A read reflects the value of the upper 32 bits of the central EVTIMER at the
- * time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are
- * implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses.
+
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU)
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U)
+/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at
+ * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();").
*/
-#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK)
+#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK)
/*! @} */
-/*! @name MATCHN_L - Local Match Low Register for CPUn */
+/*! @name MATCH_L - Match Low Register */
/*! @{ */
-#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU)
-#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U)
-/*! MATCHn_VALUE - The value written to the MATCH (L/H) register pair is compared against the
- * central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair
- * of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the
- * same pair of addresses.
+
+#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU)
+#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U)
+/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central
+ * EVTIMER. When a match occurs, an interrupt request is generated if enabled.
*/
-#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK)
+#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK)
/*! @} */
-/*! @name MATCHN_H - Match High Register for CPUn */
+/*! @name MATCH_H - Match High Register */
/*! @{ */
-#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0x3FFU)
-#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U)
-/*! MATCHn_VALUE - The value written to the MATCH (L/H) register pair is compared against the
- * central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair
- * of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the
- * same pair of addresses.
+
+#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU)
+#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U)
+/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared
+ * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled.
*/
-#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK)
+#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK)
/*! @} */
-/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */
+/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */
/*! @{ */
+
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
-/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 64-bit EVTIMER and
- * the value programmed in the Match-register pair for the associated CPU This bit is cleared by
- * writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match
- * value is written into the MATCH_L/H registers
- */
-#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & \
- OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
+/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and
+ * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes
+ * to clear this bit are asynchronous. It should be done before a new match value is written into
+ * the MATCH_L/H registers.
+ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
+
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
-/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the Domainn processor will
+/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will
* be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests
- * due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for
- * each CPU. Each CPU reads its own local value at the same address.
+ * due to the OSTIMER_INTR flag are blocked.
+ */
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
+
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U)
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U)
+/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In
+ * typical applications it should not be necessary to test this bit. [1]
*/
-#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) \
- (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & \
- OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
+#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group OSTIMER_Register_Masks */
+
/* OSTIMER - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral OSTIMER base address */
-#define OSTIMER_BASE (0x5002D000u)
-/** Peripheral OSTIMER base address */
-#define OSTIMER_BASE_NS (0x4002D000u)
-/** Peripheral OSTIMER base pointer */
-#define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE)
-/** Peripheral OSTIMER base pointer */
-#define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS)
-/** Array initializer of OSTIMER peripheral base addresses */
-#define OSTIMER_BASE_ADDRS \
- { \
- OSTIMER_BASE \
- }
-/** Array initializer of OSTIMER peripheral base pointers */
-#define OSTIMER_BASE_PTRS \
- { \
- OSTIMER \
- }
-/** Array initializer of OSTIMER peripheral base addresses */
-#define OSTIMER_BASE_ADDRS_NS \
- { \
- OSTIMER_BASE_NS \
- }
-/** Array initializer of OSTIMER peripheral base pointers */
-#define OSTIMER_BASE_PTRS_NS \
- { \
- OSTIMER_NS \
- }
+ /** Peripheral OSTIMER base address */
+ #define OSTIMER_BASE (0x5002D000u)
+ /** Peripheral OSTIMER base address */
+ #define OSTIMER_BASE_NS (0x4002D000u)
+ /** Peripheral OSTIMER base pointer */
+ #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE)
+ /** Peripheral OSTIMER base pointer */
+ #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS)
+ /** Array initializer of OSTIMER peripheral base addresses */
+ #define OSTIMER_BASE_ADDRS { OSTIMER_BASE }
+ /** Array initializer of OSTIMER peripheral base pointers */
+ #define OSTIMER_BASE_PTRS { OSTIMER }
+ /** Array initializer of OSTIMER peripheral base addresses */
+ #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS }
+ /** Array initializer of OSTIMER peripheral base pointers */
+ #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS }
#else
-/** Peripheral OSTIMER base address */
-#define OSTIMER_BASE (0x4002D000u)
-/** Peripheral OSTIMER base pointer */
-#define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE)
-/** Array initializer of OSTIMER peripheral base addresses */
-#define OSTIMER_BASE_ADDRS \
- { \
- OSTIMER_BASE \
- }
-/** Array initializer of OSTIMER peripheral base pointers */
-#define OSTIMER_BASE_PTRS \
- { \
- OSTIMER \
- }
+ /** Peripheral OSTIMER base address */
+ #define OSTIMER_BASE (0x4002D000u)
+ /** Peripheral OSTIMER base pointer */
+ #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE)
+ /** Array initializer of OSTIMER peripheral base addresses */
+ #define OSTIMER_BASE_ADDRS { OSTIMER_BASE }
+ /** Array initializer of OSTIMER peripheral base pointers */
+ #define OSTIMER_BASE_PTRS { OSTIMER }
#endif
/** Interrupt vectors for the OSTIMER peripheral type */
-#define OSTIMER_IRQS \
- { \
- OS_EVENT_IRQn \
- }
+#define OSTIMER_IRQS { OS_EVENT_IRQn }
/*!
* @}
*/ /* end of group OSTIMER_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- PINT Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -14325,21 +13575,20 @@ typedef struct
*/
/** PINT - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
- __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
- __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
- __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
- __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
- __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
- __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
- __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
- __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
- __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
- __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
- __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
- __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+typedef struct {
+ __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
+ __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+ __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+ __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+ __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+ __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+ __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+ __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
+ __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
+ __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
+ __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
+ __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+ __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
} PINT_Type;
/* ----------------------------------------------------------------------------
@@ -14353,149 +13602,161 @@ typedef struct
/*! @name ISEL - Pin Interrupt Mode register */
/*! @{ */
-#define PINT_ISEL_PMODE_MASK (0xFFU)
-#define PINT_ISEL_PMODE_SHIFT (0U)
+
+#define PINT_ISEL_PMODE_MASK (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT (0U)
/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt
* selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive
*/
-#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
/*! @} */
/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
/*! @{ */
-#define PINT_IENR_ENRL_MASK (0xFFU)
-#define PINT_IENR_ENRL_SHIFT (0U)
+
+#define PINT_IENR_ENRL_MASK (0xFFU)
+#define PINT_IENR_ENRL_SHIFT (0U)
/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the
* pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable
* rising edge or level interrupt.
*/
-#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
/*! @} */
/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
/*! @{ */
-#define PINT_SIENR_SETENRL_MASK (0xFFU)
-#define PINT_SIENR_SETENRL_SHIFT (0U)
+
+#define PINT_SIENR_SETENRL_MASK (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT (0U)
/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n
* sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt.
*/
-#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
/*! @} */
/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
/*! @{ */
-#define PINT_CIENR_CENRL_MASK (0xFFU)
-#define PINT_CIENR_CENRL_SHIFT (0U)
+
+#define PINT_CIENR_CENRL_MASK (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT (0U)
/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit
* n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level
* interrupt.
*/
-#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
/*! @} */
/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
/*! @{ */
-#define PINT_IENF_ENAF_MASK (0xFFU)
-#define PINT_IENF_ENAF_SHIFT (0U)
+
+#define PINT_IENF_ENAF_MASK (0xFFU)
+#define PINT_IENF_ENAF_SHIFT (0U)
/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt.
* Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt
* or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active
* interrupt level HIGH.
*/
-#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
/*! @} */
/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
/*! @{ */
-#define PINT_SIENF_SETENAF_MASK (0xFFU)
-#define PINT_SIENF_SETENAF_SHIFT (0U)
+
+#define PINT_SIENF_SETENAF_MASK (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT (0U)
/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n
* sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable
* falling edge interrupt.
*/
-#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
/*! @} */
/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
/*! @{ */
-#define PINT_CIENF_CENAF_MASK (0xFFU)
-#define PINT_CIENF_CENAF_SHIFT (0U)
+
+#define PINT_CIENF_CENAF_MASK (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT (0U)
/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n
* clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or
* falling edge interrupt disabled.
*/
-#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
/*! @} */
/*! @name RISE - Pin interrupt rising edge register */
/*! @{ */
-#define PINT_RISE_RDET_MASK (0xFFU)
-#define PINT_RISE_RDET_SHIFT (0U)
+
+#define PINT_RISE_RDET_MASK (0xFFU)
+#define PINT_RISE_RDET_SHIFT (0U)
/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read
* 0: No rising edge has been detected on this pin since Reset or the last time a one was written
* to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the
* last time a one was written to this bit. Write 1: clear rising edge detection for this pin.
*/
-#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
/*! @} */
/*! @name FALL - Pin interrupt falling edge register */
/*! @{ */
-#define PINT_FALL_FDET_MASK (0xFFU)
-#define PINT_FALL_FDET_SHIFT (0U)
+
+#define PINT_FALL_FDET_MASK (0xFFU)
+#define PINT_FALL_FDET_SHIFT (0U)
/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read
* 0: No falling edge has been detected on this pin since Reset or the last time a one was
* written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or
* the last time a one was written to this bit. Write 1: clear falling edge detection for this
* pin.
*/
-#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
/*! @} */
/*! @name IST - Pin interrupt status register */
/*! @{ */
-#define PINT_IST_PSTAT_MASK (0xFFU)
-#define PINT_IST_PSTAT_SHIFT (0U)
+
+#define PINT_IST_PSTAT_MASK (0xFFU)
+#define PINT_IST_PSTAT_SHIFT (0U)
/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts
* the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for
* this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this
* interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin.
* Write 1 (level-sensitive): switch the active level for this pin (in the IENF register).
*/
-#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
/*! @} */
/*! @name PMCTRL - Pattern match interrupt control register */
/*! @{ */
-#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
-#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
-/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern
- * match function. 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
+
+#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
+/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.
+ * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.
* 0b1..Pattern match. Interrupts are driven in response to pattern matches.
*/
-#define PINT_PMCTRL_SEL_PMATCH(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
-#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
-#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
-/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression
- * evaluates to true. 0b0..Disabled. RXEV output to the CPU is disabled. 0b1..Enabled. RXEV output to the CPU is
- * enabled.
- */
-#define PINT_PMCTRL_ENA_RXEV(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
-#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
-#define PINT_PMCTRL_PMAT_SHIFT (24U)
+#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+
+#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.
+ * 0b0..Disabled. RXEV output to the CPU is disabled.
+ * 0b1..Enabled. RXEV output to the CPU is enabled.
+ */
+#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+
+#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT (24U)
/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field
* indicates that the corresponding product term is matched by the current state of the appropriate
* inputs.
*/
-#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
/*! @} */
/*! @name PMSRC - Pattern match interrupt bit-slice source register */
/*! @{ */
-#define PINT_PMSRC_SRC0_MASK (0x700U)
-#define PINT_PMSRC_SRC0_SHIFT (8U)
+
+#define PINT_PMSRC_SRC0_MASK (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT (8U)
/*! SRC0 - Selects the input source for bit slice 0
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.
@@ -14506,9 +13767,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.
*/
-#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
-#define PINT_PMSRC_SRC1_MASK (0x3800U)
-#define PINT_PMSRC_SRC1_SHIFT (11U)
+#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+
+#define PINT_PMSRC_SRC1_MASK (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT (11U)
/*! SRC1 - Selects the input source for bit slice 1
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.
@@ -14519,9 +13781,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.
*/
-#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
-#define PINT_PMSRC_SRC2_MASK (0x1C000U)
-#define PINT_PMSRC_SRC2_SHIFT (14U)
+#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+
+#define PINT_PMSRC_SRC2_MASK (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT (14U)
/*! SRC2 - Selects the input source for bit slice 2
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.
@@ -14532,9 +13795,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.
*/
-#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
-#define PINT_PMSRC_SRC3_MASK (0xE0000U)
-#define PINT_PMSRC_SRC3_SHIFT (17U)
+#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+
+#define PINT_PMSRC_SRC3_MASK (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT (17U)
/*! SRC3 - Selects the input source for bit slice 3
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.
@@ -14545,9 +13809,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.
*/
-#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
-#define PINT_PMSRC_SRC4_MASK (0x700000U)
-#define PINT_PMSRC_SRC4_SHIFT (20U)
+#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+
+#define PINT_PMSRC_SRC4_MASK (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT (20U)
/*! SRC4 - Selects the input source for bit slice 4
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.
@@ -14558,9 +13823,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.
*/
-#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
-#define PINT_PMSRC_SRC5_MASK (0x3800000U)
-#define PINT_PMSRC_SRC5_SHIFT (23U)
+#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+
+#define PINT_PMSRC_SRC5_MASK (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT (23U)
/*! SRC5 - Selects the input source for bit slice 5
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.
@@ -14571,9 +13837,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.
*/
-#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
-#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
-#define PINT_PMSRC_SRC6_SHIFT (26U)
+#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+
+#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT (26U)
/*! SRC6 - Selects the input source for bit slice 6
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.
@@ -14584,9 +13851,10 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.
*/
-#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
-#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
-#define PINT_PMSRC_SRC7_SHIFT (29U)
+#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+
+#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT (29U)
/*! SRC7 - Selects the input source for bit slice 7
* 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.
* 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.
@@ -14597,76 +13865,70 @@ typedef struct
* 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.
* 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.
*/
-#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
/*! @} */
/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
/*! @{ */
-#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
-#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
+
+#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
* 0b0..No effect. Slice 0 is not an endpoint.
- * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS0(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
-#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
-#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
+#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
* 0b0..No effect. Slice 1 is not an endpoint.
- * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS1(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
-#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
-#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
+#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
* 0b0..No effect. Slice 2 is not an endpoint.
- * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS2(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
-#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
-#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
+#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
* 0b0..No effect. Slice 3 is not an endpoint.
- * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS3(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
-#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
-#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
+#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
* 0b0..No effect. Slice 4 is not an endpoint.
- * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS4(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
-#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
-#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
+#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
* 0b0..No effect. Slice 5 is not an endpoint.
- * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS5(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
-#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
-#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
+#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+
+#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
* 0b0..No effect. Slice 6 is not an endpoint.
- * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the
- * minterm evaluates as true.
+ * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
*/
-#define PINT_PMCFG_PROD_ENDPTS6(x) \
- (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
-#define PINT_PMCFG_CFG0_MASK (0x700U)
-#define PINT_PMCFG_CFG0_SHIFT (8U)
+#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+
+#define PINT_PMCFG_CFG0_MASK (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT (8U)
/*! CFG0 - Specifies the match contribution condition for bit slice 0.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14678,16 +13940,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
-#define PINT_PMCFG_CFG1_MASK (0x3800U)
-#define PINT_PMCFG_CFG1_SHIFT (11U)
+#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+
+#define PINT_PMCFG_CFG1_MASK (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT (11U)
/*! CFG1 - Specifies the match contribution condition for bit slice 1.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14699,16 +13962,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
-#define PINT_PMCFG_CFG2_MASK (0x1C000U)
-#define PINT_PMCFG_CFG2_SHIFT (14U)
+#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+
+#define PINT_PMCFG_CFG2_MASK (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT (14U)
/*! CFG2 - Specifies the match contribution condition for bit slice 2.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14720,16 +13984,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
-#define PINT_PMCFG_CFG3_MASK (0xE0000U)
-#define PINT_PMCFG_CFG3_SHIFT (17U)
+#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+
+#define PINT_PMCFG_CFG3_MASK (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT (17U)
/*! CFG3 - Specifies the match contribution condition for bit slice 3.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14741,16 +14006,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
-#define PINT_PMCFG_CFG4_MASK (0x700000U)
-#define PINT_PMCFG_CFG4_SHIFT (20U)
+#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+
+#define PINT_PMCFG_CFG4_MASK (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT (20U)
/*! CFG4 - Specifies the match contribution condition for bit slice 4.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14762,16 +14028,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
-#define PINT_PMCFG_CFG5_MASK (0x3800000U)
-#define PINT_PMCFG_CFG5_SHIFT (23U)
+#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+
+#define PINT_PMCFG_CFG5_MASK (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT (23U)
/*! CFG5 - Specifies the match contribution condition for bit slice 5.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14783,16 +14050,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
-#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
-#define PINT_PMCFG_CFG6_SHIFT (26U)
+#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+
+#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT (26U)
/*! CFG6 - Specifies the match contribution condition for bit slice 6.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14804,16 +14072,17 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
-#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
-#define PINT_PMCFG_CFG7_SHIFT (29U)
+#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+
+#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT (29U)
/*! CFG7 - Specifies the match contribution condition for bit slice 7.
* 0b000..Constant HIGH. This bit slice always contributes to a product term match.
* 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
@@ -14825,89 +14094,70 @@ typedef struct
* 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
* has occurred since the last time the edge detection for this bit slice was cleared. This bit is only
* cleared when the PMCFG or the PMSRC registers are written to.
- * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit
- * slice in the PMSRC register. 0b101..Low level. Match occurs when there is a low level on the specified input.
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.
* 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
* 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or
* falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit
* is cleared after one clock cycle.
*/
-#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group PINT_Register_Masks */
+
/* PINT - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral PINT base address */
-#define PINT_BASE (0x50004000u)
-/** Peripheral PINT base address */
-#define PINT_BASE_NS (0x40004000u)
-/** Peripheral PINT base pointer */
-#define PINT ((PINT_Type *)PINT_BASE)
-/** Peripheral PINT base pointer */
-#define PINT_NS ((PINT_Type *)PINT_BASE_NS)
-/** Peripheral SECPINT base address */
-#define SECPINT_BASE (0x50005000u)
-/** Peripheral SECPINT base address */
-#define SECPINT_BASE_NS (0x40005000u)
-/** Peripheral SECPINT base pointer */
-#define SECPINT ((PINT_Type *)SECPINT_BASE)
-/** Peripheral SECPINT base pointer */
-#define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS)
-/** Array initializer of PINT peripheral base addresses */
-#define PINT_BASE_ADDRS \
- { \
- PINT_BASE, SECPINT_BASE \
- }
-/** Array initializer of PINT peripheral base pointers */
-#define PINT_BASE_PTRS \
- { \
- PINT, SECPINT \
- }
-/** Array initializer of PINT peripheral base addresses */
-#define PINT_BASE_ADDRS_NS \
- { \
- PINT_BASE_NS, SECPINT_BASE_NS \
- }
-/** Array initializer of PINT peripheral base pointers */
-#define PINT_BASE_PTRS_NS \
- { \
- PINT_NS, SECPINT_NS \
- }
+ /** Peripheral PINT base address */
+ #define PINT_BASE (0x50004000u)
+ /** Peripheral PINT base address */
+ #define PINT_BASE_NS (0x40004000u)
+ /** Peripheral PINT base pointer */
+ #define PINT ((PINT_Type *)PINT_BASE)
+ /** Peripheral PINT base pointer */
+ #define PINT_NS ((PINT_Type *)PINT_BASE_NS)
+ /** Peripheral SECPINT base address */
+ #define SECPINT_BASE (0x50005000u)
+ /** Peripheral SECPINT base address */
+ #define SECPINT_BASE_NS (0x40005000u)
+ /** Peripheral SECPINT base pointer */
+ #define SECPINT ((PINT_Type *)SECPINT_BASE)
+ /** Peripheral SECPINT base pointer */
+ #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS)
+ /** Array initializer of PINT peripheral base addresses */
+ #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE }
+ /** Array initializer of PINT peripheral base pointers */
+ #define PINT_BASE_PTRS { PINT, SECPINT }
+ /** Array initializer of PINT peripheral base addresses */
+ #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS }
+ /** Array initializer of PINT peripheral base pointers */
+ #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS }
#else
-/** Peripheral PINT base address */
-#define PINT_BASE (0x40004000u)
-/** Peripheral PINT base pointer */
-#define PINT ((PINT_Type *)PINT_BASE)
-/** Peripheral SECPINT base address */
-#define SECPINT_BASE (0x40005000u)
-/** Peripheral SECPINT base pointer */
-#define SECPINT ((PINT_Type *)SECPINT_BASE)
-/** Array initializer of PINT peripheral base addresses */
-#define PINT_BASE_ADDRS \
- { \
- PINT_BASE, SECPINT_BASE \
- }
-/** Array initializer of PINT peripheral base pointers */
-#define PINT_BASE_PTRS \
- { \
- PINT, SECPINT \
- }
+ /** Peripheral PINT base address */
+ #define PINT_BASE (0x40004000u)
+ /** Peripheral PINT base pointer */
+ #define PINT ((PINT_Type *)PINT_BASE)
+ /** Peripheral SECPINT base address */
+ #define SECPINT_BASE (0x40005000u)
+ /** Peripheral SECPINT base pointer */
+ #define SECPINT ((PINT_Type *)SECPINT_BASE)
+ /** Array initializer of PINT peripheral base addresses */
+ #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE }
+ /** Array initializer of PINT peripheral base pointers */
+ #define PINT_BASE_PTRS { PINT, SECPINT }
#endif
/** Interrupt vectors for the PINT peripheral type */
-#define PINT_IRQS \
- { \
- PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, \
- PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn \
- }
+#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn }
/*!
* @}
*/ /* end of group PINT_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- PLU Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -14918,22 +14168,18 @@ typedef struct
*/
/** PLU - Register Layout Typedef */
-typedef struct
-{
- struct
- { /* offset: 0x0, array step: 0x20 */
- __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */
- uint8_t RESERVED_0[12];
- } LUT[26];
- uint8_t RESERVED_0[1216];
- __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents
- for LUT25, array offset: 0x800, array step: 0x4 */
- uint8_t RESERVED_1[152];
- __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */
- __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */
- uint8_t RESERVED_2[760];
- __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be
- connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x20 */
+ __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */
+ uint8_t RESERVED_0[12];
+ } LUT[26];
+ uint8_t RESERVED_0[1216];
+ __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */
+ uint8_t RESERVED_1[152];
+ __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */
+ __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */
+ uint8_t RESERVED_2[760];
+ __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */
} PLU_Type;
/* ----------------------------------------------------------------------------
@@ -14947,8 +14193,9 @@ typedef struct
/*! @name LUT_INP_MUX - LUTn input x MUX */
/*! @{ */
-#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU)
-#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U)
+
+#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU)
+#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U)
/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot
* associated with the output from LUTn itself is tied low.
* 0b000000..The PLU primary inputs 0.
@@ -14988,86 +14235,85 @@ typedef struct
* 0b100010..state(2).
* 0b100011..state(3).
*/
-#define PLU_LUT_INP_MUX_LUTn_INPx(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK)
+#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK)
/*! @} */
/* The count of PLU_LUT_INP_MUX */
-#define PLU_LUT_INP_MUX_COUNT (26U)
+#define PLU_LUT_INP_MUX_COUNT (26U)
/* The count of PLU_LUT_INP_MUX */
-#define PLU_LUT_INP_MUX_COUNT2 (5U)
+#define PLU_LUT_INP_MUX_COUNT2 (5U)
/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */
/*! @{ */
-#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU)
-#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U)
+
+#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU)
+#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U)
/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25..
*/
-#define PLU_LUT_TRUTH_LUTn_TRUTH(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK)
+#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK)
/*! @} */
/* The count of PLU_LUT_TRUTH */
-#define PLU_LUT_TRUTH_COUNT (26U)
+#define PLU_LUT_TRUTH_COUNT (26U)
/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */
/*! @{ */
-#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU)
-#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U)
+
+#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU)
+#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U)
/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs..
*/
-#define PLU_OUTPUTS_OUTPUT_STATE(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK)
+#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK)
/*! @} */
/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */
/*! @{ */
-#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU)
-#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U)
+
+#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU)
+#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U)
/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt)
*/
-#define PLU_WAKEINT_CTRL_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK)
-#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U)
-#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U)
+#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK)
+
+#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U)
+#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U)
/*! FILTER_MODE - control input of the PLU, add filtering for glitch.
* 0b00..Bypass mode.
* 0b01..Filter 1 clock period.
* 0b10..Filter 2 clock period.
* 0b11..Filter 3 clock period.
*/
-#define PLU_WAKEINT_CTRL_FILTER_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK)
-#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U)
-#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U)
+#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK)
+
+#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U)
+#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U)
/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel.
* 0b00..Selects the 1 MHz low-power oscillator as the filter clock.
* 0b01..Selects the 12 Mhz FRO as the filter clock.
* 0b10..Selects a third filter clock source, if provided.
* 0b11..Reserved.
*/
-#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK)
-#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U)
-#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U)
+#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK)
+
+#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U)
+#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U)
/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR
*/
-#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK)
-#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U)
-#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U)
+#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK)
+
+#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U)
+#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U)
/*! INTR_CLEAR - Write to clear wakeint_latched
*/
-#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)
+#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)
/*! @} */
-/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU
- * Output 7 */
+/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */
/*! @{ */
-#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU)
-#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U)
+
+#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU)
+#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U)
/*! OUTPUTn - Selects the source to be connected to PLU Output 7.
* 0b00000..The PLU output 0.
* 0b00001..The PLU output 1.
@@ -15100,68 +14346,52 @@ typedef struct
* 0b11100..state(2).
* 0b11101..state(3).
*/
-#define PLU_OUTPUT_MUX_OUTPUTn(x) \
- (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK)
+#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK)
/*! @} */
/* The count of PLU_OUTPUT_MUX */
-#define PLU_OUTPUT_MUX_COUNT (8U)
+#define PLU_OUTPUT_MUX_COUNT (8U)
+
/*!
* @}
*/ /* end of group PLU_Register_Masks */
+
/* PLU - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral PLU base address */
-#define PLU_BASE (0x5003D000u)
-/** Peripheral PLU base address */
-#define PLU_BASE_NS (0x4003D000u)
-/** Peripheral PLU base pointer */
-#define PLU ((PLU_Type *)PLU_BASE)
-/** Peripheral PLU base pointer */
-#define PLU_NS ((PLU_Type *)PLU_BASE_NS)
-/** Array initializer of PLU peripheral base addresses */
-#define PLU_BASE_ADDRS \
- { \
- PLU_BASE \
- }
-/** Array initializer of PLU peripheral base pointers */
-#define PLU_BASE_PTRS \
- { \
- PLU \
- }
-/** Array initializer of PLU peripheral base addresses */
-#define PLU_BASE_ADDRS_NS \
- { \
- PLU_BASE_NS \
- }
-/** Array initializer of PLU peripheral base pointers */
-#define PLU_BASE_PTRS_NS \
- { \
- PLU_NS \
- }
+ /** Peripheral PLU base address */
+ #define PLU_BASE (0x5003D000u)
+ /** Peripheral PLU base address */
+ #define PLU_BASE_NS (0x4003D000u)
+ /** Peripheral PLU base pointer */
+ #define PLU ((PLU_Type *)PLU_BASE)
+ /** Peripheral PLU base pointer */
+ #define PLU_NS ((PLU_Type *)PLU_BASE_NS)
+ /** Array initializer of PLU peripheral base addresses */
+ #define PLU_BASE_ADDRS { PLU_BASE }
+ /** Array initializer of PLU peripheral base pointers */
+ #define PLU_BASE_PTRS { PLU }
+ /** Array initializer of PLU peripheral base addresses */
+ #define PLU_BASE_ADDRS_NS { PLU_BASE_NS }
+ /** Array initializer of PLU peripheral base pointers */
+ #define PLU_BASE_PTRS_NS { PLU_NS }
#else
-/** Peripheral PLU base address */
-#define PLU_BASE (0x4003D000u)
-/** Peripheral PLU base pointer */
-#define PLU ((PLU_Type *)PLU_BASE)
-/** Array initializer of PLU peripheral base addresses */
-#define PLU_BASE_ADDRS \
- { \
- PLU_BASE \
- }
-/** Array initializer of PLU peripheral base pointers */
-#define PLU_BASE_PTRS \
- { \
- PLU \
- }
+ /** Peripheral PLU base address */
+ #define PLU_BASE (0x4003D000u)
+ /** Peripheral PLU base pointer */
+ #define PLU ((PLU_Type *)PLU_BASE)
+ /** Array initializer of PLU peripheral base addresses */
+ #define PLU_BASE_ADDRS { PLU_BASE }
+ /** Array initializer of PLU peripheral base pointers */
+ #define PLU_BASE_PTRS { PLU }
#endif
/*!
* @}
*/ /* end of group PLU_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -15172,38 +14402,28 @@ typedef struct
*/
/** PMC - Register Layout Typedef */
-typedef struct
-{
- uint8_t RESERVED_0[8];
- __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down
- Reset, Software Reset], offset: 0x8 */
- uint8_t RESERVED_1[36];
- __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software
- Reset], offset: 0x30 */
- uint8_t RESERVED_2[28];
- __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset,
- Deep Power Down Reset, Software Reset], offset: 0x50 */
- uint8_t RESERVED_3[20];
- __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */
- uint8_t RESERVED_4[8];
- __IO uint32_t
- STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */
- uint8_t RESERVED_5[12];
- __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset],
- offset: 0x84 */
- uint8_t RESERVED_6[16];
- __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors
- Reset], offset: 0x98 */
- __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */
- uint8_t RESERVED_7[24];
- __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out
- Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */
- uint8_t RESERVED_8[4];
- __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out
- Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */
- uint8_t RESERVED_9[4];
- __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out
- Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */
+ uint8_t RESERVED_1[36];
+ __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */
+ uint8_t RESERVED_2[28];
+ __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */
+ uint8_t RESERVED_3[20];
+ __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */
+ uint8_t RESERVED_4[8];
+ __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */
+ uint8_t RESERVED_6[16];
+ __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */
+ __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */
+ uint8_t RESERVED_7[24];
+ __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */
+ uint8_t RESERVED_8[4];
+ __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */
+ uint8_t RESERVED_9[4];
+ __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */
} PMC_Type;
/* ----------------------------------------------------------------------------
@@ -15215,40 +14435,39 @@ typedef struct
* @{
*/
-/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset,
- * Software Reset] */
+/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */
-#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U)
+
+#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U)
#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U)
/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer).
* 0b0..Reset event from DEEP POWER DOWN mode is disable.
* 0b1..Reset event from DEEP POWER DOWN mode is enable.
*/
-#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & \
- PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK)
-#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U)
-#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U)
+#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK)
+
+#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U)
+#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U)
/*! BODVBATRESETENABLE - BOD VBAT reset enable.
* 0b0..BOD VBAT reset is disable.
* 0b1..BOD VBAT reset is enable.
*/
-#define PMC_RESETCTRL_BODVBATRESETENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)
-#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U)
-#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U)
+#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)
+
+#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U)
+#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U)
/*! SWRRESETENABLE - Software reset enable.
* 0b0..Software reset is disable.
* 0b1..Software reset is enable.
*/
-#define PMC_RESETCTRL_SWRRESETENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK)
+#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK)
/*! @} */
/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */
/*! @{ */
-#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU)
-#define PMC_BODVBAT_TRIGLVL_SHIFT (0U)
+
+#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU)
+#define PMC_BODVBAT_TRIGLVL_SHIFT (0U)
/*! TRIGLVL - BoD trigger level.
* 0b00000..1.00 V.
* 0b00001..1.10 V.
@@ -15283,44 +14502,48 @@ typedef struct
* 0b11110..3.30 V.
* 0b11111..3.30 V.
*/
-#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK)
-#define PMC_BODVBAT_HYST_MASK (0x60U)
-#define PMC_BODVBAT_HYST_SHIFT (5U)
+#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK)
+
+#define PMC_BODVBAT_HYST_MASK (0x60U)
+#define PMC_BODVBAT_HYST_SHIFT (5U)
/*! HYST - BoD Hysteresis control.
* 0b00..25 mV.
* 0b01..50 mV.
* 0b10..75 mV.
* 0b11..100 mV.
*/
-#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK)
+#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK)
/*! @} */
-/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power
- * Down Reset, Software Reset] */
+/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */
-#define PMC_COMP_HYST_MASK (0x2U)
-#define PMC_COMP_HYST_SHIFT (1U)
+
+#define PMC_COMP_HYST_MASK (0x2U)
+#define PMC_COMP_HYST_SHIFT (1U)
/*! HYST - Hysteris when hyst = '1'.
* 0b0..Hysteresis is disable.
* 0b1..Hysteresis is enable.
*/
-#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK)
-#define PMC_COMP_VREFINPUT_MASK (0x4U)
-#define PMC_COMP_VREFINPUT_SHIFT (2U)
+#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK)
+
+#define PMC_COMP_VREFINPUT_MASK (0x4U)
+#define PMC_COMP_VREFINPUT_SHIFT (2U)
/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder).
* 0b0..Select internal VREF.
* 0b1..Select VDDA.
*/
-#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK)
-#define PMC_COMP_LOWPOWER_MASK (0x8U)
-#define PMC_COMP_LOWPOWER_SHIFT (3U)
+#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK)
+
+#define PMC_COMP_LOWPOWER_MASK (0x8U)
+#define PMC_COMP_LOWPOWER_SHIFT (3U)
/*! LOWPOWER - Low power mode.
* 0b0..High speed mode.
* 0b1..Low power mode (Low speed).
*/
-#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK)
-#define PMC_COMP_PMUX_MASK (0x70U)
-#define PMC_COMP_PMUX_SHIFT (4U)
+#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK)
+
+#define PMC_COMP_PMUX_MASK (0x70U)
+#define PMC_COMP_PMUX_SHIFT (4U)
/*! PMUX - Control word for P multiplexer:.
* 0b000..VREF (See fiedl VREFINPUT).
* 0b001..Pin P0_0.
@@ -15329,9 +14552,10 @@ typedef struct
* 0b100..Pin P1_14.
* 0b101..Pin P2_23.
*/
-#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK)
-#define PMC_COMP_NMUX_MASK (0x380U)
-#define PMC_COMP_NMUX_SHIFT (7U)
+#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK)
+
+#define PMC_COMP_NMUX_MASK (0x380U)
+#define PMC_COMP_NMUX_SHIFT (7U)
/*! NMUX - Control word for N multiplexer:.
* 0b000..VREF (See field VREFINPUT).
* 0b001..Pin P0_0.
@@ -15340,417 +14564,391 @@ typedef struct
* 0b100..Pin P1_14.
* 0b101..Pin P2_23.
*/
-#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK)
-#define PMC_COMP_VREF_MASK (0x7C00U)
-#define PMC_COMP_VREF_SHIFT (10U)
+#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK)
+
+#define PMC_COMP_VREF_MASK (0x7C00U)
+#define PMC_COMP_VREF_SHIFT (10U)
/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31).
*/
-#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK)
-#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U)
-#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U)
-/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output.
- * 0b00..Bypass mode.
- * 0b01..Filter 1 clock period.
- * 0b10..Filter 2 clock period.
- * 0b11..Filter 3 clock period.
+#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK)
+
+#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U)
+#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U)
+/*! FILTERCGF_SAMPLEMODE - Filter Sample mode.
*/
-#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)
-#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U)
-#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U)
-/*! FILTERCGF_CLKDIV - Filter Clock divider.
- * 0b000..Filter clock period duration equals 1 Analog Comparator clock period.
- * 0b001..Filter clock period duration equals 2 Analog Comparator clock period.
- * 0b010..Filter clock period duration equals 4 Analog Comparator clock period.
- * 0b011..Filter clock period duration equals 8 Analog Comparator clock period.
- * 0b100..Filter clock period duration equals 16 Analog Comparator clock period.
- * 0b101..Filter clock period duration equals 32 Analog Comparator clock period.
- * 0b110..Filter clock period duration equals 64 Analog Comparator clock period.
- * 0b111..Filter clock period duration equals 128 Analog Comparator clock period.
+#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)
+
+#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U)
+#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U)
+/*! FILTERCGF_CLKDIV - Filter Clock div .
*/
-#define PMC_COMP_FILTERCGF_CLKDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK)
+#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK)
/*! @} */
/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */
/*! @{ */
-#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U)
-#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U)
+
+#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U)
+#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U)
/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode.
* 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0.
* 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0.
*/
-#define PMC_WAKEIOCAUSE_WAKEUP0(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK)
-#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U)
-#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U)
+#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK)
+
+#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U)
+#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U)
/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.
* 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1.
* 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1.
*/
-#define PMC_WAKEIOCAUSE_WAKEUP1(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK)
-#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U)
-#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U)
+#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK)
+
+#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U)
+#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U)
/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.
* 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2.
* 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2.
*/
-#define PMC_WAKEIOCAUSE_WAKEUP2(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK)
-#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U)
-#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U)
+#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK)
+
+#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U)
+#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U)
/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.
* 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3.
* 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3.
*/
-#define PMC_WAKEIOCAUSE_WAKEUP3(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK)
+#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK)
/*! @} */
/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */
/*! @{ */
-#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U)
-#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U)
+
+#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U)
+#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U)
/*! XTAL32KOK - XTAL oscillator 32 K OK signal.
*/
-#define PMC_STATUSCLK_XTAL32KOK(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK)
-#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U)
-#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U)
+#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK)
+
+#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U)
+#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U)
/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator.
* 0b0..No oscillation failure has been detetced since the last time this bit has been cleared..
* 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared..
*/
-#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK)
+#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK)
/*! @} */
/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */
/*! @{ */
-#define PMC_AOREG1_POR_MASK (0x10U)
-#define PMC_AOREG1_POR_SHIFT (4U)
+
+#define PMC_AOREG1_POR_MASK (0x10U)
+#define PMC_AOREG1_POR_SHIFT (4U)
/*! POR - The last chip reset was caused by a Power On Reset.
*/
-#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK)
-#define PMC_AOREG1_PADRESET_MASK (0x20U)
-#define PMC_AOREG1_PADRESET_SHIFT (5U)
+#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK)
+
+#define PMC_AOREG1_PADRESET_MASK (0x20U)
+#define PMC_AOREG1_PADRESET_SHIFT (5U)
/*! PADRESET - The last chip reset was caused by a Pin Reset.
*/
-#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK)
-#define PMC_AOREG1_BODRESET_MASK (0x40U)
-#define PMC_AOREG1_BODRESET_SHIFT (6U)
+#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK)
+
+#define PMC_AOREG1_BODRESET_MASK (0x40U)
+#define PMC_AOREG1_BODRESET_SHIFT (6U)
/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD.
*/
-#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK)
-#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U)
-#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U)
+#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK)
+
+#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U)
+#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U)
/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU.
*/
-#define PMC_AOREG1_SYSTEMRESET(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK)
-#define PMC_AOREG1_WDTRESET_MASK (0x100U)
-#define PMC_AOREG1_WDTRESET_SHIFT (8U)
+#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK)
+
+#define PMC_AOREG1_WDTRESET_MASK (0x100U)
+#define PMC_AOREG1_WDTRESET_SHIFT (8U)
/*! WDTRESET - The last chip reset was caused by the Watchdog Timer.
*/
-#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK)
-#define PMC_AOREG1_SWRRESET_MASK (0x200U)
-#define PMC_AOREG1_SWRRESET_SHIFT (9U)
+#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK)
+
+#define PMC_AOREG1_SWRRESET_MASK (0x200U)
+#define PMC_AOREG1_SWRRESET_SHIFT (9U)
/*! SWRRESET - The last chip reset was caused by a Software event.
*/
-#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK)
-#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U)
-#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U)
+#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK)
+
+#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U)
+#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U)
/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode.
*/
-#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK)
-#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U)
-#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U)
-/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep
- * Power-Down mode.
- */
-#define PMC_AOREG1_DPDRESET_RTC(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK)
-#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U)
-#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U)
+#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK)
+
+#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U)
+#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U)
+/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode.
+ */
+#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK)
+
+#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U)
+#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U)
/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode.
*/
-#define PMC_AOREG1_DPDRESET_OSTIMER(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK)
-#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U)
-#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U)
+#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK)
+
+#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U)
+#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U)
/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter.
*/
-#define PMC_AOREG1_BOOTERRORCOUNTER(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK)
+#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK)
/*! @} */
/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */
/*! @{ */
-#define PMC_RTCOSC32K_SEL_MASK (0x1U)
-#define PMC_RTCOSC32K_SEL_SHIFT (0U)
+
+#define PMC_RTCOSC32K_SEL_MASK (0x1U)
+#define PMC_RTCOSC32K_SEL_SHIFT (0U)
/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) .
* 0b0..FRO 32 KHz.
* 0b1..XTAL 32KHz.
*/
-#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK)
-#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU)
-#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U)
+#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK)
+
+#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU)
+#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U)
/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV.
*/
-#define PMC_RTCOSC32K_CLK1KHZDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK)
-#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U)
-#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U)
+#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK)
+
+#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U)
+#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U)
/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag.
*/
-#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK)
-#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U)
-#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U)
+#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK)
+
+#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U)
+#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U)
/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV.
*/
-#define PMC_RTCOSC32K_CLK1HZDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK)
-#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U)
-#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U)
+#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK)
+
+#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U)
+#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U)
/*! CLK1HZDIVHALT - Halts the divider counter.
*/
-#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK)
-#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U)
-#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U)
+#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK)
+
+#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U)
+#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U)
/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag.
*/
-#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK)
+#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK)
/*! @} */
/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */
/*! @{ */
-#define PMC_OSTIMER_SOFTRESET_MASK (0x1U)
-#define PMC_OSTIMER_SOFTRESET_SHIFT (0U)
+
+#define PMC_OSTIMER_SOFTRESET_MASK (0x1U)
+#define PMC_OSTIMER_SOFTRESET_SHIFT (0U)
/*! SOFTRESET - Active high reset.
*/
-#define PMC_OSTIMER_SOFTRESET(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK)
-#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U)
-#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U)
+#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK)
+
+#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U)
+#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U)
/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock.
*/
-#define PMC_OSTIMER_CLOCKENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK)
-#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U)
-#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U)
+#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK)
+
+#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U)
+#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U)
/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode).
*/
-#define PMC_OSTIMER_DPDWAKEUPENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK)
-#define PMC_OSTIMER_OSC32KPD_MASK (0x8U)
-#define PMC_OSTIMER_OSC32KPD_SHIFT (3U)
+#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK)
+
+#define PMC_OSTIMER_OSC32KPD_MASK (0x8U)
+#define PMC_OSTIMER_OSC32KPD_SHIFT (3U)
/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K.
*/
-#define PMC_OSTIMER_OSC32KPD(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK)
+#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK)
/*! @} */
-/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset,
- * Deep Power Down Reset, Software Reset] */
+/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */
-#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U)
-#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U)
+
+#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U)
+#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U)
/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD).
* 0b0..BOD VBAT is powered.
* 0b1..BOD VBAT is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK)
-#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U)
-#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U)
+#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U)
+#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U)
/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz.
* 0b0..FRO32KHz is powered.
* 0b1..FRO32KHz is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_FRO32K(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)
-#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U)
-#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U)
+#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U)
+#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U)
/*! PDEN_XTAL32K - Controls power to crystal 32 KHz.
* 0b0..Crystal 32KHz is powered.
* 0b1..Crystal 32KHz is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)
-#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U)
-#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U)
+#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U)
+#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U)
/*! PDEN_XTAL32M - Controls power to crystal 32 MHz.
* 0b0..Crystal 32MHz is powered.
* 0b1..Crystal 32MHz is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK)
-#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U)
-#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U)
+#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U)
+#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U)
/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0).
* 0b0..PLL0 is powered.
* 0b1..PLL0 is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_PLL0(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK)
-#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U)
-#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U)
+#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U)
+#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U)
/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1).
* 0b0..PLL1 is powered.
* 0b1..PLL1 is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_PLL1(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK)
-#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U)
-#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U)
+#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U)
+#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U)
/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy.
* 0b0..USB Full Speed phy is powered.
* 0b1..USB Full Speed phy is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK)
-#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U)
-#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U)
+#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U)
+#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U)
/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy.
* 0b0..USB HS phy is powered.
* 0b1..USB HS phy is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK)
-#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U)
-#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U)
+#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U)
+#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U)
/*! PDEN_COMP - Controls power to Analog Comparator.
* 0b0..Analog Comparator is powered.
* 0b1..Analog Comparator is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_COMP(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK)
-#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U)
-#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U)
+#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U)
+#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U)
/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO.
* 0b0..USB high speed LDO is powered.
* 0b1..USB high speed LDO is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK)
-#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U)
-#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U)
+#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U)
+#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U)
/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS)
* 0b0..auxiliary biasing is powered.
* 0b1..auxiliary biasing is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK)
-#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U)
-#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U)
+#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U)
+#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U)
/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO.
* 0b0..crystal 32 MHz LDO is powered.
* 0b1..crystal 32 MHz LDO is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK)
-#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U)
-#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U)
+#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U)
+#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U)
/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources.
* 0b0..TRNG clocks are powered.
* 0b1..TRNG clocks are powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_RNG(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK)
-#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U)
-#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U)
+#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK)
+
+#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U)
+#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U)
/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module.
* 0b0..PLL0 Sread spectrum module is powered.
* 0b1..PLL0 Sread spectrum module is powered down.
*/
-#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK)
+#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK)
/*! @} */
-/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors
- * Reset, Deep Power Down Reset, Software Reset] */
+/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */
-#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU)
-#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U)
-/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they
- * are implemented.
+
+#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU)
+#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U)
+/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
*/
-#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK)
+#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK)
/*! @} */
-/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors
- * Reset, Deep Power Down Reset, Software Reset] */
+/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */
/*! @{ */
-#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU)
-#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U)
-/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they
- * are implemented.
+
+#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU)
+#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U)
+/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented.
*/
-#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) \
- (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK)
+#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group PMC_Register_Masks */
+
/* PMC - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral PMC base address */
-#define PMC_BASE (0x50020000u)
-/** Peripheral PMC base address */
-#define PMC_BASE_NS (0x40020000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-/** Peripheral PMC base pointer */
-#define PMC_NS ((PMC_Type *)PMC_BASE_NS)
-/** Array initializer of PMC peripheral base addresses */
-#define PMC_BASE_ADDRS \
- { \
- PMC_BASE \
- }
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASE_PTRS \
- { \
- PMC \
- }
-/** Array initializer of PMC peripheral base addresses */
-#define PMC_BASE_ADDRS_NS \
- { \
- PMC_BASE_NS \
- }
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASE_PTRS_NS \
- { \
- PMC_NS \
- }
+ /** Peripheral PMC base address */
+ #define PMC_BASE (0x50020000u)
+ /** Peripheral PMC base address */
+ #define PMC_BASE_NS (0x40020000u)
+ /** Peripheral PMC base pointer */
+ #define PMC ((PMC_Type *)PMC_BASE)
+ /** Peripheral PMC base pointer */
+ #define PMC_NS ((PMC_Type *)PMC_BASE_NS)
+ /** Array initializer of PMC peripheral base addresses */
+ #define PMC_BASE_ADDRS { PMC_BASE }
+ /** Array initializer of PMC peripheral base pointers */
+ #define PMC_BASE_PTRS { PMC }
+ /** Array initializer of PMC peripheral base addresses */
+ #define PMC_BASE_ADDRS_NS { PMC_BASE_NS }
+ /** Array initializer of PMC peripheral base pointers */
+ #define PMC_BASE_PTRS_NS { PMC_NS }
#else
-/** Peripheral PMC base address */
-#define PMC_BASE (0x40020000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-/** Array initializer of PMC peripheral base addresses */
-#define PMC_BASE_ADDRS \
- { \
- PMC_BASE \
- }
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASE_PTRS \
- { \
- PMC \
- }
+ /** Peripheral PMC base address */
+ #define PMC_BASE (0x40020000u)
+ /** Peripheral PMC base pointer */
+ #define PMC ((PMC_Type *)PMC_BASE)
+ /** Array initializer of PMC peripheral base addresses */
+ #define PMC_BASE_ADDRS { PMC_BASE }
+ /** Array initializer of PMC peripheral base pointers */
+ #define PMC_BASE_PTRS { PMC }
#endif
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- POWERQUAD Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -15761,33 +14959,32 @@ typedef struct
*/
/** POWERQUAD - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */
- __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */
- __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */
- __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */
- __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */
- __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */
- __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */
- __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */
- uint8_t RESERVED_0[224];
- __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */
- __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */
- __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */
- __IO uint32_t MISC; /**< Misc register, offset: 0x10C */
- __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */
- uint8_t RESERVED_1[108];
- __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */
- __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */
- __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */
- __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */
- __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */
- __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */
- __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */
- uint8_t RESERVED_2[100];
- __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */
- __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */
+typedef struct {
+ __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */
+ __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */
+ __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */
+ __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */
+ __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */
+ __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */
+ __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */
+ __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */
+ uint8_t RESERVED_0[224];
+ __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */
+ __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */
+ __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */
+ __IO uint32_t MISC; /**< Misc register, offset: 0x10C */
+ __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */
+ uint8_t RESERVED_1[108];
+ __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */
+ __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */
+ __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */
+ __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */
+ __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */
+ __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */
+ __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */
+ uint8_t RESERVED_2[100];
+ __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */
+ __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */
} POWERQUAD_Type;
/* ----------------------------------------------------------------------------
@@ -15801,451 +14998,434 @@ typedef struct
/*! @name OUTBASE - Base address register for output region */
/*! @{ */
-#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU)
-#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U)
+
+#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U)
/*! outbase - Base address register for the output region
*/
-#define POWERQUAD_OUTBASE_OUTBASE(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
+#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
/*! @} */
/*! @name OUTFORMAT - Output format */
/*! @{ */
-#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U)
-#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U)
+
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U)
/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
-#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U)
-#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
+
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U)
/*! out_formatext - Output External format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
-#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U)
-#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U)
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
+
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U)
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U)
/*! out_scaler - Output Scaler value (for scaled 'q31' formats)
*/
-#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
+#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
/*! @} */
/*! @name TMPBASE - Base address register for temp region */
/*! @{ */
-#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU)
-#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U)
+
+#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U)
/*! tmpbase - Base address register for the temporary region
*/
-#define POWERQUAD_TMPBASE_TMPBASE(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
+#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
/*! @} */
/*! @name TMPFORMAT - Temp format */
/*! @{ */
-#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U)
-#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U)
+
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U)
/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
-#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U)
-#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
+
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U)
/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
-#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U)
-#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U)
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
+
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U)
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U)
/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats)
*/
-#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
+#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
/*! @} */
/*! @name INABASE - Base address register for input A region */
/*! @{ */
-#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU)
-#define POWERQUAD_INABASE_INABASE_SHIFT (0U)
+
+#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_INABASE_INABASE_SHIFT (0U)
/*! inabase - Base address register for the input A region
*/
-#define POWERQUAD_INABASE_INABASE(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
+#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
/*! @} */
/*! @name INAFORMAT - Input A format */
/*! @{ */
-#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U)
-#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U)
+
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U)
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U)
/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
-#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U)
-#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U)
+#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
+
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U)
/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
-#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U)
-#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U)
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
+
+#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U)
+#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U)
/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats)
*/
-#define POWERQUAD_INAFORMAT_INA_SCALER(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
+#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
/*! @} */
/*! @name INBBASE - Base address register for input B region */
/*! @{ */
-#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU)
-#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U)
+
+#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU)
+#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U)
/*! inbbase - Base address register for the input B region
*/
-#define POWERQUAD_INBBASE_INBBASE(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
+#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
/*! @} */
/*! @name INBFORMAT - Input B format */
/*! @{ */
-#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U)
-#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U)
+
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U)
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U)
/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
-#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U)
-#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U)
+#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
+
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U)
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U)
/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float)
*/
-#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
-#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U)
-#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U)
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
+
+#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U)
+#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U)
/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats)
*/
-#define POWERQUAD_INBFORMAT_INB_SCALER(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
+#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
/*! @} */
/*! @name CONTROL - PowerQuad Control register */
/*! @{ */
-#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU)
-#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U)
+
+#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU)
+#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U)
/*! decode_opcode - opcode specific to decode_machine
*/
-#define POWERQUAD_CONTROL_DECODE_OPCODE(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
-#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U)
-#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U)
+#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
+
+#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U)
+#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U)
/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA
*/
-#define POWERQUAD_CONTROL_DECODE_MACHINE(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
-#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U)
-#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U)
+#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
+
+#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U)
+#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U)
/*! inst_busy - Instruction busy signal when high indicates processing is on
*/
-#define POWERQUAD_CONTROL_INST_BUSY(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
+#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
/*! @} */
/*! @name LENGTH - Length register */
/*! @{ */
-#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU)
-#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U)
+
+#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU)
+#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U)
/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength =
* inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b =
* inst_length[20:16]
*/
-#define POWERQUAD_LENGTH_INST_LENGTH(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
+#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
/*! @} */
/*! @name CPPRE - Pre-scale register */
/*! @{ */
-#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU)
-#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U)
+
+#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU)
+#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U)
/*! cppre_in - co-processor scaling of input
*/
-#define POWERQUAD_CPPRE_CPPRE_IN(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
-#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U)
-#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U)
+#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
+
+#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U)
+#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U)
/*! cppre_out - co-processor fixed point output
*/
-#define POWERQUAD_CPPRE_CPPRE_OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
-#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U)
-#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U)
+#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
+
+#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U)
+#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U)
/*! cppre_sat - 1 : forces sub-32 bit saturation
*/
-#define POWERQUAD_CPPRE_CPPRE_SAT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
-#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U)
-#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U)
+#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
+
+#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U)
+#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U)
/*! cppre_sat8 - 0 = 8bits, 1 = 16bits
*/
-#define POWERQUAD_CPPRE_CPPRE_SAT8(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
+#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
/*! @} */
/*! @name MISC - Misc register */
/*! @{ */
-#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU)
-#define POWERQUAD_MISC_INST_MISC_SHIFT (0U)
+
+#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU)
+#define POWERQUAD_MISC_INST_MISC_SHIFT (0U)
/*! inst_misc - Misc register. For Matrix : Used for scale factor
*/
-#define POWERQUAD_MISC_INST_MISC(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
+#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
/*! @} */
/*! @name CURSORY - Cursory register */
/*! @{ */
-#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U)
-#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U)
+
+#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U)
+#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U)
/*! cursory - 1 : Enable cursory mode
*/
-#define POWERQUAD_CURSORY_CURSORY(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
+#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
/*! @} */
/*! @name CORDIC_X - Cordic input X register */
/*! @{ */
-#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU)
-#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U)
+
+#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U)
/*! cordic_x - Cordic input x
*/
-#define POWERQUAD_CORDIC_X_CORDIC_X(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
+#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
/*! @} */
/*! @name CORDIC_Y - Cordic input Y register */
/*! @{ */
-#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU)
-#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U)
+
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U)
/*! cordic_y - Cordic input y
*/
-#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
+#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
/*! @} */
/*! @name CORDIC_Z - Cordic input Z register */
/*! @{ */
-#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU)
-#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U)
+
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU)
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U)
/*! cordic_z - Cordic input z
*/
-#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
+#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
/*! @} */
/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */
/*! @{ */
-#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U)
-#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U)
+
+#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U)
+#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U)
/*! OVERFLOW - overflow
*/
-#define POWERQUAD_ERRSTAT_OVERFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
-#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U)
-#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U)
+#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
+
+#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U)
+#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U)
/*! NAN - nan
*/
-#define POWERQUAD_ERRSTAT_NAN(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
-#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U)
-#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U)
+#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
+
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U)
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U)
/*! FIXEDOVERFLOW - fixed_pt_overflow
*/
-#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
-#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U)
-#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U)
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
+
+#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U)
+#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U)
/*! UNDERFLOW - underflow
*/
-#define POWERQUAD_ERRSTAT_UNDERFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
-#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U)
-#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U)
+#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
+
+#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U)
+#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U)
/*! BUSERROR - bus_error
*/
-#define POWERQUAD_ERRSTAT_BUSERROR(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
+#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
/*! @} */
/*! @name INTREN - INTERRUPT enable register */
/*! @{ */
-#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U)
-#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U)
+
+#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U)
+#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U)
/*! intr_oflow - 1 : Enable interrupt on Floating point overflow
*/
-#define POWERQUAD_INTREN_INTR_OFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
-#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U)
-#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U)
+#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
+
+#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U)
+#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U)
/*! intr_nan - 1 : Enable interrupt on Floating point NaN
*/
-#define POWERQUAD_INTREN_INTR_NAN(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
-#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U)
-#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U)
+#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
+
+#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U)
+#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U)
/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow
*/
-#define POWERQUAD_INTREN_INTR_FIXED(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
-#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U)
-#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U)
+#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
+
+#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U)
+#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U)
/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation
*/
-#define POWERQUAD_INTREN_INTR_UFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
-#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U)
-#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U)
+#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
+
+#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U)
+#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U)
/*! intr_berr - 1: Enable interrupt on AHBM Buss Error
*/
-#define POWERQUAD_INTREN_INTR_BERR(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
-#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U)
-#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U)
+#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
+
+#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U)
+#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U)
/*! intr_comp - 1: Enable interrupt on instruction completion
*/
-#define POWERQUAD_INTREN_INTR_COMP(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
+#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
/*! @} */
/*! @name EVENTEN - Event Enable register */
/*! @{ */
-#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U)
-#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U)
+
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U)
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U)
/*! event_oflow - 1 : Enable event trigger on Floating point overflow
*/
-#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
-#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U)
-#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U)
+#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U)
+#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U)
/*! event_nan - 1 : Enable event trigger on Floating point NaN
*/
-#define POWERQUAD_EVENTEN_EVENT_NAN(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
-#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U)
-#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U)
+#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U)
+#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U)
/*! event_fixed - 1: Enable event trigger on Fixed point Overflow
*/
-#define POWERQUAD_EVENTEN_EVENT_FIXED(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
-#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U)
-#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U)
+#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U)
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U)
/*! event_uflow - 1 : Enable event trigger on Subnormal truncation
*/
-#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
-#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U)
-#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U)
+#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U)
+#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U)
/*! event_berr - 1: Enable event trigger on AHBM Buss Error
*/
-#define POWERQUAD_EVENTEN_EVENT_BERR(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
-#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U)
-#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U)
+#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
+
+#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U)
+#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U)
/*! event_comp - 1: Enable event trigger on instruction completion
*/
-#define POWERQUAD_EVENTEN_EVENT_COMP(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
+#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
/*! @} */
/*! @name INTRSTAT - INTERRUPT STATUS register */
/*! @{ */
-#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U)
-#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U)
-/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will
- * clear this bit
+
+#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U)
+#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U)
+/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit
*/
-#define POWERQUAD_INTRSTAT_INTR_STAT(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
+#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
/*! @} */
/*! @name GPREG - General purpose register bank N. */
/*! @{ */
-#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU)
-#define POWERQUAD_GPREG_GPREG_SHIFT (0U)
+
+#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU)
+#define POWERQUAD_GPREG_GPREG_SHIFT (0U)
/*! gpreg - General purpose register bank
*/
-#define POWERQUAD_GPREG_GPREG(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
+#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
/*! @} */
/* The count of POWERQUAD_GPREG */
-#define POWERQUAD_GPREG_COUNT (16U)
+#define POWERQUAD_GPREG_COUNT (16U)
/*! @name COMPREGS_COMPREG - Compute register bank */
/*! @{ */
-#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU)
+
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU)
#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
/*! compreg - Compute register bank
*/
-#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) \
- (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & \
- POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
/*! @} */
/* The count of POWERQUAD_COMPREGS_COMPREG */
-#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U)
+#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U)
+
/*!
* @}
*/ /* end of group POWERQUAD_Register_Masks */
+
/* POWERQUAD - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral POWERQUAD base address */
-#define POWERQUAD_BASE (0x500A6000u)
-/** Peripheral POWERQUAD base address */
-#define POWERQUAD_BASE_NS (0x400A6000u)
-/** Peripheral POWERQUAD base pointer */
-#define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)
-/** Peripheral POWERQUAD base pointer */
-#define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
-/** Array initializer of POWERQUAD peripheral base addresses */
-#define POWERQUAD_BASE_ADDRS \
- { \
- POWERQUAD_BASE \
- }
-/** Array initializer of POWERQUAD peripheral base pointers */
-#define POWERQUAD_BASE_PTRS \
- { \
- POWERQUAD \
- }
-/** Array initializer of POWERQUAD peripheral base addresses */
-#define POWERQUAD_BASE_ADDRS_NS \
- { \
- POWERQUAD_BASE_NS \
- }
-/** Array initializer of POWERQUAD peripheral base pointers */
-#define POWERQUAD_BASE_PTRS_NS \
- { \
- POWERQUAD_NS \
- }
+ /** Peripheral POWERQUAD base address */
+ #define POWERQUAD_BASE (0x500A6000u)
+ /** Peripheral POWERQUAD base address */
+ #define POWERQUAD_BASE_NS (0x400A6000u)
+ /** Peripheral POWERQUAD base pointer */
+ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)
+ /** Peripheral POWERQUAD base pointer */
+ #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS)
+ /** Array initializer of POWERQUAD peripheral base addresses */
+ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE }
+ /** Array initializer of POWERQUAD peripheral base pointers */
+ #define POWERQUAD_BASE_PTRS { POWERQUAD }
+ /** Array initializer of POWERQUAD peripheral base addresses */
+ #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS }
+ /** Array initializer of POWERQUAD peripheral base pointers */
+ #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS }
#else
-/** Peripheral POWERQUAD base address */
-#define POWERQUAD_BASE (0x400A6000u)
-/** Peripheral POWERQUAD base pointer */
-#define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)
-/** Array initializer of POWERQUAD peripheral base addresses */
-#define POWERQUAD_BASE_ADDRS \
- { \
- POWERQUAD_BASE \
- }
-/** Array initializer of POWERQUAD peripheral base pointers */
-#define POWERQUAD_BASE_PTRS \
- { \
- POWERQUAD \
- }
+ /** Peripheral POWERQUAD base address */
+ #define POWERQUAD_BASE (0x400A6000u)
+ /** Peripheral POWERQUAD base pointer */
+ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)
+ /** Array initializer of POWERQUAD peripheral base addresses */
+ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE }
+ /** Array initializer of POWERQUAD peripheral base pointers */
+ #define POWERQUAD_BASE_PTRS { POWERQUAD }
#endif
/*!
* @}
*/ /* end of group POWERQUAD_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- PRINCE Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -16256,24 +15436,23 @@ typedef struct
*/
/** PRINCE - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */
- __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */
- __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */
- __IO uint32_t LOCK; /**< Lock register, offset: 0xC */
- __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */
- __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */
- __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */
- __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */
- __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */
- __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */
- __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */
- __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */
- __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */
- __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */
- __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */
- __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */
+typedef struct {
+ __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */
+ __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */
+ __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */
+ __IO uint32_t LOCK; /**< Lock register, offset: 0xC */
+ __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */
+ __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */
+ __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */
+ __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */
+ __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */
+ __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */
+ __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */
+ __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */
+ __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */
+ __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */
+ __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */
+ __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */
} PRINCE_Type;
/* ----------------------------------------------------------------------------
@@ -16287,265 +15466,250 @@ typedef struct
/*! @name ENC_ENABLE - Encryption Enable register */
/*! @{ */
-#define PRINCE_ENC_ENABLE_EN_MASK (0x1U)
-#define PRINCE_ENC_ENABLE_EN_SHIFT (0U)
+
+#define PRINCE_ENC_ENABLE_EN_MASK (0x1U)
+#define PRINCE_ENC_ENABLE_EN_SHIFT (0U)
/*! EN - Encryption Enable.
* 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.
* 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.
*/
-#define PRINCE_ENC_ENABLE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK)
+#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK)
/*! @} */
/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */
/*! @{ */
-#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U)
+
+#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U)
/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask.
*/
-#define PRINCE_MASK_LSB_MASKVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK)
+#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK)
/*! @} */
/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */
/*! @{ */
-#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U)
+
+#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U)
/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask.
*/
-#define PRINCE_MASK_MSB_MASKVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK)
+#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK)
/*! @} */
/*! @name LOCK - Lock register */
/*! @{ */
-#define PRINCE_LOCK_LOCKREG0_MASK (0x1U)
-#define PRINCE_LOCK_LOCKREG0_SHIFT (0U)
+
+#define PRINCE_LOCK_LOCKREG0_MASK (0x1U)
+#define PRINCE_LOCK_LOCKREG0_SHIFT (0U)
/*! LOCKREG0 - Lock Region 0 registers.
* 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable..
* 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable..
*/
-#define PRINCE_LOCK_LOCKREG0(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK)
-#define PRINCE_LOCK_LOCKREG1_MASK (0x2U)
-#define PRINCE_LOCK_LOCKREG1_SHIFT (1U)
+#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK)
+
+#define PRINCE_LOCK_LOCKREG1_MASK (0x2U)
+#define PRINCE_LOCK_LOCKREG1_SHIFT (1U)
/*! LOCKREG1 - Lock Region 1 registers.
* 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable..
* 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable..
*/
-#define PRINCE_LOCK_LOCKREG1(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK)
-#define PRINCE_LOCK_LOCKREG2_MASK (0x4U)
-#define PRINCE_LOCK_LOCKREG2_SHIFT (2U)
+#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK)
+
+#define PRINCE_LOCK_LOCKREG2_MASK (0x4U)
+#define PRINCE_LOCK_LOCKREG2_SHIFT (2U)
/*! LOCKREG2 - Lock Region 2 registers.
* 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable..
* 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable..
*/
-#define PRINCE_LOCK_LOCKREG2(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK)
-#define PRINCE_LOCK_LOCKMASK_MASK (0x100U)
-#define PRINCE_LOCK_LOCKMASK_SHIFT (8U)
+#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK)
+
+#define PRINCE_LOCK_LOCKMASK_MASK (0x100U)
+#define PRINCE_LOCK_LOCKMASK_SHIFT (8U)
/*! LOCKMASK - Lock the Mask registers.
* 0b0..Disabled. MASK_LSB, and MASK_MSB are writable..
* 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable..
*/
-#define PRINCE_LOCK_LOCKMASK(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK)
+#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK)
/*! @} */
/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */
/*! @{ */
-#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U)
+
+#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U)
/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
*/
-#define PRINCE_IV_LSB0_IVVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK)
+#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK)
/*! @} */
/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */
/*! @{ */
-#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U)
+
+#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U)
/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
*/
-#define PRINCE_IV_MSB0_IVVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK)
+#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK)
/*! @} */
/*! @name BASE_ADDR0 - Base Address for region 0 register */
/*! @{ */
-#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU)
-#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U)
+
+#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU)
+#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U)
/*! ADDR_FIXED - Fixed portion of the base address of region 0.
*/
-#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK)
-#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U)
-#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U)
+#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK)
+
+#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U)
+#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U)
/*! ADDR_PRG - Programmable portion of the base address of region 0.
*/
-#define PRINCE_BASE_ADDR0_ADDR_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK)
+#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK)
/*! @} */
/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */
/*! @{ */
-#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU)
-#define PRINCE_SR_ENABLE0_EN_SHIFT (0U)
+
+#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU)
+#define PRINCE_SR_ENABLE0_EN_SHIFT (0U)
/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0.
*/
-#define PRINCE_SR_ENABLE0_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK)
+#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK)
/*! @} */
/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */
/*! @{ */
-#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U)
+
+#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U)
/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
*/
-#define PRINCE_IV_LSB1_IVVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK)
+#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK)
/*! @} */
/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */
/*! @{ */
-#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U)
+
+#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U)
/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
*/
-#define PRINCE_IV_MSB1_IVVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK)
+#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK)
/*! @} */
/*! @name BASE_ADDR1 - Base Address for region 1 register */
/*! @{ */
-#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU)
-#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U)
+
+#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU)
+#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U)
/*! ADDR_FIXED - Fixed portion of the base address of region 1.
*/
-#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK)
-#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U)
-#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U)
+#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK)
+
+#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U)
+#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U)
/*! ADDR_PRG - Programmable portion of the base address of region 1.
*/
-#define PRINCE_BASE_ADDR1_ADDR_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK)
+#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK)
/*! @} */
/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */
/*! @{ */
-#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU)
-#define PRINCE_SR_ENABLE1_EN_SHIFT (0U)
+
+#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU)
+#define PRINCE_SR_ENABLE1_EN_SHIFT (0U)
/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1.
*/
-#define PRINCE_SR_ENABLE1_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK)
+#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK)
/*! @} */
/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */
/*! @{ */
-#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U)
+
+#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U)
/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.
*/
-#define PRINCE_IV_LSB2_IVVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK)
+#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK)
/*! @} */
/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */
/*! @{ */
-#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU)
-#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U)
+
+#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU)
+#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U)
/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.
*/
-#define PRINCE_IV_MSB2_IVVAL(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK)
+#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK)
/*! @} */
/*! @name BASE_ADDR2 - Base Address for region 2 register */
/*! @{ */
-#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU)
-#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U)
+
+#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU)
+#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U)
/*! ADDR_FIXED - Fixed portion of the base address of region 2.
*/
-#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK)
-#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U)
-#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U)
+#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK)
+
+#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U)
+#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U)
/*! ADDR_PRG - Programmable portion of the base address of region 2.
*/
-#define PRINCE_BASE_ADDR2_ADDR_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK)
+#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK)
/*! @} */
/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */
/*! @{ */
-#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU)
-#define PRINCE_SR_ENABLE2_EN_SHIFT (0U)
+
+#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU)
+#define PRINCE_SR_ENABLE2_EN_SHIFT (0U)
/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2.
*/
-#define PRINCE_SR_ENABLE2_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK)
+#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group PRINCE_Register_Masks */
+
/* PRINCE - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral PRINCE base address */
-#define PRINCE_BASE (0x50035000u)
-/** Peripheral PRINCE base address */
-#define PRINCE_BASE_NS (0x40035000u)
-/** Peripheral PRINCE base pointer */
-#define PRINCE ((PRINCE_Type *)PRINCE_BASE)
-/** Peripheral PRINCE base pointer */
-#define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS)
-/** Array initializer of PRINCE peripheral base addresses */
-#define PRINCE_BASE_ADDRS \
- { \
- PRINCE_BASE \
- }
-/** Array initializer of PRINCE peripheral base pointers */
-#define PRINCE_BASE_PTRS \
- { \
- PRINCE \
- }
-/** Array initializer of PRINCE peripheral base addresses */
-#define PRINCE_BASE_ADDRS_NS \
- { \
- PRINCE_BASE_NS \
- }
-/** Array initializer of PRINCE peripheral base pointers */
-#define PRINCE_BASE_PTRS_NS \
- { \
- PRINCE_NS \
- }
+ /** Peripheral PRINCE base address */
+ #define PRINCE_BASE (0x50035000u)
+ /** Peripheral PRINCE base address */
+ #define PRINCE_BASE_NS (0x40035000u)
+ /** Peripheral PRINCE base pointer */
+ #define PRINCE ((PRINCE_Type *)PRINCE_BASE)
+ /** Peripheral PRINCE base pointer */
+ #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS)
+ /** Array initializer of PRINCE peripheral base addresses */
+ #define PRINCE_BASE_ADDRS { PRINCE_BASE }
+ /** Array initializer of PRINCE peripheral base pointers */
+ #define PRINCE_BASE_PTRS { PRINCE }
+ /** Array initializer of PRINCE peripheral base addresses */
+ #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS }
+ /** Array initializer of PRINCE peripheral base pointers */
+ #define PRINCE_BASE_PTRS_NS { PRINCE_NS }
#else
-/** Peripheral PRINCE base address */
-#define PRINCE_BASE (0x40035000u)
-/** Peripheral PRINCE base pointer */
-#define PRINCE ((PRINCE_Type *)PRINCE_BASE)
-/** Array initializer of PRINCE peripheral base addresses */
-#define PRINCE_BASE_ADDRS \
- { \
- PRINCE_BASE \
- }
-/** Array initializer of PRINCE peripheral base pointers */
-#define PRINCE_BASE_PTRS \
- { \
- PRINCE \
- }
+ /** Peripheral PRINCE base address */
+ #define PRINCE_BASE (0x40035000u)
+ /** Peripheral PRINCE base pointer */
+ #define PRINCE ((PRINCE_Type *)PRINCE_BASE)
+ /** Array initializer of PRINCE peripheral base addresses */
+ #define PRINCE_BASE_ADDRS { PRINCE_BASE }
+ /** Array initializer of PRINCE peripheral base pointers */
+ #define PRINCE_BASE_PTRS { PRINCE }
#endif
/*!
* @}
*/ /* end of group PRINCE_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- PUF Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -16556,41 +15720,40 @@ typedef struct
*/
/** PUF - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */
- __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */
- __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */
- uint8_t RESERVED_0[20];
- __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */
- uint8_t RESERVED_1[4];
- __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */
- uint8_t RESERVED_2[20];
- __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */
- __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */
- __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */
- uint8_t RESERVED_3[20];
- __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */
- __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */
- uint8_t RESERVED_4[116];
- __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */
- uint8_t RESERVED_5[28];
- __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */
- __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */
- __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */
- __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */
- __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */
- uint8_t RESERVED_6[240];
- __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */
- __IO uint32_t KEYENABLE; /**< , offset: 0x204 */
- __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */
- __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */
- __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */
- __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */
- uint8_t RESERVED_7[48];
- __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */
- __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */
- __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */
+typedef struct {
+ __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */
+ __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */
+ __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */
+ uint8_t RESERVED_2[20];
+ __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */
+ __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */
+ __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */
+ uint8_t RESERVED_3[20];
+ __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */
+ __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */
+ uint8_t RESERVED_4[116];
+ __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */
+ uint8_t RESERVED_5[28];
+ __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */
+ __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */
+ __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */
+ __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */
+ __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */
+ uint8_t RESERVED_6[240];
+ __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */
+ __IO uint32_t KEYENABLE; /**< , offset: 0x204 */
+ __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */
+ __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */
+ __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */
+ __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */
+ uint8_t RESERVED_7[48];
+ __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */
+ __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */
+ __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */
} PUF_Type;
/* ----------------------------------------------------------------------------
@@ -16604,695 +15767,721 @@ typedef struct
/*! @name CTRL - PUF Control register */
/*! @{ */
-#define PUF_CTRL_ZEROIZE_MASK (0x1U)
-#define PUF_CTRL_ZEROIZE_SHIFT (0U)
+
+#define PUF_CTRL_ZEROIZE_MASK (0x1U)
+#define PUF_CTRL_ZEROIZE_SHIFT (0U)
/*! zeroize - Begin Zeroize operation for PUF and go to Error state
*/
-#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
-#define PUF_CTRL_ENROLL_MASK (0x2U)
-#define PUF_CTRL_ENROLL_SHIFT (1U)
+#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
+
+#define PUF_CTRL_ENROLL_MASK (0x2U)
+#define PUF_CTRL_ENROLL_SHIFT (1U)
/*! enroll - Begin Enroll operation
*/
-#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
-#define PUF_CTRL_START_MASK (0x4U)
-#define PUF_CTRL_START_SHIFT (2U)
+#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
+
+#define PUF_CTRL_START_MASK (0x4U)
+#define PUF_CTRL_START_SHIFT (2U)
/*! start - Begin Start operation
*/
-#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
-#define PUF_CTRL_GENERATEKEY_MASK (0x8U)
-#define PUF_CTRL_GENERATEKEY_SHIFT (3U)
+#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
+
+#define PUF_CTRL_GENERATEKEY_MASK (0x8U)
+#define PUF_CTRL_GENERATEKEY_SHIFT (3U)
/*! GENERATEKEY - Begin Set Intrinsic Key operation
*/
-#define PUF_CTRL_GENERATEKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
-#define PUF_CTRL_SETKEY_MASK (0x10U)
-#define PUF_CTRL_SETKEY_SHIFT (4U)
+#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
+
+#define PUF_CTRL_SETKEY_MASK (0x10U)
+#define PUF_CTRL_SETKEY_SHIFT (4U)
/*! SETKEY - Begin Set User Key operation
*/
-#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
-#define PUF_CTRL_GETKEY_MASK (0x40U)
-#define PUF_CTRL_GETKEY_SHIFT (6U)
+#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
+
+#define PUF_CTRL_GETKEY_MASK (0x40U)
+#define PUF_CTRL_GETKEY_SHIFT (6U)
/*! GETKEY - Begin Get Key operation
*/
-#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
+#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
/*! @} */
/*! @name KEYINDEX - PUF Key Index register */
/*! @{ */
-#define PUF_KEYINDEX_KEYIDX_MASK (0xFU)
-#define PUF_KEYINDEX_KEYIDX_SHIFT (0U)
+
+#define PUF_KEYINDEX_KEYIDX_MASK (0xFU)
+#define PUF_KEYINDEX_KEYIDX_SHIFT (0U)
/*! KEYIDX - Key index for Set Key operations
*/
-#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
+#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
/*! @} */
/*! @name KEYSIZE - PUF Key Size register */
/*! @{ */
-#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU)
-#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U)
+
+#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU)
+#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U)
/*! KEYSIZE - Key size for Set Key operations
*/
-#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
+#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
/*! @} */
/*! @name STAT - PUF Status register */
/*! @{ */
-#define PUF_STAT_BUSY_MASK (0x1U)
-#define PUF_STAT_BUSY_SHIFT (0U)
+
+#define PUF_STAT_BUSY_MASK (0x1U)
+#define PUF_STAT_BUSY_SHIFT (0U)
/*! busy - Indicates that operation is in progress
*/
-#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
-#define PUF_STAT_SUCCESS_MASK (0x2U)
-#define PUF_STAT_SUCCESS_SHIFT (1U)
+#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
+
+#define PUF_STAT_SUCCESS_MASK (0x2U)
+#define PUF_STAT_SUCCESS_SHIFT (1U)
/*! SUCCESS - Last operation was successful
*/
-#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
-#define PUF_STAT_ERROR_MASK (0x4U)
-#define PUF_STAT_ERROR_SHIFT (2U)
+#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
+
+#define PUF_STAT_ERROR_MASK (0x4U)
+#define PUF_STAT_ERROR_SHIFT (2U)
/*! error - PUF is in the Error state and no operations can be performed
*/
-#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
-#define PUF_STAT_KEYINREQ_MASK (0x10U)
-#define PUF_STAT_KEYINREQ_SHIFT (4U)
+#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
+
+#define PUF_STAT_KEYINREQ_MASK (0x10U)
+#define PUF_STAT_KEYINREQ_SHIFT (4U)
/*! KEYINREQ - Request for next part of key
*/
-#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
-#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U)
-#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U)
+#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
+
+#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U)
+#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U)
/*! KEYOUTAVAIL - Next part of key is available
*/
-#define PUF_STAT_KEYOUTAVAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
-#define PUF_STAT_CODEINREQ_MASK (0x40U)
-#define PUF_STAT_CODEINREQ_SHIFT (6U)
+#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
+
+#define PUF_STAT_CODEINREQ_MASK (0x40U)
+#define PUF_STAT_CODEINREQ_SHIFT (6U)
/*! CODEINREQ - Request for next part of AC/KC
*/
-#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
-#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U)
-#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U)
+#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
+
+#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U)
+#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U)
/*! CODEOUTAVAIL - Next part of AC/KC is available
*/
-#define PUF_STAT_CODEOUTAVAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
+#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
/*! @} */
/*! @name ALLOW - PUF Allow register */
/*! @{ */
-#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U)
-#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U)
+
+#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U)
+#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U)
/*! ALLOWENROLL - Enroll operation is allowed
*/
-#define PUF_ALLOW_ALLOWENROLL(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
-#define PUF_ALLOW_ALLOWSTART_MASK (0x2U)
-#define PUF_ALLOW_ALLOWSTART_SHIFT (1U)
+#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
+
+#define PUF_ALLOW_ALLOWSTART_MASK (0x2U)
+#define PUF_ALLOW_ALLOWSTART_SHIFT (1U)
/*! ALLOWSTART - Start operation is allowed
*/
-#define PUF_ALLOW_ALLOWSTART(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
-#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U)
-#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U)
+#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
+
+#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U)
+#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U)
/*! ALLOWSETKEY - Set Key operations are allowed
*/
-#define PUF_ALLOW_ALLOWSETKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
-#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U)
-#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U)
+#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
+
+#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U)
+#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U)
/*! ALLOWGETKEY - Get Key operation is allowed
*/
-#define PUF_ALLOW_ALLOWGETKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
+#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
/*! @} */
/*! @name KEYINPUT - PUF Key Input register */
/*! @{ */
-#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU)
-#define PUF_KEYINPUT_KEYIN_SHIFT (0U)
+
+#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU)
+#define PUF_KEYINPUT_KEYIN_SHIFT (0U)
/*! KEYIN - Key input data
*/
-#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
+#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
/*! @} */
/*! @name CODEINPUT - PUF Code Input register */
/*! @{ */
-#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU)
-#define PUF_CODEINPUT_CODEIN_SHIFT (0U)
+
+#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU)
+#define PUF_CODEINPUT_CODEIN_SHIFT (0U)
/*! CODEIN - AC/KC input data
*/
-#define PUF_CODEINPUT_CODEIN(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
+#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
/*! @} */
/*! @name CODEOUTPUT - PUF Code Output register */
/*! @{ */
-#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU)
-#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U)
+
+#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU)
+#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U)
/*! CODEOUT - AC/KC output data
*/
-#define PUF_CODEOUTPUT_CODEOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
+#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
/*! @} */
/*! @name KEYOUTINDEX - PUF Key Output Index register */
/*! @{ */
-#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU)
-#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U)
+
+#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU)
+#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U)
/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register
*/
-#define PUF_KEYOUTINDEX_KEYOUTIDX(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
+#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
/*! @} */
/*! @name KEYOUTPUT - PUF Key Output register */
/*! @{ */
-#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU)
-#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U)
+
+#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU)
+#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U)
/*! KEYOUT - Key output data
*/
-#define PUF_KEYOUTPUT_KEYOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
+#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
/*! @} */
/*! @name IFSTAT - PUF Interface Status and clear register */
/*! @{ */
-#define PUF_IFSTAT_ERROR_MASK (0x1U)
-#define PUF_IFSTAT_ERROR_SHIFT (0U)
+
+#define PUF_IFSTAT_ERROR_MASK (0x1U)
+#define PUF_IFSTAT_ERROR_SHIFT (0U)
/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit
*/
-#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
+#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
/*! @} */
/*! @name VERSION - PUF version register. */
/*! @{ */
-#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU)
-#define PUF_VERSION_VERSION_SHIFT (0U)
+
+#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU)
+#define PUF_VERSION_VERSION_SHIFT (0U)
/*! VERSION - Version of the PUF module.
*/
-#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
+#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
/*! @} */
/*! @name INTEN - PUF Interrupt Enable */
/*! @{ */
-#define PUF_INTEN_READYEN_MASK (0x1U)
-#define PUF_INTEN_READYEN_SHIFT (0U)
-/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status
- * Register)
- */
-#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
-#define PUF_INTEN_SUCCESEN_MASK (0x2U)
-#define PUF_INTEN_SUCCESEN_SHIFT (1U)
-/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status
- * Register)
- */
-#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK)
-#define PUF_INTEN_ERROREN_MASK (0x4U)
-#define PUF_INTEN_ERROREN_SHIFT (2U)
-/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status
- * Register)
- */
-#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
-#define PUF_INTEN_KEYINREQEN_MASK (0x10U)
-#define PUF_INTEN_KEYINREQEN_SHIFT (4U)
-/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status
- * Register)
- */
-#define PUF_INTEN_KEYINREQEN(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
-#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U)
-#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U)
-/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey
- * Status Register)
- */
-#define PUF_INTEN_KEYOUTAVAILEN(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
-#define PUF_INTEN_CODEINREQEN_MASK (0x40U)
-#define PUF_INTEN_CODEINREQEN_SHIFT (6U)
-/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status
- * Register)
- */
-#define PUF_INTEN_CODEINREQEN(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
-#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U)
-#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U)
-/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey
- * Status Register)
- */
-#define PUF_INTEN_CODEOUTAVAILEN(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
+
+#define PUF_INTEN_READYEN_MASK (0x1U)
+#define PUF_INTEN_READYEN_SHIFT (0U)
+/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
+
+#define PUF_INTEN_SUCCESEN_MASK (0x2U)
+#define PUF_INTEN_SUCCESEN_SHIFT (1U)
+/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK)
+
+#define PUF_INTEN_ERROREN_MASK (0x4U)
+#define PUF_INTEN_ERROREN_SHIFT (2U)
+/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
+
+#define PUF_INTEN_KEYINREQEN_MASK (0x10U)
+#define PUF_INTEN_KEYINREQEN_SHIFT (4U)
+/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
+
+#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U)
+#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U)
+/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
+
+#define PUF_INTEN_CODEINREQEN_MASK (0x40U)
+#define PUF_INTEN_CODEINREQEN_SHIFT (6U)
+/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
+
+#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U)
+#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U)
+/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register)
+ */
+#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
/*! @} */
/*! @name INTSTAT - PUF interrupt status */
/*! @{ */
-#define PUF_INTSTAT_READY_MASK (0x1U)
-#define PUF_INTSTAT_READY_SHIFT (0U)
+
+#define PUF_INTSTAT_READY_MASK (0x1U)
+#define PUF_INTSTAT_READY_SHIFT (0U)
/*! READY - Triggers on falling edge of busy, write 1 to clear
*/
-#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
-#define PUF_INTSTAT_SUCCESS_MASK (0x2U)
-#define PUF_INTSTAT_SUCCESS_SHIFT (1U)
+#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
+
+#define PUF_INTSTAT_SUCCESS_MASK (0x2U)
+#define PUF_INTSTAT_SUCCESS_SHIFT (1U)
/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears
*/
-#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
-#define PUF_INTSTAT_ERROR_MASK (0x4U)
-#define PUF_INTSTAT_ERROR_SHIFT (2U)
+#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
+
+#define PUF_INTSTAT_ERROR_MASK (0x4U)
+#define PUF_INTSTAT_ERROR_SHIFT (2U)
/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears
*/
-#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
-#define PUF_INTSTAT_KEYINREQ_MASK (0x10U)
-#define PUF_INTSTAT_KEYINREQ_SHIFT (4U)
+#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
+
+#define PUF_INTSTAT_KEYINREQ_MASK (0x10U)
+#define PUF_INTSTAT_KEYINREQ_SHIFT (4U)
/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears
*/
-#define PUF_INTSTAT_KEYINREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
-#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U)
-#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U)
+#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
+
+#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U)
+#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U)
/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears
*/
-#define PUF_INTSTAT_KEYOUTAVAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
-#define PUF_INTSTAT_CODEINREQ_MASK (0x40U)
-#define PUF_INTSTAT_CODEINREQ_SHIFT (6U)
+#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
+
+#define PUF_INTSTAT_CODEINREQ_MASK (0x40U)
+#define PUF_INTSTAT_CODEINREQ_SHIFT (6U)
/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears
*/
-#define PUF_INTSTAT_CODEINREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
-#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U)
-#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U)
+#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
+
+#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U)
+#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U)
/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears
*/
-#define PUF_INTSTAT_CODEOUTAVAIL(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
+#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
/*! @} */
/*! @name PWRCTRL - PUF RAM Power Control */
/*! @{ */
-#define PUF_PWRCTRL_RAMON_MASK (0x1U)
-#define PUF_PWRCTRL_RAMON_SHIFT (0U)
+
+#define PUF_PWRCTRL_RAMON_MASK (0x1U)
+#define PUF_PWRCTRL_RAMON_SHIFT (0U)
/*! RAMON - Power on the PUF RAM.
*/
-#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK)
-#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U)
-#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U)
+#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK)
+
+#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U)
+#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U)
/*! RAMSTAT - PUF RAM status.
*/
-#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK)
+#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK)
/*! @} */
/*! @name CFG - PUF config register for block bits */
/*! @{ */
-#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U)
-#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U)
+
+#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U)
+#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U)
/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset.
*/
-#define PUF_CFG_BLOCKENROLL_SETKEY(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK)
-#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U)
-#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U)
+#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK)
+
+#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U)
+#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U)
/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset.
*/
-#define PUF_CFG_BLOCKKEYOUTPUT(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK)
+#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK)
/*! @} */
/*! @name KEYLOCK - Only reset in case of full IC reset */
/*! @{ */
-#define PUF_KEYLOCK_KEY0_MASK (0x3U)
-#define PUF_KEYLOCK_KEY0_SHIFT (0U)
+
+#define PUF_KEYLOCK_KEY0_MASK (0x3U)
+#define PUF_KEYLOCK_KEY0_SHIFT (0U)
/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01,
* 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once
* this field is written with a value different from '10', its value can no longer be modified
* until un Power On Reset occurs."
*/
-#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK)
-#define PUF_KEYLOCK_KEY1_MASK (0xCU)
-#define PUF_KEYLOCK_KEY1_SHIFT (2U)
+#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK)
+
+#define PUF_KEYLOCK_KEY1_MASK (0xCU)
+#define PUF_KEYLOCK_KEY1_SHIFT (2U)
/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01,
* 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once
* this field is written with a value different from '10', its value can no longer be modified
* until un Power On Reset occurs."
*/
-#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK)
-#define PUF_KEYLOCK_KEY2_MASK (0x30U)
-#define PUF_KEYLOCK_KEY2_SHIFT (4U)
+#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK)
+
+#define PUF_KEYLOCK_KEY2_MASK (0x30U)
+#define PUF_KEYLOCK_KEY2_SHIFT (4U)
/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01,
* 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once
* this field is written with a value different from '10', its value can no longer be modified
* until un Power On Reset occurs."
*/
-#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK)
-#define PUF_KEYLOCK_KEY3_MASK (0xC0U)
-#define PUF_KEYLOCK_KEY3_SHIFT (6U)
+#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK)
+
+#define PUF_KEYLOCK_KEY3_MASK (0xC0U)
+#define PUF_KEYLOCK_KEY3_SHIFT (6U)
/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01,
* 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once
* this field is written with a value different from '10', its value can no longer be modified
* until un Power On Reset occurs."
*/
-#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK)
+#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK)
/*! @} */
/*! @name KEYENABLE - */
/*! @{ */
-#define PUF_KEYENABLE_KEY0_MASK (0x3U)
-#define PUF_KEYENABLE_KEY0_SHIFT (0U)
+
+#define PUF_KEYENABLE_KEY0_MASK (0x3U)
+#define PUF_KEYENABLE_KEY0_SHIFT (0U)
/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11
* : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register."
*/
-#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK)
-#define PUF_KEYENABLE_KEY1_MASK (0xCU)
-#define PUF_KEYENABLE_KEY1_SHIFT (2U)
+#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK)
+
+#define PUF_KEYENABLE_KEY1_MASK (0xCU)
+#define PUF_KEYENABLE_KEY1_SHIFT (2U)
/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11
* : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register."
*/
-#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK)
-#define PUF_KEYENABLE_KEY2_MASK (0x30U)
-#define PUF_KEYENABLE_KEY2_SHIFT (4U)
+#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK)
+
+#define PUF_KEYENABLE_KEY2_MASK (0x30U)
+#define PUF_KEYENABLE_KEY2_SHIFT (4U)
/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11
* : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register."
*/
-#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK)
-#define PUF_KEYENABLE_KEY3_MASK (0xC0U)
-#define PUF_KEYENABLE_KEY3_SHIFT (6U)
+#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK)
+
+#define PUF_KEYENABLE_KEY3_MASK (0xC0U)
+#define PUF_KEYENABLE_KEY3_SHIFT (6U)
/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11
* : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register."
*/
-#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK)
+#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK)
/*! @} */
/*! @name KEYRESET - Reinitialize Keys shift registers counters */
/*! @{ */
-#define PUF_KEYRESET_KEY0_MASK (0x3U)
-#define PUF_KEYRESET_KEY0_SHIFT (0U)
+
+#define PUF_KEYRESET_KEY0_MASK (0x3U)
+#define PUF_KEYRESET_KEY0_SHIFT (0U)
/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key.
*/
-#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK)
-#define PUF_KEYRESET_KEY1_MASK (0xCU)
-#define PUF_KEYRESET_KEY1_SHIFT (2U)
+#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK)
+
+#define PUF_KEYRESET_KEY1_MASK (0xCU)
+#define PUF_KEYRESET_KEY1_SHIFT (2U)
/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key.
*/
-#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK)
-#define PUF_KEYRESET_KEY2_MASK (0x30U)
-#define PUF_KEYRESET_KEY2_SHIFT (4U)
+#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK)
+
+#define PUF_KEYRESET_KEY2_MASK (0x30U)
+#define PUF_KEYRESET_KEY2_SHIFT (4U)
/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key.
*/
-#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK)
-#define PUF_KEYRESET_KEY3_MASK (0xC0U)
-#define PUF_KEYRESET_KEY3_SHIFT (6U)
+#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK)
+
+#define PUF_KEYRESET_KEY3_MASK (0xC0U)
+#define PUF_KEYRESET_KEY3_SHIFT (6U)
/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key.
*/
-#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK)
+#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK)
/*! @} */
/*! @name IDXBLK_L - */
/*! @{ */
-#define PUF_IDXBLK_L_IDX1_MASK (0xCU)
-#define PUF_IDXBLK_L_IDX1_SHIFT (2U)
+
+#define PUF_IDXBLK_L_IDX1_MASK (0xCU)
+#define PUF_IDXBLK_L_IDX1_SHIFT (2U)
/*! IDX1 - Use to block PUF index 1
*/
-#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK)
-#define PUF_IDXBLK_L_IDX2_MASK (0x30U)
-#define PUF_IDXBLK_L_IDX2_SHIFT (4U)
+#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK)
+
+#define PUF_IDXBLK_L_IDX2_MASK (0x30U)
+#define PUF_IDXBLK_L_IDX2_SHIFT (4U)
/*! IDX2 - Use to block PUF index 2
*/
-#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK)
-#define PUF_IDXBLK_L_IDX3_MASK (0xC0U)
-#define PUF_IDXBLK_L_IDX3_SHIFT (6U)
+#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK)
+
+#define PUF_IDXBLK_L_IDX3_MASK (0xC0U)
+#define PUF_IDXBLK_L_IDX3_SHIFT (6U)
/*! IDX3 - Use to block PUF index 3
*/
-#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK)
-#define PUF_IDXBLK_L_IDX4_MASK (0x300U)
-#define PUF_IDXBLK_L_IDX4_SHIFT (8U)
+#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK)
+
+#define PUF_IDXBLK_L_IDX4_MASK (0x300U)
+#define PUF_IDXBLK_L_IDX4_SHIFT (8U)
/*! IDX4 - Use to block PUF index 4
*/
-#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK)
-#define PUF_IDXBLK_L_IDX5_MASK (0xC00U)
-#define PUF_IDXBLK_L_IDX5_SHIFT (10U)
+#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK)
+
+#define PUF_IDXBLK_L_IDX5_MASK (0xC00U)
+#define PUF_IDXBLK_L_IDX5_SHIFT (10U)
/*! IDX5 - Use to block PUF index 5
*/
-#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK)
-#define PUF_IDXBLK_L_IDX6_MASK (0x3000U)
-#define PUF_IDXBLK_L_IDX6_SHIFT (12U)
+#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK)
+
+#define PUF_IDXBLK_L_IDX6_MASK (0x3000U)
+#define PUF_IDXBLK_L_IDX6_SHIFT (12U)
/*! IDX6 - Use to block PUF index 6
*/
-#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK)
-#define PUF_IDXBLK_L_IDX7_MASK (0xC000U)
-#define PUF_IDXBLK_L_IDX7_SHIFT (14U)
+#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK)
+
+#define PUF_IDXBLK_L_IDX7_MASK (0xC000U)
+#define PUF_IDXBLK_L_IDX7_SHIFT (14U)
/*! IDX7 - Use to block PUF index 7
*/
-#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK)
-#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U)
-#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U)
+#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK)
+
+#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U)
+#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U)
/*! LOCK_IDX - Lock 0 to 7 PUF key indexes
*/
-#define PUF_IDXBLK_L_LOCK_IDX(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK)
+#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK)
/*! @} */
/*! @name IDXBLK_H_DP - */
/*! @{ */
-#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U)
-#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U)
+
+#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U)
+#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U)
/*! IDX8 - Use to block PUF index 8
*/
-#define PUF_IDXBLK_H_DP_IDX8(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK)
-#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU)
-#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U)
+#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU)
+#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U)
/*! IDX9 - Use to block PUF index 9
*/
-#define PUF_IDXBLK_H_DP_IDX9(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
-#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U)
-#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U)
+#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U)
+#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U)
/*! IDX10 - Use to block PUF index 10
*/
-#define PUF_IDXBLK_H_DP_IDX10(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK)
-#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U)
-#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U)
+#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U)
+#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U)
/*! IDX11 - Use to block PUF index 11
*/
-#define PUF_IDXBLK_H_DP_IDX11(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK)
-#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U)
-#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U)
+#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U)
+#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U)
/*! IDX12 - Use to block PUF index 12
*/
-#define PUF_IDXBLK_H_DP_IDX12(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK)
-#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U)
-#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U)
+#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U)
+#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U)
/*! IDX13 - Use to block PUF index 13
*/
-#define PUF_IDXBLK_H_DP_IDX13(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK)
-#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U)
-#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U)
+#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U)
+#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U)
/*! IDX14 - Use to block PUF index 14
*/
-#define PUF_IDXBLK_H_DP_IDX14(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK)
-#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U)
-#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U)
+#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK)
+
+#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U)
+#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U)
/*! IDX15 - Use to block PUF index 15
*/
-#define PUF_IDXBLK_H_DP_IDX15(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK)
+#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK)
/*! @} */
/*! @name KEYMASK - Only reset in case of full IC reset */
/*! @{ */
-#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU)
-#define PUF_KEYMASK_KEYMASK_SHIFT (0U)
-#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
+
+#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU)
+#define PUF_KEYMASK_KEYMASK_SHIFT (0U)
+#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
/*! @} */
/* The count of PUF_KEYMASK */
-#define PUF_KEYMASK_COUNT (4U)
+#define PUF_KEYMASK_COUNT (4U)
/*! @name IDXBLK_H - */
/*! @{ */
-#define PUF_IDXBLK_H_IDX8_MASK (0x3U)
-#define PUF_IDXBLK_H_IDX8_SHIFT (0U)
+
+#define PUF_IDXBLK_H_IDX8_MASK (0x3U)
+#define PUF_IDXBLK_H_IDX8_SHIFT (0U)
/*! IDX8 - Use to block PUF index 8
*/
-#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK)
-#define PUF_IDXBLK_H_IDX9_MASK (0xCU)
-#define PUF_IDXBLK_H_IDX9_SHIFT (2U)
+#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK)
+
+#define PUF_IDXBLK_H_IDX9_MASK (0xCU)
+#define PUF_IDXBLK_H_IDX9_SHIFT (2U)
/*! IDX9 - Use to block PUF index 9
*/
-#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK)
-#define PUF_IDXBLK_H_IDX10_MASK (0x30U)
-#define PUF_IDXBLK_H_IDX10_SHIFT (4U)
+#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK)
+
+#define PUF_IDXBLK_H_IDX10_MASK (0x30U)
+#define PUF_IDXBLK_H_IDX10_SHIFT (4U)
/*! IDX10 - Use to block PUF index 10
*/
-#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK)
-#define PUF_IDXBLK_H_IDX11_MASK (0xC0U)
-#define PUF_IDXBLK_H_IDX11_SHIFT (6U)
+#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK)
+
+#define PUF_IDXBLK_H_IDX11_MASK (0xC0U)
+#define PUF_IDXBLK_H_IDX11_SHIFT (6U)
/*! IDX11 - Use to block PUF index 11
*/
-#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK)
-#define PUF_IDXBLK_H_IDX12_MASK (0x300U)
-#define PUF_IDXBLK_H_IDX12_SHIFT (8U)
+#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK)
+
+#define PUF_IDXBLK_H_IDX12_MASK (0x300U)
+#define PUF_IDXBLK_H_IDX12_SHIFT (8U)
/*! IDX12 - Use to block PUF index 12
*/
-#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK)
-#define PUF_IDXBLK_H_IDX13_MASK (0xC00U)
-#define PUF_IDXBLK_H_IDX13_SHIFT (10U)
+#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK)
+
+#define PUF_IDXBLK_H_IDX13_MASK (0xC00U)
+#define PUF_IDXBLK_H_IDX13_SHIFT (10U)
/*! IDX13 - Use to block PUF index 13
*/
-#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK)
-#define PUF_IDXBLK_H_IDX14_MASK (0x3000U)
-#define PUF_IDXBLK_H_IDX14_SHIFT (12U)
+#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK)
+
+#define PUF_IDXBLK_H_IDX14_MASK (0x3000U)
+#define PUF_IDXBLK_H_IDX14_SHIFT (12U)
/*! IDX14 - Use to block PUF index 14
*/
-#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK)
-#define PUF_IDXBLK_H_IDX15_MASK (0xC000U)
-#define PUF_IDXBLK_H_IDX15_SHIFT (14U)
+#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK)
+
+#define PUF_IDXBLK_H_IDX15_MASK (0xC000U)
+#define PUF_IDXBLK_H_IDX15_SHIFT (14U)
/*! IDX15 - Use to block PUF index 15
*/
-#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK)
-#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U)
-#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U)
+#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK)
+
+#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U)
+#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U)
/*! LOCK_IDX - Lock 8 to 15 PUF key indexes
*/
-#define PUF_IDXBLK_H_LOCK_IDX(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK)
+#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK)
/*! @} */
/*! @name IDXBLK_L_DP - */
/*! @{ */
-#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU)
-#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U)
+
+#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU)
+#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U)
/*! IDX1 - Use to block PUF index 1
*/
-#define PUF_IDXBLK_L_DP_IDX1(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK)
-#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U)
-#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U)
+#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK)
+
+#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U)
+#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U)
/*! IDX2 - Use to block PUF index 2
*/
-#define PUF_IDXBLK_L_DP_IDX2(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK)
-#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U)
-#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U)
+#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK)
+
+#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U)
+#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U)
/*! IDX3 - Use to block PUF index 3
*/
-#define PUF_IDXBLK_L_DP_IDX3(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK)
-#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U)
-#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U)
+#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK)
+
+#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U)
+#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U)
/*! IDX4 - Use to block PUF index 4
*/
-#define PUF_IDXBLK_L_DP_IDX4(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK)
-#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U)
-#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U)
+#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK)
+
+#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U)
+#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U)
/*! IDX5 - Use to block PUF index 5
*/
-#define PUF_IDXBLK_L_DP_IDX5(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
-#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U)
-#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U)
+#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
+
+#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U)
+#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U)
/*! IDX6 - Use to block PUF index 6
*/
-#define PUF_IDXBLK_L_DP_IDX6(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK)
-#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U)
-#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U)
+#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK)
+
+#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U)
+#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U)
/*! IDX7 - Use to block PUF index 7
*/
-#define PUF_IDXBLK_L_DP_IDX7(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK)
+#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK)
/*! @} */
/*! @name SHIFT_STATUS - */
/*! @{ */
-#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU)
-#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U)
+
+#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU)
+#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U)
/*! KEY0 - Index counter from key 0 shift register
*/
-#define PUF_SHIFT_STATUS_KEY0(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK)
-#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U)
-#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U)
+#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK)
+
+#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U)
+#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U)
/*! KEY1 - Index counter from key 1 shift register
*/
-#define PUF_SHIFT_STATUS_KEY1(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK)
-#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U)
-#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U)
+#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK)
+
+#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U)
+#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U)
/*! KEY2 - Index counter from key 2 shift register
*/
-#define PUF_SHIFT_STATUS_KEY2(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK)
-#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U)
-#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U)
+#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK)
+
+#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U)
+#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U)
/*! KEY3 - Index counter from key 3 shift register
*/
-#define PUF_SHIFT_STATUS_KEY3(x) \
- (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK)
+#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group PUF_Register_Masks */
+
/* PUF - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral PUF base address */
-#define PUF_BASE (0x5003B000u)
-/** Peripheral PUF base address */
-#define PUF_BASE_NS (0x4003B000u)
-/** Peripheral PUF base pointer */
-#define PUF ((PUF_Type *)PUF_BASE)
-/** Peripheral PUF base pointer */
-#define PUF_NS ((PUF_Type *)PUF_BASE_NS)
-/** Array initializer of PUF peripheral base addresses */
-#define PUF_BASE_ADDRS \
- { \
- PUF_BASE \
- }
-/** Array initializer of PUF peripheral base pointers */
-#define PUF_BASE_PTRS \
- { \
- PUF \
- }
-/** Array initializer of PUF peripheral base addresses */
-#define PUF_BASE_ADDRS_NS \
- { \
- PUF_BASE_NS \
- }
-/** Array initializer of PUF peripheral base pointers */
-#define PUF_BASE_PTRS_NS \
- { \
- PUF_NS \
- }
+ /** Peripheral PUF base address */
+ #define PUF_BASE (0x5003B000u)
+ /** Peripheral PUF base address */
+ #define PUF_BASE_NS (0x4003B000u)
+ /** Peripheral PUF base pointer */
+ #define PUF ((PUF_Type *)PUF_BASE)
+ /** Peripheral PUF base pointer */
+ #define PUF_NS ((PUF_Type *)PUF_BASE_NS)
+ /** Array initializer of PUF peripheral base addresses */
+ #define PUF_BASE_ADDRS { PUF_BASE }
+ /** Array initializer of PUF peripheral base pointers */
+ #define PUF_BASE_PTRS { PUF }
+ /** Array initializer of PUF peripheral base addresses */
+ #define PUF_BASE_ADDRS_NS { PUF_BASE_NS }
+ /** Array initializer of PUF peripheral base pointers */
+ #define PUF_BASE_PTRS_NS { PUF_NS }
#else
-/** Peripheral PUF base address */
-#define PUF_BASE (0x4003B000u)
-/** Peripheral PUF base pointer */
-#define PUF ((PUF_Type *)PUF_BASE)
-/** Array initializer of PUF peripheral base addresses */
-#define PUF_BASE_ADDRS \
- { \
- PUF_BASE \
- }
-/** Array initializer of PUF peripheral base pointers */
-#define PUF_BASE_PTRS \
- { \
- PUF \
- }
+ /** Peripheral PUF base address */
+ #define PUF_BASE (0x4003B000u)
+ /** Peripheral PUF base pointer */
+ #define PUF ((PUF_Type *)PUF_BASE)
+ /** Array initializer of PUF peripheral base addresses */
+ #define PUF_BASE_ADDRS { PUF_BASE }
+ /** Array initializer of PUF peripheral base pointers */
+ #define PUF_BASE_PTRS { PUF }
#endif
/** Interrupt vectors for the PUF peripheral type */
-#define PUF_IRQS \
- { \
- PUF_IRQn \
- }
+#define PUF_IRQS { PUF_IRQn }
/*!
* @}
*/ /* end of group PUF_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- RNG Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -17303,17 +16492,15 @@ typedef struct
*/
/** RNG - Register Layout Typedef */
-typedef struct
-{
- __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each
- time it is read, offset: 0x0 */
- uint8_t RESERVED_0[4];
- __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */
- __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */
- __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */
- __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */
- uint8_t RESERVED_1[4068];
- __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */
+typedef struct {
+ __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */
+ __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */
+ __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */
+ __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */
+ uint8_t RESERVED_1[4068];
+ __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */
} RNG_Type;
/* ----------------------------------------------------------------------------
@@ -17325,183 +16512,164 @@ typedef struct
* @{
*/
-/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is
- * read */
+/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */
/*! @{ */
-#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU)
-#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U)
+
+#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU)
+#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U)
/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read.
*/
-#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK)
+#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK)
/*! @} */
/*! @name COUNTER_VAL - */
/*! @{ */
-#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU)
-#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U)
+
+#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU)
+#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U)
/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock
* frequency for evaluation and certification purposes.
*/
-#define RNG_COUNTER_VAL_CLK_RATIO(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK)
-#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U)
-#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U)
-/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any
- * *_NUMBER.
+#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK)
+
+#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U)
+#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U)
+/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER.
*/
-#define RNG_COUNTER_VAL_REFRESH_CNT(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK)
+#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK)
/*! @} */
/*! @name COUNTER_CFG - */
/*! @{ */
-#define RNG_COUNTER_CFG_MODE_MASK (0x3U)
-#define RNG_COUNTER_CFG_MODE_SHIFT (0U)
+
+#define RNG_COUNTER_CFG_MODE_MASK (0x3U)
+#define RNG_COUNTER_CFG_MODE_SHIFT (0U)
/*! MODE - 00: disabled 01: update once.
*/
-#define RNG_COUNTER_CFG_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK)
-#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU)
-#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U)
+#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK)
+
+#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU)
+#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U)
/*! CLOCK_SEL - Selects the internal clock on which to compute statistics.
*/
-#define RNG_COUNTER_CFG_CLOCK_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK)
-#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U)
-#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U)
+#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK)
+
+#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U)
+#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U)
/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'.
*/
-#define RNG_COUNTER_CFG_SHIFT4X(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK)
+#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK)
/*! @} */
/*! @name ONLINE_TEST_CFG - */
/*! @{ */
-#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U)
-#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U)
+
+#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U)
+#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U)
/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER.
*/
-#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK)
-#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U)
-#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U)
+#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK)
+
+#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U)
+#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U)
/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one
* or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10:
* RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this
* field.
*/
-#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK)
+#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK)
/*! @} */
/*! @name ONLINE_TEST_VAL - */
/*! @{ */
+
#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU)
#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U)
/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'.
*/
-#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & \
- RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK)
+#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK)
+
#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U)
#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U)
/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0.
*/
-#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & \
- RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK)
+#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK)
+
#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U)
#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U)
/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0.
*/
-#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & \
- RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK)
+#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK)
/*! @} */
/*! @name MODULEID - IP identifier */
/*! @{ */
-#define RNG_MODULEID_APERTURE_MASK (0xFFU)
-#define RNG_MODULEID_APERTURE_SHIFT (0U)
+
+#define RNG_MODULEID_APERTURE_MASK (0xFFU)
+#define RNG_MODULEID_APERTURE_SHIFT (0U)
/*! APERTURE - Aperture i.
*/
-#define RNG_MODULEID_APERTURE(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK)
-#define RNG_MODULEID_MIN_REV_MASK (0xF00U)
-#define RNG_MODULEID_MIN_REV_SHIFT (8U)
+#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK)
+
+#define RNG_MODULEID_MIN_REV_MASK (0xF00U)
+#define RNG_MODULEID_MIN_REV_SHIFT (8U)
/*! MIN_REV - Minor revision i.
*/
-#define RNG_MODULEID_MIN_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK)
-#define RNG_MODULEID_MAJ_REV_MASK (0xF000U)
-#define RNG_MODULEID_MAJ_REV_SHIFT (12U)
+#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK)
+
+#define RNG_MODULEID_MAJ_REV_MASK (0xF000U)
+#define RNG_MODULEID_MAJ_REV_SHIFT (12U)
/*! MAJ_REV - Major revision i.
*/
-#define RNG_MODULEID_MAJ_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK)
-#define RNG_MODULEID_ID_MASK (0xFFFF0000U)
-#define RNG_MODULEID_ID_SHIFT (16U)
+#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK)
+
+#define RNG_MODULEID_ID_MASK (0xFFFF0000U)
+#define RNG_MODULEID_ID_SHIFT (16U)
/*! ID - Identifier.
*/
-#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK)
+#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group RNG_Register_Masks */
+
/* RNG - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral RNG base address */
-#define RNG_BASE (0x5003A000u)
-/** Peripheral RNG base address */
-#define RNG_BASE_NS (0x4003A000u)
-/** Peripheral RNG base pointer */
-#define RNG ((RNG_Type *)RNG_BASE)
-/** Peripheral RNG base pointer */
-#define RNG_NS ((RNG_Type *)RNG_BASE_NS)
-/** Array initializer of RNG peripheral base addresses */
-#define RNG_BASE_ADDRS \
- { \
- RNG_BASE \
- }
-/** Array initializer of RNG peripheral base pointers */
-#define RNG_BASE_PTRS \
- { \
- RNG \
- }
-/** Array initializer of RNG peripheral base addresses */
-#define RNG_BASE_ADDRS_NS \
- { \
- RNG_BASE_NS \
- }
-/** Array initializer of RNG peripheral base pointers */
-#define RNG_BASE_PTRS_NS \
- { \
- RNG_NS \
- }
+ /** Peripheral RNG base address */
+ #define RNG_BASE (0x5003A000u)
+ /** Peripheral RNG base address */
+ #define RNG_BASE_NS (0x4003A000u)
+ /** Peripheral RNG base pointer */
+ #define RNG ((RNG_Type *)RNG_BASE)
+ /** Peripheral RNG base pointer */
+ #define RNG_NS ((RNG_Type *)RNG_BASE_NS)
+ /** Array initializer of RNG peripheral base addresses */
+ #define RNG_BASE_ADDRS { RNG_BASE }
+ /** Array initializer of RNG peripheral base pointers */
+ #define RNG_BASE_PTRS { RNG }
+ /** Array initializer of RNG peripheral base addresses */
+ #define RNG_BASE_ADDRS_NS { RNG_BASE_NS }
+ /** Array initializer of RNG peripheral base pointers */
+ #define RNG_BASE_PTRS_NS { RNG_NS }
#else
-/** Peripheral RNG base address */
-#define RNG_BASE (0x4003A000u)
-/** Peripheral RNG base pointer */
-#define RNG ((RNG_Type *)RNG_BASE)
-/** Array initializer of RNG peripheral base addresses */
-#define RNG_BASE_ADDRS \
- { \
- RNG_BASE \
- }
-/** Array initializer of RNG peripheral base pointers */
-#define RNG_BASE_PTRS \
- { \
- RNG \
- }
+ /** Peripheral RNG base address */
+ #define RNG_BASE (0x4003A000u)
+ /** Peripheral RNG base pointer */
+ #define RNG ((RNG_Type *)RNG_BASE)
+ /** Array initializer of RNG peripheral base addresses */
+ #define RNG_BASE_ADDRS { RNG_BASE }
+ /** Array initializer of RNG peripheral base pointers */
+ #define RNG_BASE_PTRS { RNG }
#endif
/*!
* @}
*/ /* end of group RNG_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -17512,15 +16680,14 @@ typedef struct
*/
/** RTC - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
- __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
- __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
- __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
- __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */
- uint8_t RESERVED_0[44];
- __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */
+typedef struct {
+ __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
+ __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
+ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
+ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
+ __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */
+ uint8_t RESERVED_0[44];
+ __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */
} RTC_Type;
/* ----------------------------------------------------------------------------
@@ -17534,58 +16701,63 @@ typedef struct
/*! @name CTRL - RTC control register */
/*! @{ */
-#define RTC_CTRL_SWRESET_MASK (0x1U)
-#define RTC_CTRL_SWRESET_SHIFT (0U)
+
+#define RTC_CTRL_SWRESET_MASK (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT (0U)
/*! SWRESET - Software reset control
- * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any
- * operation of the RTC. 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to
- * their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including
- * writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the
- * same time that the reset bit is being cleared.
- */
-#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
-#define RTC_CTRL_ALARM1HZ_MASK (0x4U)
-#define RTC_CTRL_ALARM1HZ_SHIFT (2U)
+ * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.
+ * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value
+ * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes
+ * to set any of the other bits within this register. Do not attempt to write to any bits of this register at
+ * the same time that the reset bit is being cleared.
+ */
+#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+
+#define RTC_CTRL_ALARM1HZ_MASK (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT (2U)
/*! ALARM1HZ - RTC 1 Hz timer alarm flag status.
* 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
* 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt
* request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.
*/
-#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
-#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
-#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
+#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+
+#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.
* 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
* 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
- * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this
- * bit.
+ * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.
*/
-#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
-#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
-#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
+#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+
+#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.
* 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
* 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.
*/
-#define RTC_CTRL_ALARMDPD_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
-#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
-#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
+#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+
+#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.
* 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
* 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.
*/
-#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
-#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
-#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
+#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+
+#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz
* timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).
* 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.
* 0b1..Enable. The 1 kHz RTC timer is enabled.
*/
-#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
-#define RTC_CTRL_RTC_EN_MASK (0x80U)
-#define RTC_CTRL_RTC_EN_SHIFT (7U)
+#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+
+#define RTC_CTRL_RTC_EN_MASK (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT (7U)
/*! RTC_EN - RTC enable.
* 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should
* be 0 when writing to load a value in the RTC counter register.
@@ -17593,25 +16765,26 @@ typedef struct
* operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the
* high-resolution, 1 kHz clock, set bit 6 in this register.
*/
-#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
-#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
-#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
+#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+
+#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
/*! RTC_OSC_PD - RTC oscillator power-down control.
* 0b0..See RTC_OSC_BYPASS
* 0b1..RTC oscillator is powered-down.
*/
-#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
-#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U)
-#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U)
+#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+
+#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U)
+#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U)
/*! RTC_OSC_BYPASS - RTC oscillator bypass control.
- * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN
- * and RTC_XTALOUT pins. 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the
- * RTC_XTALIN pin.
- */
-#define RTC_CTRL_RTC_OSC_BYPASS(x) \
- (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)
-#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U)
-#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U)
+ * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins.
+ * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin.
+ */
+#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)
+
+#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U)
+#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U)
/*! RTC_SUBSEC_ENA - RTC Sub-second counter control.
* 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD
* reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second
@@ -17621,48 +16794,51 @@ typedef struct
* set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip
* exits deep power-down mode.
*/
-#define RTC_CTRL_RTC_SUBSEC_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)
+#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)
/*! @} */
/*! @name MATCH - RTC match register */
/*! @{ */
-#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
-#define RTC_MATCH_MATVAL_SHIFT (0U)
+
+#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT (0U)
/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the
* alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled.
*/
-#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
/*! @} */
/*! @name COUNT - RTC counter register */
/*! @{ */
-#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
-#define RTC_COUNT_VAL_SHIFT (0U)
+
+#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT (0U)
/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial
* value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC
* Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this
* register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after
* the RTC_EN bit is set.
*/
-#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
/*! @} */
/*! @name WAKE - High-resolution/wake-up timer control register */
/*! @{ */
-#define RTC_WAKE_VAL_MASK (0xFFFFU)
-#define RTC_WAKE_VAL_SHIFT (0U)
+
+#define RTC_WAKE_VAL_MASK (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT (0U)
/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads
* a start count value into the wake-up timer and initializes a count-down sequence. Do not write
* to this register while counting is in progress.
*/
-#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
/*! @} */
/*! @name SUBSEC - Sub-second counter register */
/*! @{ */
-#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU)
-#define RTC_SUBSEC_SUBSEC_SHIFT (0U)
+
+#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU)
+#define RTC_SUBSEC_SUBSEC_SHIFT (0U)
/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is
* cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz
* rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This
@@ -17670,81 +16846,64 @@ typedef struct
* disabled and re-enabled. On modules not equipped with a sub-second counter, this register
* will read-back as all zeroes.
*/
-#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK)
+#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK)
/*! @} */
/*! @name GPREG - General Purpose register */
/*! @{ */
-#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
-#define RTC_GPREG_GPDATA_SHIFT (0U)
+
+#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT (0U)
/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied.
*/
-#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
/*! @} */
/* The count of RTC_GPREG */
-#define RTC_GPREG_COUNT (8U)
+#define RTC_GPREG_COUNT (8U)
+
/*!
* @}
*/ /* end of group RTC_Register_Masks */
+
/* RTC - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral RTC base address */
-#define RTC_BASE (0x5002C000u)
-/** Peripheral RTC base address */
-#define RTC_BASE_NS (0x4002C000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-/** Peripheral RTC base pointer */
-#define RTC_NS ((RTC_Type *)RTC_BASE_NS)
-/** Array initializer of RTC peripheral base addresses */
-#define RTC_BASE_ADDRS \
- { \
- RTC_BASE \
- }
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASE_PTRS \
- { \
- RTC \
- }
-/** Array initializer of RTC peripheral base addresses */
-#define RTC_BASE_ADDRS_NS \
- { \
- RTC_BASE_NS \
- }
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASE_PTRS_NS \
- { \
- RTC_NS \
- }
+ /** Peripheral RTC base address */
+ #define RTC_BASE (0x5002C000u)
+ /** Peripheral RTC base address */
+ #define RTC_BASE_NS (0x4002C000u)
+ /** Peripheral RTC base pointer */
+ #define RTC ((RTC_Type *)RTC_BASE)
+ /** Peripheral RTC base pointer */
+ #define RTC_NS ((RTC_Type *)RTC_BASE_NS)
+ /** Array initializer of RTC peripheral base addresses */
+ #define RTC_BASE_ADDRS { RTC_BASE }
+ /** Array initializer of RTC peripheral base pointers */
+ #define RTC_BASE_PTRS { RTC }
+ /** Array initializer of RTC peripheral base addresses */
+ #define RTC_BASE_ADDRS_NS { RTC_BASE_NS }
+ /** Array initializer of RTC peripheral base pointers */
+ #define RTC_BASE_PTRS_NS { RTC_NS }
#else
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4002C000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-/** Array initializer of RTC peripheral base addresses */
-#define RTC_BASE_ADDRS \
- { \
- RTC_BASE \
- }
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASE_PTRS \
- { \
- RTC \
- }
+ /** Peripheral RTC base address */
+ #define RTC_BASE (0x4002C000u)
+ /** Peripheral RTC base pointer */
+ #define RTC ((RTC_Type *)RTC_BASE)
+ /** Array initializer of RTC peripheral base addresses */
+ #define RTC_BASE_ADDRS { RTC_BASE }
+ /** Array initializer of RTC peripheral base pointers */
+ #define RTC_BASE_PTRS { RTC }
#endif
/** Interrupt vectors for the RTC peripheral type */
-#define RTC_IRQS \
- { \
- RTC_IRQn \
- }
+#define RTC_IRQS { RTC_IRQn }
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- SCT Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -17755,53 +16914,119 @@ typedef struct
*/
/** SCT - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
- __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
- __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
- __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
- __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
- __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
- uint8_t RESERVED_0[40];
- __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
- __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
- __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
- __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
- __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
- __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
- __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
- __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */
- __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */
- uint8_t RESERVED_1[140];
- __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
- __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
- __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
- __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
- union
- { /* offset: 0x100 */
- __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
- __IO uint32_t
- MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+typedef struct {
+ __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */
+ __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */
+ } CTRL_ACCESS16BIT;
+ __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
+ };
+ union { /* offset: 0x8 */
+ struct { /* offset: 0x8 */
+ __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */
+ __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */
+ } LIMIT_ACCESS16BIT;
+ __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
+ };
+ union { /* offset: 0xC */
+ struct { /* offset: 0xC */
+ __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */
+ __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */
+ } HALT_ACCESS16BIT;
+ __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
+ };
+ union { /* offset: 0x10 */
+ struct { /* offset: 0x10 */
+ __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */
+ __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */
+ } STOP_ACCESS16BIT;
+ __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
+ };
+ union { /* offset: 0x14 */
+ struct { /* offset: 0x14 */
+ __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */
+ __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */
+ } START_ACCESS16BIT;
+ __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
+ };
+ uint8_t RESERVED_0[40];
+ union { /* offset: 0x40 */
+ struct { /* offset: 0x40 */
+ __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */
+ __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */
+ } COUNT_ACCESS16BIT;
+ __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
+ };
+ union { /* offset: 0x44 */
+ struct { /* offset: 0x44 */
+ __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */
+ __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */
+ } STATE_ACCESS16BIT;
+ __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
+ };
+ __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
+ union { /* offset: 0x4C */
+ struct { /* offset: 0x4C */
+ __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */
+ __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */
+ } REGMODE_ACCESS16BIT;
+ __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
+ };
+ __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
+ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
+ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
+ __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */
+ __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */
+ uint8_t RESERVED_1[140];
+ __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
+ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
+ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
+ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
+ union { /* offset: 0x100 */
+ union { /* offset: 0x100, array step: 0x4 */
+ struct { /* offset: 0x100, array step: 0x4 */
+ __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */
+ __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */
+ } CAP_ACCESS16BIT[16];
+ __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
};
- uint8_t RESERVED_2[192];
- union
- { /* offset: 0x200 */
- __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
- __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+ union { /* offset: 0x100, array step: 0x4 */
+ struct { /* offset: 0x100, array step: 0x4 */
+ __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */
+ __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */
+ } MATCH_ACCESS16BIT[16];
+ __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
};
- uint8_t RESERVED_3[192];
- struct
- { /* offset: 0x300, array step: 0x8 */
- __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
- __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
- } EV[16];
- uint8_t RESERVED_4[384];
- struct
- { /* offset: 0x500, array step: 0x8 */
- __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
- __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
- } OUT[10];
+ };
+ uint8_t RESERVED_2[192];
+ union { /* offset: 0x200 */
+ union { /* offset: 0x200, array step: 0x4 */
+ struct { /* offset: 0x200, array step: 0x4 */
+ __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */
+ __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */
+ } CAPCTRL_ACCESS16BIT[16];
+ __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+ };
+ union { /* offset: 0x200, array step: 0x4 */
+ struct { /* offset: 0x200, array step: 0x4 */
+ __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */
+ __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */
+ } MATCHREL_ACCESS16BIT[16];
+ __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+ };
+ };
+ uint8_t RESERVED_3[192];
+ struct { /* offset: 0x300, array step: 0x8 */
+ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+ } EV[16];
+ uint8_t RESERVED_4[384];
+ struct { /* offset: 0x500, array step: 0x8 */
+ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+ __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+ } OUT[10];
} SCT_Type;
/* ----------------------------------------------------------------------------
@@ -17815,21 +17040,24 @@ typedef struct
/*! @name CONFIG - SCT configuration register */
/*! @{ */
-#define SCT_CONFIG_UNIFY_MASK (0x1U)
-#define SCT_CONFIG_UNIFY_SHIFT (0U)
+
+#define SCT_CONFIG_UNIFY_MASK (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT (0U)
/*! UNIFY - SCT operation
* 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
* 0b1..The SCT operates as a unified 32-bit counter.
*/
-#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
-#define SCT_CONFIG_CLKMODE_MASK (0x6U)
-#define SCT_CONFIG_CLKMODE_SHIFT (1U)
+#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+
+#define SCT_CONFIG_CLKMODE_MASK (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT (1U)
/*! CLKMODE - SCT clock mode
- * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter
- * prescalers. 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers
- * are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum
- * pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock
- * mode. 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
+ * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.
+ * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
+ * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
+ * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
+ * high-performance, sampled-clock mode.
+ * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the
* counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
* clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
* 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
@@ -17837,9 +17065,10 @@ typedef struct
* clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
* the system clock.
*/
-#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
-#define SCT_CONFIG_CKSEL_MASK (0x78U)
-#define SCT_CONFIG_CKSEL_SHIFT (3U)
+#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+
+#define SCT_CONFIG_CKSEL_MASK (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT (3U)
/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent
* on the CLKMODE bit selection in this register.
* 0b0000..Rising edges on input 0.
@@ -17859,27 +17088,28 @@ typedef struct
* 0b1110..Rising edges on input 7.
* 0b1111..Falling edges on input 7.
*/
-#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
-#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
-#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
+#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+
+#define SCT_CONFIG_NORELOAD_L_MASK (0x80U)
+#define SCT_CONFIG_NORELOAD_L_SHIFT (7U)
/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their
* respective reload registers. Setting this bit eliminates the need to write to the reload
* registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any
* time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
*/
-#define SCT_CONFIG_NORELOAD_L(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
-#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
-#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
+#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
+
+#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their
* respective reload registers. Setting this bit eliminates the need to write to the reload
* registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at
* any time. This bit is not used when the UNIFY bit is set.
*/
-#define SCT_CONFIG_NORELOAD_H(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
-#define SCT_CONFIG_INSYNC_MASK (0x1E00U)
-#define SCT_CONFIG_INSYNC_SHIFT (9U)
+#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+
+#define SCT_CONFIG_INSYNC_MASK (0x1E00U)
+#define SCT_CONFIG_INSYNC_SHIFT (9U)
/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all
* other bits are reserved. A 1 in one of these bits subjects the corresponding input to
* synchronization to the SCT clock, before it is used to create an event. If an input is known to
@@ -17888,942 +17118,1335 @@ typedef struct
* clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation.
* It does not apply to the clock input specified in the CKSEL field.
*/
-#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
-#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
-#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
+#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+
+#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto
* LIMIT condition without the need to define an associated event. As with any LIMIT event, this
* automatic limit causes the counter to be cleared to zero in unidirectional mode or to change
* the direction of count in bi-directional mode. Software can write to set or clear this bit at
* any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.
*/
-#define SCT_CONFIG_AUTOLIMIT_L(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
-#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
-#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
+#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+
+#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a
* de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event,
* this automatic limit causes the counter to be cleared to zero in unidirectional mode or to
* change the direction of count in bi-directional mode. Software can write to set or clear this bit
* at any time. This bit is not used when the UNIFY bit is set.
*/
-#define SCT_CONFIG_AUTOLIMIT_H(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+/*! @} */
+
+/*! @name CTRLL - SCT_CTRLL register */
+/*! @{ */
+
+#define SCT_CTRLL_DOWN_L_MASK (0x1U)
+#define SCT_CTRLL_DOWN_L_SHIFT (0U)
+/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
+ * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
+ * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK)
+
+#define SCT_CTRLL_STOP_L_MASK (0x2U)
+#define SCT_CTRLL_STOP_L_SHIFT (1U)
+/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
+ * related to the counter can occur. If a designated start event occurs, this bit is cleared and
+ * counting resumes.
+ */
+#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK)
+
+#define SCT_CTRLL_HALT_L_MASK (0x4U)
+#define SCT_CTRLL_HALT_L_SHIFT (2U)
+/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
+ * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
+ * remove the halt condition while keeping the SCT in the stop condition (not running) with a
+ * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
+ * only software can clear this bit to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK)
+
+#define SCT_CTRLL_CLRCTR_L_MASK (0x8U)
+#define SCT_CTRLL_CLRCTR_L_SHIFT (3U)
+/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
+ */
+#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK)
+
+#define SCT_CTRLL_BIDIR_L_MASK (0x10U)
+#define SCT_CTRLL_BIDIR_L_SHIFT (4U)
+/*! BIDIR_L - L or unified counter direction select
+ * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
+ * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK)
+
+#define SCT_CTRLL_PRE_L_MASK (0x1FE0U)
+#define SCT_CTRLL_PRE_L_SHIFT (5U)
+/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
+ * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
+ * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK)
+/*! @} */
+
+/*! @name CTRLH - SCT_CTRLH register */
+/*! @{ */
+
+#define SCT_CTRLH_DOWN_H_MASK (0x1U)
+#define SCT_CTRLH_DOWN_H_SHIFT (0U)
+/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
+ * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
+ * when the counter is counting down and a limit condition occurs or when the counter reaches 0.
+ */
+#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK)
+
+#define SCT_CTRLH_STOP_H_MASK (0x2U)
+#define SCT_CTRLH_STOP_H_SHIFT (1U)
+/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
+ * the counter can occur. If such an event matches the mask in the Start register, this bit is
+ * cleared and counting resumes.
+ */
+#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK)
+
+#define SCT_CTRLH_HALT_H_MASK (0x4U)
+#define SCT_CTRLH_HALT_H_SHIFT (2U)
+/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
+ * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
+ * halt condition while keeping the SCT in the stop condition (not running) with a single write to
+ * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
+ * can only be cleared by software to restore counter operation. This bit is set on reset.
+ */
+#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK)
+
+#define SCT_CTRLH_CLRCTR_H_MASK (0x8U)
+#define SCT_CTRLH_CLRCTR_H_SHIFT (3U)
+/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
+ */
+#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK)
+
+#define SCT_CTRLH_BIDIR_H_MASK (0x10U)
+#define SCT_CTRLH_BIDIR_H_SHIFT (4U)
+/*! BIDIR_H - Direction select
+ * 0b0..The H counter counts up to its limit condition, then is cleared to zero.
+ * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
+ */
+#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK)
+
+#define SCT_CTRLH_PRE_H_MASK (0x1FE0U)
+#define SCT_CTRLH_PRE_H_SHIFT (5U)
+/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
+ * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
+ * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
+ */
+#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK)
/*! @} */
/*! @name CTRL - SCT control register */
/*! @{ */
-#define SCT_CTRL_DOWN_L_MASK (0x1U)
-#define SCT_CTRL_DOWN_L_SHIFT (0U)
+
+#define SCT_CTRL_DOWN_L_MASK (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT (0U)
/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit
* when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit
* when the counter is counting down and a limit condition occurs or when the counter reaches 0.
*/
-#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
-#define SCT_CTRL_STOP_L_MASK (0x2U)
-#define SCT_CTRL_STOP_L_SHIFT (1U)
+#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+
+#define SCT_CTRL_STOP_L_MASK (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT (1U)
/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events
* related to the counter can occur. If a designated start event occurs, this bit is cleared and
* counting resumes.
*/
-#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
-#define SCT_CTRL_HALT_L_MASK (0x4U)
-#define SCT_CTRL_HALT_L_SHIFT (2U)
+#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+
+#define SCT_CTRL_HALT_L_MASK (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT (2U)
/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A
* reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to
* remove the halt condition while keeping the SCT in the stop condition (not running) with a
* single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set,
* only software can clear this bit to restore counter operation. This bit is set on reset.
*/
-#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
-#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
-#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
+#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+
+#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
*/
-#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
-#define SCT_CTRL_BIDIR_L_MASK (0x10U)
-#define SCT_CTRL_BIDIR_L_SHIFT (4U)
+#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+
+#define SCT_CTRL_BIDIR_L_MASK (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT (4U)
/*! BIDIR_L - L or unified counter direction select
* 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
* 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
*/
-#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
-#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
-#define SCT_CTRL_PRE_L_SHIFT (5U)
+#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+
+#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT (5U)
/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified
* counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1.
* Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
*/
-#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
-#define SCT_CTRL_DOWN_H_MASK (0x10000U)
-#define SCT_CTRL_DOWN_H_SHIFT (16U)
+#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+
+#define SCT_CTRL_DOWN_H_MASK (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT (16U)
/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the
* counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit
* when the counter is counting down and a limit condition occurs or when the counter reaches 0.
*/
-#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
-#define SCT_CTRL_STOP_H_MASK (0x20000U)
-#define SCT_CTRL_STOP_H_SHIFT (17U)
+#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+
+#define SCT_CTRL_STOP_H_MASK (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT (17U)
/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to
* the counter can occur. If such an event matches the mask in the Start register, this bit is
* cleared and counting resumes.
*/
-#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
-#define SCT_CTRL_HALT_H_MASK (0x40000U)
-#define SCT_CTRL_HALT_H_SHIFT (18U)
+#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+
+#define SCT_CTRL_HALT_H_MASK (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT (18U)
/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets
* this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the
* halt condition while keeping the SCT in the stop condition (not running) with a single write to
* this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit
* can only be cleared by software to restore counter operation. This bit is set on reset.
*/
-#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
-#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
-#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
+#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+
+#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0.
*/
-#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
-#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
-#define SCT_CTRL_BIDIR_H_SHIFT (20U)
+#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+
+#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT (20U)
/*! BIDIR_H - Direction select
* 0b0..The H counter counts up to its limit condition, then is cleared to zero.
* 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.
*/
-#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
-#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
-#define SCT_CTRL_PRE_H_SHIFT (21U)
+#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+
+#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT (21U)
/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock.
* The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the
* counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value.
*/
-#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+/*! @} */
+
+/*! @name LIMITL - SCT_LIMITL register */
+/*! @{ */
+
+#define SCT_LIMITL_LIMITL_MASK (0xFFFFU)
+#define SCT_LIMITL_LIMITL_SHIFT (0U)
+#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK)
+/*! @} */
+
+/*! @name LIMITH - SCT_LIMITH register */
+/*! @{ */
+
+#define SCT_LIMITH_LIMITH_MASK (0xFFFFU)
+#define SCT_LIMITH_LIMITH_SHIFT (0U)
+#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK)
/*! @} */
/*! @name LIMIT - SCT limit event select register */
/*! @{ */
-#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
-#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
+
+#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter
* (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
-#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
-#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
+#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+
+#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit
* 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+/*! @} */
+
+/*! @name HALTL - SCT_HALTL register */
+/*! @{ */
+
+#define SCT_HALTL_HALTL_MASK (0xFFFFU)
+#define SCT_HALTL_HALTL_SHIFT (0U)
+#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK)
+/*! @} */
+
+/*! @name HALTH - SCT_HALTH register */
+/*! @{ */
+
+#define SCT_HALTH_HALTH_MASK (0xFFFFU)
+#define SCT_HALTH_HALTH_SHIFT (0U)
+#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK)
/*! @} */
/*! @name HALT - SCT halt event select register */
/*! @{ */
-#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
-#define SCT_HALT_HALTMSK_L_SHIFT (0U)
+
+#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT (0U)
/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0,
* event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
-#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
-#define SCT_HALT_HALTMSK_H_SHIFT (16U)
+#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+
+#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT (16U)
/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16,
* event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+/*! @} */
+
+/*! @name STOPL - SCT_STOPL register */
+/*! @{ */
+
+#define SCT_STOPL_STOPL_MASK (0xFFFFU)
+#define SCT_STOPL_STOPL_SHIFT (0U)
+#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK)
+/*! @} */
+
+/*! @name STOPH - SCT_STOPH register */
+/*! @{ */
+
+#define SCT_STOPH_STOPH_MASK (0xFFFFU)
+#define SCT_STOPH_STOPH_SHIFT (0U)
+#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK)
/*! @} */
/*! @name STOP - SCT stop event select register */
/*! @{ */
-#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
-#define SCT_STOP_STOPMSK_L_SHIFT (0U)
+
+#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT (0U)
/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0,
* event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
-#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
-#define SCT_STOP_STOPMSK_H_SHIFT (16U)
+#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+
+#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT (16U)
/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16,
* event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+/*! @} */
+
+/*! @name STARTL - SCT_STARTL register */
+/*! @{ */
+
+#define SCT_STARTL_STARTL_MASK (0xFFFFU)
+#define SCT_STARTL_STARTL_SHIFT (0U)
+#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK)
+/*! @} */
+
+/*! @name STARTH - SCT_STARTH register */
+/*! @{ */
+
+#define SCT_STARTH_STARTH_MASK (0xFFFFU)
+#define SCT_STARTH_STARTH_SHIFT (0U)
+#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK)
/*! @} */
/*! @name START - SCT start event select register */
/*! @{ */
-#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
-#define SCT_START_STARTMSK_L_SHIFT (0U)
+
+#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT (0U)
/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit
* 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_START_STARTMSK_L(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
-#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
-#define SCT_START_STARTMSK_H_SHIFT (16U)
+#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+
+#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT (16U)
/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit
* 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_START_STARTMSK_H(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+/*! @} */
+
+/*! @name COUNTL - SCT_COUNTL register */
+/*! @{ */
+
+#define SCT_COUNTL_COUNTL_MASK (0xFFFFU)
+#define SCT_COUNTL_COUNTL_SHIFT (0U)
+#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK)
+/*! @} */
+
+/*! @name COUNTH - SCT_COUNTH register */
+/*! @{ */
+
+#define SCT_COUNTH_COUNTH_MASK (0xFFFFU)
+#define SCT_COUNTH_COUNTH_SHIFT (0U)
+#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK)
/*! @} */
/*! @name COUNT - SCT counter register */
/*! @{ */
-#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
-#define SCT_COUNT_CTR_L_SHIFT (0U)
+
+#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT (0U)
/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write
* the lower 16 bits of the 32-bit unified counter.
*/
-#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
-#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
-#define SCT_COUNT_CTR_H_SHIFT (16U)
+#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+
+#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT (16U)
/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write
* the upper 16 bits of the 32-bit unified counter.
*/
-#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+/*! @} */
+
+/*! @name STATEL - SCT_STATEL register */
+/*! @{ */
+
+#define SCT_STATEL_STATEL_MASK (0xFFFFU)
+#define SCT_STATEL_STATEL_SHIFT (0U)
+#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK)
+/*! @} */
+
+/*! @name STATEH - SCT_STATEH register */
+/*! @{ */
+
+#define SCT_STATEH_STATEH_MASK (0xFFFFU)
+#define SCT_STATEH_STATEH_SHIFT (0U)
+#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK)
/*! @} */
/*! @name STATE - SCT state register */
/*! @{ */
-#define SCT_STATE_STATE_L_MASK (0x1FU)
-#define SCT_STATE_STATE_L_SHIFT (0U)
+
+#define SCT_STATE_STATE_L_MASK (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT (0U)
/*! STATE_L - State variable.
*/
-#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
-#define SCT_STATE_STATE_H_MASK (0x1F0000U)
-#define SCT_STATE_STATE_H_SHIFT (16U)
+#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+
+#define SCT_STATE_STATE_H_MASK (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT (16U)
/*! STATE_H - State variable.
*/
-#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
/*! @} */
/*! @name INPUT - SCT input register */
/*! @{ */
-#define SCT_INPUT_AIN0_MASK (0x1U)
-#define SCT_INPUT_AIN0_SHIFT (0U)
+
+#define SCT_INPUT_AIN0_MASK (0x1U)
+#define SCT_INPUT_AIN0_SHIFT (0U)
/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
-#define SCT_INPUT_AIN1_MASK (0x2U)
-#define SCT_INPUT_AIN1_SHIFT (1U)
+#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+
+#define SCT_INPUT_AIN1_MASK (0x2U)
+#define SCT_INPUT_AIN1_SHIFT (1U)
/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
-#define SCT_INPUT_AIN2_MASK (0x4U)
-#define SCT_INPUT_AIN2_SHIFT (2U)
+#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+
+#define SCT_INPUT_AIN2_MASK (0x4U)
+#define SCT_INPUT_AIN2_SHIFT (2U)
/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
-#define SCT_INPUT_AIN3_MASK (0x8U)
-#define SCT_INPUT_AIN3_SHIFT (3U)
+#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+
+#define SCT_INPUT_AIN3_MASK (0x8U)
+#define SCT_INPUT_AIN3_SHIFT (3U)
/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
-#define SCT_INPUT_AIN4_MASK (0x10U)
-#define SCT_INPUT_AIN4_SHIFT (4U)
+#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+
+#define SCT_INPUT_AIN4_MASK (0x10U)
+#define SCT_INPUT_AIN4_SHIFT (4U)
/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
-#define SCT_INPUT_AIN5_MASK (0x20U)
-#define SCT_INPUT_AIN5_SHIFT (5U)
+#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+
+#define SCT_INPUT_AIN5_MASK (0x20U)
+#define SCT_INPUT_AIN5_SHIFT (5U)
/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
-#define SCT_INPUT_AIN6_MASK (0x40U)
-#define SCT_INPUT_AIN6_SHIFT (6U)
+#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+
+#define SCT_INPUT_AIN6_MASK (0x40U)
+#define SCT_INPUT_AIN6_SHIFT (6U)
/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
-#define SCT_INPUT_AIN7_MASK (0x80U)
-#define SCT_INPUT_AIN7_SHIFT (7U)
+#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+
+#define SCT_INPUT_AIN7_MASK (0x80U)
+#define SCT_INPUT_AIN7_SHIFT (7U)
/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
-#define SCT_INPUT_AIN8_MASK (0x100U)
-#define SCT_INPUT_AIN8_SHIFT (8U)
+#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+
+#define SCT_INPUT_AIN8_MASK (0x100U)
+#define SCT_INPUT_AIN8_SHIFT (8U)
/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
-#define SCT_INPUT_AIN9_MASK (0x200U)
-#define SCT_INPUT_AIN9_SHIFT (9U)
+#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+
+#define SCT_INPUT_AIN9_MASK (0x200U)
+#define SCT_INPUT_AIN9_SHIFT (9U)
/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
-#define SCT_INPUT_AIN10_MASK (0x400U)
-#define SCT_INPUT_AIN10_SHIFT (10U)
+#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+
+#define SCT_INPUT_AIN10_MASK (0x400U)
+#define SCT_INPUT_AIN10_SHIFT (10U)
/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
-#define SCT_INPUT_AIN11_MASK (0x800U)
-#define SCT_INPUT_AIN11_SHIFT (11U)
+#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+
+#define SCT_INPUT_AIN11_MASK (0x800U)
+#define SCT_INPUT_AIN11_SHIFT (11U)
/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
-#define SCT_INPUT_AIN12_MASK (0x1000U)
-#define SCT_INPUT_AIN12_SHIFT (12U)
+#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+
+#define SCT_INPUT_AIN12_MASK (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT (12U)
/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
-#define SCT_INPUT_AIN13_MASK (0x2000U)
-#define SCT_INPUT_AIN13_SHIFT (13U)
+#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+
+#define SCT_INPUT_AIN13_MASK (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT (13U)
/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
-#define SCT_INPUT_AIN14_MASK (0x4000U)
-#define SCT_INPUT_AIN14_SHIFT (14U)
+#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+
+#define SCT_INPUT_AIN14_MASK (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT (14U)
/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
-#define SCT_INPUT_AIN15_MASK (0x8000U)
-#define SCT_INPUT_AIN15_SHIFT (15U)
+#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+
+#define SCT_INPUT_AIN15_MASK (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT (15U)
/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
*/
-#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
-#define SCT_INPUT_SIN0_MASK (0x10000U)
-#define SCT_INPUT_SIN0_SHIFT (16U)
+#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+
+#define SCT_INPUT_SIN0_MASK (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT (16U)
/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
-#define SCT_INPUT_SIN1_MASK (0x20000U)
-#define SCT_INPUT_SIN1_SHIFT (17U)
+#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+
+#define SCT_INPUT_SIN1_MASK (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT (17U)
/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
-#define SCT_INPUT_SIN2_MASK (0x40000U)
-#define SCT_INPUT_SIN2_SHIFT (18U)
+#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+
+#define SCT_INPUT_SIN2_MASK (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT (18U)
/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
-#define SCT_INPUT_SIN3_MASK (0x80000U)
-#define SCT_INPUT_SIN3_SHIFT (19U)
+#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+
+#define SCT_INPUT_SIN3_MASK (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT (19U)
/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
-#define SCT_INPUT_SIN4_MASK (0x100000U)
-#define SCT_INPUT_SIN4_SHIFT (20U)
+#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+
+#define SCT_INPUT_SIN4_MASK (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT (20U)
/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
-#define SCT_INPUT_SIN5_MASK (0x200000U)
-#define SCT_INPUT_SIN5_SHIFT (21U)
+#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+
+#define SCT_INPUT_SIN5_MASK (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT (21U)
/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
-#define SCT_INPUT_SIN6_MASK (0x400000U)
-#define SCT_INPUT_SIN6_SHIFT (22U)
+#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+
+#define SCT_INPUT_SIN6_MASK (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT (22U)
/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
-#define SCT_INPUT_SIN7_MASK (0x800000U)
-#define SCT_INPUT_SIN7_SHIFT (23U)
+#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+
+#define SCT_INPUT_SIN7_MASK (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT (23U)
/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
-#define SCT_INPUT_SIN8_MASK (0x1000000U)
-#define SCT_INPUT_SIN8_SHIFT (24U)
+#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+
+#define SCT_INPUT_SIN8_MASK (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT (24U)
/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
-#define SCT_INPUT_SIN9_MASK (0x2000000U)
-#define SCT_INPUT_SIN9_SHIFT (25U)
+#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+
+#define SCT_INPUT_SIN9_MASK (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT (25U)
/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
-#define SCT_INPUT_SIN10_MASK (0x4000000U)
-#define SCT_INPUT_SIN10_SHIFT (26U)
+#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+
+#define SCT_INPUT_SIN10_MASK (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT (26U)
/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
-#define SCT_INPUT_SIN11_MASK (0x8000000U)
-#define SCT_INPUT_SIN11_SHIFT (27U)
+#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+
+#define SCT_INPUT_SIN11_MASK (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT (27U)
/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
-#define SCT_INPUT_SIN12_MASK (0x10000000U)
-#define SCT_INPUT_SIN12_SHIFT (28U)
+#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+
+#define SCT_INPUT_SIN12_MASK (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT (28U)
/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
-#define SCT_INPUT_SIN13_MASK (0x20000000U)
-#define SCT_INPUT_SIN13_SHIFT (29U)
+#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+
+#define SCT_INPUT_SIN13_MASK (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT (29U)
/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
-#define SCT_INPUT_SIN14_MASK (0x40000000U)
-#define SCT_INPUT_SIN14_SHIFT (30U)
+#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+
+#define SCT_INPUT_SIN14_MASK (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT (30U)
/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
-#define SCT_INPUT_SIN15_MASK (0x80000000U)
-#define SCT_INPUT_SIN15_SHIFT (31U)
+#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+
+#define SCT_INPUT_SIN15_MASK (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT (31U)
/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
*/
-#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+/*! @} */
+
+/*! @name REGMODEL - SCT_REGMODEL register */
+/*! @{ */
+
+#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU)
+#define SCT_REGMODEL_REGMODEL_SHIFT (0U)
+#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK)
+/*! @} */
+
+/*! @name REGMODEH - SCT_REGMODEH register */
+/*! @{ */
+
+#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU)
+#define SCT_REGMODEH_REGMODEH_SHIFT (0U)
+#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK)
/*! @} */
/*! @name REGMODE - SCT match/capture mode register */
/*! @{ */
-#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
-#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
+
+#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1,
* etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
* match register. 1 = register operates as capture register.
*/
-#define SCT_REGMODE_REGMOD_L(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
-#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
-#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
+#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+
+#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit
* 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as
* match registers. 1 = register operates as capture registers.
*/
-#define SCT_REGMODE_REGMOD_H(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
/*! @} */
/*! @name OUTPUT - SCT output register */
/*! @{ */
-#define SCT_OUTPUT_OUT_MASK (0xFFFFU)
-#define SCT_OUTPUT_OUT_SHIFT (0U)
+
+#define SCT_OUTPUT_OUT_MASK (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT (0U)
/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the
* corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
* outputs in this SCT.
*/
-#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
/*! @} */
/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
/*! @{ */
-#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
-#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR0(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
-#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR1(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
-#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR2(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
-#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR3(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
-#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR4(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
-#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR5(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR6(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR7(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR8(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR9(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR10(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR11(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR12(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR13(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR14(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.
* 0b00..Set and clear do not depend on the direction of any counter.
* 0b01..Set and clear are reversed when counter L or the unified counter is counting down.
* 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
*/
-#define SCT_OUTPUTDIRCTRL_SETCLR15(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
/*! @} */
/*! @name RES - SCT conflict resolution register */
/*! @{ */
-#define SCT_RES_O0RES_MASK (0x3U)
-#define SCT_RES_O0RES_SHIFT (0U)
+
+#define SCT_RES_O0RES_MASK (0x3U)
+#define SCT_RES_O0RES_SHIFT (0U)
/*! O0RES - Effect of simultaneous set and clear on output 0.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR0 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
-#define SCT_RES_O1RES_MASK (0xCU)
-#define SCT_RES_O1RES_SHIFT (2U)
+#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+
+#define SCT_RES_O1RES_MASK (0xCU)
+#define SCT_RES_O1RES_SHIFT (2U)
/*! O1RES - Effect of simultaneous set and clear on output 1.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR1 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
-#define SCT_RES_O2RES_MASK (0x30U)
-#define SCT_RES_O2RES_SHIFT (4U)
+#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+
+#define SCT_RES_O2RES_MASK (0x30U)
+#define SCT_RES_O2RES_SHIFT (4U)
/*! O2RES - Effect of simultaneous set and clear on output 2.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output n (or set based on the SETCLR2 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
-#define SCT_RES_O3RES_MASK (0xC0U)
-#define SCT_RES_O3RES_SHIFT (6U)
+#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+
+#define SCT_RES_O3RES_MASK (0xC0U)
+#define SCT_RES_O3RES_SHIFT (6U)
/*! O3RES - Effect of simultaneous set and clear on output 3.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR3 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
-#define SCT_RES_O4RES_MASK (0x300U)
-#define SCT_RES_O4RES_SHIFT (8U)
+#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+
+#define SCT_RES_O4RES_MASK (0x300U)
+#define SCT_RES_O4RES_SHIFT (8U)
/*! O4RES - Effect of simultaneous set and clear on output 4.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR4 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
-#define SCT_RES_O5RES_MASK (0xC00U)
-#define SCT_RES_O5RES_SHIFT (10U)
+#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+
+#define SCT_RES_O5RES_MASK (0xC00U)
+#define SCT_RES_O5RES_SHIFT (10U)
/*! O5RES - Effect of simultaneous set and clear on output 5.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR5 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
-#define SCT_RES_O6RES_MASK (0x3000U)
-#define SCT_RES_O6RES_SHIFT (12U)
+#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+
+#define SCT_RES_O6RES_MASK (0x3000U)
+#define SCT_RES_O6RES_SHIFT (12U)
/*! O6RES - Effect of simultaneous set and clear on output 6.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR6 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
-#define SCT_RES_O7RES_MASK (0xC000U)
-#define SCT_RES_O7RES_SHIFT (14U)
+#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+
+#define SCT_RES_O7RES_MASK (0xC000U)
+#define SCT_RES_O7RES_SHIFT (14U)
/*! O7RES - Effect of simultaneous set and clear on output 7.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output n (or set based on the SETCLR7 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
-#define SCT_RES_O8RES_MASK (0x30000U)
-#define SCT_RES_O8RES_SHIFT (16U)
+#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+
+#define SCT_RES_O8RES_MASK (0x30000U)
+#define SCT_RES_O8RES_SHIFT (16U)
/*! O8RES - Effect of simultaneous set and clear on output 8.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR8 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
-#define SCT_RES_O9RES_MASK (0xC0000U)
-#define SCT_RES_O9RES_SHIFT (18U)
+#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+
+#define SCT_RES_O9RES_MASK (0xC0000U)
+#define SCT_RES_O9RES_SHIFT (18U)
/*! O9RES - Effect of simultaneous set and clear on output 9.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR9 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
-#define SCT_RES_O10RES_MASK (0x300000U)
-#define SCT_RES_O10RES_SHIFT (20U)
+#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+
+#define SCT_RES_O10RES_MASK (0x300000U)
+#define SCT_RES_O10RES_SHIFT (20U)
/*! O10RES - Effect of simultaneous set and clear on output 10.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR10 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
-#define SCT_RES_O11RES_MASK (0xC00000U)
-#define SCT_RES_O11RES_SHIFT (22U)
+#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+
+#define SCT_RES_O11RES_MASK (0xC00000U)
+#define SCT_RES_O11RES_SHIFT (22U)
/*! O11RES - Effect of simultaneous set and clear on output 11.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR11 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
-#define SCT_RES_O12RES_MASK (0x3000000U)
-#define SCT_RES_O12RES_SHIFT (24U)
+#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+
+#define SCT_RES_O12RES_MASK (0x3000000U)
+#define SCT_RES_O12RES_SHIFT (24U)
/*! O12RES - Effect of simultaneous set and clear on output 12.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR12 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
-#define SCT_RES_O13RES_MASK (0xC000000U)
-#define SCT_RES_O13RES_SHIFT (26U)
+#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+
+#define SCT_RES_O13RES_MASK (0xC000000U)
+#define SCT_RES_O13RES_SHIFT (26U)
/*! O13RES - Effect of simultaneous set and clear on output 13.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR13 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
-#define SCT_RES_O14RES_MASK (0x30000000U)
-#define SCT_RES_O14RES_SHIFT (28U)
+#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+
+#define SCT_RES_O14RES_MASK (0x30000000U)
+#define SCT_RES_O14RES_SHIFT (28U)
/*! O14RES - Effect of simultaneous set and clear on output 14.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR14 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
-#define SCT_RES_O15RES_MASK (0xC0000000U)
-#define SCT_RES_O15RES_SHIFT (30U)
+#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+
+#define SCT_RES_O15RES_MASK (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT (30U)
/*! O15RES - Effect of simultaneous set and clear on output 15.
* 0b00..No change.
* 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).
* 0b10..Clear output (or set based on the SETCLR15 field).
* 0b11..Toggle output.
*/
-#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
/*! @} */
/*! @name DMAREQ0 - SCT DMA request 0 register */
/*! @{ */
-#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU)
-#define SCT_DMAREQ0_DEV_0_SHIFT (0U)
+
+#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU)
+#define SCT_DMAREQ0_DEV_0_SHIFT (0U)
/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1,
* etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
-#define SCT_DMAREQ0_DRL0_MASK (0x40000000U)
-#define SCT_DMAREQ0_DRL0_SHIFT (30U)
-/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified
- * registers.
+#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
+
+#define SCT_DMAREQ0_DRL0_MASK (0x40000000U)
+#define SCT_DMAREQ0_DRL0_SHIFT (30U)
+/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
*/
-#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
-#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)
-#define SCT_DMAREQ0_DRQ0_SHIFT (31U)
+#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
+
+#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U)
+#define SCT_DMAREQ0_DRQ0_SHIFT (31U)
/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
* channel is enabled and properly set up, it is unlikely that software will see this flag, it will
* be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
* setup.
*/
-#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
+#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
/*! @} */
/*! @name DMAREQ1 - SCT DMA request 1 register */
/*! @{ */
-#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU)
-#define SCT_DMAREQ1_DEV_1_SHIFT (0U)
+
+#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU)
+#define SCT_DMAREQ1_DEV_1_SHIFT (0U)
/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1,
* etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
-#define SCT_DMAREQ1_DRL1_MASK (0x40000000U)
-#define SCT_DMAREQ1_DRL1_SHIFT (30U)
-/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified
- * registers.
+#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
+
+#define SCT_DMAREQ1_DRL1_MASK (0x40000000U)
+#define SCT_DMAREQ1_DRL1_SHIFT (30U)
+/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
*/
-#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
-#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)
-#define SCT_DMAREQ1_DRQ1_SHIFT (31U)
+#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
+
+#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U)
+#define SCT_DMAREQ1_DRQ1_SHIFT (31U)
/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
* channel is enabled and properly set up, it is unlikely that software will see this flag, it will
* be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA
* setup.
*/
-#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
+#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
/*! @} */
/*! @name EVEN - SCT event interrupt enable register */
/*! @{ */
-#define SCT_EVEN_IEN_MASK (0xFFFFU)
-#define SCT_EVEN_IEN_SHIFT (0U)
+
+#define SCT_EVEN_IEN_MASK (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT (0U)
/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are
* both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in
* this SCT.
*/
-#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
/*! @} */
/*! @name EVFLAG - SCT event flag register */
/*! @{ */
-#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
-#define SCT_EVFLAG_FLAG_SHIFT (0U)
+
+#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT (0U)
/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit
* (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
*/
-#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
/*! @} */
/*! @name CONEN - SCT conflict interrupt enable register */
/*! @{ */
-#define SCT_CONEN_NCEN_MASK (0xFFFFU)
-#define SCT_CONEN_NCEN_SHIFT (0U)
+
+#define SCT_CONEN_NCEN_MASK (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT (0U)
/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag
* register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of
* outputs in this SCT.
*/
-#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
/*! @} */
/*! @name CONFLAG - SCT conflict flag register */
/*! @{ */
-#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
-#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
+
+#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was
* last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits =
* number of outputs in this SCT.
*/
-#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
-#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
-#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
+#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+
+#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE
* L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write
* to certain L and H registers can be half successful and half unsuccessful.
*/
-#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
-#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
-#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
+#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+
+#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or
* the Output register when the H counter was not halted.
*/
-#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
/*! @} */
+/*! @name CAPL - SCT_CAPL register */
+/*! @{ */
+
+#define SCT_CAPL_CAPL_MASK (0xFFFFU)
+#define SCT_CAPL_CAPL_SHIFT (0U)
+#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPL */
+#define SCT_CAPL_COUNT (16U)
+
+/*! @name CAPH - SCT_CAPH register */
+/*! @{ */
+
+#define SCT_CAPH_CAPH_MASK (0xFFFFU)
+#define SCT_CAPH_CAPH_SHIFT (0U)
+#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK)
+/*! @} */
+
+/* The count of SCT_CAPH */
+#define SCT_CAPH_COUNT (16U)
+
/*! @name CAP - SCT capture register of capture channel */
/*! @{ */
-#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
-#define SCT_CAP_CAPn_L_SHIFT (0U)
+
+#define SCT_CAP_CAPn_L_MASK (0xFFFFU)
+#define SCT_CAP_CAPn_L_SHIFT (0U)
/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
* When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last
* captured.
*/
-#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
-#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
-#define SCT_CAP_CAPn_H_SHIFT (16U)
+#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
+
+#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U)
+#define SCT_CAP_CAPn_H_SHIFT (16U)
/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured.
* When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last
* captured.
*/
-#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
+#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
/*! @} */
/* The count of SCT_CAP */
-#define SCT_CAP_COUNT (16U)
+#define SCT_CAP_COUNT (16U)
+
+/*! @name MATCHL - SCT_MATCHL register */
+/*! @{ */
+
+#define SCT_MATCHL_MATCHL_MASK (0xFFFFU)
+#define SCT_MATCHL_MATCHL_SHIFT (0U)
+#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHL */
+#define SCT_MATCHL_COUNT (16U)
+
+/*! @name MATCHH - SCT_MATCHH register */
+/*! @{ */
+
+#define SCT_MATCHH_MATCHH_MASK (0xFFFFU)
+#define SCT_MATCHH_MATCHH_SHIFT (0U)
+#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHH */
+#define SCT_MATCHH_COUNT (16U)
/*! @name MATCH - SCT match value register of match channels */
/*! @{ */
-#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
-#define SCT_MATCH_MATCHn_L_SHIFT (0U)
+
+#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU)
+#define SCT_MATCH_MATCHn_L_SHIFT (0U)
/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When
* UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified
* counter.
*/
-#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
-#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
-#define SCT_MATCH_MATCHn_H_SHIFT (16U)
+#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
+
+#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U)
+#define SCT_MATCH_MATCHn_H_SHIFT (16U)
/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When
* UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified
* counter.
*/
-#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
+#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
+/*! @} */
+
+/* The count of SCT_MATCH */
+#define SCT_MATCH_COUNT (16U)
+
+/*! @name CAPCTRLL - SCT_CAPCTRLL register */
+/*! @{ */
+
+#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU)
+#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U)
+#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK)
+/*! @} */
+
+/* The count of SCT_CAPCTRLL */
+#define SCT_CAPCTRLL_COUNT (16U)
+
+/*! @name CAPCTRLH - SCT_CAPCTRLH register */
+/*! @{ */
+
+#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU)
+#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U)
+#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK)
/*! @} */
-/* The count of SCT_MATCH */
-#define SCT_MATCH_COUNT (16U)
+/* The count of SCT_CAPCTRLH */
+#define SCT_CAPCTRLH_COUNT (16U)
/*! @name CAPCTRL - SCT capture control register */
/*! @{ */
-#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
-#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
+
+#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU)
+#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U)
/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1)
* register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of
* match/captures in this SCT.
*/
-#define SCT_CAPCTRL_CAPCONn_L(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
-#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
-#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
+#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
+
+#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
+#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U)
/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event
* 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT.
*/
-#define SCT_CAPCTRL_CAPCONn_H(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
+#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
/*! @} */
/* The count of SCT_CAPCTRL */
-#define SCT_CAPCTRL_COUNT (16U)
+#define SCT_CAPCTRL_COUNT (16U)
+
+/*! @name MATCHRELL - SCT_MATCHRELL register */
+/*! @{ */
+
+#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU)
+#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U)
+#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELL */
+#define SCT_MATCHRELL_COUNT (16U)
+
+/*! @name MATCHRELH - SCT_MATCHRELH register */
+/*! @{ */
+
+#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU)
+#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U)
+#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK)
+/*! @} */
+
+/* The count of SCT_MATCHRELH */
+#define SCT_MATCHRELH_COUNT (16U)
/*! @name MATCHREL - SCT match reload value register */
/*! @{ */
-#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
-#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
+
+#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU)
+#define SCT_MATCHREL_RELOADn_L_SHIFT (0U)
/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register.
* When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn
* register.
*/
-#define SCT_MATCHREL_RELOADn_L(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
-#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
-#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
+#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
+
+#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U)
+#define SCT_MATCHREL_RELOADn_H_SHIFT (16U)
/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When
* UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn
* register.
*/
-#define SCT_MATCHREL_RELOADn_H(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
+#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
/*! @} */
/* The count of SCT_MATCHREL */
-#define SCT_MATCHREL_COUNT (16U)
+#define SCT_MATCHREL_COUNT (16U)
/*! @name EV_STATE - SCT event state register 0 */
/*! @{ */
-#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU)
-#define SCT_EV_STATE_STATEMSKn_SHIFT (0U)
+
+#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU)
+#define SCT_EV_STATE_STATEMSKn_SHIFT (0U)
/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT
* bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of
* bits = number of states in this SCT.
*/
-#define SCT_EV_STATE_STATEMSKn(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
+#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
/*! @} */
/* The count of SCT_EV_STATE */
-#define SCT_EV_STATE_COUNT (16U)
+#define SCT_EV_STATE_COUNT (16U)
/*! @name EV_CTRL - SCT event control register 0 */
/*! @{ */
-#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
-#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
+
+#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU)
+#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U)
/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur
* only when the counter selected by the HEVENT bit is running.
*/
-#define SCT_EV_CTRL_MATCHSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
-#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
-#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
+#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
+
+#define SCT_EV_CTRL_HEVENT_MASK (0x10U)
+#define SCT_EV_CTRL_HEVENT_SHIFT (4U)
/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.
* 0b0..Selects the L state and the L match register selected by MATCHSEL.
* 0b1..Selects the H state and the H match register selected by MATCHSEL.
*/
-#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
-#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
-#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
+#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
+
+#define SCT_EV_CTRL_OUTSEL_MASK (0x20U)
+#define SCT_EV_CTRL_OUTSEL_SHIFT (5U)
/*! OUTSEL - Input/output select
* 0b0..Selects the inputs selected by IOSEL.
* 0b1..Selects the outputs selected by IOSEL.
*/
-#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
-#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
-#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
+#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
+
+#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U)
+#define SCT_EV_CTRL_IOSEL_SHIFT (6U)
/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not
* select an input in this register if CKMODE is 1x. In this case the clock input is an implicit
* ingredient of every event.
*/
-#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
-#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
-#define SCT_EV_CTRL_IOCOND_SHIFT (10U)
+#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
+
+#define SCT_EV_CTRL_IOCOND_MASK (0xC00U)
+#define SCT_EV_CTRL_IOCOND_SHIFT (10U)
/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the
* conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state
* detection, an input must have a minimum pulse width of at least one SCT clock period .
@@ -18832,147 +18455,133 @@ typedef struct
* 0b10..Fall
* 0b11..HIGH
*/
-#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
-#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
-#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
+#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
+
+#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U)
+#define SCT_EV_CTRL_COMBMODE_SHIFT (12U)
/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.
* 0b00..OR. The event occurs when either the specified match or I/O condition occurs.
* 0b01..MATCH. Uses the specified match only.
* 0b10..IO. Uses the specified I/O condition only.
* 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
*/
-#define SCT_EV_CTRL_COMBMODE(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
-#define SCT_EV_CTRL_STATELD_MASK (0x4000U)
-#define SCT_EV_CTRL_STATELD_SHIFT (14U)
+#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
+
+#define SCT_EV_CTRL_STATELD_MASK (0x4000U)
+#define SCT_EV_CTRL_STATELD_SHIFT (14U)
/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this
* event is the highest-numbered event occurring for that state.
* 0b0..STATEV value is added into STATE (the carry-out is ignored).
* 0b1..STATEV value is loaded into STATE.
*/
-#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
-#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
-#define SCT_EV_CTRL_STATEV_SHIFT (15U)
+#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
+
+#define SCT_EV_CTRL_STATEV_MASK (0xF8000U)
+#define SCT_EV_CTRL_STATEV_SHIFT (15U)
/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on
* STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and
* STATEV are both zero, there is no change to the STATE value.
*/
-#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
-#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
-#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
+#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
+
+#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U)
+#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U)
/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the
* triggering of this event, then a match is considered to be active whenever the counter value is
* GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR
* EQUAL TO the match value when counting down. If this bit is zero, a match is only be active
* during the cycle when the counter is equal to the match value.
*/
-#define SCT_EV_CTRL_MATCHMEM(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
-#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
-#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
+#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
+
+#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U)
+#define SCT_EV_CTRL_DIRECTION_SHIFT (21U)
/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters
* are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.
* 0b00..Direction independent. This event is triggered regardless of the count direction.
* 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
* 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
*/
-#define SCT_EV_CTRL_DIRECTION(x) \
- (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
+#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
/*! @} */
/* The count of SCT_EV_CTRL */
-#define SCT_EV_CTRL_COUNT (16U)
+#define SCT_EV_CTRL_COUNT (16U)
/*! @name OUT_SET - SCT output 0 set register */
/*! @{ */
-#define SCT_OUT_SET_SET_MASK (0xFFFFU)
-#define SCT_OUT_SET_SET_SHIFT (0U)
+
+#define SCT_OUT_SET_SET_MASK (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT (0U)
/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output
* 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
* counter is used in bi-directional mode, it is possible to reverse the action specified by the
* output set and clear registers when counting down, See the OUTPUTCTRL register.
*/
-#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
/*! @} */
/* The count of SCT_OUT_SET */
-#define SCT_OUT_SET_COUNT (10U)
+#define SCT_OUT_SET_COUNT (10U)
/*! @name OUT_CLR - SCT output 0 clear register */
/*! @{ */
-#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
-#define SCT_OUT_CLR_CLR_SHIFT (0U)
+
+#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT (0U)
/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0
* = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the
* counter is used in bi-directional mode, it is possible to reverse the action specified by the
* output set and clear registers when counting down, See the OUTPUTCTRL register.
*/
-#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
/*! @} */
/* The count of SCT_OUT_CLR */
-#define SCT_OUT_CLR_COUNT (10U)
+#define SCT_OUT_CLR_COUNT (10U)
+
/*!
* @}
*/ /* end of group SCT_Register_Masks */
+
/* SCT - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral SCT0 base address */
-#define SCT0_BASE (0x50085000u)
-/** Peripheral SCT0 base address */
-#define SCT0_BASE_NS (0x40085000u)
-/** Peripheral SCT0 base pointer */
-#define SCT0 ((SCT_Type *)SCT0_BASE)
-/** Peripheral SCT0 base pointer */
-#define SCT0_NS ((SCT_Type *)SCT0_BASE_NS)
-/** Array initializer of SCT peripheral base addresses */
-#define SCT_BASE_ADDRS \
- { \
- SCT0_BASE \
- }
-/** Array initializer of SCT peripheral base pointers */
-#define SCT_BASE_PTRS \
- { \
- SCT0 \
- }
-/** Array initializer of SCT peripheral base addresses */
-#define SCT_BASE_ADDRS_NS \
- { \
- SCT0_BASE_NS \
- }
-/** Array initializer of SCT peripheral base pointers */
-#define SCT_BASE_PTRS_NS \
- { \
- SCT0_NS \
- }
+ /** Peripheral SCT0 base address */
+ #define SCT0_BASE (0x50085000u)
+ /** Peripheral SCT0 base address */
+ #define SCT0_BASE_NS (0x40085000u)
+ /** Peripheral SCT0 base pointer */
+ #define SCT0 ((SCT_Type *)SCT0_BASE)
+ /** Peripheral SCT0 base pointer */
+ #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS)
+ /** Array initializer of SCT peripheral base addresses */
+ #define SCT_BASE_ADDRS { SCT0_BASE }
+ /** Array initializer of SCT peripheral base pointers */
+ #define SCT_BASE_PTRS { SCT0 }
+ /** Array initializer of SCT peripheral base addresses */
+ #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS }
+ /** Array initializer of SCT peripheral base pointers */
+ #define SCT_BASE_PTRS_NS { SCT0_NS }
#else
-/** Peripheral SCT0 base address */
-#define SCT0_BASE (0x40085000u)
-/** Peripheral SCT0 base pointer */
-#define SCT0 ((SCT_Type *)SCT0_BASE)
-/** Array initializer of SCT peripheral base addresses */
-#define SCT_BASE_ADDRS \
- { \
- SCT0_BASE \
- }
-/** Array initializer of SCT peripheral base pointers */
-#define SCT_BASE_PTRS \
- { \
- SCT0 \
- }
+ /** Peripheral SCT0 base address */
+ #define SCT0_BASE (0x40085000u)
+ /** Peripheral SCT0 base pointer */
+ #define SCT0 ((SCT_Type *)SCT0_BASE)
+ /** Array initializer of SCT peripheral base addresses */
+ #define SCT_BASE_ADDRS { SCT0_BASE }
+ /** Array initializer of SCT peripheral base pointers */
+ #define SCT_BASE_PTRS { SCT0 }
#endif
/** Interrupt vectors for the SCT peripheral type */
-#define SCT_IRQS \
- { \
- SCT0_IRQn \
- }
+#define SCT_IRQS { SCT0_IRQn }
/*!
* @}
*/ /* end of group SCT_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- SDIF Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -18983,46 +18592,45 @@ typedef struct
*/
/** SDIF - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
- __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */
- __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */
- __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */
- __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */
- __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */
- __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */
- __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */
- __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */
- __IO uint32_t CMD; /**< Command register, offset: 0x2C */
- __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */
- __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */
- __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */
- __IO uint32_t STATUS; /**< Status register, offset: 0x48 */
- __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */
- __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */
- __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */
- uint8_t RESERVED_1[4];
- __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */
- __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
- __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */
- uint8_t RESERVED_2[16];
- __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */
- uint8_t RESERVED_3[4];
- __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */
- __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */
- __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */
- __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */
- __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
- __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */
- __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */
- uint8_t RESERVED_4[100];
- __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */
- __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */
- uint8_t RESERVED_5[248];
- __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
+ __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */
+ __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */
+ __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */
+ __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */
+ __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */
+ __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */
+ __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */
+ __IO uint32_t CMD; /**< Command register, offset: 0x2C */
+ __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */
+ __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */
+ __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */
+ __IO uint32_t STATUS; /**< Status register, offset: 0x48 */
+ __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */
+ __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */
+ __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */
+ __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
+ __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */
+ __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */
+ __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */
+ __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */
+ __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
+ __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */
+ __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */
+ uint8_t RESERVED_4[100];
+ __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */
+ __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */
+ uint8_t RESERVED_5[248];
+ __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
} SDIF_Type;
/* ----------------------------------------------------------------------------
@@ -19036,1066 +18644,1129 @@ typedef struct
/*! @name CTRL - Control register */
/*! @{ */
-#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)
-#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)
+
+#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)
/*! CONTROLLER_RESET - Controller reset.
*/
-#define SDIF_CTRL_CONTROLLER_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
-#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)
-#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)
+#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+
+#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)
/*! FIFO_RESET - Fifo reset.
*/
-#define SDIF_CTRL_FIFO_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
-#define SDIF_CTRL_DMA_RESET_MASK (0x4U)
-#define SDIF_CTRL_DMA_RESET_SHIFT (2U)
+#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+
+#define SDIF_CTRL_DMA_RESET_MASK (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT (2U)
/*! DMA_RESET - DMA reset.
*/
-#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
-#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)
-#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)
+#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+
+#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)
/*! INT_ENABLE - Global interrupt enable/disable bit.
*/
-#define SDIF_CTRL_INT_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
-#define SDIF_CTRL_READ_WAIT_MASK (0x40U)
-#define SDIF_CTRL_READ_WAIT_SHIFT (6U)
+#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+
+#define SDIF_CTRL_READ_WAIT_MASK (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT (6U)
/*! READ_WAIT - Read/wait.
*/
-#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)
+#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)
/*! SEND_IRQ_RESPONSE - Send irq response.
*/
-#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
-#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)
-#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+
+#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)
/*! ABORT_READ_DATA - Abort read data.
*/
-#define SDIF_CTRL_ABORT_READ_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
-#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)
-#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)
+#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+
+#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)
/*! SEND_CCSD - Send ccsd.
*/
-#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)
+#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)
/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd.
*/
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+
#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status.
*/
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & \
- SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)
/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin.
*/
-#define SDIF_CTRL_CARD_VOLTAGE_A0(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)
/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin.
*/
-#define SDIF_CTRL_CARD_VOLTAGE_A1(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)
/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin.
*/
-#define SDIF_CTRL_CARD_VOLTAGE_A2(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
-#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)
-#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)
/*! USE_INTERNAL_DMAC - SD/MMC DMA use.
*/
-#define SDIF_CTRL_USE_INTERNAL_DMAC(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
/*! @} */
/*! @name PWREN - Power Enable register */
/*! @{ */
-#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U)
-#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U)
+
+#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U)
+#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U)
/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait
* for regulator/switch ramp-up time before trying to initialize card 0.
*/
-#define SDIF_PWREN_POWER_ENABLE0(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK)
-#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U)
-#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U)
+#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK)
+
+#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U)
+#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U)
/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait
* for regulator/switch ramp-up time before trying to initialize card 1.
*/
-#define SDIF_PWREN_POWER_ENABLE1(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK)
+#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK)
/*! @} */
/*! @name CLKDIV - Clock Divider register */
/*! @{ */
-#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)
-#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)
+
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)
/*! CLK_DIVIDER0 - Clock divider-0 value.
*/
-#define SDIF_CLKDIV_CLK_DIVIDER0(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
/*! @} */
/*! @name CLKENA - Clock Enable register */
/*! @{ */
-#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U)
-#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U)
+
+#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U)
+#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U)
/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock.
*/
-#define SDIF_CLKENA_CCLK0_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK)
-#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U)
-#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U)
+#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK)
+
+#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U)
+#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U)
/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock.
*/
-#define SDIF_CLKENA_CCLK1_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK)
-#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U)
-#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U)
+#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK)
+
+#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U)
+#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U)
/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock.
*/
-#define SDIF_CLKENA_CCLK0_LOW_POWER(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK)
-#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U)
-#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U)
+#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK)
+
+#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U)
+#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U)
/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock.
*/
-#define SDIF_CLKENA_CCLK1_LOW_POWER(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK)
+#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK)
/*! @} */
/*! @name TMOUT - Time-out register */
/*! @{ */
-#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)
-#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)
+
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)
/*! RESPONSE_TIMEOUT - Response time-out value.
*/
-#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
-#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)
-#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)
/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out.
*/
-#define SDIF_TMOUT_DATA_TIMEOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
/*! @} */
/*! @name CTYPE - Card Type register */
/*! @{ */
-#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U)
-#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U)
+
+#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U)
+#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U)
/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
* modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set
* to 0).
*/
-#define SDIF_CTYPE_CARD0_WIDTH0(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK)
-#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U)
-#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U)
+#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK)
+
+#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U)
+#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U)
/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit
* modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set
* to 0).
*/
-#define SDIF_CTYPE_CARD1_WIDTH0(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK)
-#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U)
-#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U)
+#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK)
+
+#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U)
+#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U)
/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
*/
-#define SDIF_CTYPE_CARD0_WIDTH1(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK)
-#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U)
-#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U)
+#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK)
+
+#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U)
+#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U)
/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode.
*/
-#define SDIF_CTYPE_CARD1_WIDTH1(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK)
+#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK)
/*! @} */
/*! @name BLKSIZ - Block Size register */
/*! @{ */
-#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)
-#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)
+
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)
/*! BLOCK_SIZE - Block size.
*/
-#define SDIF_BLKSIZ_BLOCK_SIZE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
/*! @} */
/*! @name BYTCNT - Byte Count register */
/*! @{ */
-#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)
-#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)
+
+#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)
/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers.
*/
-#define SDIF_BYTCNT_BYTE_COUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
/*! @} */
/*! @name INTMASK - Interrupt Mask register */
/*! @{ */
-#define SDIF_INTMASK_CDET_MASK (0x1U)
-#define SDIF_INTMASK_CDET_SHIFT (0U)
+
+#define SDIF_INTMASK_CDET_MASK (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT (0U)
/*! CDET - Card detect.
*/
-#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
-#define SDIF_INTMASK_RE_MASK (0x2U)
-#define SDIF_INTMASK_RE_SHIFT (1U)
+#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+
+#define SDIF_INTMASK_RE_MASK (0x2U)
+#define SDIF_INTMASK_RE_SHIFT (1U)
/*! RE - Response error.
*/
-#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
-#define SDIF_INTMASK_CDONE_MASK (0x4U)
-#define SDIF_INTMASK_CDONE_SHIFT (2U)
+#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+
+#define SDIF_INTMASK_CDONE_MASK (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT (2U)
/*! CDONE - Command done.
*/
-#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
-#define SDIF_INTMASK_DTO_MASK (0x8U)
-#define SDIF_INTMASK_DTO_SHIFT (3U)
+#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+
+#define SDIF_INTMASK_DTO_MASK (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT (3U)
/*! DTO - Data transfer over.
*/
-#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
-#define SDIF_INTMASK_TXDR_MASK (0x10U)
-#define SDIF_INTMASK_TXDR_SHIFT (4U)
+#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+
+#define SDIF_INTMASK_TXDR_MASK (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT (4U)
/*! TXDR - Transmit FIFO data request.
*/
-#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
-#define SDIF_INTMASK_RXDR_MASK (0x20U)
-#define SDIF_INTMASK_RXDR_SHIFT (5U)
+#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+
+#define SDIF_INTMASK_RXDR_MASK (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT (5U)
/*! RXDR - Receive FIFO data request.
*/
-#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
-#define SDIF_INTMASK_RCRC_MASK (0x40U)
-#define SDIF_INTMASK_RCRC_SHIFT (6U)
+#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+
+#define SDIF_INTMASK_RCRC_MASK (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT (6U)
/*! RCRC - Response CRC error.
*/
-#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
-#define SDIF_INTMASK_DCRC_MASK (0x80U)
-#define SDIF_INTMASK_DCRC_SHIFT (7U)
+#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+
+#define SDIF_INTMASK_DCRC_MASK (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT (7U)
/*! DCRC - Data CRC error.
*/
-#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
-#define SDIF_INTMASK_RTO_MASK (0x100U)
-#define SDIF_INTMASK_RTO_SHIFT (8U)
+#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+
+#define SDIF_INTMASK_RTO_MASK (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT (8U)
/*! RTO - Response time-out.
*/
-#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
-#define SDIF_INTMASK_DRTO_MASK (0x200U)
-#define SDIF_INTMASK_DRTO_SHIFT (9U)
+#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+
+#define SDIF_INTMASK_DRTO_MASK (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT (9U)
/*! DRTO - Data read time-out.
*/
-#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
-#define SDIF_INTMASK_HTO_MASK (0x400U)
-#define SDIF_INTMASK_HTO_SHIFT (10U)
+#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+
+#define SDIF_INTMASK_HTO_MASK (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT (10U)
/*! HTO - Data starvation-by-host time-out (HTO).
*/
-#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
-#define SDIF_INTMASK_FRUN_MASK (0x800U)
-#define SDIF_INTMASK_FRUN_SHIFT (11U)
+#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+
+#define SDIF_INTMASK_FRUN_MASK (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT (11U)
/*! FRUN - FIFO underrun/overrun error.
*/
-#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
-#define SDIF_INTMASK_HLE_MASK (0x1000U)
-#define SDIF_INTMASK_HLE_SHIFT (12U)
+#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+
+#define SDIF_INTMASK_HLE_MASK (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT (12U)
/*! HLE - Hardware locked write error.
*/
-#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
-#define SDIF_INTMASK_SBE_MASK (0x2000U)
-#define SDIF_INTMASK_SBE_SHIFT (13U)
+#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+
+#define SDIF_INTMASK_SBE_MASK (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT (13U)
/*! SBE - Start-bit error.
*/
-#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
-#define SDIF_INTMASK_ACD_MASK (0x4000U)
-#define SDIF_INTMASK_ACD_SHIFT (14U)
+#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+
+#define SDIF_INTMASK_ACD_MASK (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT (14U)
/*! ACD - Auto command done.
*/
-#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
-#define SDIF_INTMASK_EBE_MASK (0x8000U)
-#define SDIF_INTMASK_EBE_SHIFT (15U)
+#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+
+#define SDIF_INTMASK_EBE_MASK (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT (15U)
/*! EBE - End-bit error (read)/Write no CRC.
*/
-#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
-#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)
-#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)
+#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)
/*! SDIO_INT_MASK - Mask SDIO interrupt.
*/
-#define SDIF_INTMASK_SDIO_INT_MASK(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
/*! @} */
/*! @name CMDARG - Command Argument register */
/*! @{ */
-#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)
-#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)
+
+#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)
/*! CMD_ARG - Value indicates command argument to be passed to card.
*/
-#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
/*! @} */
/*! @name CMD - Command register */
/*! @{ */
-#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)
-#define SDIF_CMD_CMD_INDEX_SHIFT (0U)
+
+#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT (0U)
/*! CMD_INDEX - Command index.
*/
-#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
-#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)
-#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)
+#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+
+#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)
/*! RESPONSE_EXPECT - Response expect.
*/
-#define SDIF_CMD_RESPONSE_EXPECT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
-#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)
-#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)
+#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+
+#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)
/*! RESPONSE_LENGTH - Response length.
*/
-#define SDIF_CMD_RESPONSE_LENGTH(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
-#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)
-#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)
+#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)
/*! CHECK_RESPONSE_CRC - Check response CRC.
*/
-#define SDIF_CMD_CHECK_RESPONSE_CRC(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
-#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)
-#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+
+#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)
/*! DATA_EXPECTED - Data expected.
*/
-#define SDIF_CMD_DATA_EXPECTED(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
-#define SDIF_CMD_READ_WRITE_MASK (0x400U)
-#define SDIF_CMD_READ_WRITE_SHIFT (10U)
+#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+
+#define SDIF_CMD_READ_WRITE_MASK (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT (10U)
/*! READ_WRITE - read/write.
*/
-#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
-#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)
-#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)
+#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+
+#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)
/*! TRANSFER_MODE - Transfer mode.
*/
-#define SDIF_CMD_TRANSFER_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
-#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)
-#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)
+#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+
+#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)
/*! SEND_AUTO_STOP - Send auto stop.
*/
-#define SDIF_CMD_SEND_AUTO_STOP(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)
+#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)
/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete.
*/
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
-#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)
-#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+
+#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)
/*! STOP_ABORT_CMD - Stop abort command.
*/
-#define SDIF_CMD_STOP_ABORT_CMD(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
-#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)
-#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)
+#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+
+#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)
/*! SEND_INITIALIZATION - Send initialization.
*/
-#define SDIF_CMD_SEND_INITIALIZATION(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
-#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U)
-#define SDIF_CMD_CARD_NUMBER_SHIFT (16U)
+#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+
+#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U)
+#define SDIF_CMD_CARD_NUMBER_SHIFT (16U)
/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed
* 0b00000..Command will be execute on SDCARD 0
* 0b00001..Command will be execute on SDCARD 1
*/
-#define SDIF_CMD_CARD_NUMBER(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK)
+#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK)
+
#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only.
*/
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & \
- SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
-#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)
-#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)
/*! READ_CEATA_DEVICE - Read ceata device.
*/
-#define SDIF_CMD_READ_CEATA_DEVICE(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
-#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)
-#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)
+#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+
+#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)
/*! CCS_EXPECTED - CCS expected.
*/
-#define SDIF_CMD_CCS_EXPECTED(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
-#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)
-#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)
+#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+
+#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)
/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode.
*/
-#define SDIF_CMD_ENABLE_BOOT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
-#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)
-#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)
+#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)
/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge.
*/
-#define SDIF_CMD_EXPECT_BOOT_ACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
-#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)
-#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)
+#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+
+#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)
/*! DISABLE_BOOT - Disable Boot.
*/
-#define SDIF_CMD_DISABLE_BOOT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
-#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)
-#define SDIF_CMD_BOOT_MODE_SHIFT (27U)
+#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+
+#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT (27U)
/*! BOOT_MODE - Boot Mode.
*/
-#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
-#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)
-#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)
+#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+
+#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)
/*! VOLT_SWITCH - Voltage switch bit.
*/
-#define SDIF_CMD_VOLT_SWITCH(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
-#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)
-#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)
+#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+
+#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)
/*! USE_HOLD_REG - Use Hold Register.
*/
-#define SDIF_CMD_USE_HOLD_REG(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
-#define SDIF_CMD_START_CMD_MASK (0x80000000U)
-#define SDIF_CMD_START_CMD_SHIFT (31U)
+#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+
+#define SDIF_CMD_START_CMD_MASK (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT (31U)
/*! START_CMD - Start command.
*/
-#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
/*! @} */
/*! @name RESP - Response register */
/*! @{ */
-#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)
-#define SDIF_RESP_RESPONSE_SHIFT (0U)
+
+#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT (0U)
/*! RESPONSE - Bits of response.
*/
-#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
/*! @} */
/* The count of SDIF_RESP */
-#define SDIF_RESP_COUNT (4U)
+#define SDIF_RESP_COUNT (4U)
/*! @name MINTSTS - Masked Interrupt Status register */
/*! @{ */
-#define SDIF_MINTSTS_CDET_MASK (0x1U)
-#define SDIF_MINTSTS_CDET_SHIFT (0U)
+
+#define SDIF_MINTSTS_CDET_MASK (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT (0U)
/*! CDET - Card detect.
*/
-#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
-#define SDIF_MINTSTS_RE_MASK (0x2U)
-#define SDIF_MINTSTS_RE_SHIFT (1U)
+#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+
+#define SDIF_MINTSTS_RE_MASK (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT (1U)
/*! RE - Response error.
*/
-#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
-#define SDIF_MINTSTS_CDONE_MASK (0x4U)
-#define SDIF_MINTSTS_CDONE_SHIFT (2U)
+#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+
+#define SDIF_MINTSTS_CDONE_MASK (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT (2U)
/*! CDONE - Command done.
*/
-#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
-#define SDIF_MINTSTS_DTO_MASK (0x8U)
-#define SDIF_MINTSTS_DTO_SHIFT (3U)
+#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+
+#define SDIF_MINTSTS_DTO_MASK (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT (3U)
/*! DTO - Data transfer over.
*/
-#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
-#define SDIF_MINTSTS_TXDR_MASK (0x10U)
-#define SDIF_MINTSTS_TXDR_SHIFT (4U)
+#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+
+#define SDIF_MINTSTS_TXDR_MASK (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT (4U)
/*! TXDR - Transmit FIFO data request.
*/
-#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
-#define SDIF_MINTSTS_RXDR_MASK (0x20U)
-#define SDIF_MINTSTS_RXDR_SHIFT (5U)
+#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+
+#define SDIF_MINTSTS_RXDR_MASK (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT (5U)
/*! RXDR - Receive FIFO data request.
*/
-#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
-#define SDIF_MINTSTS_RCRC_MASK (0x40U)
-#define SDIF_MINTSTS_RCRC_SHIFT (6U)
+#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+
+#define SDIF_MINTSTS_RCRC_MASK (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT (6U)
/*! RCRC - Response CRC error.
*/
-#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
-#define SDIF_MINTSTS_DCRC_MASK (0x80U)
-#define SDIF_MINTSTS_DCRC_SHIFT (7U)
+#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+
+#define SDIF_MINTSTS_DCRC_MASK (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT (7U)
/*! DCRC - Data CRC error.
*/
-#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
-#define SDIF_MINTSTS_RTO_MASK (0x100U)
-#define SDIF_MINTSTS_RTO_SHIFT (8U)
+#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+
+#define SDIF_MINTSTS_RTO_MASK (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT (8U)
/*! RTO - Response time-out.
*/
-#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
-#define SDIF_MINTSTS_DRTO_MASK (0x200U)
-#define SDIF_MINTSTS_DRTO_SHIFT (9U)
+#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+
+#define SDIF_MINTSTS_DRTO_MASK (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT (9U)
/*! DRTO - Data read time-out.
*/
-#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
-#define SDIF_MINTSTS_HTO_MASK (0x400U)
-#define SDIF_MINTSTS_HTO_SHIFT (10U)
+#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+
+#define SDIF_MINTSTS_HTO_MASK (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT (10U)
/*! HTO - Data starvation-by-host time-out (HTO).
*/
-#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
-#define SDIF_MINTSTS_FRUN_MASK (0x800U)
-#define SDIF_MINTSTS_FRUN_SHIFT (11U)
+#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+
+#define SDIF_MINTSTS_FRUN_MASK (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT (11U)
/*! FRUN - FIFO underrun/overrun error.
*/
-#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
-#define SDIF_MINTSTS_HLE_MASK (0x1000U)
-#define SDIF_MINTSTS_HLE_SHIFT (12U)
+#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+
+#define SDIF_MINTSTS_HLE_MASK (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT (12U)
/*! HLE - Hardware locked write error.
*/
-#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
-#define SDIF_MINTSTS_SBE_MASK (0x2000U)
-#define SDIF_MINTSTS_SBE_SHIFT (13U)
+#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+
+#define SDIF_MINTSTS_SBE_MASK (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT (13U)
/*! SBE - Start-bit error.
*/
-#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
-#define SDIF_MINTSTS_ACD_MASK (0x4000U)
-#define SDIF_MINTSTS_ACD_SHIFT (14U)
+#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+
+#define SDIF_MINTSTS_ACD_MASK (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT (14U)
/*! ACD - Auto command done.
*/
-#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
-#define SDIF_MINTSTS_EBE_MASK (0x8000U)
-#define SDIF_MINTSTS_EBE_SHIFT (15U)
+#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+
+#define SDIF_MINTSTS_EBE_MASK (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT (15U)
/*! EBE - End-bit error (read)/write no CRC.
*/
-#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
-#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
-#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)
+#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)
/*! SDIO_INTERRUPT - Interrupt from SDIO card.
*/
-#define SDIF_MINTSTS_SDIO_INTERRUPT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
/*! @} */
/*! @name RINTSTS - Raw Interrupt Status register */
/*! @{ */
-#define SDIF_RINTSTS_CDET_MASK (0x1U)
-#define SDIF_RINTSTS_CDET_SHIFT (0U)
+
+#define SDIF_RINTSTS_CDET_MASK (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT (0U)
/*! CDET - Card detect.
*/
-#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
-#define SDIF_RINTSTS_RE_MASK (0x2U)
-#define SDIF_RINTSTS_RE_SHIFT (1U)
+#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+
+#define SDIF_RINTSTS_RE_MASK (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT (1U)
/*! RE - Response error.
*/
-#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
-#define SDIF_RINTSTS_CDONE_MASK (0x4U)
-#define SDIF_RINTSTS_CDONE_SHIFT (2U)
+#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+
+#define SDIF_RINTSTS_CDONE_MASK (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT (2U)
/*! CDONE - Command done.
*/
-#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
-#define SDIF_RINTSTS_DTO_MASK (0x8U)
-#define SDIF_RINTSTS_DTO_SHIFT (3U)
+#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+
+#define SDIF_RINTSTS_DTO_MASK (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT (3U)
/*! DTO - Data transfer over.
*/
-#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
-#define SDIF_RINTSTS_TXDR_MASK (0x10U)
-#define SDIF_RINTSTS_TXDR_SHIFT (4U)
+#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+
+#define SDIF_RINTSTS_TXDR_MASK (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT (4U)
/*! TXDR - Transmit FIFO data request.
*/
-#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
-#define SDIF_RINTSTS_RXDR_MASK (0x20U)
-#define SDIF_RINTSTS_RXDR_SHIFT (5U)
+#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+
+#define SDIF_RINTSTS_RXDR_MASK (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT (5U)
/*! RXDR - Receive FIFO data request.
*/
-#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
-#define SDIF_RINTSTS_RCRC_MASK (0x40U)
-#define SDIF_RINTSTS_RCRC_SHIFT (6U)
+#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+
+#define SDIF_RINTSTS_RCRC_MASK (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT (6U)
/*! RCRC - Response CRC error.
*/
-#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
-#define SDIF_RINTSTS_DCRC_MASK (0x80U)
-#define SDIF_RINTSTS_DCRC_SHIFT (7U)
+#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+
+#define SDIF_RINTSTS_DCRC_MASK (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT (7U)
/*! DCRC - Data CRC error.
*/
-#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
-#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)
-#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)
+#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+
+#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)
/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR).
*/
-#define SDIF_RINTSTS_RTO_BAR(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
-#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)
-#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)
+#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+
+#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)
/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS).
*/
-#define SDIF_RINTSTS_DRTO_BDS(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
-#define SDIF_RINTSTS_HTO_MASK (0x400U)
-#define SDIF_RINTSTS_HTO_SHIFT (10U)
+#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+
+#define SDIF_RINTSTS_HTO_MASK (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT (10U)
/*! HTO - Data starvation-by-host time-out (HTO).
*/
-#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
-#define SDIF_RINTSTS_FRUN_MASK (0x800U)
-#define SDIF_RINTSTS_FRUN_SHIFT (11U)
+#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+
+#define SDIF_RINTSTS_FRUN_MASK (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT (11U)
/*! FRUN - FIFO underrun/overrun error.
*/
-#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
-#define SDIF_RINTSTS_HLE_MASK (0x1000U)
-#define SDIF_RINTSTS_HLE_SHIFT (12U)
+#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+
+#define SDIF_RINTSTS_HLE_MASK (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT (12U)
/*! HLE - Hardware locked write error.
*/
-#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
-#define SDIF_RINTSTS_SBE_MASK (0x2000U)
-#define SDIF_RINTSTS_SBE_SHIFT (13U)
+#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+
+#define SDIF_RINTSTS_SBE_MASK (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT (13U)
/*! SBE - Start-bit error.
*/
-#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
-#define SDIF_RINTSTS_ACD_MASK (0x4000U)
-#define SDIF_RINTSTS_ACD_SHIFT (14U)
+#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+
+#define SDIF_RINTSTS_ACD_MASK (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT (14U)
/*! ACD - Auto command done.
*/
-#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
-#define SDIF_RINTSTS_EBE_MASK (0x8000U)
-#define SDIF_RINTSTS_EBE_SHIFT (15U)
+#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+
+#define SDIF_RINTSTS_EBE_MASK (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT (15U)
/*! EBE - End-bit error (read)/write no CRC.
*/
-#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
-#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
-#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)
+#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)
/*! SDIO_INTERRUPT - Interrupt from SDIO card.
*/
-#define SDIF_RINTSTS_SDIO_INTERRUPT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
/*! @} */
/*! @name STATUS - Status register */
/*! @{ */
-#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)
-#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)
+
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)
/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer.
*/
-#define SDIF_STATUS_FIFO_RX_WATERMARK(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
-#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)
-#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)
/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer.
*/
-#define SDIF_STATUS_FIFO_TX_WATERMARK(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
-#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)
-#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+
+#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)
/*! FIFO_EMPTY - FIFO is empty status.
*/
-#define SDIF_STATUS_FIFO_EMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
-#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)
-#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)
+#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+
+#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)
/*! FIFO_FULL - FIFO is full status.
*/
-#define SDIF_STATUS_FIFO_FULL(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
-#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)
-#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)
+#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+
+#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)
/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx
* cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 -
* Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp
* crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The
* command FSM state is represented using 19 bits.
*/
-#define SDIF_STATUS_CMDFSMSTATES(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
-#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)
-#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)
+#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+
+#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)
/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.
*/
-#define SDIF_STATUS_DATA_3_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
-#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)
-#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)
+#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+
+#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)
/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.
*/
-#define SDIF_STATUS_DATA_BUSY(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)
+#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)
/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy.
*/
-#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
-#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)
-#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+
+#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)
/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core.
*/
-#define SDIF_STATUS_RESPONSE_INDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
-#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)
-#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)
+#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+
+#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)
/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO.
*/
-#define SDIF_STATUS_FIFO_COUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
-#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)
-#define SDIF_STATUS_DMA_ACK_SHIFT (30U)
+#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+
+#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT (30U)
/*! DMA_ACK - DMA acknowledge signal state.
*/
-#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
-#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)
-#define SDIF_STATUS_DMA_REQ_SHIFT (31U)
+#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+
+#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT (31U)
/*! DMA_REQ - DMA request signal state.
*/
-#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
/*! @} */
/*! @name FIFOTH - FIFO Threshold Watermark register */
/*! @{ */
-#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)
-#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)
+
+#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)
/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card.
*/
-#define SDIF_FIFOTH_TX_WMARK(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
-#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)
-#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)
+#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+
+#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)
/*! RX_WMARK - FIFO threshold watermark level when receiving data to card.
*/
-#define SDIF_FIFOTH_RX_WMARK(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
-#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)
-#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)
+#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+
+#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)
/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller
* multiple-transaction-size SRC/DEST_MSIZE.
*/
-#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
/*! @} */
/*! @name CDETECT - Card Detect register */
/*! @{ */
-#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U)
-#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U)
+
+#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U)
+#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U)
/*! CARD0_DETECT - Card 0 detect
*/
-#define SDIF_CDETECT_CARD0_DETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK)
-#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U)
-#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U)
+#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK)
+
+#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U)
+#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U)
/*! CARD1_DETECT - Card 1 detect
*/
-#define SDIF_CDETECT_CARD1_DETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK)
+#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK)
/*! @} */
/*! @name WRTPRT - Write Protect register */
/*! @{ */
-#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)
-#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)
+
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)
/*! WRITE_PROTECT - Write protect.
*/
-#define SDIF_WRTPRT_WRITE_PROTECT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
/*! @} */
/*! @name TCBCNT - Transferred CIU Card Byte Count register */
/*! @{ */
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)
+
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)
/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card.
*/
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
/*! @} */
/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
/*! @{ */
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)
+
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)
/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO.
*/
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
/*! @} */
/*! @name DEBNCE - Debounce Count register */
/*! @{ */
-#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)
-#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)
-/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time
- * is 5-25 ms.
+
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)
+/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms.
*/
-#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
/*! @} */
/*! @name RST_N - Hardware Reset */
/*! @{ */
-#define SDIF_RST_N_CARD_RESET_MASK (0x1U)
-#define SDIF_RST_N_CARD_RESET_SHIFT (0U)
+
+#define SDIF_RST_N_CARD_RESET_MASK (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT (0U)
/*! CARD_RESET - Hardware reset.
*/
-#define SDIF_RST_N_CARD_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
/*! @} */
/*! @name BMOD - Bus Mode register */
/*! @{ */
-#define SDIF_BMOD_SWR_MASK (0x1U)
-#define SDIF_BMOD_SWR_SHIFT (0U)
+
+#define SDIF_BMOD_SWR_MASK (0x1U)
+#define SDIF_BMOD_SWR_SHIFT (0U)
/*! SWR - Software Reset.
*/
-#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
-#define SDIF_BMOD_FB_MASK (0x2U)
-#define SDIF_BMOD_FB_SHIFT (1U)
+#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+
+#define SDIF_BMOD_FB_MASK (0x2U)
+#define SDIF_BMOD_FB_SHIFT (1U)
/*! FB - Fixed Burst.
*/
-#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
-#define SDIF_BMOD_DSL_MASK (0x7CU)
-#define SDIF_BMOD_DSL_SHIFT (2U)
+#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+
+#define SDIF_BMOD_DSL_MASK (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT (2U)
/*! DSL - Descriptor Skip Length.
*/
-#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
-#define SDIF_BMOD_DE_MASK (0x80U)
-#define SDIF_BMOD_DE_SHIFT (7U)
+#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+
+#define SDIF_BMOD_DE_MASK (0x80U)
+#define SDIF_BMOD_DE_SHIFT (7U)
/*! DE - SD/MMC DMA Enable.
*/
-#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
-#define SDIF_BMOD_PBL_MASK (0x700U)
-#define SDIF_BMOD_PBL_SHIFT (8U)
+#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+
+#define SDIF_BMOD_PBL_MASK (0x700U)
+#define SDIF_BMOD_PBL_SHIFT (8U)
/*! PBL - Programmable Burst Length.
*/
-#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
/*! @} */
/*! @name PLDMND - Poll Demand register */
/*! @{ */
-#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)
-#define SDIF_PLDMND_PD_SHIFT (0U)
+
+#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT (0U)
/*! PD - Poll Demand.
*/
-#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
/*! @} */
/*! @name DBADDR - Descriptor List Base Address register */
/*! @{ */
-#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)
-#define SDIF_DBADDR_SDL_SHIFT (0U)
+
+#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT (0U)
/*! SDL - Start of Descriptor List.
*/
-#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
/*! @} */
/*! @name IDSTS - Internal DMAC Status register */
/*! @{ */
-#define SDIF_IDSTS_TI_MASK (0x1U)
-#define SDIF_IDSTS_TI_SHIFT (0U)
+
+#define SDIF_IDSTS_TI_MASK (0x1U)
+#define SDIF_IDSTS_TI_SHIFT (0U)
/*! TI - Transmit Interrupt.
*/
-#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
-#define SDIF_IDSTS_RI_MASK (0x2U)
-#define SDIF_IDSTS_RI_SHIFT (1U)
+#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+
+#define SDIF_IDSTS_RI_MASK (0x2U)
+#define SDIF_IDSTS_RI_SHIFT (1U)
/*! RI - Receive Interrupt.
*/
-#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
-#define SDIF_IDSTS_FBE_MASK (0x4U)
-#define SDIF_IDSTS_FBE_SHIFT (2U)
+#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+
+#define SDIF_IDSTS_FBE_MASK (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT (2U)
/*! FBE - Fatal Bus Error Interrupt.
*/
-#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
-#define SDIF_IDSTS_DU_MASK (0x10U)
-#define SDIF_IDSTS_DU_SHIFT (4U)
+#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+
+#define SDIF_IDSTS_DU_MASK (0x10U)
+#define SDIF_IDSTS_DU_SHIFT (4U)
/*! DU - Descriptor Unavailable Interrupt.
*/
-#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
-#define SDIF_IDSTS_CES_MASK (0x20U)
-#define SDIF_IDSTS_CES_SHIFT (5U)
+#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+
+#define SDIF_IDSTS_CES_MASK (0x20U)
+#define SDIF_IDSTS_CES_SHIFT (5U)
/*! CES - Card Error Summary.
*/
-#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
-#define SDIF_IDSTS_NIS_MASK (0x100U)
-#define SDIF_IDSTS_NIS_SHIFT (8U)
+#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+
+#define SDIF_IDSTS_NIS_MASK (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT (8U)
/*! NIS - Normal Interrupt Summary.
*/
-#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
-#define SDIF_IDSTS_AIS_MASK (0x200U)
-#define SDIF_IDSTS_AIS_SHIFT (9U)
+#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+
+#define SDIF_IDSTS_AIS_MASK (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT (9U)
/*! AIS - Abnormal Interrupt Summary.
*/
-#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
-#define SDIF_IDSTS_EB_MASK (0x1C00U)
-#define SDIF_IDSTS_EB_SHIFT (10U)
+#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+
+#define SDIF_IDSTS_EB_MASK (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT (10U)
/*! EB - Error Bits.
*/
-#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
-#define SDIF_IDSTS_FSM_MASK (0x1E000U)
-#define SDIF_IDSTS_FSM_SHIFT (13U)
+#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+
+#define SDIF_IDSTS_FSM_MASK (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT (13U)
/*! FSM - DMAC state machine present state.
*/
-#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
/*! @} */
/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
/*! @{ */
-#define SDIF_IDINTEN_TI_MASK (0x1U)
-#define SDIF_IDINTEN_TI_SHIFT (0U)
+
+#define SDIF_IDINTEN_TI_MASK (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT (0U)
/*! TI - Transmit Interrupt Enable.
*/
-#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
-#define SDIF_IDINTEN_RI_MASK (0x2U)
-#define SDIF_IDINTEN_RI_SHIFT (1U)
+#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+
+#define SDIF_IDINTEN_RI_MASK (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT (1U)
/*! RI - Receive Interrupt Enable.
*/
-#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
-#define SDIF_IDINTEN_FBE_MASK (0x4U)
-#define SDIF_IDINTEN_FBE_SHIFT (2U)
+#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+
+#define SDIF_IDINTEN_FBE_MASK (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT (2U)
/*! FBE - Fatal Bus Error Enable.
*/
-#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
-#define SDIF_IDINTEN_DU_MASK (0x10U)
-#define SDIF_IDINTEN_DU_SHIFT (4U)
+#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+
+#define SDIF_IDINTEN_DU_MASK (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT (4U)
/*! DU - Descriptor Unavailable Interrupt.
*/
-#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
-#define SDIF_IDINTEN_CES_MASK (0x20U)
-#define SDIF_IDINTEN_CES_SHIFT (5U)
+#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+
+#define SDIF_IDINTEN_CES_MASK (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT (5U)
/*! CES - Card Error summary Interrupt Enable.
*/
-#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
-#define SDIF_IDINTEN_NIS_MASK (0x100U)
-#define SDIF_IDINTEN_NIS_SHIFT (8U)
+#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+
+#define SDIF_IDINTEN_NIS_MASK (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT (8U)
/*! NIS - Normal Interrupt Summary Enable.
*/
-#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
-#define SDIF_IDINTEN_AIS_MASK (0x200U)
-#define SDIF_IDINTEN_AIS_SHIFT (9U)
+#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+
+#define SDIF_IDINTEN_AIS_MASK (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT (9U)
/*! AIS - Abnormal Interrupt Summary Enable.
*/
-#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
/*! @} */
/*! @name DSCADDR - Current Host Descriptor Address register */
/*! @{ */
-#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)
-#define SDIF_DSCADDR_HDA_SHIFT (0U)
+
+#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT (0U)
/*! HDA - Host Descriptor Address Pointer.
*/
-#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
/*! @} */
/*! @name BUFADDR - Current Buffer Descriptor Address register */
/*! @{ */
-#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)
-#define SDIF_BUFADDR_HBA_SHIFT (0U)
+
+#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT (0U)
/*! HBA - Host Buffer Address Pointer.
*/
-#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
/*! @} */
/*! @name CARDTHRCTL - Card Threshold Control */
/*! @{ */
-#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)
-#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)
+
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)
/*! CARDRDTHREN - Card Read Threshold Enable.
*/
-#define SDIF_CARDTHRCTL_CARDRDTHREN(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)
/*! BSYCLRINTEN - Busy Clear Interrupt Enable.
*/
-#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)
/*! CARDTHRESHOLD - Card Threshold size.
*/
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
/*! @} */
/*! @name BACKENDPWR - Power control */
/*! @{ */
-#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)
-#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)
+
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)
/*! BACKENDPWR - Back-end Power control for card application.
*/
-#define SDIF_BACKENDPWR_BACKENDPWR(x) \
- (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
/*! @} */
/*! @name FIFO - SDIF FIFO */
/*! @{ */
-#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)
-#define SDIF_FIFO_DATA_SHIFT (0U)
+
+#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT (0U)
/*! DATA - SDIF FIFO.
*/
-#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
/*! @} */
/* The count of SDIF_FIFO */
-#define SDIF_FIFO_COUNT (64U)
+#define SDIF_FIFO_COUNT (64U)
+
/*!
* @}
*/ /* end of group SDIF_Register_Masks */
+
/* SDIF - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral SDIF base address */
-#define SDIF_BASE (0x5009B000u)
-/** Peripheral SDIF base address */
-#define SDIF_BASE_NS (0x4009B000u)
-/** Peripheral SDIF base pointer */
-#define SDIF ((SDIF_Type *)SDIF_BASE)
-/** Peripheral SDIF base pointer */
-#define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS)
-/** Array initializer of SDIF peripheral base addresses */
-#define SDIF_BASE_ADDRS \
- { \
- SDIF_BASE \
- }
-/** Array initializer of SDIF peripheral base pointers */
-#define SDIF_BASE_PTRS \
- { \
- SDIF \
- }
-/** Array initializer of SDIF peripheral base addresses */
-#define SDIF_BASE_ADDRS_NS \
- { \
- SDIF_BASE_NS \
- }
-/** Array initializer of SDIF peripheral base pointers */
-#define SDIF_BASE_PTRS_NS \
- { \
- SDIF_NS \
- }
+ /** Peripheral SDIF base address */
+ #define SDIF_BASE (0x5009B000u)
+ /** Peripheral SDIF base address */
+ #define SDIF_BASE_NS (0x4009B000u)
+ /** Peripheral SDIF base pointer */
+ #define SDIF ((SDIF_Type *)SDIF_BASE)
+ /** Peripheral SDIF base pointer */
+ #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS)
+ /** Array initializer of SDIF peripheral base addresses */
+ #define SDIF_BASE_ADDRS { SDIF_BASE }
+ /** Array initializer of SDIF peripheral base pointers */
+ #define SDIF_BASE_PTRS { SDIF }
+ /** Array initializer of SDIF peripheral base addresses */
+ #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS }
+ /** Array initializer of SDIF peripheral base pointers */
+ #define SDIF_BASE_PTRS_NS { SDIF_NS }
#else
-/** Peripheral SDIF base address */
-#define SDIF_BASE (0x4009B000u)
-/** Peripheral SDIF base pointer */
-#define SDIF ((SDIF_Type *)SDIF_BASE)
-/** Array initializer of SDIF peripheral base addresses */
-#define SDIF_BASE_ADDRS \
- { \
- SDIF_BASE \
- }
-/** Array initializer of SDIF peripheral base pointers */
-#define SDIF_BASE_PTRS \
- { \
- SDIF \
- }
+ /** Peripheral SDIF base address */
+ #define SDIF_BASE (0x4009B000u)
+ /** Peripheral SDIF base pointer */
+ #define SDIF ((SDIF_Type *)SDIF_BASE)
+ /** Array initializer of SDIF peripheral base addresses */
+ #define SDIF_BASE_ADDRS { SDIF_BASE }
+ /** Array initializer of SDIF peripheral base pointers */
+ #define SDIF_BASE_PTRS { SDIF }
#endif
/** Interrupt vectors for the SDIF peripheral type */
-#define SDIF_IRQS \
- { \
- SDIO_IRQn \
- }
+#define SDIF_IRQS { SDIO_IRQn }
/*!
* @}
*/ /* end of group SDIF_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- SPI Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -20106,36 +19777,32 @@ typedef struct
*/
/** SPI - Register Layout Typedef */
-typedef struct
-{
- uint8_t RESERVED_0[1024];
- __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
- __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
- __IO uint32_t
- STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
- __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register.
- Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
- __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the
- corresponding bit in INTENSET to be cleared., offset: 0x410 */
- uint8_t RESERVED_1[16];
- __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
- __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
- uint8_t RESERVED_2[2516];
- __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
- __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
- __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
- uint8_t RESERVED_3[4];
- __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
- __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
- __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
- uint8_t RESERVED_4[4];
- __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
- uint8_t RESERVED_5[12];
- __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
- uint8_t RESERVED_6[12];
- __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
- uint8_t RESERVED_7[440];
- __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+typedef struct {
+ uint8_t RESERVED_0[1024];
+ __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
+ __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
+ __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+ __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+ __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
+ __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
+ uint8_t RESERVED_2[2516];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ uint8_t RESERVED_6[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ uint8_t RESERVED_7[440];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
} SPI_Type;
/* ----------------------------------------------------------------------------
@@ -20149,144 +19816,160 @@ typedef struct
/*! @name CFG - SPI Configuration register */
/*! @{ */
-#define SPI_CFG_ENABLE_MASK (0x1U)
-#define SPI_CFG_ENABLE_SHIFT (0U)
+
+#define SPI_CFG_ENABLE_MASK (0x1U)
+#define SPI_CFG_ENABLE_SHIFT (0U)
/*! ENABLE - SPI enable.
* 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
* 0b1..Enabled. The SPI is enabled for operation.
*/
-#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
-#define SPI_CFG_MASTER_MASK (0x4U)
-#define SPI_CFG_MASTER_SHIFT (2U)
+#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+
+#define SPI_CFG_MASTER_MASK (0x4U)
+#define SPI_CFG_MASTER_SHIFT (2U)
/*! MASTER - Master mode select.
* 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.
- * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an
- * input.
+ * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.
*/
-#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
-#define SPI_CFG_LSBF_MASK (0x8U)
-#define SPI_CFG_LSBF_SHIFT (3U)
+#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+
+#define SPI_CFG_LSBF_MASK (0x8U)
+#define SPI_CFG_LSBF_SHIFT (3U)
/*! LSBF - LSB First mode enable.
* 0b0..Standard. Data is transmitted and received in standard MSB first order.
* 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
*/
-#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
-#define SPI_CFG_CPHA_MASK (0x10U)
-#define SPI_CFG_CPHA_SHIFT (4U)
+#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+
+#define SPI_CFG_CPHA_MASK (0x10U)
+#define SPI_CFG_CPHA_SHIFT (4U)
/*! CPHA - Clock Phase select.
* 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock
* changes away from the rest state). Data is changed on the following edge.
* 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock
* changes away from the rest state). Data is captured on the following edge.
*/
-#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
-#define SPI_CFG_CPOL_MASK (0x20U)
-#define SPI_CFG_CPOL_SHIFT (5U)
+#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+
+#define SPI_CFG_CPOL_MASK (0x20U)
+#define SPI_CFG_CPOL_SHIFT (5U)
/*! CPOL - Clock Polarity select.
* 0b0..Low. The rest state of the clock (between transfers) is low.
* 0b1..High. The rest state of the clock (between transfers) is high.
*/
-#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
-#define SPI_CFG_LOOP_MASK (0x80U)
-#define SPI_CFG_LOOP_SHIFT (7U)
+#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+
+#define SPI_CFG_LOOP_MASK (0x80U)
+#define SPI_CFG_LOOP_SHIFT (7U)
/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit
* and receive data connected together to allow simple software testing.
* 0b0..Disabled.
* 0b1..Enabled.
*/
-#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
-#define SPI_CFG_SPOL0_MASK (0x100U)
-#define SPI_CFG_SPOL0_SHIFT (8U)
+#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+
+#define SPI_CFG_SPOL0_MASK (0x100U)
+#define SPI_CFG_SPOL0_SHIFT (8U)
/*! SPOL0 - SSEL0 Polarity select.
* 0b0..Low. The SSEL0 pin is active low.
* 0b1..High. The SSEL0 pin is active high.
*/
-#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
-#define SPI_CFG_SPOL1_MASK (0x200U)
-#define SPI_CFG_SPOL1_SHIFT (9U)
+#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+
+#define SPI_CFG_SPOL1_MASK (0x200U)
+#define SPI_CFG_SPOL1_SHIFT (9U)
/*! SPOL1 - SSEL1 Polarity select.
* 0b0..Low. The SSEL1 pin is active low.
* 0b1..High. The SSEL1 pin is active high.
*/
-#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
-#define SPI_CFG_SPOL2_MASK (0x400U)
-#define SPI_CFG_SPOL2_SHIFT (10U)
+#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+
+#define SPI_CFG_SPOL2_MASK (0x400U)
+#define SPI_CFG_SPOL2_SHIFT (10U)
/*! SPOL2 - SSEL2 Polarity select.
* 0b0..Low. The SSEL2 pin is active low.
* 0b1..High. The SSEL2 pin is active high.
*/
-#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
-#define SPI_CFG_SPOL3_MASK (0x800U)
-#define SPI_CFG_SPOL3_SHIFT (11U)
+#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+
+#define SPI_CFG_SPOL3_MASK (0x800U)
+#define SPI_CFG_SPOL3_SHIFT (11U)
/*! SPOL3 - SSEL3 Polarity select.
* 0b0..Low. The SSEL3 pin is active low.
* 0b1..High. The SSEL3 pin is active high.
*/
-#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
/*! @} */
/*! @name DLY - SPI Delay register */
/*! @{ */
-#define SPI_DLY_PRE_DELAY_MASK (0xFU)
-#define SPI_DLY_PRE_DELAY_SHIFT (0U)
+
+#define SPI_DLY_PRE_DELAY_MASK (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT (0U)
/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data
* transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This
* is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI
* clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are
* inserted.
*/
-#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
-#define SPI_DLY_POST_DELAY_MASK (0xF0U)
-#define SPI_DLY_POST_DELAY_SHIFT (4U)
+#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+
+#define SPI_DLY_POST_DELAY_MASK (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT (4U)
/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL
* deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock
* times are inserted. 0xF = 15 SPI clock times are inserted.
*/
-#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
-#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
-#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
+#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+
+#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current
* frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1
* = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock
* times are inserted.
*/
-#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
-#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
-#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
+#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+
+#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between
* transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1
* = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that
* SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16
* SPI clock times.
*/
-#define SPI_DLY_TRANSFER_DELAY(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
/*! @} */
/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
/*! @{ */
-#define SPI_STAT_SSA_MASK (0x10U)
-#define SPI_STAT_SSA_SHIFT (4U)
+
+#define SPI_STAT_SSA_MASK (0x10U)
+#define SPI_STAT_SSA_SHIFT (4U)
/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from
* deasserted to asserted, in both master and slave modes. This allows determining when the SPI
* transmit/receive functions become busy, and allows waking up the device from reduced power modes when a
* slave mode access begins. This flag is cleared by software.
*/
-#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
-#define SPI_STAT_SSD_MASK (0x20U)
-#define SPI_STAT_SSD_SHIFT (5U)
+#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+
+#define SPI_STAT_SSD_MASK (0x20U)
+#define SPI_STAT_SSD_SHIFT (5U)
/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to
* deasserted, in both master and slave modes. This allows determining when the SPI
* transmit/receive functions become idle. This flag is cleared by software.
*/
-#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
-#define SPI_STAT_STALLED_MASK (0x40U)
-#define SPI_STAT_STALLED_SHIFT (6U)
+#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+
+#define SPI_STAT_STALLED_MASK (0x40U)
+#define SPI_STAT_STALLED_SHIFT (6U)
/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition.
*/
-#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
-#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
-#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
+#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+
+#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current
* transfer when the transmitter finishes any activity already in progress, as if the EOT flag
* had been set prior to the last transmission. This capability is included to support cases where
@@ -20294,138 +19977,146 @@ typedef struct
* is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end
* of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
*/
-#define SPI_STAT_ENDTRANSFER(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
-#define SPI_STAT_MSTIDLE_MASK (0x100U)
-#define SPI_STAT_MSTIDLE_SHIFT (8U)
+#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+
+#define SPI_STAT_MSTIDLE_MASK (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT (8U)
/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle.
* This means that the transmit holding register is empty and the transmitter is not in the
* process of sending data.
*/
-#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
/*! @} */
-/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to
- * any implemented bit position causes that bit to be set. */
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
/*! @{ */
-#define SPI_INTENSET_SSAEN_MASK (0x10U)
-#define SPI_INTENSET_SSAEN_SHIFT (4U)
-/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is
- * asserted. 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to
- * asserted. 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+
+#define SPI_INTENSET_SSAEN_MASK (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT (4U)
+/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.
+ * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
+ * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
*/
-#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
-#define SPI_INTENSET_SSDEN_MASK (0x20U)
-#define SPI_INTENSET_SSDEN_SHIFT (5U)
-/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is
- * deasserted. 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
+#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+
+#define SPI_INTENSET_SSDEN_MASK (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT (5U)
+/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.
+ * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
* 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
*/
-#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
-#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
-#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
+#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+
+#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
/*! MSTIDLEEN - Master idle interrupt enable.
* 0b0..No interrupt will be generated when the SPI master function is idle.
* 0b1..An interrupt will be generated when the SPI master function is fully idle.
*/
-#define SPI_INTENSET_MSTIDLEEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
/*! @} */
-/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding
- * bit in INTENSET to be cleared. */
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
/*! @{ */
-#define SPI_INTENCLR_SSAEN_MASK (0x10U)
-#define SPI_INTENCLR_SSAEN_SHIFT (4U)
+
+#define SPI_INTENCLR_SSAEN_MASK (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT (4U)
/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
-#define SPI_INTENCLR_SSDEN_MASK (0x20U)
-#define SPI_INTENCLR_SSDEN_SHIFT (5U)
+#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+
+#define SPI_INTENCLR_SSDEN_MASK (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT (5U)
/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
-#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
-#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
+#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+
+#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define SPI_INTENCLR_MSTIDLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
/*! @} */
/*! @name DIV - SPI clock Divider */
/*! @{ */
-#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
-#define SPI_DIV_DIVVAL_SHIFT (0U)
+
+#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT (0U)
/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the
* SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1,
* the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results
* in FCLK/65536.
*/
-#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
/*! @} */
/*! @name INTSTAT - SPI Interrupt Status */
/*! @{ */
-#define SPI_INTSTAT_SSA_MASK (0x10U)
-#define SPI_INTSTAT_SSA_SHIFT (4U)
+
+#define SPI_INTSTAT_SSA_MASK (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT (4U)
/*! SSA - Slave Select Assert.
*/
-#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
-#define SPI_INTSTAT_SSD_MASK (0x20U)
-#define SPI_INTSTAT_SSD_SHIFT (5U)
+#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+
+#define SPI_INTSTAT_SSD_MASK (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT (5U)
/*! SSD - Slave Select Deassert.
*/
-#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
-#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
-#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
+#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+
+#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
/*! MSTIDLE - Master Idle status flag.
*/
-#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
/*! @} */
/*! @name FIFOCFG - FIFO configuration and enable register. */
/*! @{ */
-#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
-#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
+
+#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
/*! ENABLETX - Enable the transmit FIFO.
* 0b0..The transmit FIFO is not enabled.
* 0b1..The transmit FIFO is enabled.
*/
-#define SPI_FIFOCFG_ENABLETX(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
-#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
-#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
+#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+
+#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
/*! ENABLERX - Enable the receive FIFO.
* 0b0..The receive FIFO is not enabled.
* 0b1..The receive FIFO is enabled.
*/
-#define SPI_FIFOCFG_ENABLERX(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
-#define SPI_FIFOCFG_SIZE_MASK (0x30U)
-#define SPI_FIFOCFG_SIZE_SHIFT (4U)
+#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+
+#define SPI_FIFOCFG_SIZE_MASK (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT (4U)
/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
* entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
*/
-#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
-#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
-#define SPI_FIFOCFG_DMATX_SHIFT (12U)
+#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+
+#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT (12U)
/*! DMATX - DMA configuration for transmit.
* 0b0..DMA is not used for the transmit function.
- * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if
- * DMA is enabled.
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
*/
-#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
-#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
-#define SPI_FIFOCFG_DMARX_SHIFT (13U)
+#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+
+#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT (13U)
/*! DMARX - DMA configuration for receive.
* 0b0..DMA is not used for the receive function.
- * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if
- * DMA is enabled.
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
*/
-#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
-#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
-#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
+#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+
+#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
* modes (up to power-down, as long as the peripheral function works in that power mode) without
* enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
@@ -20435,9 +20126,10 @@ typedef struct
* 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
* FIFOTRIG, even when the TXLVL interrupt is not enabled.
*/
-#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
-#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
-#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
+#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+
+#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
* modes (up to power-down, as long as the peripheral function works in that power mode) without
* enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
@@ -20447,118 +20139,124 @@ typedef struct
* 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
* FIFOTRIG, even when the RXLVL interrupt is not enabled.
*/
-#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
-#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
-#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
+#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+
+#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
*/
-#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
-#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
-#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
+#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+
+#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
*/
-#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
/*! @} */
/*! @name FIFOSTAT - FIFO status register. */
/*! @{ */
-#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
-#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
+
+#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
* caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
* needed. Cleared by writing a 1 to this bit.
*/
-#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
-#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
-#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
+#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+
+#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
* not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
*/
-#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
-#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
-#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
+#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+
+#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
* an interrupt. The details can be found by reading the peripheral's STAT register.
*/
-#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
-#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
-#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
-/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last
- * piece of data.
+#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+
+#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
*/
-#define SPI_FIFOSTAT_TXEMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
-#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
-#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+
+#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
* written. When 0, the transmit FIFO is full and another write would cause it to overflow.
*/
-#define SPI_FIFOSTAT_TXNOTFULL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
-#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
-#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
-/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive
- * FIFO is empty.
- */
-#define SPI_FIFOSTAT_RXNOTEMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
-#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
-#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
+#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+
+#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
* prevent the peripheral from causing an overflow.
*/
-#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
-#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
-#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
+#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+
+#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
* and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
* the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
* 0.
*/
-#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
-#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
-#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
+#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+
+#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
* RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
* point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
* 1.
*/
-#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
/*! @} */
/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
/*! @{ */
-#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
-#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
+
+#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
* in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
* 0b0..Transmit FIFO level does not generate a FIFO level trigger.
- * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this
- * register.
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
*/
-#define SPI_FIFOTRIG_TXLVLENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
-#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
-#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
+#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+
+#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
* in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
* 0b0..Receive FIFO level does not generate a FIFO level trigger.
- * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this
- * register.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
*/
-#define SPI_FIFOTRIG_RXLVLENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
-#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
-#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
+#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+
+#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
* to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
* the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
* becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
* FIFO level decreases to 15 entries (is no longer full).
*/
-#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
-#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
-#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
+#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+
+#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
* is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
* can wake up the device just enough to perform DMA, then return to the reduced power mode. See
@@ -20566,157 +20264,163 @@ typedef struct
* longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
* FIFO has received 16 entries (has become full).
*/
-#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
/*! @{ */
-#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
-#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
-/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT
- * register. 0b0..No interrupt will be generated for a transmit error. 0b1..An interrupt will be generated when a
- * transmit error occurs.
- */
-#define SPI_FIFOINTENSET_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
-#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
-#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
-/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT
- * register. 0b0..No interrupt will be generated for a receive error. 0b1..An interrupt will be generated when a receive
- * error occurs.
- */
-#define SPI_FIFOINTENSET_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
-#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
-#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
+
+#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+
+#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+
+#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
* specified by the TXLVL field in the FIFOTRIG register.
* 0b0..No interrupt will be generated based on the TX FIFO level.
* 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
* to the level specified by TXLVL in the FIFOTRIG register.
*/
-#define SPI_FIFOINTENSET_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
-#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
-#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
+#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+
+#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
* specified by the TXLVL field in the FIFOTRIG register.
* 0b0..No interrupt will be generated based on the RX FIFO level.
* 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
* increases to the level specified by RXLVL in the FIFOTRIG register.
*/
-#define SPI_FIFOINTENSET_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
/*! @{ */
-#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
-#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
+
+#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define SPI_FIFOINTENCLR_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
-#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
-#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
+#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+
+#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define SPI_FIFOINTENCLR_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
-#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
-#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
+#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+
+#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define SPI_FIFOINTENCLR_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
-#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
-#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
+#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+
+#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define SPI_FIFOINTENCLR_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTSTAT - FIFO interrupt status register. */
/*! @{ */
-#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
-#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
+
+#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
/*! TXERR - TX FIFO error.
*/
-#define SPI_FIFOINTSTAT_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
-#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
-#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
+#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+
+#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
/*! RXERR - RX FIFO error.
*/
-#define SPI_FIFOINTSTAT_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
-#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
-#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
+#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+
+#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
/*! TXLVL - Transmit FIFO level interrupt.
*/
-#define SPI_FIFOINTSTAT_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
-#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
-#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
+#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+
+#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
/*! RXLVL - Receive FIFO level interrupt.
*/
-#define SPI_FIFOINTSTAT_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
-#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
-#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
+#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+
+#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
/*! PERINT - Peripheral interrupt.
*/
-#define SPI_FIFOINTSTAT_PERINT(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
/*! @} */
/*! @name FIFOWR - FIFO write data. */
/*! @{ */
-#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
-#define SPI_FIFOWR_TXDATA_SHIFT (0U)
+
+#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT (0U)
/*! TXDATA - Transmit data to the FIFO.
*/
-#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
-#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
-#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
-/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by
- * default. 0b0..SSEL0 asserted. 0b1..SSEL0 not asserted.
- */
-#define SPI_FIFOWR_TXSSEL0_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
-#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
-#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
-/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by
- * default. 0b0..SSEL1 asserted. 0b1..SSEL1 not asserted.
- */
-#define SPI_FIFOWR_TXSSEL1_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
-#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
-#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
-/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by
- * default. 0b0..SSEL2 asserted. 0b1..SSEL2 not asserted.
- */
-#define SPI_FIFOWR_TXSSEL2_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
-#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
-/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by
- * default. 0b0..SSEL3 asserted. 0b1..SSEL3 not asserted.
- */
-#define SPI_FIFOWR_TXSSEL3_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
-#define SPI_FIFOWR_EOT_MASK (0x100000U)
-#define SPI_FIFOWR_EOT_SHIFT (20U)
+#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+
+#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
+/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL0 asserted.
+ * 0b1..SSEL0 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+
+#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
+/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL1 asserted.
+ * 0b1..SSEL1 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+
+#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
+/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL2 asserted.
+ * 0b1..SSEL2 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+
+#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
+/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
+ * 0b0..SSEL3 asserted.
+ * 0b1..SSEL3 not asserted.
+ */
+#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+
+#define SPI_FIFOWR_EOT_MASK (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT (20U)
/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain
* so far at least the time specified by the Transfer_delay value in the DLY register.
- * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at
- * the end of this data. 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be
- * deasserted at the end of this piece of data.
+ * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
+ * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
*/
-#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
-#define SPI_FIFOWR_EOF_MASK (0x200000U)
-#define SPI_FIFOWR_EOF_SHIFT (21U)
+#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+
+#define SPI_FIFOWR_EOF_MASK (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT (21U)
/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value
* in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay
* value = 0. This control can be used as part of the support for frame lengths greater than 16
@@ -20725,9 +20429,10 @@ typedef struct
* 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
* inserted before subsequent data is transmitted.
*/
-#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
-#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
-#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
+#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+
+#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to
* read unneeded data from the receiver. Setting this bit simplifies the transmit process and can
* be used with the DMA.
@@ -20737,291 +20442,279 @@ typedef struct
* 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
* data. No receiver flags are generated.
*/
-#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
-#define SPI_FIFOWR_LEN_MASK (0xF000000U)
-#define SPI_FIFOWR_LEN_SHIFT (24U)
+#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+
+#define SPI_FIFOWR_LEN_MASK (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT (24U)
/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths
* greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved.
* 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data
* transfer is 16 bits in length.
*/
-#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
/*! @} */
/*! @name FIFORD - FIFO read data. */
/*! @{ */
-#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
-#define SPI_FIFORD_RXDATA_SHIFT (0U)
+
+#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT (0U)
/*! RXDATA - Received data from the FIFO.
*/
-#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
-#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
-#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
+#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+
+#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved
* along with received data. The value will reflect the SSEL0 pin for both master and slave
* operation. A zero indicates that a slave select is active. The actual polarity of each slave select
* pin is configured by the related SPOL bit in CFG.
*/
-#define SPI_FIFORD_RXSSEL0_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
-#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
-#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
+#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+
+#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved
* along with received data. The value will reflect the SSEL1 pin for both master and slave
* operation. A zero indicates that a slave select is active. The actual polarity of each slave select
* pin is configured by the related SPOL bit in CFG.
*/
-#define SPI_FIFORD_RXSSEL1_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
-#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
-#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
+#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+
+#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved
* along with received data. The value will reflect the SSEL2 pin for both master and slave
* operation. A zero indicates that a slave select is active. The actual polarity of each slave select
* pin is configured by the related SPOL bit in CFG.
*/
-#define SPI_FIFORD_RXSSEL2_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
-#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
+#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+
+#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved
* along with received data. The value will reflect the SSEL3 pin for both master and slave
* operation. A zero indicates that a slave select is active. The actual polarity of each slave select
* pin is configured by the related SPOL bit in CFG.
*/
-#define SPI_FIFORD_RXSSEL3_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
-#define SPI_FIFORD_SOT_MASK (0x100000U)
-#define SPI_FIFORD_SOT_SHIFT (20U)
+#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+
+#define SPI_FIFORD_SOT_MASK (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT (20U)
/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went
* from deasserted to asserted (i.e., any previous transfer has ended). This information can be
* used to identify the first piece of data in cases where the transfer length is greater than 16
* bits.
*/
-#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
/*! @} */
/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
/*! @{ */
-#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
-#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
+
+#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
/*! RXDATA - Received data from the FIFO.
*/
-#define SPI_FIFORDNOPOP_RXDATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
-#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
+#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
/*! RXSSEL0_N - Slave Select for receive.
*/
-#define SPI_FIFORDNOPOP_RXSSEL0_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
-#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
/*! RXSSEL1_N - Slave Select for receive.
*/
-#define SPI_FIFORDNOPOP_RXSSEL1_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
-#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
/*! RXSSEL2_N - Slave Select for receive.
*/
-#define SPI_FIFORDNOPOP_RXSSEL2_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
/*! RXSSEL3_N - Slave Select for receive.
*/
-#define SPI_FIFORDNOPOP_RXSSEL3_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
-#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
-#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+
+#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
/*! SOT - Start of transfer flag.
*/
-#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
/*! @} */
/*! @name ID - Peripheral identification register. */
/*! @{ */
-#define SPI_ID_APERTURE_MASK (0xFFU)
-#define SPI_ID_APERTURE_SHIFT (0U)
+
+#define SPI_ID_APERTURE_MASK (0xFFU)
+#define SPI_ID_APERTURE_SHIFT (0U)
/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
*/
-#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
-#define SPI_ID_MINOR_REV_MASK (0xF00U)
-#define SPI_ID_MINOR_REV_SHIFT (8U)
+#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+
+#define SPI_ID_MINOR_REV_MASK (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT (8U)
/*! MINOR_REV - Minor revision of module implementation.
*/
-#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
-#define SPI_ID_MAJOR_REV_MASK (0xF000U)
-#define SPI_ID_MAJOR_REV_SHIFT (12U)
+#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+
+#define SPI_ID_MAJOR_REV_MASK (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT (12U)
/*! MAJOR_REV - Major revision of module implementation.
*/
-#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
-#define SPI_ID_ID_MASK (0xFFFF0000U)
-#define SPI_ID_ID_SHIFT (16U)
+#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+
+#define SPI_ID_ID_MASK (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT (16U)
/*! ID - Module identifier for the selected function.
*/
-#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group SPI_Register_Masks */
+
/* SPI - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x50086000u)
-/** Peripheral SPI0 base address */
-#define SPI0_BASE_NS (0x40086000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-/** Peripheral SPI0 base pointer */
-#define SPI0_NS ((SPI_Type *)SPI0_BASE_NS)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE (0x50087000u)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE_NS (0x40087000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1 ((SPI_Type *)SPI1_BASE)
-/** Peripheral SPI1 base pointer */
-#define SPI1_NS ((SPI_Type *)SPI1_BASE_NS)
-/** Peripheral SPI2 base address */
-#define SPI2_BASE (0x50088000u)
-/** Peripheral SPI2 base address */
-#define SPI2_BASE_NS (0x40088000u)
-/** Peripheral SPI2 base pointer */
-#define SPI2 ((SPI_Type *)SPI2_BASE)
-/** Peripheral SPI2 base pointer */
-#define SPI2_NS ((SPI_Type *)SPI2_BASE_NS)
-/** Peripheral SPI3 base address */
-#define SPI3_BASE (0x50089000u)
-/** Peripheral SPI3 base address */
-#define SPI3_BASE_NS (0x40089000u)
-/** Peripheral SPI3 base pointer */
-#define SPI3 ((SPI_Type *)SPI3_BASE)
-/** Peripheral SPI3 base pointer */
-#define SPI3_NS ((SPI_Type *)SPI3_BASE_NS)
-/** Peripheral SPI4 base address */
-#define SPI4_BASE (0x5008A000u)
-/** Peripheral SPI4 base address */
-#define SPI4_BASE_NS (0x4008A000u)
-/** Peripheral SPI4 base pointer */
-#define SPI4 ((SPI_Type *)SPI4_BASE)
-/** Peripheral SPI4 base pointer */
-#define SPI4_NS ((SPI_Type *)SPI4_BASE_NS)
-/** Peripheral SPI5 base address */
-#define SPI5_BASE (0x50096000u)
-/** Peripheral SPI5 base address */
-#define SPI5_BASE_NS (0x40096000u)
-/** Peripheral SPI5 base pointer */
-#define SPI5 ((SPI_Type *)SPI5_BASE)
-/** Peripheral SPI5 base pointer */
-#define SPI5_NS ((SPI_Type *)SPI5_BASE_NS)
-/** Peripheral SPI6 base address */
-#define SPI6_BASE (0x50097000u)
-/** Peripheral SPI6 base address */
-#define SPI6_BASE_NS (0x40097000u)
-/** Peripheral SPI6 base pointer */
-#define SPI6 ((SPI_Type *)SPI6_BASE)
-/** Peripheral SPI6 base pointer */
-#define SPI6_NS ((SPI_Type *)SPI6_BASE_NS)
-/** Peripheral SPI7 base address */
-#define SPI7_BASE (0x50098000u)
-/** Peripheral SPI7 base address */
-#define SPI7_BASE_NS (0x40098000u)
-/** Peripheral SPI7 base pointer */
-#define SPI7 ((SPI_Type *)SPI7_BASE)
-/** Peripheral SPI7 base pointer */
-#define SPI7_NS ((SPI_Type *)SPI7_BASE_NS)
-/** Peripheral SPI8 base address */
-#define SPI8_BASE (0x5009F000u)
-/** Peripheral SPI8 base address */
-#define SPI8_BASE_NS (0x4009F000u)
-/** Peripheral SPI8 base pointer */
-#define SPI8 ((SPI_Type *)SPI8_BASE)
-/** Peripheral SPI8 base pointer */
-#define SPI8_NS ((SPI_Type *)SPI8_BASE_NS)
-/** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS \
- { \
- SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE \
- }
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS \
- { \
- SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 \
- }
-/** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS_NS \
- { \
- SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, \
- SPI7_BASE_NS, SPI8_BASE_NS \
- }
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS_NS \
- { \
- SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS \
- }
+ /** Peripheral SPI0 base address */
+ #define SPI0_BASE (0x50086000u)
+ /** Peripheral SPI0 base address */
+ #define SPI0_BASE_NS (0x40086000u)
+ /** Peripheral SPI0 base pointer */
+ #define SPI0 ((SPI_Type *)SPI0_BASE)
+ /** Peripheral SPI0 base pointer */
+ #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS)
+ /** Peripheral SPI1 base address */
+ #define SPI1_BASE (0x50087000u)
+ /** Peripheral SPI1 base address */
+ #define SPI1_BASE_NS (0x40087000u)
+ /** Peripheral SPI1 base pointer */
+ #define SPI1 ((SPI_Type *)SPI1_BASE)
+ /** Peripheral SPI1 base pointer */
+ #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS)
+ /** Peripheral SPI2 base address */
+ #define SPI2_BASE (0x50088000u)
+ /** Peripheral SPI2 base address */
+ #define SPI2_BASE_NS (0x40088000u)
+ /** Peripheral SPI2 base pointer */
+ #define SPI2 ((SPI_Type *)SPI2_BASE)
+ /** Peripheral SPI2 base pointer */
+ #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS)
+ /** Peripheral SPI3 base address */
+ #define SPI3_BASE (0x50089000u)
+ /** Peripheral SPI3 base address */
+ #define SPI3_BASE_NS (0x40089000u)
+ /** Peripheral SPI3 base pointer */
+ #define SPI3 ((SPI_Type *)SPI3_BASE)
+ /** Peripheral SPI3 base pointer */
+ #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS)
+ /** Peripheral SPI4 base address */
+ #define SPI4_BASE (0x5008A000u)
+ /** Peripheral SPI4 base address */
+ #define SPI4_BASE_NS (0x4008A000u)
+ /** Peripheral SPI4 base pointer */
+ #define SPI4 ((SPI_Type *)SPI4_BASE)
+ /** Peripheral SPI4 base pointer */
+ #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS)
+ /** Peripheral SPI5 base address */
+ #define SPI5_BASE (0x50096000u)
+ /** Peripheral SPI5 base address */
+ #define SPI5_BASE_NS (0x40096000u)
+ /** Peripheral SPI5 base pointer */
+ #define SPI5 ((SPI_Type *)SPI5_BASE)
+ /** Peripheral SPI5 base pointer */
+ #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS)
+ /** Peripheral SPI6 base address */
+ #define SPI6_BASE (0x50097000u)
+ /** Peripheral SPI6 base address */
+ #define SPI6_BASE_NS (0x40097000u)
+ /** Peripheral SPI6 base pointer */
+ #define SPI6 ((SPI_Type *)SPI6_BASE)
+ /** Peripheral SPI6 base pointer */
+ #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS)
+ /** Peripheral SPI7 base address */
+ #define SPI7_BASE (0x50098000u)
+ /** Peripheral SPI7 base address */
+ #define SPI7_BASE_NS (0x40098000u)
+ /** Peripheral SPI7 base pointer */
+ #define SPI7 ((SPI_Type *)SPI7_BASE)
+ /** Peripheral SPI7 base pointer */
+ #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS)
+ /** Peripheral SPI8 base address */
+ #define SPI8_BASE (0x5009F000u)
+ /** Peripheral SPI8 base address */
+ #define SPI8_BASE_NS (0x4009F000u)
+ /** Peripheral SPI8 base pointer */
+ #define SPI8 ((SPI_Type *)SPI8_BASE)
+ /** Peripheral SPI8 base pointer */
+ #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS)
+ /** Array initializer of SPI peripheral base addresses */
+ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }
+ /** Array initializer of SPI peripheral base pointers */
+ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }
+ /** Array initializer of SPI peripheral base addresses */
+ #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS }
+ /** Array initializer of SPI peripheral base pointers */
+ #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS }
#else
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x40086000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE (0x40087000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1 ((SPI_Type *)SPI1_BASE)
-/** Peripheral SPI2 base address */
-#define SPI2_BASE (0x40088000u)
-/** Peripheral SPI2 base pointer */
-#define SPI2 ((SPI_Type *)SPI2_BASE)
-/** Peripheral SPI3 base address */
-#define SPI3_BASE (0x40089000u)
-/** Peripheral SPI3 base pointer */
-#define SPI3 ((SPI_Type *)SPI3_BASE)
-/** Peripheral SPI4 base address */
-#define SPI4_BASE (0x4008A000u)
-/** Peripheral SPI4 base pointer */
-#define SPI4 ((SPI_Type *)SPI4_BASE)
-/** Peripheral SPI5 base address */
-#define SPI5_BASE (0x40096000u)
-/** Peripheral SPI5 base pointer */
-#define SPI5 ((SPI_Type *)SPI5_BASE)
-/** Peripheral SPI6 base address */
-#define SPI6_BASE (0x40097000u)
-/** Peripheral SPI6 base pointer */
-#define SPI6 ((SPI_Type *)SPI6_BASE)
-/** Peripheral SPI7 base address */
-#define SPI7_BASE (0x40098000u)
-/** Peripheral SPI7 base pointer */
-#define SPI7 ((SPI_Type *)SPI7_BASE)
-/** Peripheral SPI8 base address */
-#define SPI8_BASE (0x4009F000u)
-/** Peripheral SPI8 base pointer */
-#define SPI8 ((SPI_Type *)SPI8_BASE)
-/** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS \
- { \
- SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE \
- }
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS \
- { \
- SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 \
- }
+ /** Peripheral SPI0 base address */
+ #define SPI0_BASE (0x40086000u)
+ /** Peripheral SPI0 base pointer */
+ #define SPI0 ((SPI_Type *)SPI0_BASE)
+ /** Peripheral SPI1 base address */
+ #define SPI1_BASE (0x40087000u)
+ /** Peripheral SPI1 base pointer */
+ #define SPI1 ((SPI_Type *)SPI1_BASE)
+ /** Peripheral SPI2 base address */
+ #define SPI2_BASE (0x40088000u)
+ /** Peripheral SPI2 base pointer */
+ #define SPI2 ((SPI_Type *)SPI2_BASE)
+ /** Peripheral SPI3 base address */
+ #define SPI3_BASE (0x40089000u)
+ /** Peripheral SPI3 base pointer */
+ #define SPI3 ((SPI_Type *)SPI3_BASE)
+ /** Peripheral SPI4 base address */
+ #define SPI4_BASE (0x4008A000u)
+ /** Peripheral SPI4 base pointer */
+ #define SPI4 ((SPI_Type *)SPI4_BASE)
+ /** Peripheral SPI5 base address */
+ #define SPI5_BASE (0x40096000u)
+ /** Peripheral SPI5 base pointer */
+ #define SPI5 ((SPI_Type *)SPI5_BASE)
+ /** Peripheral SPI6 base address */
+ #define SPI6_BASE (0x40097000u)
+ /** Peripheral SPI6 base pointer */
+ #define SPI6 ((SPI_Type *)SPI6_BASE)
+ /** Peripheral SPI7 base address */
+ #define SPI7_BASE (0x40098000u)
+ /** Peripheral SPI7 base pointer */
+ #define SPI7 ((SPI_Type *)SPI7_BASE)
+ /** Peripheral SPI8 base address */
+ #define SPI8_BASE (0x4009F000u)
+ /** Peripheral SPI8 base pointer */
+ #define SPI8 ((SPI_Type *)SPI8_BASE)
+ /** Array initializer of SPI peripheral base addresses */
+ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }
+ /** Array initializer of SPI peripheral base pointers */
+ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }
#endif
/** Interrupt vectors for the SPI peripheral type */
-#define SPI_IRQS \
- { \
- FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, \
- FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn \
- }
+#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn }
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- SYSCON Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -21032,206 +20725,178 @@ typedef struct
*/
/** SYSCON - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */
- uint8_t RESERVED_0[12];
- __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest,
- offset: 0x10 */
- uint8_t RESERVED_1[36];
- __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */
- __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */
- __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */
- uint8_t RESERVED_2[4];
- __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
- uint8_t RESERVED_3[180];
- union
- { /* offset: 0x100 */
- struct
- { /* offset: 0x100 */
- __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */
- __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */
- __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */
- } PRESETCTRL;
- __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */
- };
- uint8_t RESERVED_4[20];
- __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */
- uint8_t RESERVED_5[20];
- __IO uint32_t
- PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */
- uint8_t RESERVED_6[20];
- __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */
- uint8_t RESERVED_7[156];
- union
- { /* offset: 0x200 */
- struct
- { /* offset: 0x200 */
- __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */
- __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */
- __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */
- } AHBCLKCTRL;
- __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */
- };
- uint8_t RESERVED_8[20];
- __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */
- uint8_t RESERVED_9[20];
- __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */
- uint8_t RESERVED_10[20];
- union
- { /* offset: 0x260 */
- struct
- { /* offset: 0x260 */
- __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */
- __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */
- } SYSTICKCLKSEL;
- __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */
- };
- __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */
- union
- { /* offset: 0x26C */
- struct
- { /* offset: 0x26C */
- __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */
- __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */
- __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */
- __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */
- __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */
- } CTIMERCLKSEL;
- __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */
- };
- __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */
- __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */
- __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */
- uint8_t RESERVED_11[4];
- __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */
- __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */
- uint8_t RESERVED_12[12];
- __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
- __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */
- uint8_t RESERVED_13[4];
- union
- { /* offset: 0x2B0 */
- struct
- { /* offset: 0x2B0 */
- __IO uint32_t
- FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */
- __IO uint32_t
- FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */
- __IO uint32_t
- FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */
- __IO uint32_t
- FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */
- __IO uint32_t
- FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */
- __IO uint32_t
- FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */
- __IO uint32_t
- FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */
- __IO uint32_t
- FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */
- } FCCLKSEL;
- __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */
- };
- __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */
- uint8_t RESERVED_14[12];
- __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
- uint8_t RESERVED_15[12];
- __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */
- uint8_t RESERVED_16[4];
- __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */
- uint8_t RESERVED_17[4];
- __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */
- __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */
- __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */
- uint8_t RESERVED_18[20];
- union
- { /* offset: 0x320 */
- struct
- { /* offset: 0x320 */
- __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */
- __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */
- __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */
- __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */
- __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */
- __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */
- __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */
- __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */
- } FLEXFRGCTRL;
- __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */
- };
- uint8_t RESERVED_19[64];
- __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */
- __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
- __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */
- __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */
- uint8_t RESERVED_20[4];
- __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
- __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */
- uint8_t RESERVED_21[16];
- __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
- uint8_t RESERVED_22[4];
- __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */
- uint8_t RESERVED_23[4];
- __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */
- uint8_t RESERVED_24[4];
- __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */
- uint8_t RESERVED_25[52];
- __IO uint32_t
- CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */
- __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */
- uint8_t RESERVED_26[8];
- __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */
- __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */
- uint8_t RESERVED_27[8];
- __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */
- __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */
- __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */
- __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */
- uint8_t RESERVED_28[52];
- __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
- uint8_t RESERVED_29[252];
- __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */
- __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */
- __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */
- __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */
- __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */
- uint8_t RESERVED_30[12];
- __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */
- __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */
- __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */
- __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */
- __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */
- __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */
- uint8_t RESERVED_31[616];
- __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */
- __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */
- uint8_t RESERVED_32[4];
- __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */
- uint8_t RESERVED_33[520];
- __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency
- Measures, offset: 0xA18 */
- uint8_t RESERVED_34[244];
- __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */
- __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */
- uint8_t RESERVED_35[748];
- __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */
- __IO uint32_t
- GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */
- uint8_t RESERVED_36[404];
- __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */
- __IO uint32_t
- DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */
- __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE
- register., offset: 0xFA8 */
- uint8_t RESERVED_37[16];
- __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */
- __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */
- uint8_t RESERVED_38[16];
- __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */
- uint8_t RESERVED_39[32];
- __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */
- __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */
+typedef struct {
+ __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */
+ uint8_t RESERVED_1[36];
+ __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */
+ __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */
+ __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
+ uint8_t RESERVED_3[180];
+ union { /* offset: 0x100 */
+ struct { /* offset: 0x100 */
+ __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */
+ __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */
+ __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */
+ } PRESETCTRL;
+ __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */
+ };
+ uint8_t RESERVED_4[20];
+ __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */
+ uint8_t RESERVED_5[20];
+ __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */
+ uint8_t RESERVED_6[20];
+ __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */
+ uint8_t RESERVED_7[156];
+ union { /* offset: 0x200 */
+ struct { /* offset: 0x200 */
+ __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */
+ __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */
+ __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */
+ } AHBCLKCTRL;
+ __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */
+ };
+ uint8_t RESERVED_8[20];
+ __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */
+ uint8_t RESERVED_9[20];
+ __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */
+ uint8_t RESERVED_10[20];
+ union { /* offset: 0x260 */
+ struct { /* offset: 0x260 */
+ __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */
+ __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */
+ } SYSTICKCLKSEL;
+ __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */
+ };
+ __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */
+ union { /* offset: 0x26C */
+ struct { /* offset: 0x26C */
+ __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */
+ __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */
+ __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */
+ __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */
+ __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */
+ } CTIMERCLKSEL;
+ __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */
+ };
+ __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */
+ __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */
+ __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */
+ uint8_t RESERVED_11[4];
+ __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */
+ __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */
+ uint8_t RESERVED_12[12];
+ __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
+ __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */
+ uint8_t RESERVED_13[4];
+ union { /* offset: 0x2B0 */
+ struct { /* offset: 0x2B0 */
+ __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */
+ __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */
+ __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */
+ __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */
+ __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */
+ __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */
+ __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */
+ __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */
+ } FCCLKSEL;
+ __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */
+ };
+ __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */
+ uint8_t RESERVED_14[12];
+ __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
+ uint8_t RESERVED_15[12];
+ __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */
+ uint8_t RESERVED_16[4];
+ __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */
+ uint8_t RESERVED_17[4];
+ __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */
+ __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */
+ __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */
+ uint8_t RESERVED_18[20];
+ union { /* offset: 0x320 */
+ struct { /* offset: 0x320 */
+ __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */
+ __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */
+ __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */
+ __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */
+ __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */
+ __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */
+ __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */
+ __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */
+ } FLEXFRGCTRL;
+ __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */
+ };
+ uint8_t RESERVED_19[64];
+ __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */
+ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
+ __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */
+ __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */
+ uint8_t RESERVED_20[4];
+ __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
+ __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */
+ uint8_t RESERVED_21[16];
+ __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
+ uint8_t RESERVED_22[4];
+ __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */
+ uint8_t RESERVED_23[4];
+ __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */
+ uint8_t RESERVED_24[4];
+ __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */
+ uint8_t RESERVED_25[52];
+ __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */
+ __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */
+ uint8_t RESERVED_26[8];
+ __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */
+ __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */
+ uint8_t RESERVED_27[8];
+ __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */
+ __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */
+ __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */
+ __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */
+ uint8_t RESERVED_28[52];
+ __O uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
+ uint8_t RESERVED_29[252];
+ __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */
+ __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */
+ __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */
+ __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */
+ __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */
+ uint8_t RESERVED_30[12];
+ __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */
+ __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */
+ __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */
+ __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */
+ __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */
+ __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */
+ uint8_t RESERVED_31[616];
+ __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */
+ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */
+ uint8_t RESERVED_32[4];
+ __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */
+ uint8_t RESERVED_33[520];
+ __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */
+ uint8_t RESERVED_34[244];
+ __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */
+ __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */
+ uint8_t RESERVED_35[748];
+ __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */
+ __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */
+ uint8_t RESERVED_36[404];
+ __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */
+ __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */
+ __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */
+ uint8_t RESERVED_37[16];
+ __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */
+ __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */
+ uint8_t RESERVED_38[16];
+ __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */
+ uint8_t RESERVED_39[32];
+ __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */
+ __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */
} SYSCON_Type;
/* ----------------------------------------------------------------------------
@@ -21245,1279 +20910,1274 @@ typedef struct
/*! @name MEMORYREMAP - Memory Remap control register */
/*! @{ */
-#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U)
-#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U)
+
+#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U)
+#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U)
/*! MAP - Select the location of the vector table :.
* 0b00..Vector Table in ROM.
* 0b01..Vector Table in RAM.
* 0b10..Vector Table in Flash.
* 0b11..Vector Table in Flash.
*/
-#define SYSCON_MEMORYREMAP_MAP(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)
+#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)
/*! @} */
/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */
/*! @{ */
-#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U)
-#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U)
+
+#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U)
/*! PRI_CPU0_CBUS - CPU0 C-AHB bus.
*/
-#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU)
-#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U)
+#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U)
/*! PRI_CPU0_SBUS - CPU0 S-AHB bus.
*/
-#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U)
-#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U)
+#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U)
/*! PRI_CPU1_CBUS - CPU1 C-AHB bus.
*/
-#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U)
-#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U)
+#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U)
+#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U)
/*! PRI_CPU1_SBUS - CPU1 S-AHB bus.
*/
-#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U)
-#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U)
+#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U)
+#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U)
/*! PRI_USB_FS - USB-FS.(USB0)
*/
-#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U)
-#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U)
+#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U)
/*! PRI_SDMA0 - DMA0 controller priority.
*/
-#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U)
-#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U)
+#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U)
/*! PRI_SDIO - SDIO.
*/
-#define SYSCON_AHBMATPRIO_PRI_SDIO(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
-#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U)
-#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U)
+#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U)
/*! PRI_PQ - PQ (HW Accelerator).
*/
-#define SYSCON_AHBMATPRIO_PRI_PQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK)
-#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U)
-#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U)
+#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U)
+#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U)
/*! PRI_HASH_AES - HASH_AES.
*/
-#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK)
-#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U)
-#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U)
+#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U)
+#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U)
/*! PRI_USB_HS - USB-HS.(USB1)
*/
-#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U)
-#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U)
+#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK)
+
+#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U)
+#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U)
/*! PRI_SDMA1 - DMA1 controller priority.
*/
-#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK)
/*! @} */
/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */
/*! @{ */
-#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU)
-#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U)
+
+#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU)
+#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U)
/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
* reads as zero, the calibration value is not known.
*/
-#define SYSCON_CPU0STCKCAL_TENMS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK)
-#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U)
-#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U)
+#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK)
+
+#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U)
+#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U)
/*! SKEW - Initial value for the Systick timer.
*/
-#define SYSCON_CPU0STCKCAL_SKEW(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK)
-#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U)
-#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U)
+#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK)
+
+#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U)
+#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U)
/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference
* clock provided; 1 = no reference clock provided.
*/
-#define SYSCON_CPU0STCKCAL_NOREF(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK)
+#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK)
/*! @} */
/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */
/*! @{ */
-#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU)
-#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U)
+
+#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU)
+#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U)
/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the
* value reads as zero, the calibration value is not known.
*/
-#define SYSCON_CPU0NSTCKCAL_TENMS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)
-#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U)
-#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U)
-/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not
- * given.
- */
-#define SYSCON_CPU0NSTCKCAL_SKEW(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)
-#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U)
-#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U)
+#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK)
+
+#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U)
+#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U)
+/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.
+ */
+#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)
+
+#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U)
+#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U)
/*! NOREF - Initial value for the Systick timer.
*/
-#define SYSCON_CPU0NSTCKCAL_NOREF(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
+#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)
/*! @} */
/*! @name CPU1STCKCAL - System tick calibration for CPU1 */
/*! @{ */
-#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU)
-#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U)
+
+#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU)
+#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U)
/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
* reads as zero, the calibration value is not known.
*/
-#define SYSCON_CPU1STCKCAL_TENMS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK)
-#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U)
-#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U)
-/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not
- * given.
- */
-#define SYSCON_CPU1STCKCAL_SKEW(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK)
-#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U)
-#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U)
+#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK)
+
+#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U)
+#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U)
+/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given.
+ */
+#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK)
+
+#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U)
+#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U)
/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference
* clock provided; 1 = no reference clock provided.
*/
-#define SYSCON_CPU1STCKCAL_NOREF(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK)
+#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK)
/*! @} */
/*! @name NMISRC - NMI Source Select */
/*! @{ */
-#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU)
-#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U)
-/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by
- * NMIENCPU0.
- */
-#define SYSCON_NMISRC_IRQCPU0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)
-#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U)
-#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U)
-/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by
- * NMIENCPU1.
- */
-#define SYSCON_NMISRC_IRQCPU1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK)
-#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U)
-#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U)
+
+#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU)
+#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U)
+/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0.
+ */
+#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)
+
+#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U)
+#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U)
+/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1.
+ */
+#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK)
+
+#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U)
+#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U)
/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1.
*/
-#define SYSCON_NMISRC_NMIENCPU1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK)
-#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U)
-#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U)
+#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK)
+
+#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U)
+#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U)
/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.
*/
-#define SYSCON_NMISRC_NMIENCPU0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
+#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)
/*! @} */
/*! @name PRESETCTRL0 - Peripheral reset control 0 */
/*! @{ */
-#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U)
-#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U)
+
+#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U)
+#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U)
/*! ROM_RST - ROM reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_ROM_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U)
+#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U)
/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U)
/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U)
/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U)
-#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U)
/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK)
-#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U)
-#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U)
+#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U)
+#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U)
/*! FLASH_RST - Flash controller reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_FLASH_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)
-#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U)
+#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U)
/*! FMC_RST - FMC controller reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_FMC_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK)
-#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U)
-#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U)
+#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U)
/*! MUX_RST - Input Mux reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_MUX_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK)
-#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U)
-#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U)
+#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U)
/*! IOCON_RST - I/O controller reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_IOCON_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK)
-#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U)
-#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U)
+#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U)
/*! GPIO0_RST - GPIO0 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_GPIO0_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK)
-#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U)
-#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U)
+#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U)
/*! GPIO1_RST - GPIO1 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_GPIO1_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK)
-#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U)
-#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U)
+#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U)
/*! GPIO2_RST - GPIO2 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_GPIO2_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK)
-#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U)
-#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U)
+#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U)
/*! GPIO3_RST - GPIO3 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_GPIO3_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK)
-#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U)
-#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U)
+#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U)
/*! PINT_RST - Pin interrupt (PINT) reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_PINT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK)
-#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U)
-#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U)
+#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U)
/*! GINT_RST - Group interrupt (GINT) reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_GINT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK)
-#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U)
-#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U)
+#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U)
+#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U)
/*! DMA0_RST - DMA0 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_DMA0_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK)
-#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U)
-#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U)
+#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U)
+#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U)
/*! CRCGEN_RST - CRCGEN reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK)
-#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U)
-#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U)
+#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U)
/*! WWDT_RST - Watchdog Timer reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_WWDT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK)
-#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U)
-#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U)
+#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U)
+#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U)
/*! RTC_RST - Real Time Clock (RTC) reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_RTC_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK)
-#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U)
-#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U)
+#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U)
+#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U)
/*! MAILBOX_RST - Inter CPU communication Mailbox reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK)
-#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U)
-#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U)
+#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK)
+
+#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U)
/*! ADC_RST - ADC reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL0_ADC_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK)
+#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK)
/*! @} */
/*! @name PRESETCTRL1 - Peripheral reset control 1 */
/*! @{ */
-#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U)
-#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U)
+
+#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U)
+#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U)
/*! MRT_RST - MRT reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_MRT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK)
-#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U)
-#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U)
+#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U)
+#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U)
/*! OSTIMER_RST - OS Event Timer reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK)
-#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U)
-#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U)
+#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U)
+#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U)
/*! SCT_RST - SCT reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_SCT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK)
-#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U)
-#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U)
+#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U)
+#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U)
/*! SCTIPU_RST - SCTIPU reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK)
-#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U)
-#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U)
+#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U)
/*! UTICK_RST - UTICK reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_UTICK_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U)
-#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U)
+#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U)
/*! FC0_RST - FC0 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC0_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U)
-#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U)
+#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U)
+#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U)
/*! FC1_RST - FC1 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC1_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U)
-#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U)
+#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U)
/*! FC2_RST - FC2 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC2_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U)
-#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U)
+#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U)
/*! FC3_RST - FC3 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC3_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U)
-#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U)
+#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U)
/*! FC4_RST - FC4 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC4_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U)
-#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U)
+#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U)
/*! FC5_RST - FC5 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC5_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U)
-#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U)
+#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U)
/*! FC6_RST - FC6 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC6_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK)
-#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U)
-#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U)
+#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U)
/*! FC7_RST - FC7 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_FC7_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK)
-#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U)
-#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U)
+#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U)
/*! TIMER2_RST - Timer 2 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_TIMER2_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK)
-#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U)
-#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U)
+#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U)
+#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U)
/*! USB0_DEV_RST - USB0 DEV reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK)
-#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U)
-#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U)
+#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U)
+#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U)
/*! TIMER0_RST - Timer 0 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_TIMER0_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK)
-#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U)
-#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U)
+#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK)
+
+#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U)
/*! TIMER1_RST - Timer 1 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL1_TIMER1_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK)
+#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK)
/*! @} */
/*! @name PRESETCTRL2 - Peripheral reset control 2 */
/*! @{ */
-#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U)
-#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U)
+
+#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U)
+#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U)
/*! DMA1_RST - DMA1 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_DMA1_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK)
-#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U)
-#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U)
+#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U)
+#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U)
/*! COMP_RST - Comparator reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_COMP_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK)
-#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U)
-#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U)
+#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U)
+#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U)
/*! SDIO_RST - SDIO reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_SDIO_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK)
-#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U)
-#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U)
+#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U)
+#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U)
/*! USB1_HOST_RST - USB1 Host reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK)
-#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U)
-#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U)
+#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U)
+#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U)
/*! USB1_DEV_RST - USB1 dev reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK)
-#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U)
-#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U)
+#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U)
+#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U)
/*! USB1_RAM_RST - USB1 RAM reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK)
-#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U)
-#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U)
+#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U)
+#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U)
/*! USB1_PHY_RST - USB1 PHY reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK)
-#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U)
+#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U)
/*! FREQME_RST - Frequency meter reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_FREQME_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK)
-#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U)
-#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U)
+#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U)
/*! RNG_RST - RNG reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_RNG_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK)
-#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U)
-#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U)
+#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U)
/*! SYSCTL_RST - SYSCTL Block reset.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK)
-#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U)
-#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U)
+#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U)
/*! USB0_HOSTM_RST - USB0 Host Master reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK)
-#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U)
-#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U)
+#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U)
/*! USB0_HOSTS_RST - USB0 Host Slave reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK)
-#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U)
-#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U)
+#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U)
/*! HASH_AES_RST - HASH_AES reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK)
-#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U)
-#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U)
+#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U)
/*! PQ_RST - Power Quad reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_PQ_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK)
-#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U)
-#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U)
+#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U)
+#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U)
/*! PLULUT_RST - PLU LUT reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_PLULUT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK)
-#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U)
-#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U)
+#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U)
+#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U)
/*! TIMER3_RST - Timer 3 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_TIMER3_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK)
-#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U)
-#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U)
+#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U)
/*! TIMER4_RST - Timer 4 reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_TIMER4_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK)
-#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U)
-#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U)
+#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U)
+#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U)
/*! PUF_RST - PUF reset control reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_PUF_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK)
-#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U)
-#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U)
+#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U)
+#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U)
/*! CASPER_RST - Casper reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_CASPER_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK)
-#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U)
#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U)
/*! ANALOG_CTRL_RST - analog control reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & \
- SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK)
-#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U)
-#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U)
+#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U)
+#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U)
/*! HS_LSPI_RST - HS LSPI reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK)
-#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U)
-#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U)
+#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK)
+
+#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U)
+#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U)
/*! GPIO_SEC_RST - GPIO secure reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK)
+#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK)
+
#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U)
#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U)
/*! GPIO_SEC_INT_RST - GPIO secure int reset control.
* 0b1..Bloc is reset.
* 0b0..Bloc is not reset.
*/
-#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & \
- SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK)
+#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK)
/*! @} */
/*! @name PRESETCTRLX - Peripheral reset control register */
/*! @{ */
-#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U)
+
+#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_PRESETCTRLX_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK)
+#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK)
/*! @} */
/* The count of SYSCON_PRESETCTRLX */
-#define SYSCON_PRESETCTRLX_COUNT (3U)
+#define SYSCON_PRESETCTRLX_COUNT (3U)
/*! @name PRESETCTRLSET - Peripheral reset control set register */
/*! @{ */
-#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U)
+
+#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_PRESETCTRLSET_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK)
+#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK)
/*! @} */
/* The count of SYSCON_PRESETCTRLSET */
-#define SYSCON_PRESETCTRLSET_COUNT (3U)
+#define SYSCON_PRESETCTRLSET_COUNT (3U)
/*! @name PRESETCTRLCLR - Peripheral reset control clear register */
/*! @{ */
-#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U)
+
+#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_PRESETCTRLCLR_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK)
+#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK)
/*! @} */
/* The count of SYSCON_PRESETCTRLCLR */
-#define SYSCON_PRESETCTRLCLR_COUNT (3U)
+#define SYSCON_PRESETCTRLCLR_COUNT (3U)
/*! @name SWR_RESET - generate a software_reset */
/*! @{ */
-#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU)
-#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U)
+
+#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU)
+#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U)
/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset.
* 0b01011010000000000000000000000001..Generate a software reset.
* 0b00000000000000000000000000000000..Bloc is not reset.
*/
-#define SYSCON_SWR_RESET_SWR_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK)
+#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK)
/*! @} */
/*! @name AHBCLKCTRL0 - AHB Clock control 0 */
/*! @{ */
-#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U)
+
+#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U)
/*! ROM - Enables the clock for the ROM.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_ROM(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U)
+#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)
+
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U)
/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)
+
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U)
/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK)
+
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U)
/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U)
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK)
+
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U)
/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK)
-#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U)
-#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U)
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK)
+
+#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U)
/*! FLASH - Enables the clock for the Flash controller.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_FLASH(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)
-#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U)
+#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)
+
+#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U)
/*! FMC - Enables the clock for the FMC controller.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_FMC(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK)
-#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U)
-#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U)
+#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK)
+
+#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U)
/*! MUX - Enables the clock for the Input Mux.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_MUX(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK)
-#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U)
-#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U)
+#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK)
+
+#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U)
/*! IOCON - Enables the clock for the I/O controller.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_IOCON(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK)
-#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U)
-#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U)
+#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK)
+
+#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U)
/*! GPIO0 - Enables the clock for the GPIO0.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_GPIO0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK)
-#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U)
-#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U)
+#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK)
+
+#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U)
/*! GPIO1 - Enables the clock for the GPIO1.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_GPIO1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK)
-#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U)
-#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U)
+#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK)
+
+#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U)
/*! GPIO2 - Enables the clock for the GPIO2.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_GPIO2(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK)
-#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U)
-#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U)
+#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK)
+
+#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U)
/*! GPIO3 - Enables the clock for the GPIO3.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_GPIO3(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK)
-#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U)
-#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U)
+#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK)
+
+#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U)
/*! PINT - Enables the clock for the Pin interrupt (PINT).
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_PINT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK)
-#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U)
-#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U)
+#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK)
+
+#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U)
/*! GINT - Enables the clock for the Group interrupt (GINT).
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_GINT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK)
-#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U)
-#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U)
+#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK)
+
+#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U)
+#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U)
/*! DMA0 - Enables the clock for the DMA0.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_DMA0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK)
-#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U)
-#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U)
+#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK)
+
+#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U)
+#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U)
/*! CRCGEN - Enables the clock for the CRCGEN.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_CRCGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK)
-#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U)
-#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U)
+#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK)
+
+#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U)
/*! WWDT - Enables the clock for the Watchdog Timer.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_WWDT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK)
-#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U)
-#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U)
+#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK)
+
+#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U)
+#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U)
/*! RTC - Enables the clock for the Real Time Clock (RTC).
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_RTC(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK)
-#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U)
-#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U)
+#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK)
+
+#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U)
+#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U)
/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_MAILBOX(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK)
-#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U)
-#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U)
+#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK)
+
+#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U)
/*! ADC - Enables the clock for the ADC.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL0_ADC(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK)
+#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK)
/*! @} */
/*! @name AHBCLKCTRL1 - AHB Clock control 1 */
/*! @{ */
-#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U)
-#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U)
+
+#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U)
+#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U)
/*! MRT - Enables the clock for the MRT.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_MRT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK)
-#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U)
+#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK)
+
+#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U)
/*! OSTIMER - Enables the clock for the OS Event Timer.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_OSTIMER(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK)
-#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U)
-#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U)
+#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK)
+
+#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U)
+#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U)
/*! SCT - Enables the clock for the SCT.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_SCT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK)
-#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U)
-#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U)
+#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK)
+
+#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U)
/*! UTICK - Enables the clock for the UTICK.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_UTICK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK)
-#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U)
-#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U)
+#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U)
/*! FC0 - Enables the clock for the FC0.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK)
-#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U)
-#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U)
+#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U)
+#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U)
/*! FC1 - Enables the clock for the FC1.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK)
-#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U)
-#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U)
+#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U)
/*! FC2 - Enables the clock for the FC2.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC2(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK)
-#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U)
-#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U)
+#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U)
/*! FC3 - Enables the clock for the FC3.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC3(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK)
-#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U)
-#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U)
+#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U)
/*! FC4 - Enables the clock for the FC4.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC4(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK)
-#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U)
-#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U)
+#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U)
/*! FC5 - Enables the clock for the FC5.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC5(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK)
-#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U)
-#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U)
+#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U)
/*! FC6 - Enables the clock for the FC6.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC6(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK)
-#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U)
-#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U)
+#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK)
+
+#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U)
/*! FC7 - Enables the clock for the FC7.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_FC7(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK)
-#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U)
-#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U)
+#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK)
+
+#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U)
/*! TIMER2 - Enables the clock for the Timer 2.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_TIMER2(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK)
-#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U)
-#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U)
+#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK)
+
+#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U)
+#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U)
/*! USB0_DEV - Enables the clock for the USB0 DEV.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK)
-#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U)
-#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U)
+#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK)
+
+#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U)
+#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U)
/*! TIMER0 - Enables the clock for the Timer 0.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_TIMER0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK)
-#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U)
-#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U)
+#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK)
+
+#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U)
/*! TIMER1 - Enables the clock for the Timer 1.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL1_TIMER1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK)
+#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK)
/*! @} */
/*! @name AHBCLKCTRL2 - AHB Clock control 2 */
/*! @{ */
-#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U)
+
+#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U)
/*! DMA1 - Enables the clock for the DMA1.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_DMA1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK)
-#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U)
-#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U)
+#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK)
+
+#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U)
+#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U)
/*! COMP - Enables the clock for the Comparator.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_COMP(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK)
-#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U)
-#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U)
+#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK)
+
+#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U)
+#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U)
/*! SDIO - Enables the clock for the SDIO.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_SDIO(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK)
-#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U)
-#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U)
+#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK)
+
+#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U)
+#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U)
/*! USB1_HOST - Enables the clock for the USB1 Host.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK)
-#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U)
-#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U)
+#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK)
+
+#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U)
+#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U)
/*! USB1_DEV - Enables the clock for the USB1 dev.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK)
-#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U)
-#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U)
+#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK)
+
+#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U)
+#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U)
/*! USB1_RAM - Enables the clock for the USB1 RAM.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK)
-#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U)
-#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U)
+#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK)
+
+#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U)
/*! USB1_PHY - Enables the clock for the USB1 PHY.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK)
-#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U)
+#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK)
+
+#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U)
/*! FREQME - Enables the clock for the Frequency meter.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_FREQME(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK)
-#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U)
-#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U)
+#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK)
+
+#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U)
/*! RNG - Enables the clock for the RNG.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_RNG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK)
-#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U)
-#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U)
+#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK)
+
+#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U)
/*! SYSCTL - SYSCTL block clock.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_SYSCTL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK)
-#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U)
-#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U)
+#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK)
+
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U)
/*! USB0_HOSTM - Enables the clock for the USB0 Host Master.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK)
-#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U)
-#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U)
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK)
+
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U)
/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK)
-#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U)
-#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U)
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK)
+
+#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U)
/*! HASH_AES - Enables the clock for the HASH_AES.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_HASH_AES(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK)
-#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U)
-#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U)
+#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK)
+
+#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U)
/*! PQ - Enables the clock for the Power Quad.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_PQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK)
-#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U)
-#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U)
+#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK)
+
+#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U)
+#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U)
/*! PLULUT - Enables the clock for the PLU LUT.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_PLULUT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK)
-#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U)
-#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U)
+#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK)
+
+#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U)
+#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U)
/*! TIMER3 - Enables the clock for the Timer 3.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_TIMER3(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK)
-#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U)
-#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U)
+#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK)
+
+#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U)
/*! TIMER4 - Enables the clock for the Timer 4.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_TIMER4(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK)
-#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U)
-#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U)
+#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK)
+
+#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U)
+#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U)
/*! PUF - Enables the clock for the PUF reset control.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_PUF(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK)
-#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U)
-#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U)
+#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK)
+
+#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U)
+#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U)
/*! CASPER - Enables the clock for the Casper.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_CASPER(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK)
-#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U)
-#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U)
+#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK)
+
+#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U)
/*! ANALOG_CTRL - Enables the clock for the analog control.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK)
-#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U)
-#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U)
+#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK)
+
+#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U)
+#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U)
/*! HS_LSPI - Enables the clock for the HS LSPI.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK)
-#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U)
-#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U)
+#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK)
+
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U)
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U)
/*! GPIO_SEC - Enables the clock for the GPIO secure.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK)
-#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U)
-#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U)
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK)
+
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U)
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U)
/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int.
* 0b1..Enable Clock.
* 0b0..Disable Clock.
*/
-#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK)
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK)
/*! @} */
/*! @name AHBCLKCTRLX - Peripheral reset control register */
/*! @{ */
-#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U)
+
+#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_AHBCLKCTRLX_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK)
+#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK)
/*! @} */
/* The count of SYSCON_AHBCLKCTRLX */
-#define SYSCON_AHBCLKCTRLX_COUNT (3U)
+#define SYSCON_AHBCLKCTRLX_COUNT (3U)
/*! @name AHBCLKCTRLSET - Peripheral reset control register */
/*! @{ */
-#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U)
+
+#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_AHBCLKCTRLSET_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK)
+#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK)
/*! @} */
/* The count of SYSCON_AHBCLKCTRLSET */
-#define SYSCON_AHBCLKCTRLSET_COUNT (3U)
+#define SYSCON_AHBCLKCTRLSET_COUNT (3U)
/*! @name AHBCLKCTRLCLR - Peripheral reset control register */
/*! @{ */
-#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U)
+
+#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_AHBCLKCTRLCLR_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK)
+#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK)
/*! @} */
/* The count of SYSCON_AHBCLKCTRLCLR */
-#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)
+#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)
/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */
/*! @{ */
-#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U)
-#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U)
+
+#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U)
+#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U)
/*! SEL - System Tick Timer for CPU0 source select.
* 0b000..System Tick 0 divided clock.
* 0b001..FRO 1MHz clock.
@@ -22528,14 +22188,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_SYSTICKCLKSEL0_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK)
+#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK)
/*! @} */
/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */
/*! @{ */
-#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U)
-#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U)
+
+#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U)
+#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U)
/*! SEL - System Tick Timer for CPU1 source select.
* 0b000..System Tick 1 divided clock.
* 0b001..FRO 1MHz clock.
@@ -22546,27 +22206,27 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_SYSTICKCLKSEL1_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK)
+#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK)
/*! @} */
/*! @name SYSTICKCLKSELX - Peripheral reset control register */
/*! @{ */
-#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U)
+
+#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_SYSTICKCLKSELX_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK)
+#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK)
/*! @} */
/* The count of SYSCON_SYSTICKCLKSELX */
-#define SYSCON_SYSTICKCLKSELX_COUNT (2U)
+#define SYSCON_SYSTICKCLKSELX_COUNT (2U)
/*! @name TRACECLKSEL - Trace clock source select */
/*! @{ */
-#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U)
-#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U)
+#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U)
/*! SEL - Trace clock source select.
* 0b000..Trace divided clock.
* 0b001..FRO 1MHz clock.
@@ -22577,14 +22237,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_TRACECLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK)
+#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK)
/*! @} */
/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */
/*! @{ */
-#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U)
-#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U)
+
+#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U)
+#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U)
/*! SEL - CTimer 0 clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22595,14 +22255,14 @@ typedef struct
* 0b110..Oscillator 32kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_CTIMERCLKSEL0_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK)
+#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK)
/*! @} */
/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */
/*! @{ */
-#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U)
-#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U)
+
+#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U)
+#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U)
/*! SEL - CTimer 1 clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22613,14 +22273,14 @@ typedef struct
* 0b110..Oscillator 32kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_CTIMERCLKSEL1_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK)
+#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK)
/*! @} */
/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */
/*! @{ */
-#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U)
-#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U)
+
+#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U)
+#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U)
/*! SEL - CTimer 2 clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22631,14 +22291,14 @@ typedef struct
* 0b110..Oscillator 32kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_CTIMERCLKSEL2_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK)
+#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK)
/*! @} */
/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */
/*! @{ */
-#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U)
-#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U)
+
+#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U)
+#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U)
/*! SEL - CTimer 3 clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22649,14 +22309,14 @@ typedef struct
* 0b110..Oscillator 32kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_CTIMERCLKSEL3_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK)
+#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK)
/*! @} */
/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */
/*! @{ */
-#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U)
-#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U)
+
+#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U)
+#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U)
/*! SEL - CTimer 4 clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22667,27 +22327,27 @@ typedef struct
* 0b110..Oscillator 32kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_CTIMERCLKSEL4_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK)
+#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK)
/*! @} */
/*! @name CTIMERCLKSELX - Peripheral reset control register */
/*! @{ */
-#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U)
+
+#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_CTIMERCLKSELX_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK)
+#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK)
/*! @} */
/* The count of SYSCON_CTIMERCLKSELX */
-#define SYSCON_CTIMERCLKSELX_COUNT (5U)
+#define SYSCON_CTIMERCLKSELX_COUNT (5U)
/*! @name MAINCLKSELA - Main clock A source select */
/*! @{ */
-#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U)
-#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
+
+#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
/*! SEL - Main clock A source select.
* 0b000..FRO 12 MHz clock.
* 0b001..CLKIN clock.
@@ -22698,14 +22358,14 @@ typedef struct
* 0b110..Reserved.
* 0b111..Reserved.
*/
-#define SYSCON_MAINCLKSELA_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
/*! @} */
/*! @name MAINCLKSELB - Main clock source select */
/*! @{ */
-#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U)
-#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
+
+#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
/*! SEL - Main clock source select.
* 0b000..Main Clock A.
* 0b001..PLL0 clock.
@@ -22716,14 +22376,14 @@ typedef struct
* 0b110..Reserved.
* 0b111..Reserved.
*/
-#define SYSCON_MAINCLKSELB_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
/*! @} */
/*! @name CLKOUTSEL - CLKOUT clock source select */
/*! @{ */
-#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U)
-#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U)
+
+#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U)
+#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U)
/*! SEL - CLKOUT clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22734,14 +22394,14 @@ typedef struct
* 0b110..Oscillator 32kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_CLKOUTSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
+#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)
/*! @} */
/*! @name PLL0CLKSEL - PLL0 clock source select */
/*! @{ */
-#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U)
-#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U)
/*! SEL - PLL0 clock source select.
* 0b000..FRO 12 MHz clock.
* 0b001..CLKIN clock.
@@ -22752,14 +22412,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_PLL0CLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK)
+#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK)
/*! @} */
/*! @name PLL1CLKSEL - PLL1 clock source select */
/*! @{ */
-#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U)
-#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U)
/*! SEL - PLL1 clock source select.
* 0b000..FRO 12 MHz clock.
* 0b001..CLKIN clock.
@@ -22770,14 +22430,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_PLL1CLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK)
+#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK)
/*! @} */
/*! @name ADCCLKSEL - ADC clock source select */
/*! @{ */
-#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
/*! SEL - ADC clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22788,14 +22448,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_ADCCLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
/*! @} */
/*! @name USB0CLKSEL - FS USB clock source select */
/*! @{ */
-#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)
-#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)
/*! SEL - FS USB clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -22806,14 +22466,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_USB0CLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
+#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22824,14 +22484,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL0_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK)
+#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22842,14 +22502,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL1_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK)
+#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22860,14 +22520,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL2_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK)
+#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22878,14 +22538,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL3_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK)
+#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22896,14 +22556,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL4_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK)
+#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22914,14 +22574,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL5_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK)
+#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22932,14 +22592,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL6_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK)
+#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK)
/*! @} */
/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */
/*! @{ */
-#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U)
-#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U)
+
+#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U)
+#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U)
/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22950,27 +22610,27 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_FCCLKSEL7_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK)
+#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK)
/*! @} */
/*! @name FCCLKSELX - Peripheral reset control register */
/*! @{ */
-#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_FCCLKSELX_DATA_SHIFT (0U)
+
+#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_FCCLKSELX_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_FCCLKSELX_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK)
+#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK)
/*! @} */
/* The count of SYSCON_FCCLKSELX */
-#define SYSCON_FCCLKSELX_COUNT (8U)
+#define SYSCON_FCCLKSELX_COUNT (8U)
/*! @name HSLSPICLKSEL - HS LSPI clock source select */
/*! @{ */
-#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U)
-#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U)
+#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U)
/*! SEL - HS LSPI clock source select.
* 0b000..Main clock.
* 0b001..system PLL divided clock.
@@ -22981,14 +22641,14 @@ typedef struct
* 0b110..Oscillator 32 kHz clock.
* 0b111..No clock.
*/
-#define SYSCON_HSLSPICLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK)
+#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK)
/*! @} */
/*! @name MCLKCLKSEL - MCLK clock source select */
/*! @{ */
-#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
/*! SEL - MCLK clock source select.
* 0b000..FRO 96 MHz clock.
* 0b001..PLL0 clock.
@@ -22999,14 +22659,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_MCLKCLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
/*! @} */
/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
/*! @{ */
-#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)
/*! SEL - SCTimer/PWM clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -23017,14 +22677,14 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_SCTCLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
+#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
/*! @} */
/*! @name SDIOCLKSEL - SDIO clock source select */
/*! @{ */
-#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)
+
+#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)
/*! SEL - SDIO clock source select.
* 0b000..Main clock.
* 0b001..PLL0 clock.
@@ -23035,607 +22695,652 @@ typedef struct
* 0b110..No clock.
* 0b111..No clock.
*/
-#define SYSCON_SDIOCLKSEL_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
+#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
/*! @} */
/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */
/*! @{ */
-#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU)
-#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U)
+
+#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU)
+#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_SYSTICKCLKDIV0_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK)
-#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U)
-#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U)
+#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK)
+
+#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_SYSTICKCLKDIV0_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK)
-#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U)
-#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U)
+#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK)
+
+#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_SYSTICKCLKDIV0_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK)
-#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U)
+#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK)
+
+#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK)
+#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK)
/*! @} */
/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */
/*! @{ */
-#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU)
-#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U)
+
+#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU)
+#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_SYSTICKCLKDIV1_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK)
-#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U)
-#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U)
+#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK)
+
+#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_SYSTICKCLKDIV1_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK)
-#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U)
-#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U)
+#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK)
+
+#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_SYSTICKCLKDIV1_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK)
-#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U)
+#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK)
+
+#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK)
+#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK)
/*! @} */
/*! @name TRACECLKDIV - TRACE clock divider */
/*! @{ */
-#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_TRACECLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)
-#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U)
+#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)
+
+#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_TRACECLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)
-#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U)
+#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)
+
+#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_TRACECLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)
-#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)
+
+#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_TRACECLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK)
+#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */
/*! @{ */
-#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG0CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG0CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */
/*! @{ */
-#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG1CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG1CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */
/*! @{ */
-#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG2CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG2CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */
/*! @{ */
-#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG3CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG3CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */
/*! @{ */
-#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG4CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG4CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */
/*! @{ */
-#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG5CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG5CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */
/*! @{ */
-#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG6CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG6CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */
/*! @{ */
-#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU)
-#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U)
+
+#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU)
+#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U)
/*! DIV - Denominator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG7CTRL_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK)
-#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U)
+#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK)
+
+#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U)
/*! MULT - Numerator of the fractional rate divider.
*/
-#define SYSCON_FLEXFRG7CTRL_MULT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK)
+#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK)
/*! @} */
/*! @name FLEXFRGXCTRL - Peripheral reset control register */
/*! @{ */
-#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU)
-#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U)
+
+#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU)
+#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U)
/*! DATA - Data array value
*/
-#define SYSCON_FLEXFRGXCTRL_DATA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK)
+#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK)
/*! @} */
/* The count of SYSCON_FLEXFRGXCTRL */
-#define SYSCON_FLEXFRGXCTRL_COUNT (8U)
+#define SYSCON_FLEXFRGXCTRL_COUNT (8U)
/*! @name AHBCLKDIV - System clock divider */
/*! @{ */
-#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_AHBCLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
-#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+
+#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_AHBCLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)
-#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)
+
+#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_AHBCLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)
-#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)
+
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_AHBCLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
+#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name CLKOUTDIV - CLKOUT clock divider */
/*! @{ */
-#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
-#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
+
+#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_CLKOUTDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
-#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
-#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
+#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+
+#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_CLKOUTDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
-#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
-#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
+#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+
+#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_CLKOUTDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
-#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_CLKOUTDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
+#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
/*! @} */
/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */
/*! @{ */
-#define SYSCON_FROHFDIV_DIV_MASK (0xFFU)
-#define SYSCON_FROHFDIV_DIV_SHIFT (0U)
+
+#define SYSCON_FROHFDIV_DIV_MASK (0xFFU)
+#define SYSCON_FROHFDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
-#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U)
-#define SYSCON_FROHFDIV_RESET_SHIFT (29U)
+#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)
+
+#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U)
+#define SYSCON_FROHFDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_FROHFDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
-#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U)
-#define SYSCON_FROHFDIV_HALT_SHIFT (30U)
+#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)
+
+#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U)
+#define SYSCON_FROHFDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_FROHFDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
-#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)
+
+#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_FROHFDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)
+#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)
/*! @} */
/*! @name WDTCLKDIV - WDT clock divider */
/*! @{ */
-#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU)
-#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU)
+#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_WDTCLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK)
-#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK)
+
+#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_WDTCLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK)
-#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK)
+
+#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_WDTCLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK)
-#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK)
+
+#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_WDTCLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK)
+#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name ADCCLKDIV - ADC clock divider */
/*! @{ */
-#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U)
-#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_ADCCLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
-#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+
+#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_ADCCLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
-#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+
+#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_ADCCLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
-#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_ADCCLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
+#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name USB0CLKDIV - USB0 Clock divider */
/*! @{ */
-#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_USB0CLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
-#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
+
+#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_USB0CLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
-#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
+
+#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_USB0CLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
-#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
+
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_USB0CLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
+#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name MCLKDIV - I2S MCLK clock divider */
/*! @{ */
-#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_MCLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
-#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_MCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+
+#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_MCLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
-#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_MCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+
+#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
-#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+
+#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_MCLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
+#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name SCTCLKDIV - SCT/PWM clock divider */
/*! @{ */
-#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_SCTCLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
-#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
+
+#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_SCTCLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
-#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
+
+#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_SCTCLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
-#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
+
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_SCTCLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
+#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name SDIOCLKDIV - SDIO clock divider */
/*! @{ */
-#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_SDIOCLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
-#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
+
+#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_SDIOCLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
-#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
+
+#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_SDIOCLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
-#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
+
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_SDIOCLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
+#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name PLL0CLKDIV - PLL0 clock divider */
/*! @{ */
-#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U)
+
+#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U)
/*! DIV - Clock divider value.
*/
-#define SYSCON_PLL0CLKDIV_DIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK)
-#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK)
+
+#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U)
/*! RESET - Resets the divider counter.
* 0b1..Divider is reset.
* 0b0..Divider is not reset.
*/
-#define SYSCON_PLL0CLKDIV_RESET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK)
-#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK)
+
+#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U)
/*! HALT - Halts the divider counter.
* 0b1..Divider clock is stoped.
* 0b0..Divider clock is running.
*/
-#define SYSCON_PLL0CLKDIV_HALT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK)
-#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK)
+
+#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U)
/*! REQFLAG - Divider status flag.
* 0b1..Clock frequency is not stable.
* 0b0..Divider clock is stable.
*/
-#define SYSCON_PLL0CLKDIV_REQFLAG(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK)
+#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK)
/*! @} */
/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */
/*! @{ */
+
#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU)
#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U)
/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL).
* 0b00000000000000000000000000000001..update all clock configuration.
* 0b00000000000000000000000000000000..all hardware clock configruration are freeze.
*/
-#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & \
- SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK)
+#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK)
/*! @} */
/*! @name FMCCR - FMC configuration register */
/*! @{ */
-#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U)
-#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U)
+
+#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U)
+#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U)
+/*! FETCHCFG - Instruction fetch configuration.
+ * 0b00..Instruction fetches from flash are not buffered.
+ * 0b01..One buffer is used for all instruction fetches.
+ * 0b10..All buffers may be used for instruction fetches.
+ */
+#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK)
+
+#define SYSCON_FMCCR_DATACFG_MASK (0xCU)
+#define SYSCON_FMCCR_DATACFG_SHIFT (2U)
+/*! DATACFG - Data read configuration.
+ * 0b00..Data accesses from flash are not buffered.
+ * 0b01..One buffer is used for all data accesses.
+ * 0b10..All buffers can be used for data accesses.
+ */
+#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK)
+
+#define SYSCON_FMCCR_ACCEL_MASK (0x10U)
+#define SYSCON_FMCCR_ACCEL_SHIFT (4U)
+/*! ACCEL - Acceleration enable.
+ * 0b0..Flash acceleration is disabled.
+ * 0b1..Flash acceleration is enabled.
+ */
+#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK)
+
+#define SYSCON_FMCCR_PREFEN_MASK (0x20U)
+#define SYSCON_FMCCR_PREFEN_SHIFT (5U)
+/*! PREFEN - Prefetch enable.
+ * 0b0..No instruction prefetch is performed.
+ * 0b1..Instruction prefetch is enabled.
+ */
+#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK)
+
+#define SYSCON_FMCCR_PREFOVR_MASK (0x40U)
+#define SYSCON_FMCCR_PREFOVR_SHIFT (6U)
+/*! PREFOVR - Prefetch override.
+ * 0b0..Any previously initiated prefetch will be completed.
+ * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current
+ * execution address will be prefetched if not already buffered.
+ */
+#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK)
+
+#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U)
+#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U)
/*! FLASHTIM - Flash memory access time.
* 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz).
* 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz).
@@ -23646,180 +23351,170 @@ typedef struct
* 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz).
* 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz).
* 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz).
+ * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz).
+ * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz).
+ * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz).
*/
-#define SYSCON_FMCCR_FLASHTIM(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK)
+#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK)
/*! @} */
/*! @name USB0NEEDCLKCTRL - USB0 need clock control */
/*! @{ */
+
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U)
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U)
/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:.
* 0b0..Under hardware control.
* 0b1..Forced high.
*/
-#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & \
- SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK)
+#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK)
+
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U)
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U)
/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
* 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.
* 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.
*/
-#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & \
- SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK)
+#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK)
+
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U)
#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U)
/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:.
* 0b0..Under hardware control.
* 0b1..Forced high.
*/
-#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & \
- SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK)
+#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK)
+
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U)
#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U)
/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
* 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.
* 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.
*/
-#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & \
- SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK)
+#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK)
/*! @} */
/*! @name USB0NEEDCLKSTAT - USB0 need clock status */
/*! @{ */
-#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U)
+
+#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U)
#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U)
/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:.
* 0b1..USB0 Device clock is high.
* 0b0..USB0 Device clock is low.
*/
-#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & \
- SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK)
+#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK)
+
#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U)
#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U)
/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:.
* 0b1..USB0 Host clock is high.
* 0b0..USB0 Host clock is low.
*/
-#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & \
- SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK)
+#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK)
/*! @} */
/*! @name FMCFLUSH - FMCflush control */
/*! @{ */
-#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U)
-#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U)
+
+#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U)
+#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U)
/*! FLUSH - Flush control
* 0b1..Flush the FMC buffer contents.
* 0b0..No action is performed.
*/
-#define SYSCON_FMCFLUSH_FLUSH(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK)
+#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK)
/*! @} */
/*! @name MCLKIO - MCLK control */
/*! @{ */
-#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U)
-#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U)
+
+#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U)
+#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U)
/*! MCLKIO - MCLK control.
* 0b0..input mode.
* 0b1..output mode.
*/
-#define SYSCON_MCLKIO_MCLKIO(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK)
+#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK)
/*! @} */
/*! @name USB1NEEDCLKCTRL - USB1 need clock control */
/*! @{ */
+
#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U)
#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U)
/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control:
* 0b0..HOST_NEEDCLK is under hardware control.
* 0b1..HOST_NEEDCLK is forced high.
*/
-#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & \
- SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK)
+#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK)
+
#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U)
#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U)
/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt:
* 0b0..Falling edge of DEV_NEEDCLK triggers wake-up.
* 0b1..Rising edge of DEV_NEEDCLK triggers wake-up.
*/
-#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & \
- SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK)
+#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK)
+
#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U)
#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U)
/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control:
* 0b0..HOST_NEEDCLK is under hardware control.
* 0b1..HOST_NEEDCLK is forced high.
*/
-#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & \
- SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK)
+#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK)
+
#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U)
#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U)
/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt.
* 0b0..Falling edge of HOST_NEEDCLK triggers wake-up.
* 0b1..Rising edge of HOST_NEEDCLK triggers wake-up.
*/
-#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & \
- SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK)
+#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK)
+
#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic.
* 0b0..Forces USB1_PHY to wake-up.
* 0b1..Normal USB1_PHY behavior.
*/
-#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & \
- SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK)
+#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK)
/*! @} */
/*! @name USB1NEEDCLKSTAT - USB1 need clock status */
/*! @{ */
-#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U)
+
+#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U)
#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U)
/*! DEV_NEEDCLK - USB1 Device need_clock signal status:.
* 0b1..DEV_NEEDCLK is high.
* 0b0..DEV_NEEDCLK is low.
*/
-#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & \
- SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK)
+#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK)
+
#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U)
#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U)
/*! HOST_NEEDCLK - USB1 Host need_clock signal status:.
* 0b1..HOST_NEEDCLK is high.
* 0b0..HOST_NEEDCLK is low.
*/
-#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & \
- SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK)
+#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK)
/*! @} */
/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
/*! @{ */
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)
+
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)
/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
* 0b00..0 degree shift.
* 0b01..90 degree shift.
* 0b10..180 degree shift.
* 0b11..270 degree shift.
*/
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+
#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
@@ -23828,634 +23523,622 @@ typedef struct
* 0b10..180 degree shift.
* 0b11..270 degree shift.
*/
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & \
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
+
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)
/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
* 0b0..Bypassed.
* 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled.
*/
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
+
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)
/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
*/
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+
#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
* 0b1..Enable drive delay.
* 0b0..Disable drive delay.
*/
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & \
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+
#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
*/
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & \
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+
#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
* 0b1..Enables sample delay.
* 0b0..Disables sample delay.
*/
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & \
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
/*! @} */
/*! @name PLL1CTRL - PLL1 550m control */
/*! @{ */
-#define SYSCON_PLL1CTRL_SELR_MASK (0xFU)
-#define SYSCON_PLL1CTRL_SELR_SHIFT (0U)
+
+#define SYSCON_PLL1CTRL_SELR_MASK (0xFU)
+#define SYSCON_PLL1CTRL_SELR_SHIFT (0U)
/*! SELR - Bandwidth select R value.
*/
-#define SYSCON_PLL1CTRL_SELR(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK)
-#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U)
-#define SYSCON_PLL1CTRL_SELI_SHIFT (4U)
+#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK)
+
+#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U)
+#define SYSCON_PLL1CTRL_SELI_SHIFT (4U)
/*! SELI - Bandwidth select I value.
*/
-#define SYSCON_PLL1CTRL_SELI(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK)
-#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U)
-#define SYSCON_PLL1CTRL_SELP_SHIFT (10U)
+#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK)
+
+#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U)
+#define SYSCON_PLL1CTRL_SELP_SHIFT (10U)
/*! SELP - Bandwidth select P value.
*/
-#define SYSCON_PLL1CTRL_SELP(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK)
-#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U)
-#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U)
+#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK)
+
+#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U)
+#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U)
/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).
* 0b1..PLL input clock is sent directly to the PLL output.
* 0b0..use PLL.
*/
-#define SYSCON_PLL1CTRL_BYPASSPLL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK)
-#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U)
-#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U)
+#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK)
+
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U)
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U)
/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.
* 0b1..bypass of the divide-by-2 divider in the post-divider.
* 0b0..use the divide-by-2 divider in the post-divider.
*/
-#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
-#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U)
-#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U)
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
+
+#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U)
+#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U)
/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications.
*/
-#define SYSCON_PLL1CTRL_LIMUPOFF(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK)
-#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U)
-#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U)
+#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK)
+
+#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U)
+#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U)
/*! BWDIRECT - control of the bandwidth of the PLL.
* 0b1..modify the bandwidth of the PLL directly.
* 0b0..the bandwidth is changed synchronously with the feedback-divider.
*/
-#define SYSCON_PLL1CTRL_BWDIRECT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK)
-#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U)
-#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U)
+#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK)
+
+#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U)
+#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U)
/*! BYPASSPREDIV - bypass of the pre-divider.
* 0b1..bypass of the pre-divider.
* 0b0..use the pre-divider.
*/
-#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK)
-#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U)
-#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U)
+#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK)
+
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U)
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U)
/*! BYPASSPOSTDIV - bypass of the post-divider.
* 0b1..bypass of the post-divider.
* 0b0..use the post-divider.
*/
-#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK)
-#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U)
-#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U)
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK)
+
+#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U)
+#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U)
/*! CLKEN - enable the output clock.
* 0b1..Enable the output clock.
* 0b0..Disable the output clock.
*/
-#define SYSCON_PLL1CTRL_CLKEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK)
-#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U)
-#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U)
+#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK)
+
+#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U)
+#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U)
/*! FRMEN - 1: free running mode.
*/
-#define SYSCON_PLL1CTRL_FRMEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK)
-#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U)
-#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U)
-/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency
- * is stable.
- */
-#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK)
-#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U)
-#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U)
+#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK)
+
+#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U)
+#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U)
+/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.
+ */
+#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK)
+
+#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U)
+#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U)
/*! SKEWEN - Skew mode.
* 0b1..skewmode is enable.
* 0b0..skewmode is disable.
*/
-#define SYSCON_PLL1CTRL_SKEWEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK)
+#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK)
/*! @} */
/*! @name PLL1STAT - PLL1 550m status */
/*! @{ */
-#define SYSCON_PLL1STAT_LOCK_MASK (0x1U)
-#define SYSCON_PLL1STAT_LOCK_SHIFT (0U)
-/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20
- * MHz.
+
+#define SYSCON_PLL1STAT_LOCK_MASK (0x1U)
+#define SYSCON_PLL1STAT_LOCK_SHIFT (0U)
+/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
*/
-#define SYSCON_PLL1STAT_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK)
-#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U)
-#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U)
+#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK)
+
+#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U)
+#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U)
/*! PREDIVACK - pre-divider ratio change acknowledge.
*/
-#define SYSCON_PLL1STAT_PREDIVACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK)
-#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U)
-#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U)
+#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK)
+
+#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U)
+#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U)
/*! FEEDDIVACK - feedback divider ratio change acknowledge.
*/
-#define SYSCON_PLL1STAT_FEEDDIVACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK)
-#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U)
-#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U)
+#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK)
+
+#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U)
+#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U)
/*! POSTDIVACK - post-divider ratio change acknowledge.
*/
-#define SYSCON_PLL1STAT_POSTDIVACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK)
-#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U)
-#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U)
+#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK)
+
+#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U)
+#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U)
/*! FRMDET - free running detector output (active high).
*/
-#define SYSCON_PLL1STAT_FRMDET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK)
+#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK)
/*! @} */
/*! @name PLL1NDEC - PLL1 550m N divider */
/*! @{ */
-#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU)
-#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U)
+
+#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU)
+#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U)
/*! NDIV - pre-divider divider ratio (N-divider).
*/
-#define SYSCON_PLL1NDEC_NDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK)
-#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U)
-#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U)
+#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK)
+
+#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U)
+#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U)
/*! NREQ - pre-divider ratio change request.
*/
-#define SYSCON_PLL1NDEC_NREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK)
+#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK)
/*! @} */
/*! @name PLL1MDEC - PLL1 550m M divider */
/*! @{ */
-#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU)
-#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U)
+
+#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU)
+#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U)
/*! MDIV - feedback divider divider ratio (M-divider).
*/
-#define SYSCON_PLL1MDEC_MDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK)
-#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U)
-#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U)
+#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK)
+
+#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U)
+#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U)
/*! MREQ - feedback ratio change request.
*/
-#define SYSCON_PLL1MDEC_MREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK)
+#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK)
/*! @} */
/*! @name PLL1PDEC - PLL1 550m P divider */
/*! @{ */
-#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU)
-#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U)
+
+#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU)
+#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U)
/*! PDIV - post-divider divider ratio (P-divider)
*/
-#define SYSCON_PLL1PDEC_PDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK)
-#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U)
-#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U)
+#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK)
+
+#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U)
+#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U)
/*! PREQ - feedback ratio change request.
*/
-#define SYSCON_PLL1PDEC_PREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK)
+#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK)
/*! @} */
/*! @name PLL0CTRL - PLL0 550m control */
/*! @{ */
-#define SYSCON_PLL0CTRL_SELR_MASK (0xFU)
-#define SYSCON_PLL0CTRL_SELR_SHIFT (0U)
+
+#define SYSCON_PLL0CTRL_SELR_MASK (0xFU)
+#define SYSCON_PLL0CTRL_SELR_SHIFT (0U)
/*! SELR - Bandwidth select R value.
*/
-#define SYSCON_PLL0CTRL_SELR(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK)
-#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U)
-#define SYSCON_PLL0CTRL_SELI_SHIFT (4U)
+#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK)
+
+#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U)
+#define SYSCON_PLL0CTRL_SELI_SHIFT (4U)
/*! SELI - Bandwidth select I value.
*/
-#define SYSCON_PLL0CTRL_SELI(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK)
-#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U)
-#define SYSCON_PLL0CTRL_SELP_SHIFT (10U)
+#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK)
+
+#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U)
+#define SYSCON_PLL0CTRL_SELP_SHIFT (10U)
/*! SELP - Bandwidth select P value.
*/
-#define SYSCON_PLL0CTRL_SELP(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK)
-#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U)
-#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U)
+#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK)
+
+#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U)
+#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U)
/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).
* 0b1..Bypass PLL input clock is sent directly to the PLL output.
* 0b0..use PLL.
*/
-#define SYSCON_PLL0CTRL_BYPASSPLL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK)
-#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U)
-#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U)
+#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK)
+
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U)
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U)
/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.
* 0b1..bypass of the divide-by-2 divider in the post-divider.
* 0b0..use the divide-by-2 divider in the post-divider.
*/
-#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
-#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U)
-#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U)
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
+
+#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U)
+#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U)
/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications.
*/
-#define SYSCON_PLL0CTRL_LIMUPOFF(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK)
-#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U)
-#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U)
+#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK)
+
+#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U)
+#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U)
/*! BWDIRECT - Control of the bandwidth of the PLL.
* 0b1..modify the bandwidth of the PLL directly.
* 0b0..the bandwidth is changed synchronously with the feedback-divider.
*/
-#define SYSCON_PLL0CTRL_BWDIRECT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK)
-#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U)
-#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U)
+#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK)
+
+#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U)
+#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U)
/*! BYPASSPREDIV - bypass of the pre-divider.
* 0b1..bypass of the pre-divider.
* 0b0..use the pre-divider.
*/
-#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK)
-#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U)
-#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U)
+#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK)
+
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U)
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U)
/*! BYPASSPOSTDIV - bypass of the post-divider.
* 0b1..bypass of the post-divider.
* 0b0..use the post-divider.
*/
-#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK)
-#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U)
-#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U)
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK)
+
+#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U)
+#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U)
/*! CLKEN - enable the output clock.
* 0b1..enable the output clock.
* 0b0..disable the output clock.
*/
-#define SYSCON_PLL0CTRL_CLKEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK)
-#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U)
-#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U)
+#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK)
+
+#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U)
+#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U)
/*! FRMEN - free running mode.
* 0b1..free running mode is enable.
* 0b0..free running mode is disable.
*/
-#define SYSCON_PLL0CTRL_FRMEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK)
-#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U)
-#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U)
-/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency
- * is stable.
- */
-#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK)
-#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U)
-#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U)
+#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK)
+
+#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U)
+#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U)
+/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable.
+ */
+#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK)
+
+#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U)
+#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U)
/*! SKEWEN - skew mode.
* 0b1..skew mode is enable.
* 0b0..skew mode is disable.
*/
-#define SYSCON_PLL0CTRL_SKEWEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK)
+#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK)
/*! @} */
/*! @name PLL0STAT - PLL0 550m status */
/*! @{ */
-#define SYSCON_PLL0STAT_LOCK_MASK (0x1U)
-#define SYSCON_PLL0STAT_LOCK_SHIFT (0U)
-/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20
- * MHz.
+
+#define SYSCON_PLL0STAT_LOCK_MASK (0x1U)
+#define SYSCON_PLL0STAT_LOCK_SHIFT (0U)
+/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz.
*/
-#define SYSCON_PLL0STAT_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK)
-#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U)
-#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U)
+#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK)
+
+#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U)
+#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U)
/*! PREDIVACK - pre-divider ratio change acknowledge.
*/
-#define SYSCON_PLL0STAT_PREDIVACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK)
-#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U)
-#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U)
+#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK)
+
+#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U)
+#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U)
/*! FEEDDIVACK - feedback divider ratio change acknowledge.
*/
-#define SYSCON_PLL0STAT_FEEDDIVACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK)
-#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U)
-#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U)
+#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK)
+
+#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U)
+#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U)
/*! POSTDIVACK - post-divider ratio change acknowledge.
*/
-#define SYSCON_PLL0STAT_POSTDIVACK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK)
-#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U)
-#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U)
+#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK)
+
+#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U)
+#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U)
/*! FRMDET - free running detector output (active high).
*/
-#define SYSCON_PLL0STAT_FRMDET(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK)
+#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK)
/*! @} */
/*! @name PLL0NDEC - PLL0 550m N divider */
/*! @{ */
-#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU)
-#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U)
+
+#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU)
+#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U)
/*! NDIV - pre-divider divider ratio (N-divider).
*/
-#define SYSCON_PLL0NDEC_NDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK)
-#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U)
-#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U)
+#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK)
+
+#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U)
+#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U)
/*! NREQ - pre-divider ratio change request.
*/
-#define SYSCON_PLL0NDEC_NREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK)
+#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK)
/*! @} */
/*! @name PLL0PDEC - PLL0 550m P divider */
/*! @{ */
-#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU)
-#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U)
+
+#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU)
+#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U)
/*! PDIV - post-divider divider ratio (P-divider)
*/
-#define SYSCON_PLL0PDEC_PDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK)
-#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U)
-#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U)
+#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK)
+
+#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U)
+#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U)
/*! PREQ - feedback ratio change request.
*/
-#define SYSCON_PLL0PDEC_PREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK)
+#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK)
/*! @} */
/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */
/*! @{ */
-#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU)
-#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U)
+
+#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU)
+#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U)
/*! MD_LBS - input word of the wrapper bit 31 to 0.
*/
-#define SYSCON_PLL0SSCG0_MD_LBS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK)
+#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK)
/*! @} */
/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */
/*! @{ */
-#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U)
-#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U)
+
+#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U)
+#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U)
/*! MD_MBS - input word of the wrapper bit 32.
*/
-#define SYSCON_PLL0SSCG1_MD_MBS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK)
-#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U)
-#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U)
+#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK)
+
+#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U)
+#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U)
/*! MD_REQ - md change request.
*/
-#define SYSCON_PLL0SSCG1_MD_REQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK)
-#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU)
-#define SYSCON_PLL0SSCG1_MF_SHIFT (2U)
+#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK)
+
+#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU)
+#define SYSCON_PLL0SSCG1_MF_SHIFT (2U)
/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3.
*/
-#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)
-#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U)
-#define SYSCON_PLL0SSCG1_MR_SHIFT (5U)
+#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)
+
+#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U)
+#define SYSCON_PLL0SSCG1_MR_SHIFT (5U)
/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec)
* mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1.
*/
-#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK)
-#define SYSCON_PLL0SSCG1_MC_MASK (0x300U)
-#define SYSCON_PLL0SSCG1_MC_SHIFT (8U)
+#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK)
+
+#define SYSCON_PLL0SSCG1_MC_MASK (0x300U)
+#define SYSCON_PLL0SSCG1_MC_SHIFT (8U)
/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a
* triangular modulation at the output of the PLL, giving a flat frequency spectrum.
*/
-#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK)
-#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U)
-#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U)
+#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK)
+
+#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U)
+#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U)
/*! MDIV_EXT - to select an external mdiv value.
*/
-#define SYSCON_PLL0SSCG1_MDIV_EXT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)
-#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U)
-#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U)
+#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)
+
+#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U)
+#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U)
/*! MREQ - to select an external mreq value.
*/
-#define SYSCON_PLL0SSCG1_MREQ(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK)
-#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U)
-#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U)
+#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK)
+
+#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U)
+#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U)
/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way
* (white noise), in order to decrease the probability that the modulated waveform will occur
* with the same phase on a particular point on the screen.
*/
-#define SYSCON_PLL0SSCG1_DITHER(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK)
-#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U)
-#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U)
-/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq
- * = mreq_ext.
+#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK)
+
+#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U)
+#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U)
+/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext.
*/
-#define SYSCON_PLL0SSCG1_SEL_EXT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
+#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
/*! @} */
/*! @name CPUCTRL - CPU Control for multiple processors */
/*! @{ */
-#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U)
-#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U)
+
+#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U)
+#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U)
/*! CPU1CLKEN - CPU1 clock enable.
* 0b1..The CPU1 clock is enabled.
* 0b0..The CPU1 clock is not enabled.
*/
-#define SYSCON_CPUCTRL_CPU1CLKEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK)
-#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U)
-#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U)
+#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK)
+
+#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U)
+#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U)
/*! CPU1RSTEN - CPU1 reset.
* 0b1..The CPU1 is being reset.
* 0b0..The CPU1 is not being reset.
*/
-#define SYSCON_CPUCTRL_CPU1RSTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK)
+#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK)
/*! @} */
/*! @name CPBOOT - Coprocessor Boot Address */
/*! @{ */
-#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU)
-#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U)
+
+#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU)
+#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U)
/*! CPBOOT - Coprocessor Boot Address for CPU1.
*/
-#define SYSCON_CPBOOT_CPBOOT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK)
+#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK)
/*! @} */
/*! @name CPSTAT - CPU Status */
/*! @{ */
-#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U)
-#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U)
+
+#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U)
+#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U)
/*! CPU0SLEEPING - The CPU0 sleeping state.
* 0b1..the CPU is sleeping.
* 0b0..the CPU is not sleeping.
*/
-#define SYSCON_CPSTAT_CPU0SLEEPING(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK)
-#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U)
-#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U)
+#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK)
+
+#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U)
+#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U)
/*! CPU1SLEEPING - The CPU1 sleeping state.
* 0b1..the CPU is sleeping.
* 0b0..the CPU is not sleeping.
*/
-#define SYSCON_CPSTAT_CPU1SLEEPING(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK)
-#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U)
-#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U)
+#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK)
+
+#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U)
+#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U)
/*! CPU0LOCKUP - The CPU0 lockup state.
* 0b1..the CPU is in lockup.
* 0b0..the CPU is not in lockup.
*/
-#define SYSCON_CPSTAT_CPU0LOCKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK)
-#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U)
-#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U)
+#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK)
+
+#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U)
+#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U)
/*! CPU1LOCKUP - The CPU1 lockup state.
* 0b1..the CPU is in lockup.
* 0b0..the CPU is not in lockup.
*/
-#define SYSCON_CPSTAT_CPU1LOCKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK)
+#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK)
/*! @} */
/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */
/*! @{ */
+
#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U)
#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U)
/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & \
- SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK)
+#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK)
+
#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U)
#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U)
/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & \
- SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK)
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK)
+
#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U)
#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U)
/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & \
- SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK)
-#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U)
+#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK)
+
+#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U)
#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U)
/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & \
- SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK)
-#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U)
-#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U)
+#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK)
+
+#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U)
+#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U)
/*! CLKIN_ENA - Enable clock_in clock for clock module.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK)
-#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U)
-#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U)
+#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK)
+
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U)
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U)
/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK)
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK)
+
#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U)
#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U)
/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & \
- SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK)
-#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U)
-#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U)
+#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK)
+
+#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U)
+#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U)
/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK)
+#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK)
+
#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U)
#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U)
/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching.
* 0b1..The clock is enabled.
* 0b0..The clock is not enabled.
*/
-#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & \
- SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK)
+#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK)
/*! @} */
/*! @name COMP_INT_CTRL - Comparator Interrupt control */
/*! @{ */
-#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U)
-#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U)
+
+#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U)
+#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U)
/*! INT_ENABLE - Analog Comparator interrupt enable control:.
* 0b1..interrupt enable.
* 0b0..interrupt disable.
*/
-#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK)
-#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U)
-#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U)
+#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK)
+
+#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U)
+#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U)
/*! INT_CLEAR - Analog Comparator interrupt clear.
* 0b0..No effect.
* 0b1..Clear the interrupt. Self-cleared bit.
*/
-#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK)
-#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU)
-#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U)
+#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK)
+
+#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU)
+#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U)
/*! INT_CTRL - Comparator interrupt type selector:.
* 0b000..The analog comparator interrupt edge sensitive is disabled.
* 0b010..analog comparator interrupt is rising edge sensitive.
@@ -24466,430 +24149,398 @@ typedef struct
* 0b101..Analog Comparator interrupt is low level sensitive.
* 0b111..The analog comparator interrupt level sensitive is disabled.
*/
-#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK)
-#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U)
-#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U)
+#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK)
+
+#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U)
+#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U)
/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection.
* 0b0..Select Analog Comparator filtered output as input for interrupt detection.
* 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when
* Analog comparator is used as wake up source in Power down mode.
*/
-#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK)
+#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK)
/*! @} */
/*! @name COMP_INT_STATUS - Comparator Interrupt status */
/*! @{ */
-#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U)
-#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U)
+
+#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U)
+#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U)
/*! STATUS - Interrupt status BEFORE Interrupt Enable.
* 0b0..no interrupt pending.
* 0b1..interrupt pending.
*/
-#define SYSCON_COMP_INT_STATUS_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK)
-#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U)
-#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U)
+#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK)
+
+#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U)
+#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U)
/*! INT_STATUS - Interrupt status AFTER Interrupt Enable.
* 0b0..no interrupt pending.
* 0b1..interrupt pending.
*/
-#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK)
-#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U)
-#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U)
+#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK)
+
+#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U)
+#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U)
/*! VAL - comparator analog output.
* 0b1..P+ is greater than P-.
* 0b0..P+ is smaller than P-.
*/
-#define SYSCON_COMP_INT_STATUS_VAL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK)
+#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK)
/*! @} */
/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */
/*! @{ */
-#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U)
-#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U)
+
+#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U)
/*! ROM - Control automatic clock gating of ROM controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U)
/*! RAMX_CTRL - Control automatic clock gating of RAMX controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U)
/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U)
/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U)
/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U)
/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U)
#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U)
/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U)
/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U)
#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U)
/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK)
-#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U)
-#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK)
+
+#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U)
/*! CRCGEN - Control automatic clock gating of CRCGEN controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK)
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U)
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK)
+
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U)
/*! SDMA0 - Control automatic clock gating of DMA0 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK)
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U)
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK)
+
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U)
/*! SDMA1 - Control automatic clock gating of DMA1 controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK)
-#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U)
-#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK)
+
+#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U)
/*! USB0 - Control automatic clock gating of USB controller.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK)
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U)
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK)
+
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U)
/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank.
* 0b1..Automatic clock gating is overridden (Clock gating is disabled).
* 0b0..Automatic clock gating is not overridden.
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK)
+
#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U)
#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U)
/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect.
* 0b1100000011011110..Bit Fields 0 - 15 of this register are updated
* 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated
*/
-#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & \
- SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK)
+#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK)
/*! @} */
/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */
/*! @{ */
-#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U)
-#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U)
+
+#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U)
+#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U)
/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module.
* 0b1..bypass of the first stage of synchonization inside GPIO_INT module.
* 0b0..use the first stage of synchonization inside GPIO_INT module.
*/
-#define SYSCON_GPIOPSYNC_PSYNC(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK)
+#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK)
/*! @} */
/*! @name DEBUG_LOCK_EN - Control write access to security registers. */
/*! @{ */
-#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU)
-#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U)
+
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU)
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U)
/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0,
* CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers.
* 0b1010..1010: Enable write access to all 6 registers.
* 0b0000..Any other value than b1010: disable write access to all 6 registers.
*/
-#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)
/*! @} */
/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */
/*! @{ */
-#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U)
-#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U)
+
+#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U)
+#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U)
/*! CPU0_DBGEN - CPU0 Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)
-#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU)
-#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U)
+#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU)
+#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U)
/*! CPU0_NIDEN - CPU0 Non Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)
-#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U)
-#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U)
+#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U)
+#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U)
/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK)
-#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U)
+#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U)
#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U)
/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK)
-#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U)
-#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U)
+#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U)
+#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U)
/*! CPU1_DBGEN - CPU1 Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK)
-#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U)
-#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U)
+#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK)
+
+#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U)
+#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U)
/*! CPU1_NIDEN - CPU1 Non Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK)
+#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK)
/*! @} */
-/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register.
- */
+/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */
/*! @{ */
+
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U)
/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK)
+
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U)
/*! CPU0_NIDEN - CPU0 Non Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK)
+
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U)
/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK)
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK)
+
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U)
#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U)
/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK)
+#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK)
+
#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U)
#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U)
/*! CPU1_DBGEN - CPU1 Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK)
+#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK)
+
#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U)
#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U)
/*! CPU1_NIDEN - CPU1 Non Invasive debug control:.
* 0b10..10: Invasive debug is enabled.
* 0b01..Any other value than b10: invasive debug is disable.
*/
-#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & \
- SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK)
+#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK)
/*! @} */
/*! @name KEY_BLOCK - block quiddikey/PUF all index. */
/*! @{ */
-#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU)
-#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U)
+
+#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU)
+#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U)
/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index.
*/
-#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK)
+#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK)
/*! @} */
/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */
/*! @{ */
-#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU)
-#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U)
+
+#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU)
+#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U)
/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential
* Beacon and Authentication Beacon) to application code.
*/
-#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
+#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK)
/*! @} */
/*! @name CPUCFG - CPUs configuration register */
/*! @{ */
-#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U)
-#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U)
+
+#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U)
+#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U)
/*! CPU1ENABLE - Enable CPU1.
* 0b0..CPU1 is disable (Processor in reset).
* 0b1..CPU1 is enable.
*/
-#define SYSCON_CPUCFG_CPU1ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK)
+#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK)
/*! @} */
/*! @name DEVICE_ID0 - Device ID */
/*! @{ */
-#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U)
-#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U)
+
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U)
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U)
/*! ROM_REV_MINOR - ROM revision.
*/
-#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)
/*! @} */
/*! @name DIEID - Chip revision ID and Number */
/*! @{ */
-#define SYSCON_DIEID_REV_ID_MASK (0xFU)
-#define SYSCON_DIEID_REV_ID_SHIFT (0U)
+
+#define SYSCON_DIEID_REV_ID_MASK (0xFU)
+#define SYSCON_DIEID_REV_ID_SHIFT (0U)
/*! REV_ID - Chip Metal Revision ID.
*/
-#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK)
-#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U)
-#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U)
+#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK)
+
+#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U)
+#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U)
/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B.
*/
-#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)
+#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group SYSCON_Register_Masks */
+
/* SYSCON - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral SYSCON base address */
-#define SYSCON_BASE (0x50000000u)
-/** Peripheral SYSCON base address */
-#define SYSCON_BASE_NS (0x40000000u)
-/** Peripheral SYSCON base pointer */
-#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
-/** Peripheral SYSCON base pointer */
-#define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS)
-/** Array initializer of SYSCON peripheral base addresses */
-#define SYSCON_BASE_ADDRS \
- { \
- SYSCON_BASE \
- }
-/** Array initializer of SYSCON peripheral base pointers */
-#define SYSCON_BASE_PTRS \
- { \
- SYSCON \
- }
-/** Array initializer of SYSCON peripheral base addresses */
-#define SYSCON_BASE_ADDRS_NS \
- { \
- SYSCON_BASE_NS \
- }
-/** Array initializer of SYSCON peripheral base pointers */
-#define SYSCON_BASE_PTRS_NS \
- { \
- SYSCON_NS \
- }
+ /** Peripheral SYSCON base address */
+ #define SYSCON_BASE (0x50000000u)
+ /** Peripheral SYSCON base address */
+ #define SYSCON_BASE_NS (0x40000000u)
+ /** Peripheral SYSCON base pointer */
+ #define SYSCON ((SYSCON_Type *)SYSCON_BASE)
+ /** Peripheral SYSCON base pointer */
+ #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS)
+ /** Array initializer of SYSCON peripheral base addresses */
+ #define SYSCON_BASE_ADDRS { SYSCON_BASE }
+ /** Array initializer of SYSCON peripheral base pointers */
+ #define SYSCON_BASE_PTRS { SYSCON }
+ /** Array initializer of SYSCON peripheral base addresses */
+ #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS }
+ /** Array initializer of SYSCON peripheral base pointers */
+ #define SYSCON_BASE_PTRS_NS { SYSCON_NS }
#else
-/** Peripheral SYSCON base address */
-#define SYSCON_BASE (0x40000000u)
-/** Peripheral SYSCON base pointer */
-#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
-/** Array initializer of SYSCON peripheral base addresses */
-#define SYSCON_BASE_ADDRS \
- { \
- SYSCON_BASE \
- }
-/** Array initializer of SYSCON peripheral base pointers */
-#define SYSCON_BASE_PTRS \
- { \
- SYSCON \
- }
+ /** Peripheral SYSCON base address */
+ #define SYSCON_BASE (0x40000000u)
+ /** Peripheral SYSCON base pointer */
+ #define SYSCON ((SYSCON_Type *)SYSCON_BASE)
+ /** Array initializer of SYSCON peripheral base addresses */
+ #define SYSCON_BASE_ADDRS { SYSCON_BASE }
+ /** Array initializer of SYSCON peripheral base pointers */
+ #define SYSCON_BASE_PTRS { SYSCON }
#endif
/*!
* @}
*/ /* end of group SYSCON_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- SYSCTL Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -24900,18 +24551,14 @@ typedef struct
*/
/** SYSCTL - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */
- uint8_t RESERVED_0[60];
- __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going
- into Flexcomm 7, array offset: 0x40, array step: 0x4 */
- uint8_t RESERVED_1[32];
- __IO uint32_t
- SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data
- combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */
- uint8_t RESERVED_2[120];
- __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */
+typedef struct {
+ __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */
+ uint8_t RESERVED_0[60];
+ __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_1[32];
+ __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_2[120];
+ __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */
} SYSCTL_Type;
/* ----------------------------------------------------------------------------
@@ -24925,69 +24572,68 @@ typedef struct
/*! @name UPDATELCKOUT - update lock out control */
/*! @{ */
-#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U)
-#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U)
+
+#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U)
+#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U)
/*! UPDATELCKOUT - All Registers
* 0b0..Normal Mode. Can be written to.
* 0b1..Protected Mode. Cannot be written to.
*/
-#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK)
+#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK)
/*! @} */
-/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7
- */
+/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */
/*! @{ */
-#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U)
-#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U)
+
+#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U)
+#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U)
/*! SCKINSEL - Selects the source for SCK going into this Flexcomm.
* 0b00..Selects the dedicated FCn_SCK function for this Flexcomm.
* 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
* 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
* 0b11..Reserved.
*/
-#define SYSCTL_FCCTRLSEL_SCKINSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK)
-#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U)
-#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U)
+#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK)
+
+#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U)
+#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U)
/*! WSINSEL - Selects the source for WS going into this Flexcomm.
* 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm.
* 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
* 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
* 0b11..Reserved.
*/
-#define SYSCTL_FCCTRLSEL_WSINSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK)
-#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U)
-#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U)
+#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK)
+
+#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U)
+#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U)
/*! DATAINSEL - Selects the source for DATA input to this Flexcomm.
* 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm.
* 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
* 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
* 0b11..Reserved.
*/
-#define SYSCTL_FCCTRLSEL_DATAINSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK)
-#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U)
-#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U)
+#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK)
+
+#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U)
+#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U)
/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm.
* 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm.
* 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0).
* 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1).
* 0b11..Reserved.
*/
-#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK)
+#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK)
/*! @} */
/* The count of SYSCTL_FCCTRLSEL */
-#define SYSCTL_FCCTRLSEL_COUNT (8U)
+#define SYSCTL_FCCTRLSEL_COUNT (8U)
-/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data
- * combinations for shared signal set 1. */
+/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */
/*! @{ */
-#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U)
-#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U)
+
+#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U)
+#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U)
/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set.
* 0b000..SCK for this shared signal set comes from Flexcomm 0.
* 0b001..SCK for this shared signal set comes from Flexcomm 1.
@@ -24998,10 +24644,10 @@ typedef struct
* 0b110..SCK for this shared signal set comes from Flexcomm 6.
* 0b111..SCK for this shared signal set comes from Flexcomm 7.
*/
-#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK)
-#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U)
-#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U)
+#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U)
+#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U)
/*! SHAREDWSSEL - Selects the source for WS of this shared signal set.
* 0b000..WS for this shared signal set comes from Flexcomm 0.
* 0b001..WS for this shared signal set comes from Flexcomm 1.
@@ -25012,9 +24658,9 @@ typedef struct
* 0b110..WS for this shared signal set comes from Flexcomm 6.
* 0b111..WS for this shared signal set comes from Flexcomm 7.
*/
-#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK)
-#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U)
+#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U)
#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)
/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set.
* 0b000..DATA input for this shared signal set comes from Flexcomm 0.
@@ -25026,137 +24672,120 @@ typedef struct
* 0b110..DATA input for this shared signal set comes from Flexcomm 6.
* 0b111..DATA input for this shared signal set comes from Flexcomm 7.
*/
-#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & \
- SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U)
-#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U)
+#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U)
+#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U)
/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC0 does not contribute to this shared set.
* 0b1..Data output from FC0 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U)
-#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U)
+#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U)
+#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U)
/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC1 does not contribute to this shared set.
* 0b1..Data output from FC1 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U)
-#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U)
+#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U)
+#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U)
/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC2 does not contribute to this shared set.
* 0b1..Data output from FC2 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U)
-#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U)
+#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U)
+#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U)
/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC4 does not contribute to this shared set.
* 0b1..Data output from FC4 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U)
-#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U)
+#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U)
+#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U)
/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC5 does not contribute to this shared set.
* 0b1..Data output from FC5 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U)
-#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U)
+#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U)
+#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U)
/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC6 does not contribute to this shared set.
* 0b1..Data output from FC6 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK)
-#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U)
-#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U)
+#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK)
+
+#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U)
+#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U)
/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set.
* 0b0..Data output from FC7 does not contribute to this shared set.
* 0b1..Data output from FC7 does contribute to this shared set.
*/
-#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK)
+#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK)
/*! @} */
/* The count of SYSCTL_SHAREDCTRLSET */
-#define SYSCTL_SHAREDCTRLSET_COUNT (2U)
+#define SYSCTL_SHAREDCTRLSET_COUNT (2U)
/*! @name USB_HS_STATUS - Status register for USB HS */
/*! @{ */
-#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U)
-#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U)
+
+#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U)
+#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U)
/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply.
* 0b0..3v3 supply is good.
* 0b1..3v3 supply is too low.
*/
-#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) \
- (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK)
+#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group SYSCTL_Register_Masks */
+
/* SYSCTL - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral SYSCTL base address */
-#define SYSCTL_BASE (0x50023000u)
-/** Peripheral SYSCTL base address */
-#define SYSCTL_BASE_NS (0x40023000u)
-/** Peripheral SYSCTL base pointer */
-#define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE)
-/** Peripheral SYSCTL base pointer */
-#define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS)
-/** Array initializer of SYSCTL peripheral base addresses */
-#define SYSCTL_BASE_ADDRS \
- { \
- SYSCTL_BASE \
- }
-/** Array initializer of SYSCTL peripheral base pointers */
-#define SYSCTL_BASE_PTRS \
- { \
- SYSCTL \
- }
-/** Array initializer of SYSCTL peripheral base addresses */
-#define SYSCTL_BASE_ADDRS_NS \
- { \
- SYSCTL_BASE_NS \
- }
-/** Array initializer of SYSCTL peripheral base pointers */
-#define SYSCTL_BASE_PTRS_NS \
- { \
- SYSCTL_NS \
- }
+ /** Peripheral SYSCTL base address */
+ #define SYSCTL_BASE (0x50023000u)
+ /** Peripheral SYSCTL base address */
+ #define SYSCTL_BASE_NS (0x40023000u)
+ /** Peripheral SYSCTL base pointer */
+ #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE)
+ /** Peripheral SYSCTL base pointer */
+ #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS)
+ /** Array initializer of SYSCTL peripheral base addresses */
+ #define SYSCTL_BASE_ADDRS { SYSCTL_BASE }
+ /** Array initializer of SYSCTL peripheral base pointers */
+ #define SYSCTL_BASE_PTRS { SYSCTL }
+ /** Array initializer of SYSCTL peripheral base addresses */
+ #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS }
+ /** Array initializer of SYSCTL peripheral base pointers */
+ #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS }
#else
-/** Peripheral SYSCTL base address */
-#define SYSCTL_BASE (0x40023000u)
-/** Peripheral SYSCTL base pointer */
-#define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE)
-/** Array initializer of SYSCTL peripheral base addresses */
-#define SYSCTL_BASE_ADDRS \
- { \
- SYSCTL_BASE \
- }
-/** Array initializer of SYSCTL peripheral base pointers */
-#define SYSCTL_BASE_PTRS \
- { \
- SYSCTL \
- }
+ /** Peripheral SYSCTL base address */
+ #define SYSCTL_BASE (0x40023000u)
+ /** Peripheral SYSCTL base pointer */
+ #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE)
+ /** Array initializer of SYSCTL peripheral base addresses */
+ #define SYSCTL_BASE_ADDRS { SYSCTL_BASE }
+ /** Array initializer of SYSCTL peripheral base pointers */
+ #define SYSCTL_BASE_PTRS { SYSCTL }
#endif
/*!
* @}
*/ /* end of group SYSCTL_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- USART Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -25167,43 +24796,33 @@ typedef struct
*/
/** USART - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not
- changed during operation., offset: 0x0 */
- __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during
- operation., offset: 0x4 */
- __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some
- bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
- __IO uint32_t
- INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt
- enable bits for each potential USART interrupt. A complete value may be read from this register.
- Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
- __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET
- register. Writing a 1 to any implemented bit position causes the corresponding bit to be
- cleared., offset: 0x10 */
- uint8_t RESERVED_0[12];
- __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
- __I uint32_t
- INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
- __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
- __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
- uint8_t RESERVED_1[3536];
- __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
- __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
- __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
- uint8_t RESERVED_2[4];
- __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
- __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
- __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
- uint8_t RESERVED_3[4];
- __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
- uint8_t RESERVED_4[12];
- __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
- uint8_t RESERVED_5[12];
- __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
- uint8_t RESERVED_6[440];
- __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+typedef struct {
+ __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+ __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+ __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+ __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+ __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+ __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
+ uint8_t RESERVED_1[3536];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_3[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ uint8_t RESERVED_4[12];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ uint8_t RESERVED_6[440];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
} USART_Type;
/* ----------------------------------------------------------------------------
@@ -25215,11 +24834,11 @@ typedef struct
* @{
*/
-/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during
- * operation. */
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
/*! @{ */
-#define USART_CFG_ENABLE_MASK (0x1U)
-#define USART_CFG_ENABLE_SHIFT (0U)
+
+#define USART_CFG_ENABLE_MASK (0x1U)
+#define USART_CFG_ENABLE_SHIFT (0U)
/*! ENABLE - USART Enable.
* 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0,
* all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control
@@ -25227,18 +24846,20 @@ typedef struct
* transmitter has been reset and is therefore available.
* 0b1..Enabled. The USART is enabled for operation.
*/
-#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
-#define USART_CFG_DATALEN_MASK (0xCU)
-#define USART_CFG_DATALEN_SHIFT (2U)
+#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+
+#define USART_CFG_DATALEN_MASK (0xCU)
+#define USART_CFG_DATALEN_SHIFT (2U)
/*! DATALEN - Selects the data size for the USART.
* 0b00..7 bit Data length.
* 0b01..8 bit Data length.
- * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the
- * CTL register. 0b11..Reserved.
+ * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.
+ * 0b11..Reserved.
*/
-#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
-#define USART_CFG_PARITYSEL_MASK (0x30U)
-#define USART_CFG_PARITYSEL_SHIFT (4U)
+#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+
+#define USART_CFG_PARITYSEL_MASK (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT (4U)
/*! PARITYSEL - Selects what type of parity is used by the USART.
* 0b00..No parity.
* 0b01..Reserved.
@@ -25247,61 +24868,67 @@ typedef struct
* 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,
* and the number of 1s in a received character is expected to be odd.
*/
-#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
-#define USART_CFG_STOPLEN_MASK (0x40U)
-#define USART_CFG_STOPLEN_SHIFT (6U)
+#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+
+#define USART_CFG_STOPLEN_MASK (0x40U)
+#define USART_CFG_STOPLEN_SHIFT (6U)
/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.
* 0b0..1 stop bit.
* 0b1..2 stop bits. This setting should only be used for asynchronous communication.
*/
-#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
-#define USART_CFG_MODE32K_MASK (0x80U)
-#define USART_CFG_MODE32K_SHIFT (7U)
+#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+
+#define USART_CFG_MODE32K_MASK (0x80U)
+#define USART_CFG_MODE32K_SHIFT (7U)
/*! MODE32K - Selects standard or 32 kHz clocking mode.
* 0b0..Disabled. USART uses standard clocking.
- * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special
- * bit clocking scheme.
+ * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
*/
-#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
-#define USART_CFG_LINMODE_MASK (0x100U)
-#define USART_CFG_LINMODE_SHIFT (8U)
+#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+
+#define USART_CFG_LINMODE_MASK (0x100U)
+#define USART_CFG_LINMODE_SHIFT (8U)
/*! LINMODE - LIN break mode enable.
* 0b0..Disabled. Break detect and generate is configured for normal operation.
* 0b1..Enabled. Break detect and generate is configured for LIN bus operation.
*/
-#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
-#define USART_CFG_CTSEN_MASK (0x200U)
-#define USART_CFG_CTSEN_SHIFT (9U)
+#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+
+#define USART_CFG_CTSEN_MASK (0x200U)
+#define USART_CFG_CTSEN_SHIFT (9U)
/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input
* pin, or from the USART's own RTS if loopback mode is enabled.
* 0b0..No flow control. The transmitter does not receive any automatic flow control signal.
- * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control
- * purposes.
+ * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
*/
-#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
-#define USART_CFG_SYNCEN_MASK (0x800U)
-#define USART_CFG_SYNCEN_SHIFT (11U)
+#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+
+#define USART_CFG_SYNCEN_MASK (0x800U)
+#define USART_CFG_SYNCEN_SHIFT (11U)
/*! SYNCEN - Selects synchronous or asynchronous operation.
* 0b0..Asynchronous mode.
* 0b1..Synchronous mode.
*/
-#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
-#define USART_CFG_CLKPOL_MASK (0x1000U)
-#define USART_CFG_CLKPOL_SHIFT (12U)
+#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+
+#define USART_CFG_CLKPOL_MASK (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT (12U)
/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.
* 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.
* 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.
*/
-#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
-#define USART_CFG_SYNCMST_MASK (0x4000U)
-#define USART_CFG_SYNCMST_SHIFT (14U)
+#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+
+#define USART_CFG_SYNCMST_MASK (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT (14U)
/*! SYNCMST - Synchronous mode Master select.
* 0b0..Slave. When synchronous mode is enabled, the USART is a slave.
* 0b1..Master. When synchronous mode is enabled, the USART is a master.
*/
-#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
-#define USART_CFG_LOOP_MASK (0x8000U)
-#define USART_CFG_LOOP_SHIFT (15U)
+#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+
+#define USART_CFG_LOOP_MASK (0x8000U)
+#define USART_CFG_LOOP_SHIFT (15U)
/*! LOOP - Selects data loopback mode.
* 0b0..Normal operation.
* 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial
@@ -25309,63 +24936,70 @@ typedef struct
* and Un_RTS activity will also appear on external pins if these functions are configured to appear on device
* pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
*/
-#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
-#define USART_CFG_OETA_MASK (0x40000U)
-#define USART_CFG_OETA_SHIFT (18U)
+#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+
+#define USART_CFG_OETA_MASK (0x40000U)
+#define USART_CFG_OETA_SHIFT (18U)
/*! OETA - Output Enable Turnaround time enable for RS-485 operation.
- * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a
- * transmission. 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time
- * after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before
- * it is deasserted.
- */
-#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
-#define USART_CFG_AUTOADDR_MASK (0x80000U)
-#define USART_CFG_AUTOADDR_SHIFT (19U)
+ * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.
+ * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the
+ * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins
+ * before it is deasserted.
+ */
+#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+
+#define USART_CFG_AUTOADDR_MASK (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT (19U)
/*! AUTOADDR - Automatic Address matching enable.
* 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the
* possibility of versatile addressing (e.g. respond to more than one address).
* 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in
* the ADDR register as the address to match.
*/
-#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
-#define USART_CFG_OESEL_MASK (0x100000U)
-#define USART_CFG_OESEL_SHIFT (20U)
+#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+
+#define USART_CFG_OESEL_MASK (0x100000U)
+#define USART_CFG_OESEL_SHIFT (20U)
/*! OESEL - Output Enable Select.
* 0b0..Standard. The RTS signal is used as the standard flow control function.
* 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.
*/
-#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
-#define USART_CFG_OEPOL_MASK (0x200000U)
-#define USART_CFG_OEPOL_SHIFT (21U)
+#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+
+#define USART_CFG_OEPOL_MASK (0x200000U)
+#define USART_CFG_OEPOL_SHIFT (21U)
/*! OEPOL - Output Enable Polarity.
* 0b0..Low. If selected by OESEL, the output enable is active low.
* 0b1..High. If selected by OESEL, the output enable is active high.
*/
-#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
-#define USART_CFG_RXPOL_MASK (0x400000U)
-#define USART_CFG_RXPOL_SHIFT (22U)
+#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+
+#define USART_CFG_RXPOL_MASK (0x400000U)
+#define USART_CFG_RXPOL_SHIFT (22U)
/*! RXPOL - Receive data polarity.
* 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start
* bit is 0, data is not inverted, and the stop bit is 1.
* 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is
* 0, start bit is 1, data is inverted, and the stop bit is 0.
*/
-#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
-#define USART_CFG_TXPOL_MASK (0x800000U)
-#define USART_CFG_TXPOL_SHIFT (23U)
+#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+
+#define USART_CFG_TXPOL_MASK (0x800000U)
+#define USART_CFG_TXPOL_SHIFT (23U)
/*! TXPOL - Transmit data polarity.
* 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is
* 0, data is not inverted, and the stop bit is 1.
* 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value
* is 0, start bit is 1, data is inverted, and the stop bit is 0.
*/
-#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
/*! @} */
/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
/*! @{ */
-#define USART_CTL_TXBRKEN_MASK (0x2U)
-#define USART_CTL_TXBRKEN_SHIFT (1U)
+
+#define USART_CTL_TXBRKEN_MASK (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT (1U)
/*! TXBRKEN - Break Enable.
* 0b0..Normal operation.
* 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit
@@ -25373,9 +25007,10 @@ typedef struct
* transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled
* (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
*/
-#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
-#define USART_CTL_ADDRDET_MASK (0x4U)
-#define USART_CTL_ADDRDET_SHIFT (2U)
+#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+
+#define USART_CTL_ADDRDET_MASK (0x4U)
+#define USART_CTL_ADDRDET_SHIFT (2U)
/*! ADDRDET - Enable address detect mode.
* 0b0..Disabled. The USART presents all incoming data.
* 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data
@@ -25384,387 +25019,397 @@ typedef struct
* should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled
* normally.
*/
-#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
-#define USART_CTL_TXDIS_MASK (0x40U)
-#define USART_CTL_TXDIS_SHIFT (6U)
+#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+
+#define USART_CTL_TXDIS_MASK (0x40U)
+#define USART_CTL_TXDIS_SHIFT (6U)
/*! TXDIS - Transmit Disable.
* 0b0..Not disabled. USART transmitter is not disabled.
* 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
* feature can be used to facilitate software flow control.
*/
-#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
-#define USART_CTL_CC_MASK (0x100U)
-#define USART_CTL_CC_SHIFT (8U)
-/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous
- * mode. 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to
+#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+
+#define USART_CTL_CC_MASK (0x100U)
+#define USART_CTL_CC_SHIFT (8U)
+/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to
* complete a character that is being received.
* 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on
* Un_RxD independently from transmission on Un_TXD).
*/
-#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
-#define USART_CTL_CLRCCONRX_MASK (0x200U)
-#define USART_CTL_CLRCCONRX_SHIFT (9U)
+#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+
+#define USART_CTL_CLRCCONRX_MASK (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT (9U)
/*! CLRCCONRX - Clear Continuous Clock.
* 0b0..No effect. No effect on the CC bit.
- * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is
- * cleared at the same time.
+ * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
*/
-#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
-#define USART_CTL_AUTOBAUD_MASK (0x10000U)
-#define USART_CTL_AUTOBAUD_SHIFT (16U)
+#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+
+#define USART_CTL_AUTOBAUD_MASK (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT (16U)
/*! AUTOBAUD - Autobaud enable.
* 0b0..Disabled. USART is in normal operating mode.
* 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The
* first start bit of RX is measured and used the update the BRG register to match the received data rate.
* AUTOBAUD is cleared once this process is complete, or if there is an AERR.
*/
-#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
/*! @} */
-/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the
- * register. Some bits can be cleared by writing a 1 to them. */
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
/*! @{ */
-#define USART_STAT_RXIDLE_MASK (0x2U)
-#define USART_STAT_RXIDLE_SHIFT (1U)
+
+#define USART_STAT_RXIDLE_MASK (0x2U)
+#define USART_STAT_RXIDLE_SHIFT (1U)
/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of
* receiving data. When 1, indicates that the receiver is not currently in the process of receiving
* data.
*/
-#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
-#define USART_STAT_TXIDLE_MASK (0x8U)
-#define USART_STAT_TXIDLE_SHIFT (3U)
+#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+
+#define USART_STAT_TXIDLE_MASK (0x8U)
+#define USART_STAT_TXIDLE_SHIFT (3U)
/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of
* sending data.When 1, indicate that the transmitter is not currently in the process of sending
* data.
*/
-#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
-#define USART_STAT_CTS_MASK (0x10U)
-#define USART_STAT_CTS_SHIFT (4U)
+#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+
+#define USART_STAT_CTS_MASK (0x10U)
+#define USART_STAT_CTS_SHIFT (4U)
/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the
* CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode
* is enabled.
*/
-#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
-#define USART_STAT_DELTACTS_MASK (0x20U)
-#define USART_STAT_DELTACTS_SHIFT (5U)
-/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by
- * software.
+#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+
+#define USART_STAT_DELTACTS_MASK (0x20U)
+#define USART_STAT_DELTACTS_SHIFT (5U)
+/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software.
*/
-#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
-#define USART_STAT_TXDISSTAT_MASK (0x40U)
-#define USART_STAT_TXDISSTAT_SHIFT (6U)
+#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+
+#define USART_STAT_TXDISSTAT_MASK (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT (6U)
/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART
* transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1).
*/
-#define USART_STAT_TXDISSTAT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
-#define USART_STAT_RXBRK_MASK (0x400U)
-#define USART_STAT_RXBRK_SHIFT (10U)
+#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+
+#define USART_STAT_RXBRK_MASK (0x400U)
+#define USART_STAT_RXBRK_SHIFT (10U)
/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection
* logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also
* be set when this condition occurs because the stop bit(s) for the character would be missing.
* RXBRK is cleared when the Un_RXD pin goes high.
*/
-#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
-#define USART_STAT_DELTARXBRK_MASK (0x800U)
-#define USART_STAT_DELTARXBRK_SHIFT (11U)
+#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+
+#define USART_STAT_DELTARXBRK_MASK (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT (11U)
/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software.
*/
-#define USART_STAT_DELTARXBRK(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
-#define USART_STAT_START_MASK (0x1000U)
-#define USART_STAT_START_SHIFT (12U)
+#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+
+#define USART_STAT_START_MASK (0x1000U)
+#define USART_STAT_START_SHIFT (12U)
/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily
* to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected.
* Cleared by software.
*/
-#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
-#define USART_STAT_FRAMERRINT_MASK (0x2000U)
-#define USART_STAT_FRAMERRINT_SHIFT (13U)
+#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+
+#define USART_STAT_FRAMERRINT_MASK (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT (13U)
/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a
* missing stop bit at the expected location. This could be an indication of a baud rate or
* configuration mismatch with the transmitting source.
*/
-#define USART_STAT_FRAMERRINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
-#define USART_STAT_PARITYERRINT_MASK (0x4000U)
-#define USART_STAT_PARITYERRINT_SHIFT (14U)
-/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received
- * character.
- */
-#define USART_STAT_PARITYERRINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
-#define USART_STAT_RXNOISEINT_MASK (0x8000U)
-#define USART_STAT_RXNOISEINT_SHIFT (15U)
+#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+
+#define USART_STAT_PARITYERRINT_MASK (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT (14U)
+/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
+ */
+#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+
+#define USART_STAT_RXNOISEINT_MASK (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT (15U)
/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to
* determine the value of each received data bit, except in synchronous mode. This acts as a
* noise filter if one sample disagrees. This flag is set when a received data bit contains one
* disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or
* loss of synchronization during data reception.
*/
-#define USART_STAT_RXNOISEINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
-#define USART_STAT_ABERR_MASK (0x10000U)
-#define USART_STAT_ABERR_SHIFT (16U)
+#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+
+#define USART_STAT_ABERR_MASK (0x10000U)
+#define USART_STAT_ABERR_SHIFT (16U)
/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the
* end of the start bit that is being measured, essentially an auto baud time-out.
*/
-#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
/*! @} */
-/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt
- * enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any
- * implemented bit position causes that bit to be set. */
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
/*! @{ */
-#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
-#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
+
+#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
*/
-#define USART_INTENSET_TXIDLEEN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
-#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
-#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
+#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+
+#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input.
*/
-#define USART_INTENSET_DELTACTSEN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
-#define USART_INTENSET_TXDISEN_MASK (0x40U)
-#define USART_INTENSET_TXDISEN_SHIFT (6U)
+#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+
+#define USART_INTENSET_TXDISEN_MASK (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT (6U)
/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by
* the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
*/
-#define USART_INTENSET_TXDISEN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
-#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
-#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
+#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+
+#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection
* of a received break condition (break condition asserted or deasserted).
*/
-#define USART_INTENSET_DELTARXBRKEN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
-#define USART_INTENSET_STARTEN_MASK (0x1000U)
-#define USART_INTENSET_STARTEN_SHIFT (12U)
+#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+
+#define USART_INTENSET_STARTEN_MASK (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT (12U)
/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected.
*/
-#define USART_INTENSET_STARTEN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
-#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
-#define USART_INTENSET_FRAMERREN_SHIFT (13U)
+#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+
+#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT (13U)
/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected.
*/
-#define USART_INTENSET_FRAMERREN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
-#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
-#define USART_INTENSET_PARITYERREN_SHIFT (14U)
+#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+
+#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT (14U)
/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected.
*/
-#define USART_INTENSET_PARITYERREN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
-#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
-#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
+#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+
+#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354.
*/
-#define USART_INTENSET_RXNOISEEN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
-#define USART_INTENSET_ABERREN_MASK (0x10000U)
-#define USART_INTENSET_ABERREN_SHIFT (16U)
+#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+
+#define USART_INTENSET_ABERREN_MASK (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT (16U)
/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs.
*/
-#define USART_INTENSET_ABERREN(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
/*! @} */
-/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register.
- * Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
/*! @{ */
-#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
-#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
+
+#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_TXIDLECLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
-#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
-#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
+#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+
+#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_DELTACTSCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
-#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
-#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
+#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+
+#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_TXDISCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
-#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
-#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
+#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+
+#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_DELTARXBRKCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
-#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
-#define USART_INTENCLR_STARTCLR_SHIFT (12U)
+#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+
+#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT (12U)
/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_STARTCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
-#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
-#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
+#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+
+#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_FRAMERRCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
-#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
-#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
+#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+
+#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_PARITYERRCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
-#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
-#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
+#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+
+#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_RXNOISECLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
-#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
-#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
+#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+
+#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register.
*/
-#define USART_INTENCLR_ABERRCLR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
/*! @} */
/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
/*! @{ */
-#define USART_BRG_BRGVAL_MASK (0xFFFFU)
-#define USART_BRG_BRGVAL_SHIFT (0U)
+
+#define USART_BRG_BRGVAL_MASK (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT (0U)
/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on
* the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is
* divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART
* function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function.
*/
-#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
/*! @} */
/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
/*! @{ */
-#define USART_INTSTAT_TXIDLE_MASK (0x8U)
-#define USART_INTSTAT_TXIDLE_SHIFT (3U)
+
+#define USART_INTSTAT_TXIDLE_MASK (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT (3U)
/*! TXIDLE - Transmitter Idle status.
*/
-#define USART_INTSTAT_TXIDLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
-#define USART_INTSTAT_DELTACTS_MASK (0x20U)
-#define USART_INTSTAT_DELTACTS_SHIFT (5U)
+#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+
+#define USART_INTSTAT_DELTACTS_MASK (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT (5U)
/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected.
*/
-#define USART_INTSTAT_DELTACTS(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
-#define USART_INTSTAT_TXDISINT_MASK (0x40U)
-#define USART_INTSTAT_TXDISINT_SHIFT (6U)
+#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+
+#define USART_INTSTAT_TXDISINT_MASK (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT (6U)
/*! TXDISINT - Transmitter Disabled Interrupt flag.
*/
-#define USART_INTSTAT_TXDISINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
-#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
-#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
+#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+
+#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.
*/
-#define USART_INTSTAT_DELTARXBRK(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
-#define USART_INTSTAT_START_MASK (0x1000U)
-#define USART_INTSTAT_START_SHIFT (12U)
+#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+
+#define USART_INTSTAT_START_MASK (0x1000U)
+#define USART_INTSTAT_START_SHIFT (12U)
/*! START - This bit is set when a start is detected on the receiver input.
*/
-#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
-#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
-#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
+#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+
+#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
/*! FRAMERRINT - Framing Error interrupt flag.
*/
-#define USART_INTSTAT_FRAMERRINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
-#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
-#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
+#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+
+#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
/*! PARITYERRINT - Parity Error interrupt flag.
*/
-#define USART_INTSTAT_PARITYERRINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
-#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
-#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
+#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+
+#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
/*! RXNOISEINT - Received Noise interrupt flag.
*/
-#define USART_INTSTAT_RXNOISEINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
-#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
-#define USART_INTSTAT_ABERRINT_SHIFT (16U)
+#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+
+#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT (16U)
/*! ABERRINT - Auto baud Error Interrupt flag.
*/
-#define USART_INTSTAT_ABERRINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
/*! @} */
/*! @name OSR - Oversample selection register for asynchronous communication. */
/*! @{ */
-#define USART_OSR_OSRVAL_MASK (0xFU)
-#define USART_OSR_OSRVAL_SHIFT (0U)
+
+#define USART_OSR_OSRVAL_MASK (0xFU)
+#define USART_OSR_OSRVAL_SHIFT (0U)
/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to
* transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive
* each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit.
*/
-#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
/*! @} */
/*! @name ADDR - Address register for automatic address matching. */
/*! @{ */
-#define USART_ADDR_ADDRESS_MASK (0xFFU)
-#define USART_ADDR_ADDRESS_SHIFT (0U)
+
+#define USART_ADDR_ADDRESS_MASK (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT (0U)
/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is
* enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1).
*/
-#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
/*! @} */
/*! @name FIFOCFG - FIFO configuration and enable register. */
/*! @{ */
-#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
-#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
+
+#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
/*! ENABLETX - Enable the transmit FIFO.
* 0b0..The transmit FIFO is not enabled.
* 0b1..The transmit FIFO is enabled.
*/
-#define USART_FIFOCFG_ENABLETX(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
-#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
-#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
+#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+
+#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
/*! ENABLERX - Enable the receive FIFO.
* 0b0..The receive FIFO is not enabled.
* 0b1..The receive FIFO is enabled.
*/
-#define USART_FIFOCFG_ENABLERX(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
-#define USART_FIFOCFG_SIZE_MASK (0x30U)
-#define USART_FIFOCFG_SIZE_SHIFT (4U)
+#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+
+#define USART_FIFOCFG_SIZE_MASK (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT (4U)
/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16
* entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
*/
-#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
-#define USART_FIFOCFG_DMATX_MASK (0x1000U)
-#define USART_FIFOCFG_DMATX_SHIFT (12U)
+#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+
+#define USART_FIFOCFG_DMATX_MASK (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT (12U)
/*! DMATX - DMA configuration for transmit.
* 0b0..DMA is not used for the transmit function.
- * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if
- * DMA is enabled.
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
*/
-#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
-#define USART_FIFOCFG_DMARX_MASK (0x2000U)
-#define USART_FIFOCFG_DMARX_SHIFT (13U)
+#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+
+#define USART_FIFOCFG_DMARX_MASK (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT (13U)
/*! DMARX - DMA configuration for receive.
* 0b0..DMA is not used for the receive function.
- * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if
- * DMA is enabled.
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
*/
-#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
-#define USART_FIFOCFG_WAKETX_MASK (0x4000U)
-#define USART_FIFOCFG_WAKETX_SHIFT (14U)
+#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+
+#define USART_FIFOCFG_WAKETX_MASK (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT (14U)
/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power
* modes (up to power-down, as long as the peripheral function works in that power mode) without
* enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
@@ -25774,10 +25419,10 @@ typedef struct
* 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
* FIFOTRIG, even when the TXLVL interrupt is not enabled.
*/
-#define USART_FIFOCFG_WAKETX(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
-#define USART_FIFOCFG_WAKERX_MASK (0x8000U)
-#define USART_FIFOCFG_WAKERX_SHIFT (15U)
+#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+
+#define USART_FIFOCFG_WAKERX_MASK (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT (15U)
/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power
* modes (up to power-down, as long as the peripheral function works in that power mode) without
* enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The
@@ -25787,128 +25432,124 @@ typedef struct
* 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in
* FIFOTRIG, even when the RXLVL interrupt is not enabled.
*/
-#define USART_FIFOCFG_WAKERX(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
-#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
-#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
+#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+
+#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
*/
-#define USART_FIFOCFG_EMPTYTX(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
-#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
-#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
+#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+
+#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
*/
-#define USART_FIFOCFG_EMPTYRX(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
/*! @} */
/*! @name FIFOSTAT - FIFO status register. */
/*! @{ */
-#define USART_FIFOSTAT_TXERR_MASK (0x1U)
-#define USART_FIFOSTAT_TXERR_SHIFT (0U)
+
+#define USART_FIFOSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT (0U)
/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow
* caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is
* needed. Cleared by writing a 1 to this bit.
*/
-#define USART_FIFOSTAT_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
-#define USART_FIFOSTAT_RXERR_MASK (0x2U)
-#define USART_FIFOSTAT_RXERR_SHIFT (1U)
+#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+
+#define USART_FIFOSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT (1U)
/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA
* not emptying the FIFO fast enough. Cleared by writing a 1 to this bit.
*/
-#define USART_FIFOSTAT_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
-#define USART_FIFOSTAT_PERINT_MASK (0x8U)
-#define USART_FIFOSTAT_PERINT_SHIFT (3U)
+#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+
+#define USART_FIFOSTAT_PERINT_MASK (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT (3U)
/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted
* an interrupt. The details can be found by reading the peripheral's STAT register.
*/
-#define USART_FIFOSTAT_PERINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
-#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
-#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
-/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last
- * piece of data.
- */
-#define USART_FIFOSTAT_TXEMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
-#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
-#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+
+#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
+/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data.
+ */
+#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+
+#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be
* written. When 0, the transmit FIFO is full and another write would cause it to overflow.
*/
-#define USART_FIFOSTAT_TXNOTFULL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
-#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
-#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
-/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive
- * FIFO is empty.
- */
-#define USART_FIFOSTAT_RXNOTEMPTY(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
-#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
-#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
+#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty.
+ */
+#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+
+#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to
* prevent the peripheral from causing an overflow.
*/
-#define USART_FIFOSTAT_RXFULL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
-#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
-#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
+#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+
+#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY
* and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at
* the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be
* 0.
*/
-#define USART_FIFOSTAT_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
-#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
-#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
+#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+
+#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and
* RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the
* point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be
* 1.
*/
-#define USART_FIFOSTAT_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
/*! @} */
/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
/*! @{ */
-#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
-#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
+
+#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled
* in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.
* 0b0..Transmit FIFO level does not generate a FIFO level trigger.
- * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this
- * register.
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
*/
-#define USART_FIFOTRIG_TXLVLENA(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
-#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
-#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
+#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+
+#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled
* in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.
* 0b0..Receive FIFO level does not generate a FIFO level trigger.
- * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this
- * register.
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.
*/
-#define USART_FIFOTRIG_RXLVLENA(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
-#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
-#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
+#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+
+#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled
* to do so, the FIFO level can wake up the device just enough to perform DMA, then return to
* the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO
* becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX
* FIFO level decreases to 15 entries (is no longer full).
*/
-#define USART_FIFOTRIG_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
-#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
-#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
+#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+
+#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data
* is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level
* can wake up the device just enough to perform DMA, then return to the reduced power mode. See
@@ -25916,356 +25557,341 @@ typedef struct
* longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX
* FIFO has received 16 entries (has become full).
*/
-#define USART_FIFOTRIG_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
/*! @{ */
-#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
-#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
-/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT
- * register. 0b0..No interrupt will be generated for a transmit error. 0b1..An interrupt will be generated when a
- * transmit error occurs.
- */
-#define USART_FIFOINTENSET_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
-#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
-#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
-/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT
- * register. 0b0..No interrupt will be generated for a receive error. 0b1..An interrupt will be generated when a receive
- * error occurs.
- */
-#define USART_FIFOINTENSET_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
-#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
-#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
+
+#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a transmit error.
+ * 0b1..An interrupt will be generated when a transmit error occurs.
+ */
+#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+
+#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.
+ * 0b0..No interrupt will be generated for a receive error.
+ * 0b1..An interrupt will be generated when a receive error occurs.
+ */
+#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+
+#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level
* specified by the TXLVL field in the FIFOTRIG register.
* 0b0..No interrupt will be generated based on the TX FIFO level.
* 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases
* to the level specified by TXLVL in the FIFOTRIG register.
*/
-#define USART_FIFOINTENSET_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
-#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
-#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
+#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+
+#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level
* specified by the TXLVL field in the FIFOTRIG register.
* 0b0..No interrupt will be generated based on the RX FIFO level.
* 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level
* increases to the level specified by RXLVL in the FIFOTRIG register.
*/
-#define USART_FIFOINTENSET_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
/*! @{ */
-#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
-#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
+
+#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define USART_FIFOINTENCLR_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
-#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
-#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
+#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+
+#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define USART_FIFOINTENCLR_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
-#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
-#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
+#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+
+#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define USART_FIFOINTENCLR_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
-#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
-#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
+#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+
+#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register.
*/
-#define USART_FIFOINTENCLR_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
/*! @} */
/*! @name FIFOINTSTAT - FIFO interrupt status register. */
/*! @{ */
-#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
-#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
+
+#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
/*! TXERR - TX FIFO error.
*/
-#define USART_FIFOINTSTAT_TXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
-#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
-#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
+#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+
+#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
/*! RXERR - RX FIFO error.
*/
-#define USART_FIFOINTSTAT_RXERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
-#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
-#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
+#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+
+#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
/*! TXLVL - Transmit FIFO level interrupt.
*/
-#define USART_FIFOINTSTAT_TXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
-#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
-#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
+#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+
+#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
/*! RXLVL - Receive FIFO level interrupt.
*/
-#define USART_FIFOINTSTAT_RXLVL(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
-#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
-#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
+#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+
+#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
/*! PERINT - Peripheral interrupt.
*/
-#define USART_FIFOINTSTAT_PERINT(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
/*! @} */
/*! @name FIFOWR - FIFO write data. */
/*! @{ */
-#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
-#define USART_FIFOWR_TXDATA_SHIFT (0U)
+
+#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT (0U)
/*! TXDATA - Transmit data to the FIFO.
*/
-#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
/*! @} */
/*! @name FIFORD - FIFO read data. */
/*! @{ */
-#define USART_FIFORD_RXDATA_MASK (0x1FFU)
-#define USART_FIFORD_RXDATA_SHIFT (0U)
+
+#define USART_FIFORD_RXDATA_MASK (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT (0U)
/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
*/
-#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
-#define USART_FIFORD_FRAMERR_MASK (0x2000U)
-#define USART_FIFORD_FRAMERR_SHIFT (13U)
+#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+
+#define USART_FIFORD_FRAMERR_MASK (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT (13U)
/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
* with from the FIFO, and indicates that the character was received with a missing stop bit at
* the expected location. This could be an indication of a baud rate or configuration mismatch
* with the transmitting source.
*/
-#define USART_FIFORD_FRAMERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
-#define USART_FIFORD_PARITYERR_MASK (0x4000U)
-#define USART_FIFORD_PARITYERR_SHIFT (14U)
+#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+
+#define USART_FIFORD_PARITYERR_MASK (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT (14U)
/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
* with from the FIFO. This bit will be set when a parity error is detected in a received
* character.
*/
-#define USART_FIFORD_PARITYERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
-#define USART_FIFORD_RXNOISE_MASK (0x8000U)
-#define USART_FIFORD_RXNOISE_SHIFT (15U)
+#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+
+#define USART_FIFORD_RXNOISE_MASK (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT (15U)
/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
*/
-#define USART_FIFORD_RXNOISE(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
/*! @} */
/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
/*! @{ */
-#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
-#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
+
+#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings.
*/
-#define USART_FIFORDNOPOP_RXDATA(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
-#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
-#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
+#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+
+#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along
* with from the FIFO, and indicates that the character was received with a missing stop bit at
* the expected location. This could be an indication of a baud rate or configuration mismatch
* with the transmitting source.
*/
-#define USART_FIFORDNOPOP_FRAMERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
-#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
-#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
+#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+
+#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along
* with from the FIFO. This bit will be set when a parity error is detected in a received
* character.
*/
-#define USART_FIFORDNOPOP_PARITYERR(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
-#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
-#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
+#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+
+#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354.
*/
-#define USART_FIFORDNOPOP_RXNOISE(x) \
- (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
/*! @} */
/*! @name ID - Peripheral identification register. */
/*! @{ */
-#define USART_ID_APERTURE_MASK (0xFFU)
-#define USART_ID_APERTURE_SHIFT (0U)
+
+#define USART_ID_APERTURE_MASK (0xFFU)
+#define USART_ID_APERTURE_SHIFT (0U)
/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture.
*/
-#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
-#define USART_ID_MINOR_REV_MASK (0xF00U)
-#define USART_ID_MINOR_REV_SHIFT (8U)
+#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+
+#define USART_ID_MINOR_REV_MASK (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT (8U)
/*! MINOR_REV - Minor revision of module implementation.
*/
-#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
-#define USART_ID_MAJOR_REV_MASK (0xF000U)
-#define USART_ID_MAJOR_REV_SHIFT (12U)
+#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+
+#define USART_ID_MAJOR_REV_MASK (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT (12U)
/*! MAJOR_REV - Major revision of module implementation.
*/
-#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
-#define USART_ID_ID_MASK (0xFFFF0000U)
-#define USART_ID_ID_SHIFT (16U)
+#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+
+#define USART_ID_ID_MASK (0xFFFF0000U)
+#define USART_ID_ID_SHIFT (16U)
/*! ID - Module identifier for the selected function.
*/
-#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group USART_Register_Masks */
+
/* USART - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral USART0 base address */
-#define USART0_BASE (0x50086000u)
-/** Peripheral USART0 base address */
-#define USART0_BASE_NS (0x40086000u)
-/** Peripheral USART0 base pointer */
-#define USART0 ((USART_Type *)USART0_BASE)
-/** Peripheral USART0 base pointer */
-#define USART0_NS ((USART_Type *)USART0_BASE_NS)
-/** Peripheral USART1 base address */
-#define USART1_BASE (0x50087000u)
-/** Peripheral USART1 base address */
-#define USART1_BASE_NS (0x40087000u)
-/** Peripheral USART1 base pointer */
-#define USART1 ((USART_Type *)USART1_BASE)
-/** Peripheral USART1 base pointer */
-#define USART1_NS ((USART_Type *)USART1_BASE_NS)
-/** Peripheral USART2 base address */
-#define USART2_BASE (0x50088000u)
-/** Peripheral USART2 base address */
-#define USART2_BASE_NS (0x40088000u)
-/** Peripheral USART2 base pointer */
-#define USART2 ((USART_Type *)USART2_BASE)
-/** Peripheral USART2 base pointer */
-#define USART2_NS ((USART_Type *)USART2_BASE_NS)
-/** Peripheral USART3 base address */
-#define USART3_BASE (0x50089000u)
-/** Peripheral USART3 base address */
-#define USART3_BASE_NS (0x40089000u)
-/** Peripheral USART3 base pointer */
-#define USART3 ((USART_Type *)USART3_BASE)
-/** Peripheral USART3 base pointer */
-#define USART3_NS ((USART_Type *)USART3_BASE_NS)
-/** Peripheral USART4 base address */
-#define USART4_BASE (0x5008A000u)
-/** Peripheral USART4 base address */
-#define USART4_BASE_NS (0x4008A000u)
-/** Peripheral USART4 base pointer */
-#define USART4 ((USART_Type *)USART4_BASE)
-/** Peripheral USART4 base pointer */
-#define USART4_NS ((USART_Type *)USART4_BASE_NS)
-/** Peripheral USART5 base address */
-#define USART5_BASE (0x50096000u)
-/** Peripheral USART5 base address */
-#define USART5_BASE_NS (0x40096000u)
-/** Peripheral USART5 base pointer */
-#define USART5 ((USART_Type *)USART5_BASE)
-/** Peripheral USART5 base pointer */
-#define USART5_NS ((USART_Type *)USART5_BASE_NS)
-/** Peripheral USART6 base address */
-#define USART6_BASE (0x50097000u)
-/** Peripheral USART6 base address */
-#define USART6_BASE_NS (0x40097000u)
-/** Peripheral USART6 base pointer */
-#define USART6 ((USART_Type *)USART6_BASE)
-/** Peripheral USART6 base pointer */
-#define USART6_NS ((USART_Type *)USART6_BASE_NS)
-/** Peripheral USART7 base address */
-#define USART7_BASE (0x50098000u)
-/** Peripheral USART7 base address */
-#define USART7_BASE_NS (0x40098000u)
-/** Peripheral USART7 base pointer */
-#define USART7 ((USART_Type *)USART7_BASE)
-/** Peripheral USART7 base pointer */
-#define USART7_NS ((USART_Type *)USART7_BASE_NS)
-/** Array initializer of USART peripheral base addresses */
-#define USART_BASE_ADDRS \
- { \
- USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE \
- }
-/** Array initializer of USART peripheral base pointers */
-#define USART_BASE_PTRS \
- { \
- USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 \
- }
-/** Array initializer of USART peripheral base addresses */
-#define USART_BASE_ADDRS_NS \
- { \
- USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, \
- USART6_BASE_NS, USART7_BASE_NS \
- }
-/** Array initializer of USART peripheral base pointers */
-#define USART_BASE_PTRS_NS \
- { \
- USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS \
- }
+ /** Peripheral USART0 base address */
+ #define USART0_BASE (0x50086000u)
+ /** Peripheral USART0 base address */
+ #define USART0_BASE_NS (0x40086000u)
+ /** Peripheral USART0 base pointer */
+ #define USART0 ((USART_Type *)USART0_BASE)
+ /** Peripheral USART0 base pointer */
+ #define USART0_NS ((USART_Type *)USART0_BASE_NS)
+ /** Peripheral USART1 base address */
+ #define USART1_BASE (0x50087000u)
+ /** Peripheral USART1 base address */
+ #define USART1_BASE_NS (0x40087000u)
+ /** Peripheral USART1 base pointer */
+ #define USART1 ((USART_Type *)USART1_BASE)
+ /** Peripheral USART1 base pointer */
+ #define USART1_NS ((USART_Type *)USART1_BASE_NS)
+ /** Peripheral USART2 base address */
+ #define USART2_BASE (0x50088000u)
+ /** Peripheral USART2 base address */
+ #define USART2_BASE_NS (0x40088000u)
+ /** Peripheral USART2 base pointer */
+ #define USART2 ((USART_Type *)USART2_BASE)
+ /** Peripheral USART2 base pointer */
+ #define USART2_NS ((USART_Type *)USART2_BASE_NS)
+ /** Peripheral USART3 base address */
+ #define USART3_BASE (0x50089000u)
+ /** Peripheral USART3 base address */
+ #define USART3_BASE_NS (0x40089000u)
+ /** Peripheral USART3 base pointer */
+ #define USART3 ((USART_Type *)USART3_BASE)
+ /** Peripheral USART3 base pointer */
+ #define USART3_NS ((USART_Type *)USART3_BASE_NS)
+ /** Peripheral USART4 base address */
+ #define USART4_BASE (0x5008A000u)
+ /** Peripheral USART4 base address */
+ #define USART4_BASE_NS (0x4008A000u)
+ /** Peripheral USART4 base pointer */
+ #define USART4 ((USART_Type *)USART4_BASE)
+ /** Peripheral USART4 base pointer */
+ #define USART4_NS ((USART_Type *)USART4_BASE_NS)
+ /** Peripheral USART5 base address */
+ #define USART5_BASE (0x50096000u)
+ /** Peripheral USART5 base address */
+ #define USART5_BASE_NS (0x40096000u)
+ /** Peripheral USART5 base pointer */
+ #define USART5 ((USART_Type *)USART5_BASE)
+ /** Peripheral USART5 base pointer */
+ #define USART5_NS ((USART_Type *)USART5_BASE_NS)
+ /** Peripheral USART6 base address */
+ #define USART6_BASE (0x50097000u)
+ /** Peripheral USART6 base address */
+ #define USART6_BASE_NS (0x40097000u)
+ /** Peripheral USART6 base pointer */
+ #define USART6 ((USART_Type *)USART6_BASE)
+ /** Peripheral USART6 base pointer */
+ #define USART6_NS ((USART_Type *)USART6_BASE_NS)
+ /** Peripheral USART7 base address */
+ #define USART7_BASE (0x50098000u)
+ /** Peripheral USART7 base address */
+ #define USART7_BASE_NS (0x40098000u)
+ /** Peripheral USART7 base pointer */
+ #define USART7 ((USART_Type *)USART7_BASE)
+ /** Peripheral USART7 base pointer */
+ #define USART7_NS ((USART_Type *)USART7_BASE_NS)
+ /** Array initializer of USART peripheral base addresses */
+ #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
+ /** Array initializer of USART peripheral base pointers */
+ #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
+ /** Array initializer of USART peripheral base addresses */
+ #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS }
+ /** Array initializer of USART peripheral base pointers */
+ #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS }
#else
-/** Peripheral USART0 base address */
-#define USART0_BASE (0x40086000u)
-/** Peripheral USART0 base pointer */
-#define USART0 ((USART_Type *)USART0_BASE)
-/** Peripheral USART1 base address */
-#define USART1_BASE (0x40087000u)
-/** Peripheral USART1 base pointer */
-#define USART1 ((USART_Type *)USART1_BASE)
-/** Peripheral USART2 base address */
-#define USART2_BASE (0x40088000u)
-/** Peripheral USART2 base pointer */
-#define USART2 ((USART_Type *)USART2_BASE)
-/** Peripheral USART3 base address */
-#define USART3_BASE (0x40089000u)
-/** Peripheral USART3 base pointer */
-#define USART3 ((USART_Type *)USART3_BASE)
-/** Peripheral USART4 base address */
-#define USART4_BASE (0x4008A000u)
-/** Peripheral USART4 base pointer */
-#define USART4 ((USART_Type *)USART4_BASE)
-/** Peripheral USART5 base address */
-#define USART5_BASE (0x40096000u)
-/** Peripheral USART5 base pointer */
-#define USART5 ((USART_Type *)USART5_BASE)
-/** Peripheral USART6 base address */
-#define USART6_BASE (0x40097000u)
-/** Peripheral USART6 base pointer */
-#define USART6 ((USART_Type *)USART6_BASE)
-/** Peripheral USART7 base address */
-#define USART7_BASE (0x40098000u)
-/** Peripheral USART7 base pointer */
-#define USART7 ((USART_Type *)USART7_BASE)
-/** Array initializer of USART peripheral base addresses */
-#define USART_BASE_ADDRS \
- { \
- USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE \
- }
-/** Array initializer of USART peripheral base pointers */
-#define USART_BASE_PTRS \
- { \
- USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 \
- }
+ /** Peripheral USART0 base address */
+ #define USART0_BASE (0x40086000u)
+ /** Peripheral USART0 base pointer */
+ #define USART0 ((USART_Type *)USART0_BASE)
+ /** Peripheral USART1 base address */
+ #define USART1_BASE (0x40087000u)
+ /** Peripheral USART1 base pointer */
+ #define USART1 ((USART_Type *)USART1_BASE)
+ /** Peripheral USART2 base address */
+ #define USART2_BASE (0x40088000u)
+ /** Peripheral USART2 base pointer */
+ #define USART2 ((USART_Type *)USART2_BASE)
+ /** Peripheral USART3 base address */
+ #define USART3_BASE (0x40089000u)
+ /** Peripheral USART3 base pointer */
+ #define USART3 ((USART_Type *)USART3_BASE)
+ /** Peripheral USART4 base address */
+ #define USART4_BASE (0x4008A000u)
+ /** Peripheral USART4 base pointer */
+ #define USART4 ((USART_Type *)USART4_BASE)
+ /** Peripheral USART5 base address */
+ #define USART5_BASE (0x40096000u)
+ /** Peripheral USART5 base pointer */
+ #define USART5 ((USART_Type *)USART5_BASE)
+ /** Peripheral USART6 base address */
+ #define USART6_BASE (0x40097000u)
+ /** Peripheral USART6 base pointer */
+ #define USART6 ((USART_Type *)USART6_BASE)
+ /** Peripheral USART7 base address */
+ #define USART7_BASE (0x40098000u)
+ /** Peripheral USART7 base pointer */
+ #define USART7 ((USART_Type *)USART7_BASE)
+ /** Array initializer of USART peripheral base addresses */
+ #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }
+ /** Array initializer of USART peripheral base pointers */
+ #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }
#endif
/** Interrupt vectors for the USART peripheral type */
-#define USART_IRQS \
- { \
- FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, \
- FLEXCOMM6_IRQn, FLEXCOMM7_IRQn \
- }
+#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
/*!
* @}
*/ /* end of group USART_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -26276,21 +25902,20 @@ typedef struct
*/
/** USB - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
- __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
- __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
- __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
- __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
- __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
- __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
- __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
- __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
- __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
- __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
- uint8_t RESERVED_0[8];
- __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
+ __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
} USB_Type;
/* ----------------------------------------------------------------------------
@@ -26304,88 +25929,89 @@ typedef struct
/*! @name DEVCMDSTAT - USB Device Command/Status register */
/*! @{ */
-#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
-#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit
* is set, the device will respond on packets for function address DEV_ADDR. When receiving a
* SetAddress Control Request from the USB host, software must program the new address before
* completing the status phase of the SetAddress Control Request.
*/
-#define USB_DEVCMDSTAT_DEV_ADDR(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
-#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
-#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
-/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address
- * DEV_ADDR.
- */
-#define USB_DEVCMDSTAT_DEV_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
-#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
-#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
+#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+
+#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR.
+ */
+#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+
+#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this
* bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW
* must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the
* CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW.
*/
-#define USB_DEVCMDSTAT_SETUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:
* 0b0..USB_NEEDCLK has normal function.
* 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.
*/
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
-#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
-#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+
+#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
/*! LPM_SUP - LPM Supported:
* 0b0..LPM not supported.
* 0b1..LPM supported.
*/
-#define USB_DEVCMDSTAT_LPM_SUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
-#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP
* 0b0..Only acknowledged packets generate an interrupt
* 0b1..Both acknowledged and NAKed packets generate interrupts.
*/
-#define USB_DEVCMDSTAT_INTONNAK_AO(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
-#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP
* 0b0..Only acknowledged packets generate an interrupt
* 0b1..Both acknowledged and NAKed packets generate interrupts.
*/
-#define USB_DEVCMDSTAT_INTONNAK_AI(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
-#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
/*! INTONNAK_CO - Interrupt on NAK for control OUT EP
* 0b0..Only acknowledged packets generate an interrupt
* 0b1..Both acknowledged and NAKed packets generate interrupts.
*/
-#define USB_DEVCMDSTAT_INTONNAK_CO(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
-#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
/*! INTONNAK_CI - Interrupt on NAK for control IN EP
* 0b0..Only acknowledged packets generate an interrupt
* 0b1..Both acknowledged and NAKed packets generate interrupts.
*/
-#define USB_DEVCMDSTAT_INTONNAK_CI(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
-#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
-#define USB_DEVCMDSTAT_DCON_SHIFT (16U)
+#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+
+#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT (16U)
/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device
* must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and
* the VBUSDEBOUNCED bit is one.
*/
-#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
-#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
-#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
+#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+
+#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set
* to 1 when the device hasn't seen any activity on its upstream port for more than 3
* milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and
@@ -26393,9 +26019,10 @@ typedef struct
* when the device is connected (Connect bit = 1). When the device is not connected or not
* suspended, a writing a 0 has no effect. Writing a 1 never has an effect.
*/
-#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
-#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
-#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+
+#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is
* set to 1 by HW when the device has acknowledged the LPM request from the USB host and the
* Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend
@@ -26404,64 +26031,65 @@ typedef struct
* bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the
* LPM_SUPP bit is equal to one.
*/
-#define USB_DEVCMDSTAT_LPM_SUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
-#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
-#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+
+#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake
* bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the
* host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset
* is received. Software can use this bit to check if the remote wake-up feature is enabled by the
* host for the LPM transaction.
*/
-#define USB_DEVCMDSTAT_LPM_REWP(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
-#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
-#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
+#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+
+#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up
* resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it.
*/
-#define USB_DEVCMDSTAT_DCON_C(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
-#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
-#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+
+#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit
* toggles. The suspend bit can toggle because: - The device goes in the suspended state - The
* device is disconnected - The device receives resume signaling on its upstream port. The bit is
* reset by writing a one to it.
*/
-#define USB_DEVCMDSTAT_DSUS_C(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
-#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
-#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
+#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+
+#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On
* a bus reset the device will automatically go to the default state (unconfigured and responding
* to address 0). The bit is reset by writing a one to it.
*/
-#define USB_DEVCMDSTAT_DRES_C(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
+#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when
* Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and
* the DCon bit is set, the HW will enable the pull-up resistor to signal a connect.
*/
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
/*! @} */
/*! @name INFO - USB Info register */
/*! @{ */
-#define USB_INFO_FRAME_NR_MASK (0x7FFU)
-#define USB_INFO_FRAME_NR_SHIFT (0U)
+
+#define USB_INFO_FRAME_NR_MASK (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT (0U)
/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF.
* In case no SOF was received by the device at the beginning of a frame, the frame number
* returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC
* error, the frame number returned will be the corrupted frame number as received by the device.
*/
-#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
-#define USB_INFO_ERR_CODE_MASK (0x7800U)
-#define USB_INFO_ERR_CODE_SHIFT (11U)
+#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+
+#define USB_INFO_ERR_CODE_MASK (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT (11U)
/*! ERR_CODE - The error code which last occurred:
* 0b0000..No error
* 0b0001..PID encoding error
@@ -26480,334 +26108,332 @@ typedef struct
* 0b1110..Sync error
* 0b1111..Wrong data toggle
*/
-#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
-#define USB_INFO_MINREV_MASK (0xFF0000U)
-#define USB_INFO_MINREV_SHIFT (16U)
+#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+
+#define USB_INFO_MINREV_MASK (0xFF0000U)
+#define USB_INFO_MINREV_SHIFT (16U)
/*! MINREV - Minor Revision.
*/
-#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
-#define USB_INFO_MAJREV_MASK (0xFF000000U)
-#define USB_INFO_MAJREV_SHIFT (24U)
+#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
+
+#define USB_INFO_MAJREV_MASK (0xFF000000U)
+#define USB_INFO_MAJREV_SHIFT (24U)
/*! MAJREV - Major Revision.
*/
-#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
+#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
/*! @} */
/*! @name EPLISTSTART - USB EP Command/Status List start address */
/*! @{ */
-#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
-#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
+
+#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
/*! EP_LIST - Start address of the USB EP Command/Status List.
*/
-#define USB_EPLISTSTART_EP_LIST(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
/*! @} */
/*! @name DATABUFSTART - USB Data buffer start address */
/*! @{ */
-#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
-#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
+
+#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located.
*/
-#define USB_DATABUFSTART_DA_BUF(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
/*! @} */
/*! @name LPM - USB Link Power Management register */
/*! @{ */
-#define USB_LPM_HIRD_HW_MASK (0xFU)
-#define USB_LPM_HIRD_HW_SHIFT (0U)
+
+#define USB_LPM_HIRD_HW_MASK (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT (0U)
/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token
*/
-#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
-#define USB_LPM_HIRD_SW_MASK (0xF0U)
-#define USB_LPM_HIRD_SW_SHIFT (4U)
+#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+
+#define USB_LPM_HIRD_SW_MASK (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT (4U)
/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB
* device system to come out of LPM initiated suspend after receiving the host initiated LPM resume.
*/
-#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
-#define USB_LPM_DATA_PENDING_MASK (0x100U)
-#define USB_LPM_DATA_PENDING_SHIFT (8U)
+#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+
+#define USB_LPM_DATA_PENDING_MASK (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT (8U)
/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
* return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and
* this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has
* still data pending and LPM is supported, it must set this bit to 1.
*/
-#define USB_LPM_DATA_PENDING(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
/*! @} */
/*! @name EPSKIP - USB Endpoint skip */
/*! @{ */
-#define USB_EPSKIP_SKIP_MASK (0x3FFU)
-#define USB_EPSKIP_SKIP_SHIFT (0U)
+
+#define USB_EPSKIP_SKIP_MASK (0x3FFU)
+#define USB_EPSKIP_SKIP_SHIFT (0U)
/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
* deactivate the buffer assigned to this endpoint and return control back to software. When HW has
* deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An
* interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering,
* HW will only clear the Active bit of the buffer indicated by the EPINUSE bit.
*/
-#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
/*! @} */
/*! @name EPINUSE - USB Endpoint Buffer in use */
/*! @{ */
-#define USB_EPINUSE_BUF_MASK (0x3FCU)
-#define USB_EPINUSE_BUF_SHIFT (2U)
+
+#define USB_EPINUSE_BUF_MASK (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT (2U)
/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer
* 0. 1: HW is accessing buffer 1.
*/
-#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
/*! @} */
/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
/*! @{ */
-#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
-#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
+
+#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1:
* Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding
* EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle
* the EPINUSE bit when it clears the Active bit for the buffer.
*/
-#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
/*! @} */
/*! @name INTSTAT - USB interrupt status register */
/*! @{ */
-#define USB_INTSTAT_EP0OUT_MASK (0x1U)
-#define USB_INTSTAT_EP0OUT_SHIFT (0U)
+
+#define USB_INTSTAT_EP0OUT_MASK (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT (0U)
/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set
* if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is
* successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a
* NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a
* one to it.
*/
-#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
-#define USB_INTSTAT_EP0IN_MASK (0x2U)
-#define USB_INTSTAT_EP0IN_SHIFT (1U)
+#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+
+#define USB_INTSTAT_EP0IN_MASK (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT (1U)
/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if
* NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this
* bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can
* clear this bit by writing a one to it.
*/
-#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
-#define USB_INTSTAT_EP1OUT_MASK (0x4U)
-#define USB_INTSTAT_EP1OUT_SHIFT (2U)
+#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+
+#define USB_INTSTAT_EP1OUT_MASK (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT (2U)
/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
* transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
* set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by
* writing a one to it.
*/
-#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
-#define USB_INTSTAT_EP1IN_MASK (0x8U)
-#define USB_INTSTAT_EP1IN_SHIFT (3U)
+#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+
+#define USB_INTSTAT_EP1IN_MASK (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT (3U)
/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
* to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
* set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing
* a one to it.
*/
-#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
-#define USB_INTSTAT_EP2OUT_MASK (0x10U)
-#define USB_INTSTAT_EP2OUT_SHIFT (4U)
+#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+
+#define USB_INTSTAT_EP2OUT_MASK (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT (4U)
/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
* transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
* set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by
* writing a one to it.
*/
-#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
-#define USB_INTSTAT_EP2IN_MASK (0x20U)
-#define USB_INTSTAT_EP2IN_SHIFT (5U)
+#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+
+#define USB_INTSTAT_EP2IN_MASK (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT (5U)
/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
* to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
* set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing
* a one to it.
*/
-#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
-#define USB_INTSTAT_EP3OUT_MASK (0x40U)
-#define USB_INTSTAT_EP3OUT_SHIFT (6U)
+#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+
+#define USB_INTSTAT_EP3OUT_MASK (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT (6U)
/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
* transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
* set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by
* writing a one to it.
*/
-#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
-#define USB_INTSTAT_EP3IN_MASK (0x80U)
-#define USB_INTSTAT_EP3IN_SHIFT (7U)
+#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+
+#define USB_INTSTAT_EP3IN_MASK (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT (7U)
/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
* to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
* set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing
* a one to it.
*/
-#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
-#define USB_INTSTAT_EP4OUT_MASK (0x100U)
-#define USB_INTSTAT_EP4OUT_SHIFT (8U)
+#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+
+#define USB_INTSTAT_EP4OUT_MASK (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT (8U)
/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes
* transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be
* set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by
* writing a one to it.
*/
-#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
-#define USB_INTSTAT_EP4IN_MASK (0x200U)
-#define USB_INTSTAT_EP4IN_SHIFT (9U)
+#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+
+#define USB_INTSTAT_EP4IN_MASK (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT (9U)
/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the
* corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions
* to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be
* set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing
* a one to it.
*/
-#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
-#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
-#define USB_INTSTAT_FRAME_INT_SHIFT (30U)
+#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+
+#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT (30U)
/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit
* and the DCON bit are set. This bit can be used by software when handling isochronous
* endpoints. Software can clear this bit by writing a one to it.
*/
-#define USB_INTSTAT_FRAME_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
-#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
-#define USB_INTSTAT_DEV_INT_SHIFT (31U)
+#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+
+#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT (31U)
/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device
* Status Change register are set. Software can clear this bit by writing a one to it.
*/
-#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
/*! @} */
/*! @name INTEN - USB interrupt enable register */
/*! @{ */
-#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
-#define USB_INTEN_EP_INT_EN_SHIFT (0U)
+
+#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT (0U)
/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
* interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
* bit.
*/
-#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
-#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
-#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
+#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+
+#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
* interrupt is generated on the interrupt line indicated by the corresponding USB interrupt
* routing bit.
*/
-#define USB_INTEN_FRAME_INT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
-#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
-#define USB_INTEN_DEV_INT_EN_SHIFT (31U)
+#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+
+#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT (31U)
/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
* interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing
* bit.
*/
-#define USB_INTEN_DEV_INT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
/*! @} */
/*! @name INTSETSTAT - USB set interrupt status register */
/*! @{ */
-#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
-#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+
+#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
* status bit is set. When this register is read, the same value as the USB interrupt status register
* is returned.
*/
-#define USB_INTSETSTAT_EP_SET_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
-#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
-#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
* status bit is set. When this register is read, the same value as the USB interrupt status
* register is returned.
*/
-#define USB_INTSETSTAT_FRAME_SET_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
-#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
-#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+
+#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt
* status bit is set. When this register is read, the same value as the USB interrupt status
* register is returned.
*/
-#define USB_INTSETSTAT_DEV_SET_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
/*! @} */
/*! @name EPTOGGLE - USB Endpoint toggle register */
/*! @{ */
-#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
-#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
-/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding
- * endpoint.
+
+#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
*/
-#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group USB_Register_Masks */
+
/* USB - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x50084000u)
-/** Peripheral USB0 base address */
-#define USB0_BASE_NS (0x40084000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-/** Peripheral USB0 base pointer */
-#define USB0_NS ((USB_Type *)USB0_BASE_NS)
-/** Array initializer of USB peripheral base addresses */
-#define USB_BASE_ADDRS \
- { \
- USB0_BASE \
- }
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASE_PTRS \
- { \
- USB0 \
- }
-/** Array initializer of USB peripheral base addresses */
-#define USB_BASE_ADDRS_NS \
- { \
- USB0_BASE_NS \
- }
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASE_PTRS_NS \
- { \
- USB0_NS \
- }
+ /** Peripheral USB0 base address */
+ #define USB0_BASE (0x50084000u)
+ /** Peripheral USB0 base address */
+ #define USB0_BASE_NS (0x40084000u)
+ /** Peripheral USB0 base pointer */
+ #define USB0 ((USB_Type *)USB0_BASE)
+ /** Peripheral USB0 base pointer */
+ #define USB0_NS ((USB_Type *)USB0_BASE_NS)
+ /** Array initializer of USB peripheral base addresses */
+ #define USB_BASE_ADDRS { USB0_BASE }
+ /** Array initializer of USB peripheral base pointers */
+ #define USB_BASE_PTRS { USB0 }
+ /** Array initializer of USB peripheral base addresses */
+ #define USB_BASE_ADDRS_NS { USB0_BASE_NS }
+ /** Array initializer of USB peripheral base pointers */
+ #define USB_BASE_PTRS_NS { USB0_NS }
#else
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40084000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-/** Array initializer of USB peripheral base addresses */
-#define USB_BASE_ADDRS \
- { \
- USB0_BASE \
- }
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASE_PTRS \
- { \
- USB0 \
- }
+ /** Peripheral USB0 base address */
+ #define USB0_BASE (0x40084000u)
+ /** Peripheral USB0 base pointer */
+ #define USB0 ((USB_Type *)USB0_BASE)
+ /** Array initializer of USB peripheral base addresses */
+ #define USB_BASE_ADDRS { USB0_BASE }
+ /** Array initializer of USB peripheral base pointers */
+ #define USB_BASE_PTRS { USB0 }
#endif
/** Interrupt vectors for the USB peripheral type */
-#define USB_IRQS \
- { \
- USB0_IRQn \
- }
-#define USB_NEEDCLK_IRQS \
- { \
- USB0_NEEDCLK_IRQn \
- }
+#define USB_IRQS { USB0_IRQn }
+#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- USBFSH Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -26818,52 +26444,31 @@ typedef struct
*/
/** USBFSH - Register Layout Typedef */
-typedef struct
-{
- __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the
- Host Controller (HC), offset: 0x0 */
- __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */
- __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver
- (HCD), offset: 0x8 */
- __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by
- setting the appropriate bits, offset: 0xC */
- __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events
- will generate a hardware interrupt, offset: 0x10 */
- __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the
- HCInterruptStatus register and in turn disable that event leading to hardware
- interrupt, offset: 0x14 */
- __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */
- __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint
- descriptor, offset: 0x1C */
- __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control
- list, offset: 0x20 */
- __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the
- control list, offset: 0x24 */
- __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list,
- offset: 0x28 */
- __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk
- list, offset: 0x2C */
- __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done'
- queue, offset: 0x30 */
- __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size
- which would not cause an overrun, offset: 0x34 */
- __I uint32_t
- HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
- __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in
- the HC and the HCD, offset: 0x3C */
- __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC
- should start processing a periodic list, offset: 0x40 */
- __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to
- transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
- __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub,
- offset: 0x48 */
- __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub,
- offset: 0x4C */
- __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */
- __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
- uint8_t RESERVED_0[4];
- __IO uint32_t
- PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
+typedef struct {
+ __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
+ __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */
+ __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
+ __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
+ __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
+ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
+ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */
+ __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
+ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
+ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
+ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
+ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
+ __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
+ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
+ __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
+ __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
+ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
+ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
+ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
+ __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
+ __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */
+ __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
} USBFSH_Type;
/* ----------------------------------------------------------------------------
@@ -26875,703 +26480,673 @@ typedef struct
* @{
*/
-/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host
- * Controller (HC) */
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
/*! @{ */
-#define USBFSH_HCREVISION_REV_MASK (0xFFU)
-#define USBFSH_HCREVISION_REV_SHIFT (0U)
+
+#define USBFSH_HCREVISION_REV_MASK (0xFFU)
+#define USBFSH_HCREVISION_REV_SHIFT (0U)
/*! REV - Revision.
*/
-#define USBFSH_HCREVISION_REV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
+#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
/*! @} */
/*! @name HCCONTROL - Defines the operating modes of the HC */
/*! @{ */
-#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)
-#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)
+
+#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)
+#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)
/*! CBSR - ControlBulkServiceRatio.
*/
-#define USBFSH_HCCONTROL_CBSR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
-#define USBFSH_HCCONTROL_PLE_MASK (0x4U)
-#define USBFSH_HCCONTROL_PLE_SHIFT (2U)
+#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
+
+#define USBFSH_HCCONTROL_PLE_MASK (0x4U)
+#define USBFSH_HCCONTROL_PLE_SHIFT (2U)
/*! PLE - PeriodicListEnable.
*/
-#define USBFSH_HCCONTROL_PLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
-#define USBFSH_HCCONTROL_IE_MASK (0x8U)
-#define USBFSH_HCCONTROL_IE_SHIFT (3U)
+#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
+
+#define USBFSH_HCCONTROL_IE_MASK (0x8U)
+#define USBFSH_HCCONTROL_IE_SHIFT (3U)
/*! IE - IsochronousEnable.
*/
-#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
-#define USBFSH_HCCONTROL_CLE_MASK (0x10U)
-#define USBFSH_HCCONTROL_CLE_SHIFT (4U)
+#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
+
+#define USBFSH_HCCONTROL_CLE_MASK (0x10U)
+#define USBFSH_HCCONTROL_CLE_SHIFT (4U)
/*! CLE - ControlListEnable.
*/
-#define USBFSH_HCCONTROL_CLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
-#define USBFSH_HCCONTROL_BLE_MASK (0x20U)
-#define USBFSH_HCCONTROL_BLE_SHIFT (5U)
+#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
+
+#define USBFSH_HCCONTROL_BLE_MASK (0x20U)
+#define USBFSH_HCCONTROL_BLE_SHIFT (5U)
/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame.
*/
-#define USBFSH_HCCONTROL_BLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
-#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)
-#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)
+#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
+
+#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)
+#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)
/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL
* 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin
* 1 ms later.
*/
-#define USBFSH_HCCONTROL_HCFS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
-#define USBFSH_HCCONTROL_IR_MASK (0x100U)
-#define USBFSH_HCCONTROL_IR_SHIFT (8U)
-/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in
- * HcInterruptStatus.
+#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
+
+#define USBFSH_HCCONTROL_IR_MASK (0x100U)
+#define USBFSH_HCCONTROL_IR_SHIFT (8U)
+/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus.
*/
-#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
-#define USBFSH_HCCONTROL_RWC_MASK (0x200U)
-#define USBFSH_HCCONTROL_RWC_SHIFT (9U)
+#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
+
+#define USBFSH_HCCONTROL_RWC_MASK (0x200U)
+#define USBFSH_HCCONTROL_RWC_SHIFT (9U)
/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling.
*/
-#define USBFSH_HCCONTROL_RWC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
-#define USBFSH_HCCONTROL_RWE_MASK (0x400U)
-#define USBFSH_HCCONTROL_RWE_SHIFT (10U)
+#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
+
+#define USBFSH_HCCONTROL_RWE_MASK (0x400U)
+#define USBFSH_HCCONTROL_RWE_SHIFT (10U)
/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature
* upon the detection of upstream resume signaling.
*/
-#define USBFSH_HCCONTROL_RWE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
+#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
/*! @} */
/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
/*! @{ */
-#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)
-#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)
+
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)
/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC.
*/
-#define USBFSH_HCCOMMANDSTATUS_HCR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
-#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)
-#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
+
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)
/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list.
*/
-#define USBFSH_HCCOMMANDSTATUS_CLF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
-#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)
-#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
+
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)
/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list.
*/
-#define USBFSH_HCCOMMANDSTATUS_BLF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
-#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)
-#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)
+#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
+
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)
/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC.
*/
-#define USBFSH_HCCOMMANDSTATUS_OCR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
-#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)
-#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)
+#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
+
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)
/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error.
*/
-#define USBFSH_HCCOMMANDSTATUS_SOC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
+#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
/*! @} */
-/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the
- * appropriate bits */
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
/*! @{ */
-#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)
-#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)
+
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)
/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and
* after the update of HccaFrameNumber.
*/
-#define USBFSH_HCINTERRUPTSTATUS_SO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)
-#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)
/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead.
*/
-#define USBFSH_HCINTERRUPTSTATUS_WDH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)
-#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)
/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber.
*/
-#define USBFSH_HCINTERRUPTSTATUS_SF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)
-#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)
+#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)
/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling.
*/
-#define USBFSH_HCINTERRUPTSTATUS_RD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)
-#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)
+#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)
/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB.
*/
-#define USBFSH_HCINTERRUPTSTATUS_UE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)
-#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)
+#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)
/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value,
* from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated.
*/
-#define USBFSH_HCINTERRUPTSTATUS_FNO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)
/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any
* of HcRhPortStatus[NumberofDownstreamPort] has changed.
*/
-#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)
-#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
+
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)
/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus.
*/
-#define USBFSH_HCINTERRUPTSTATUS_OC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
/*! @} */
-/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will
- * generate a hardware interrupt */
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
/*! @{ */
-#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)
-#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)
+
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)
/*! SO - Scheduling Overrun interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_SO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
-#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)
-#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)
+#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)
/*! WDH - HcDoneHead Writeback interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_WDH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
-#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)
-#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)
/*! SF - Start of Frame interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_SF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
-#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)
-#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)
+#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)
/*! RD - Resume Detect interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_RD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
-#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)
-#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)
+#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)
/*! UE - Unrecoverable Error interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_UE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
-#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)
-#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)
+#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)
/*! FNO - Frame Number Overflow interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_FNO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
-#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)
-#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)
+#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)
/*! RHSC - Root Hub Status Change interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_RHSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
-#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)
-#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)
/*! OC - Ownership Change interrupt.
*/
-#define USBFSH_HCINTERRUPTENABLE_OC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
-#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)
-#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)
+#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
+
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)
/*! MIE - Master Interrupt Enable.
*/
-#define USBFSH_HCINTERRUPTENABLE_MIE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
+#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
/*! @} */
-/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus
- * register and in turn disable that event leading to hardware interrupt */
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
/*! @{ */
-#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)
-#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)
+
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)
/*! SO - Scheduling Overrun interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_SO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)
-#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)
/*! WDH - HcDoneHead Writeback interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_WDH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)
-#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)
/*! SF - Start of Frame interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_SF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)
-#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)
+#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)
/*! RD - Resume Detect interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_RD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)
-#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)
+#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)
/*! UE - Unrecoverable Error interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_UE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)
-#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)
+#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)
/*! FNO - Frame Number Overflow interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_FNO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)
/*! RHSC - Root Hub Status Change interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)
-#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)
/*! OC - Ownership Change interrupt.
*/
-#define USBFSH_HCINTERRUPTDISABLE_OC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)
-#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)
+#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
+
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)
/*! MIE - A 0 written to this field is ignored by HC.
*/
-#define USBFSH_HCINTERRUPTDISABLE_MIE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
/*! @} */
/*! @name HCHCCA - Contains the physical address of the host controller communication area */
/*! @{ */
-#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)
-#define USBFSH_HCHCCA_HCCA_SHIFT (8U)
+
+#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)
+#define USBFSH_HCHCCA_HCCA_SHIFT (8U)
/*! HCCA - Base address of the Host Controller Communication Area.
*/
-#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
+#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
/*! @} */
-/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor
- */
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
/*! @{ */
-#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)
+
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)
/*! PCED - The content of this register is updated by HC after a periodic ED is processed.
*/
-#define USBFSH_HCPERIODCURRENTED_PCED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
+#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
/*! @} */
/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
/*! @{ */
-#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)
+
+#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)
/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer.
*/
-#define USBFSH_HCCONTROLHEADED_CHED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
+#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
/*! @} */
/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
/*! @{ */
-#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)
+
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)
/*! CCED - ControlCurrentED.
*/
-#define USBFSH_HCCONTROLCURRENTED_CCED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
+#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
/*! @} */
/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
/*! @{ */
-#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)
+
+#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)
/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer.
*/
-#define USBFSH_HCBULKHEADED_BHED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
+#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
/*! @} */
/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
/*! @{ */
-#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)
+
+#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)
/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one.
*/
-#define USBFSH_HCBULKCURRENTED_BCED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
+#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
/*! @} */
/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
/*! @{ */
-#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)
-#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)
+
+#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)
+#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)
/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD.
*/
-#define USBFSH_HCDONEHEAD_DH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
+#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
/*! @} */
-/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not
- * cause an overrun */
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
/*! @{ */
-#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)
-#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)
+
+#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)
+#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)
/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times.
*/
-#define USBFSH_HCFMINTERVAL_FI(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
-#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)
-#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)
+#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
+
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)
/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data
* Packet Counter at the beginning of each frame.
*/
-#define USBFSH_HCFMINTERVAL_FSMPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
-#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)
-#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)
+#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
+
+#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)
/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval.
*/
-#define USBFSH_HCFMINTERVAL_FIT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
+#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
/*! @} */
/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
/*! @{ */
-#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)
-#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)
+
+#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)
+#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)
/*! FR - FrameRemaining This counter is decremented at each bit time.
*/
-#define USBFSH_HCFMREMAINING_FR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
-#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)
-#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)
+#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
+
+#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)
+#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)
/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval
* whenever FrameRemaining reaches 0.
*/
-#define USBFSH_HCFMREMAINING_FRT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
+#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
/*! @} */
-/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and
- * the HCD */
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
/*! @{ */
-#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)
-#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)
+
+#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)
+#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)
/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded.
*/
-#define USBFSH_HCFMNUMBER_FN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
+#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
/*! @} */
-/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start
- * processing a periodic list */
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
/*! @{ */
-#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)
-#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)
+
+#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)
+#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)
/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization.
*/
-#define USBFSH_HCPERIODICSTART_PS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
+#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
/*! @} */
-/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a
- * maximum of 8-byte LS packet before EOF */
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
/*! @{ */
-#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)
-#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)
+
+#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)
/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field
* prior to initiating a Low Speed transaction.
*/
-#define USBFSH_HCLSTHRESHOLD_LST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
+#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
/*! @} */
/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
/*! @{ */
-#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)
-#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)
+
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)
/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub.
*/
-#define USBFSH_HCRHDESCRIPTORA_NDP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
-#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)
-#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)
+#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
+
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)
/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled.
*/
-#define USBFSH_HCRHDESCRIPTORA_PSM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
-#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)
-#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)
-/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always
- * powered.
- */
-#define USBFSH_HCRHDESCRIPTORA_NPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
-#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)
-#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)
+#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
+
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)
+/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered.
+ */
+#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
+
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)
/*! DT - DeviceType This bit specifies that the root hub is not a compound device.
*/
-#define USBFSH_HCRHDESCRIPTORA_DT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
-#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)
-#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)
+#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
+
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)
/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported.
*/
-#define USBFSH_HCRHDESCRIPTORA_OCPM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
-#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)
-#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
+
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)
/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported.
*/
-#define USBFSH_HCRHDESCRIPTORA_NOCP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
+
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)
/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before
* accessing a powered-on port of the root hub.
*/
-#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
/*! @} */
/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
/*! @{ */
-#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)
-#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)
+
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)
/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub.
*/
-#define USBFSH_HCRHDESCRIPTORB_DR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
-#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)
-#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)
+#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
+
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)
/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control
* command when PowerSwitchingMode is set.
*/
-#define USBFSH_HCRHDESCRIPTORB_PPCM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
/*! @} */
/*! @name HCRHSTATUS - This register is divided into two parts */
/*! @{ */
-#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)
-#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)
+
+#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)
+#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)
/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature;
* thus, this bit is always read as 0.
*/
-#define USBFSH_HCRHSTATUS_LPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
-#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)
-#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)
+#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
+
+#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)
+#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)
/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented.
*/
-#define USBFSH_HCRHSTATUS_OCI(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
-#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)
-#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)
+#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
+
+#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)
/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume
* event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected
* interrupt.
*/
-#define USBFSH_HCRHSTATUS_DRWE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
-#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)
-#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)
+#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
+
+#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)
/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature.
*/
-#define USBFSH_HCRHSTATUS_LPSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
-#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)
-#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)
-/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this
- * register.
- */
-#define USBFSH_HCRHSTATUS_OCIC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
-#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)
-#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)
+#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
+
+#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)
+/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register.
+ */
+#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
+
+#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)
/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable.
*/
-#define USBFSH_HCRHSTATUS_CRWE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
+#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
/*! @} */
/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
/*! @{ */
-#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)
-#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)
+
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)
/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port.
*/
-#define USBFSH_HCRHPORTSTATUS_CCS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
-#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)
-#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)
+#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)
/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled.
*/
-#define USBFSH_HCRHPORTSTATUS_PES(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
-#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)
-#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)
+#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)
/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence.
*/
-#define USBFSH_HCRHPORTSTATUS_PSS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
-#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)
-#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)
+#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)
/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in
* such a way that overcurrent conditions are reported on a per-port basis.
*/
-#define USBFSH_HCRHPORTSTATUS_POCI(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
-#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)
-#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)
+#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)
/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted.
*/
-#define USBFSH_HCRHPORTSTATUS_PRS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
-#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)
-#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)
+#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)
/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type
* of power switching implemented.
*/
-#define USBFSH_HCRHPORTSTATUS_PPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
-#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)
-#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)
+#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)
/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port.
*/
-#define USBFSH_HCRHPORTSTATUS_LSDA(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
-#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)
-#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)
+#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)
/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs.
*/
-#define USBFSH_HCRHPORTSTATUS_CSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)
-#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)
+#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)
/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared.
*/
-#define USBFSH_HCRHPORTSTATUS_PESC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)
-#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)
+#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)
/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed.
*/
-#define USBFSH_HCRHPORTSTATUS_PSSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
-#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)
-#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)
-/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port
- * basis.
- */
-#define USBFSH_HCRHPORTSTATUS_OCIC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)
-#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)
+#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)
+/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis.
+ */
+#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
+
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)
/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal.
*/
-#define USBFSH_HCRHPORTSTATUS_PRSC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
/*! @} */
/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
/*! @{ */
-#define USBFSH_PORTMODE_ID_MASK (0x1U)
-#define USBFSH_PORTMODE_ID_SHIFT (0U)
+
+#define USBFSH_PORTMODE_ID_MASK (0x1U)
+#define USBFSH_PORTMODE_ID_SHIFT (0U)
/*! ID - Port ID pin value.
*/
-#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
-#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)
-#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)
+#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
+
+#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)
+#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)
/*! ID_EN - Port ID pin pull-up enable.
*/
-#define USBFSH_PORTMODE_ID_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
-#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
-#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
+
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
/*! DEV_ENABLE - 1: device 0: host.
*/
-#define USBFSH_PORTMODE_DEV_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
+#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group USBFSH_Register_Masks */
+
/* USBFSH - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral USBFSH base address */
-#define USBFSH_BASE (0x500A2000u)
-/** Peripheral USBFSH base address */
-#define USBFSH_BASE_NS (0x400A2000u)
-/** Peripheral USBFSH base pointer */
-#define USBFSH ((USBFSH_Type *)USBFSH_BASE)
-/** Peripheral USBFSH base pointer */
-#define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS)
-/** Array initializer of USBFSH peripheral base addresses */
-#define USBFSH_BASE_ADDRS \
- { \
- USBFSH_BASE \
- }
-/** Array initializer of USBFSH peripheral base pointers */
-#define USBFSH_BASE_PTRS \
- { \
- USBFSH \
- }
-/** Array initializer of USBFSH peripheral base addresses */
-#define USBFSH_BASE_ADDRS_NS \
- { \
- USBFSH_BASE_NS \
- }
-/** Array initializer of USBFSH peripheral base pointers */
-#define USBFSH_BASE_PTRS_NS \
- { \
- USBFSH_NS \
- }
+ /** Peripheral USBFSH base address */
+ #define USBFSH_BASE (0x500A2000u)
+ /** Peripheral USBFSH base address */
+ #define USBFSH_BASE_NS (0x400A2000u)
+ /** Peripheral USBFSH base pointer */
+ #define USBFSH ((USBFSH_Type *)USBFSH_BASE)
+ /** Peripheral USBFSH base pointer */
+ #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS)
+ /** Array initializer of USBFSH peripheral base addresses */
+ #define USBFSH_BASE_ADDRS { USBFSH_BASE }
+ /** Array initializer of USBFSH peripheral base pointers */
+ #define USBFSH_BASE_PTRS { USBFSH }
+ /** Array initializer of USBFSH peripheral base addresses */
+ #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS }
+ /** Array initializer of USBFSH peripheral base pointers */
+ #define USBFSH_BASE_PTRS_NS { USBFSH_NS }
#else
-/** Peripheral USBFSH base address */
-#define USBFSH_BASE (0x400A2000u)
-/** Peripheral USBFSH base pointer */
-#define USBFSH ((USBFSH_Type *)USBFSH_BASE)
-/** Array initializer of USBFSH peripheral base addresses */
-#define USBFSH_BASE_ADDRS \
- { \
- USBFSH_BASE \
- }
-/** Array initializer of USBFSH peripheral base pointers */
-#define USBFSH_BASE_PTRS \
- { \
- USBFSH \
- }
+ /** Peripheral USBFSH base address */
+ #define USBFSH_BASE (0x400A2000u)
+ /** Peripheral USBFSH base pointer */
+ #define USBFSH ((USBFSH_Type *)USBFSH_BASE)
+ /** Array initializer of USBFSH peripheral base addresses */
+ #define USBFSH_BASE_ADDRS { USBFSH_BASE }
+ /** Array initializer of USBFSH peripheral base pointers */
+ #define USBFSH_BASE_PTRS { USBFSH }
#endif
/** Interrupt vectors for the USBFSH peripheral type */
-#define USBFSH_IRQS \
- { \
- USB0_IRQn \
- }
-#define USBFSH_NEEDCLK_IRQS \
- { \
- USB0_NEEDCLK_IRQn \
- }
+#define USBFSH_IRQS { USB0_IRQn }
+#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
/*!
* @}
*/ /* end of group USBFSH_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- USBHSD Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -27582,21 +27157,20 @@ typedef struct
*/
/** USBHSD - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
- __I uint32_t INFO; /**< USB Info register, offset: 0x4 */
- __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
- __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
- __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
- __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
- __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
- __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
- __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
- __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
- __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
- uint8_t RESERVED_0[8];
- __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
+ __I uint32_t INFO; /**< USB Info register, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
} USBHSD_Type;
/* ----------------------------------------------------------------------------
@@ -27610,436 +27184,419 @@ typedef struct
/*! @name DEVCMDSTAT - USB Device Command/Status register */
/*! @{ */
-#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
-#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
/*! DEV_ADDR - USB device address.
*/
-#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
-#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
-#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
/*! DEV_EN - USB device enable.
*/
-#define USBHSD_DEVCMDSTAT_DEV_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
-#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
-#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
+#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+
+#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
/*! SETUP - SETUP token received.
*/
-#define USBHSD_DEVCMDSTAT_SETUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:.
*/
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
-#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
/*! LPM_SUP - LPM Supported:.
*/
-#define USBHSD_DEVCMDSTAT_LPM_SUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:.
*/
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:.
*/
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:.
*/
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
/*! INTONNAK_CI - Interrupt on NAK for control IN EP:.
*/
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
-#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
-#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+
+#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
/*! DCON - Device status - connect.
*/
-#define USBHSD_DEVCMDSTAT_DCON(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
-#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
-#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
+#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+
+#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
/*! DSUS - Device status - suspend.
*/
-#define USBHSD_DEVCMDSTAT_DSUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
-#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
/*! LPM_SUS - Device status - LPM Suspend.
*/
-#define USBHSD_DEVCMDSTAT_LPM_SUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
-#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host.
*/
-#define USBHSD_DEVCMDSTAT_LPM_REWP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
-#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)
-#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+
+#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)
/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b:
* full-speed 10b: high-speed 11b: super-speed (reserved for future use).
*/
-#define USBHSD_DEVCMDSTAT_Speed(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
-#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
-#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
+#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
+
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
/*! DCON_C - Device status - connect change.
*/
-#define USBHSD_DEVCMDSTAT_DCON_C(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
-#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
-#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
/*! DSUS_C - Device status - suspend change.
*/
-#define USBHSD_DEVCMDSTAT_DSUS_C(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
-#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
-#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
+#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
/*! DRES_C - Device status - reset change.
*/
-#define USBHSD_DEVCMDSTAT_DRES_C(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
+#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not.
*/
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
-/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0
- * specification
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
+/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification
*/
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
/*! @} */
/*! @name INFO - USB Info register */
/*! @{ */
-#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
-#define USBHSD_INFO_FRAME_NR_SHIFT (0U)
+
+#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT (0U)
/*! FRAME_NR - Frame number.
*/
-#define USBHSD_INFO_FRAME_NR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
-#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
-#define USBHSD_INFO_ERR_CODE_SHIFT (11U)
+#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+
+#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT (11U)
/*! ERR_CODE - The error code which last occurred:.
*/
-#define USBHSD_INFO_ERR_CODE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
-#define USBHSD_INFO_MINREV_MASK (0xFF0000U)
-#define USBHSD_INFO_MINREV_SHIFT (16U)
+#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+
+#define USBHSD_INFO_MINREV_MASK (0xFF0000U)
+#define USBHSD_INFO_MINREV_SHIFT (16U)
/*! MINREV - Minor revision.
*/
-#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK)
-#define USBHSD_INFO_MAJREV_MASK (0xFF000000U)
-#define USBHSD_INFO_MAJREV_SHIFT (24U)
+#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK)
+
+#define USBHSD_INFO_MAJREV_MASK (0xFF000000U)
+#define USBHSD_INFO_MAJREV_SHIFT (24U)
/*! MAJREV - Major revision.
*/
-#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK)
+#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK)
/*! @} */
/*! @name EPLISTSTART - USB EP Command/Status List start address */
/*! @{ */
-#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
-#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
+
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address.
*/
-#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address.
*/
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
/*! @} */
/*! @name DATABUFSTART - USB Data buffer start address */
/*! @{ */
-#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU)
-#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U)
+
+#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U)
/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located.
*/
-#define USBHSD_DATABUFSTART_DA_BUF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
/*! @} */
/*! @name LPM - USB Link Power Management register */
/*! @{ */
-#define USBHSD_LPM_HIRD_HW_MASK (0xFU)
-#define USBHSD_LPM_HIRD_HW_SHIFT (0U)
+
+#define USBHSD_LPM_HIRD_HW_MASK (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT (0U)
/*! HIRD_HW - Host Initiated Resume Duration - HW.
*/
-#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
-#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
-#define USBHSD_LPM_HIRD_SW_SHIFT (4U)
+#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+
+#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT (4U)
/*! HIRD_SW - Host Initiated Resume Duration - SW.
*/
-#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
-#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
-#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
+#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+
+#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will
* return a NYET handshake on every LPM token it receives.
*/
-#define USBHSD_LPM_DATA_PENDING(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
/*! @} */
/*! @name EPSKIP - USB Endpoint skip */
/*! @{ */
-#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
-#define USBHSD_EPSKIP_SKIP_SHIFT (0U)
+
+#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT (0U)
/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must
* deactivate the buffer assigned to this endpoint and return control back to software.
*/
-#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
/*! @} */
/*! @name EPINUSE - USB Endpoint Buffer in use */
/*! @{ */
-#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
-#define USBHSD_EPINUSE_BUF_SHIFT (2U)
+
+#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT (2U)
/*! BUF - Buffer in use: This register has one bit per physical endpoint.
*/
-#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
/*! @} */
/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
/*! @{ */
-#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
-#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
+
+#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint.
*/
-#define USBHSD_EPBUFCFG_BUF_SB(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
/*! @} */
/*! @name INTSTAT - USB interrupt status register */
/*! @{ */
-#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
-#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
+
+#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction.
*/
-#define USBHSD_INTSTAT_EP0OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
-#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
-#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
+#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+
+#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction.
*/
-#define USBHSD_INTSTAT_EP0IN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
-#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
-#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
+#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+
+#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction.
*/
-#define USBHSD_INTSTAT_EP1OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
-#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
-#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
+#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+
+#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
/*! EP1IN - Interrupt status register bit for the EP1 IN direction.
*/
-#define USBHSD_INTSTAT_EP1IN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
-#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
-#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
+#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+
+#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction.
*/
-#define USBHSD_INTSTAT_EP2OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
-#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
-#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
+#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+
+#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
/*! EP2IN - Interrupt status register bit for the EP2 IN direction.
*/
-#define USBHSD_INTSTAT_EP2IN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
-#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
-#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
+#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+
+#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction.
*/
-#define USBHSD_INTSTAT_EP3OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
-#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
-#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
+#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+
+#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
/*! EP3IN - Interrupt status register bit for the EP3 IN direction.
*/
-#define USBHSD_INTSTAT_EP3IN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
-#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
-#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
+#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+
+#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction.
*/
-#define USBHSD_INTSTAT_EP4OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
-#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
-#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
+#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+
+#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
/*! EP4IN - Interrupt status register bit for the EP4 IN direction.
*/
-#define USBHSD_INTSTAT_EP4IN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
-#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
-#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
+#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+
+#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction.
*/
-#define USBHSD_INTSTAT_EP5OUT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
-#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
-#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
+#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+
+#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
/*! EP5IN - Interrupt status register bit for the EP5 IN direction.
*/
-#define USBHSD_INTSTAT_EP5IN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
-#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
-#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
+#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+
+#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
/*! FRAME_INT - Frame interrupt.
*/
-#define USBHSD_INTSTAT_FRAME_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
-#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
-#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
+#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+
+#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
/*! DEV_INT - Device status interrupt.
*/
-#define USBHSD_INTSTAT_DEV_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
/*! @} */
/*! @name INTEN - USB interrupt enable register */
/*! @{ */
-#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
-#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
+
+#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
* interrupt is generated on the interrupt line.
*/
-#define USBHSD_INTEN_EP_INT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
-#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
-#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
+#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+
+#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
* interrupt is generated on the interrupt line.
*/
-#define USBHSD_INTEN_FRAME_INT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
-#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
-#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
+#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+
+#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW
* interrupt is generated on the interrupt line.
*/
-#define USBHSD_INTEN_DEV_INT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
/*! @} */
/*! @name INTSETSTAT - USB set interrupt status register */
/*! @{ */
-#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
-#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
*/
-#define USBHSD_INTSETSTAT_EP_SET_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
*/
-#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
-#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
-#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.
*/
-#define USBHSD_INTSETSTAT_DEV_SET_INT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
/*! @} */
/*! @name EPTOGGLE - USB Endpoint toggle register */
/*! @{ */
-#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
-#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
-/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding
- * endpoint.
+
+#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
+/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint.
*/
-#define USBHSD_EPTOGGLE_TOGGLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group USBHSD_Register_Masks */
+
/* USBHSD - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral USBHSD base address */
-#define USBHSD_BASE (0x50094000u)
-/** Peripheral USBHSD base address */
-#define USBHSD_BASE_NS (0x40094000u)
-/** Peripheral USBHSD base pointer */
-#define USBHSD ((USBHSD_Type *)USBHSD_BASE)
-/** Peripheral USBHSD base pointer */
-#define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS)
-/** Array initializer of USBHSD peripheral base addresses */
-#define USBHSD_BASE_ADDRS \
- { \
- USBHSD_BASE \
- }
-/** Array initializer of USBHSD peripheral base pointers */
-#define USBHSD_BASE_PTRS \
- { \
- USBHSD \
- }
-/** Array initializer of USBHSD peripheral base addresses */
-#define USBHSD_BASE_ADDRS_NS \
- { \
- USBHSD_BASE_NS \
- }
-/** Array initializer of USBHSD peripheral base pointers */
-#define USBHSD_BASE_PTRS_NS \
- { \
- USBHSD_NS \
- }
+ /** Peripheral USBHSD base address */
+ #define USBHSD_BASE (0x50094000u)
+ /** Peripheral USBHSD base address */
+ #define USBHSD_BASE_NS (0x40094000u)
+ /** Peripheral USBHSD base pointer */
+ #define USBHSD ((USBHSD_Type *)USBHSD_BASE)
+ /** Peripheral USBHSD base pointer */
+ #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS)
+ /** Array initializer of USBHSD peripheral base addresses */
+ #define USBHSD_BASE_ADDRS { USBHSD_BASE }
+ /** Array initializer of USBHSD peripheral base pointers */
+ #define USBHSD_BASE_PTRS { USBHSD }
+ /** Array initializer of USBHSD peripheral base addresses */
+ #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS }
+ /** Array initializer of USBHSD peripheral base pointers */
+ #define USBHSD_BASE_PTRS_NS { USBHSD_NS }
#else
-/** Peripheral USBHSD base address */
-#define USBHSD_BASE (0x40094000u)
-/** Peripheral USBHSD base pointer */
-#define USBHSD ((USBHSD_Type *)USBHSD_BASE)
-/** Array initializer of USBHSD peripheral base addresses */
-#define USBHSD_BASE_ADDRS \
- { \
- USBHSD_BASE \
- }
-/** Array initializer of USBHSD peripheral base pointers */
-#define USBHSD_BASE_PTRS \
- { \
- USBHSD \
- }
+ /** Peripheral USBHSD base address */
+ #define USBHSD_BASE (0x40094000u)
+ /** Peripheral USBHSD base pointer */
+ #define USBHSD ((USBHSD_Type *)USBHSD_BASE)
+ /** Array initializer of USBHSD peripheral base addresses */
+ #define USBHSD_BASE_ADDRS { USBHSD_BASE }
+ /** Array initializer of USBHSD peripheral base pointers */
+ #define USBHSD_BASE_PTRS { USBHSD }
#endif
/** Interrupt vectors for the USBHSD peripheral type */
-#define USBHSD_IRQS \
- { \
- USB1_IRQn \
- }
-#define USBHSD_NEEDCLK_IRQS \
- { \
- USB1_NEEDCLK_IRQn \
- }
+#define USBHSD_IRQS { USB1_IRQn }
+#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
/*!
* @}
*/ /* end of group USBHSD_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- USBHSH Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -28050,32 +27607,28 @@ typedef struct
*/
/** USBHSH - Register Layout Typedef */
-typedef struct
-{
- __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational
- register space and the version number of the IP block, offset: 0x0 */
- __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
- uint8_t RESERVED_0[4];
- __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
- __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
- __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
- __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
- __IO uint32_t
- DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
- __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */
- __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */
- __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */
- __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */
- __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */
- __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */
- __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */
- __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */
- __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */
- __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */
- __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
- uint8_t RESERVED_1[4];
- __IO uint32_t
- PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
+typedef struct {
+ __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
+ __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
+ __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
+ __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
+ __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
+ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */
+ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */
+ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */
+ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */
+ __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */
+ __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */
+ __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */
+ __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */
+ __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */
+ __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */
+ __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
} USBHSH_Type;
/* ----------------------------------------------------------------------------
@@ -28087,497 +27640,494 @@ typedef struct
* @{
*/
-/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space
- * and the version number of the IP block */
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
/*! @{ */
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
+
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
/*! CAPLENGTH - Capability Length: This is used as an offset.
*/
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major
* revision [23:16] = Minor revision Major revisions used: 0x01: USB2.
*/
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
/*! @} */
/*! @name HCSPARAMS - Host Controller Structural Parameters */
/*! @{ */
-#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
-#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
+
+#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller.
*/
-#define USBHSH_HCSPARAMS_N_PORTS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
-#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
-#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
+#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+
+#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
/*! PPC - This field indicates whether the host controller implementation includes port power control.
*/
-#define USBHSH_HCSPARAMS_PPC(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
-#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
-#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
+#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
/*! P_INDICATOR - This bit indicates whether the ports support port indicator control.
*/
-#define USBHSH_HCSPARAMS_P_INDICATOR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
/*! @} */
/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
/*! @{ */
-#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
-#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
+
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
/*! FLADJ - Frame Length Timing Value.
*/
-#define USBHSH_FLADJ_FRINDEX_FLADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet.
*/
-#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
/*! @} */
/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */
/*! @{ */
-#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U)
-#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U)
+
+#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U)
+#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U)
/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list.
*/
-#define USBHSH_ATLPTD_ATL_CUR(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK)
-#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U)
-#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U)
+#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK)
+
+#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U)
+#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U)
/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list.
*/
-#define USBHSH_ATLPTD_ATL_BASE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK)
+#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK)
/*! @} */
/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */
/*! @{ */
-#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U)
-#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U)
+
+#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U)
+#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U)
/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list.
*/
-#define USBHSH_ISOPTD_ISO_FIRST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK)
-#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U)
-#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U)
+#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK)
+
+#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U)
/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list.
*/
-#define USBHSH_ISOPTD_ISO_BASE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK)
+#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK)
/*! @} */
/*! @name INTPTD - Memory base address where INT PTD0 is stored */
/*! @{ */
-#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U)
-#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U)
+
+#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U)
+#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U)
/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list.
*/
-#define USBHSH_INTPTD_INT_FIRST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK)
-#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U)
-#define USBHSH_INTPTD_INT_BASE_SHIFT (10U)
+#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK)
+
+#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_INTPTD_INT_BASE_SHIFT (10U)
/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list.
*/
-#define USBHSH_INTPTD_INT_BASE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK)
+#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK)
/*! @} */
/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */
/*! @{ */
-#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U)
-#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U)
+
+#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U)
/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section.
*/
-#define USBHSH_DATAPAYLOAD_DAT_BASE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK)
+#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK)
/*! @} */
/*! @name USBCMD - USB Command register */
/*! @{ */
-#define USBHSH_USBCMD_RS_MASK (0x1U)
-#define USBHSH_USBCMD_RS_SHIFT (0U)
+
+#define USBHSH_USBCMD_RS_MASK (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT (0U)
/*! RS - Run/Stop: 1b = Run.
*/
-#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
-#define USBHSH_USBCMD_HCRESET_MASK (0x2U)
-#define USBHSH_USBCMD_HCRESET_SHIFT (1U)
+#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+
+#define USBHSH_USBCMD_HCRESET_MASK (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT (1U)
/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller.
*/
-#define USBHSH_USBCMD_HCRESET(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
-#define USBHSH_USBCMD_FLS_MASK (0xCU)
-#define USBHSH_USBCMD_FLS_SHIFT (2U)
+#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+
+#define USBHSH_USBCMD_FLS_MASK (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT (2U)
/*! FLS - Frame List Size: This field specifies the size of the frame list.
*/
-#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
-#define USBHSH_USBCMD_LHCR_MASK (0x80U)
-#define USBHSH_USBCMD_LHCR_SHIFT (7U)
+#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+
+#define USBHSH_USBCMD_LHCR_MASK (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT (7U)
/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host
* controller without affecting the state of the ports.
*/
-#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
-#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
-#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
+#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+
+#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
/*! ATL_EN - ATL List enabled.
*/
-#define USBHSH_USBCMD_ATL_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
-#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
-#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
+#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+
+#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
/*! ISO_EN - ISO List enabled.
*/
-#define USBHSH_USBCMD_ISO_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
-#define USBHSH_USBCMD_INT_EN_MASK (0x400U)
-#define USBHSH_USBCMD_INT_EN_SHIFT (10U)
+#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+
+#define USBHSH_USBCMD_INT_EN_MASK (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT (10U)
/*! INT_EN - INT List enabled.
*/
-#define USBHSH_USBCMD_INT_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
/*! @} */
/*! @name USBSTS - USB Interrupt Status register */
/*! @{ */
-#define USBHSH_USBSTS_PCD_MASK (0x4U)
-#define USBHSH_USBSTS_PCD_SHIFT (2U)
+
+#define USBHSH_USBSTS_PCD_MASK (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT (2U)
/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a
* change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a
* result of a J-K transition detected on a suspended port.
*/
-#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
-#define USBHSH_USBSTS_FLR_MASK (0x8U)
-#define USBHSH_USBSTS_FLR_SHIFT (3U)
+#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+
+#define USBHSH_USBSTS_FLR_MASK (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT (3U)
/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list
* index rolls over its maximum value to 0.
*/
-#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
-#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
-#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
+#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+
+#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed.
*/
-#define USBHSH_USBSTS_ATL_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
-#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
-#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
+#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+
+#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed.
*/
-#define USBHSH_USBSTS_ISO_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
-#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
-#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
+#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+
+#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed.
*/
-#define USBHSH_USBSTS_INT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
-#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
-#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
+#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+
+#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set.
*/
-#define USBHSH_USBSTS_SOF_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
/*! @} */
/*! @name USBINTR - USB Interrupt Enable register */
/*! @{ */
-#define USBHSH_USBINTR_PCDE_MASK (0x4U)
-#define USBHSH_USBINTR_PCDE_SHIFT (2U)
+
+#define USBHSH_USBINTR_PCDE_MASK (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT (2U)
/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable.
*/
-#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
-#define USBHSH_USBINTR_FLRE_MASK (0x8U)
-#define USBHSH_USBINTR_FLRE_SHIFT (3U)
+#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+
+#define USBHSH_USBINTR_FLRE_MASK (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT (3U)
/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable.
*/
-#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
-#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
-#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
+#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable.
*/
-#define USBHSH_USBINTR_ATL_IRQ_E(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
-#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
-#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
+#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable.
*/
-#define USBHSH_USBINTR_ISO_IRQ_E(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
-#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
-#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
+#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+
+#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable.
*/
-#define USBHSH_USBINTR_INT_IRQ_E(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
-#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
-#define USBHSH_USBINTR_SOF_E_SHIFT (19U)
+#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+
+#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT (19U)
/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable.
*/
-#define USBHSH_USBINTR_SOF_E(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
/*! @} */
/*! @name PORTSC1 - Port Status and Control register */
/*! @{ */
-#define USBHSH_PORTSC1_CCS_MASK (0x1U)
-#define USBHSH_PORTSC1_CCS_SHIFT (0U)
+
+#define USBHSH_PORTSC1_CCS_MASK (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT (0U)
/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port.
*/
-#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
-#define USBHSH_PORTSC1_CSC_MASK (0x2U)
-#define USBHSH_PORTSC1_CSC_SHIFT (1U)
+#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+
+#define USBHSH_PORTSC1_CSC_MASK (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT (1U)
/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed.
*/
-#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
-#define USBHSH_PORTSC1_PED_MASK (0x4U)
-#define USBHSH_PORTSC1_PED_SHIFT (2U)
+#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+
+#define USBHSH_PORTSC1_PED_MASK (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT (2U)
/*! PED - Port Enabled/Disabled.
*/
-#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
-#define USBHSH_PORTSC1_PEDC_MASK (0x8U)
-#define USBHSH_PORTSC1_PEDC_SHIFT (3U)
+#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+
+#define USBHSH_PORTSC1_PEDC_MASK (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT (3U)
/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed.
*/
-#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
-#define USBHSH_PORTSC1_OCA_MASK (0x10U)
-#define USBHSH_PORTSC1_OCA_SHIFT (4U)
+#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+
+#define USBHSH_PORTSC1_OCA_MASK (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT (4U)
/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition.
*/
-#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
-#define USBHSH_PORTSC1_OCC_MASK (0x20U)
-#define USBHSH_PORTSC1_OCC_SHIFT (5U)
+#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+
+#define USBHSH_PORTSC1_OCC_MASK (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT (5U)
/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed.
*/
-#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
-#define USBHSH_PORTSC1_FPR_MASK (0x40U)
-#define USBHSH_PORTSC1_FPR_SHIFT (6U)
+#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+
+#define USBHSH_PORTSC1_FPR_MASK (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT (6U)
/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port.
*/
-#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
-#define USBHSH_PORTSC1_SUSP_MASK (0x80U)
-#define USBHSH_PORTSC1_SUSP_SHIFT (7U)
+#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+
+#define USBHSH_PORTSC1_SUSP_MASK (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT (7U)
/*! SUSP - Suspend: Logic 1 means port is in the suspend state.
*/
-#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
-#define USBHSH_PORTSC1_PR_MASK (0x100U)
-#define USBHSH_PORTSC1_PR_SHIFT (8U)
+#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+
+#define USBHSH_PORTSC1_PR_MASK (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT (8U)
/*! PR - Port Reset: Logic 1 means the port is in the reset state.
*/
-#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
-#define USBHSH_PORTSC1_LS_MASK (0xC00U)
-#define USBHSH_PORTSC1_LS_SHIFT (10U)
+#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+
+#define USBHSH_PORTSC1_LS_MASK (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT (10U)
/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines.
*/
-#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
-#define USBHSH_PORTSC1_PP_MASK (0x1000U)
-#define USBHSH_PORTSC1_PP_SHIFT (12U)
-/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS
- * register.
+#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+
+#define USBHSH_PORTSC1_PP_MASK (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT (12U)
+/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register.
*/
-#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
-#define USBHSH_PORTSC1_PIC_MASK (0xC000U)
-#define USBHSH_PORTSC1_PIC_SHIFT (14U)
+#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+
+#define USBHSH_PORTSC1_PIC_MASK (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT (14U)
/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the
* HCSPARAMS register is logic 0.
*/
-#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
-#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
-#define USBHSH_PORTSC1_PTC_SHIFT (16U)
-/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the
- * value.
+#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+
+#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT (16U)
+/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value.
*/
-#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
-#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
-#define USBHSH_PORTSC1_PSPD_SHIFT (20U)
+#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+
+#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT (20U)
/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved.
*/
-#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
-#define USBHSH_PORTSC1_WOO_MASK (0x400000U)
-#define USBHSH_PORTSC1_WOO_SHIFT (22U)
+#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+
+#define USBHSH_PORTSC1_WOO_MASK (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT (22U)
/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to
* overcurrent conditions as wake-up events.
*/
-#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
/*! @} */
/*! @name ATLPTDD - Done map for each ATL PTD */
/*! @{ */
-#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU)
-#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U)
+
+#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U)
/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
*/
-#define USBHSH_ATLPTDD_ATL_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK)
+#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK)
/*! @} */
/*! @name ATLPTDS - Skip map for each ATL PTD */
/*! @{ */
-#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU)
-#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U)
+
+#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U)
/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
* skipped, independent of the V bit setting.
*/
-#define USBHSH_ATLPTDS_ATL_SKIP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK)
+#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK)
/*! @} */
/*! @name ISOPTDD - Done map for each ISO PTD */
/*! @{ */
-#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU)
-#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U)
+
+#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U)
/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
*/
-#define USBHSH_ISOPTDD_ISO_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK)
+#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK)
/*! @} */
/*! @name ISOPTDS - Skip map for each ISO PTD */
/*! @{ */
-#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU)
-#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U)
+
+#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U)
/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
*/
-#define USBHSH_ISOPTDS_ISO_SKIP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK)
+#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK)
/*! @} */
/*! @name INTPTDD - Done map for each INT PTD */
/*! @{ */
-#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU)
-#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U)
+
+#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U)
/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed.
*/
-#define USBHSH_INTPTDD_INT_DONE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK)
+#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK)
/*! @} */
/*! @name INTPTDS - Skip map for each INT PTD */
/*! @{ */
-#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU)
-#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U)
+
+#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U)
/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be
* skipped, independent of the V bit setting.
*/
-#define USBHSH_INTPTDS_INT_SKIP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK)
+#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK)
/*! @} */
/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */
/*! @{ */
-#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU)
-#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U)
-/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be
- * processed.
+
+#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU)
+#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U)
+/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed.
*/
-#define USBHSH_LASTPTD_ATL_LAST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)
-#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U)
-#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U)
+#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK)
+
+#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U)
+#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U)
/*! ISO_LAST - This indicates the last PTD in the ISO list.
*/
-#define USBHSH_LASTPTD_ISO_LAST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)
-#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U)
-#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U)
+#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK)
+
+#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U)
+#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U)
/*! INT_LAST - This indicates the last PTD in the INT list.
*/
-#define USBHSH_LASTPTD_INT_LAST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)
+#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK)
/*! @} */
/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
/*! @{ */
-#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
-#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device.
*/
-#define USBHSH_PORTMODE_DEV_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)
+#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)
/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware.
*/
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
-#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)
-#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
+
+#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)
/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b.
*/
-#define USBHSH_PORTMODE_SW_PDCOM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
+#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group USBHSH_Register_Masks */
+
/* USBHSH - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral USBHSH base address */
-#define USBHSH_BASE (0x500A3000u)
-/** Peripheral USBHSH base address */
-#define USBHSH_BASE_NS (0x400A3000u)
-/** Peripheral USBHSH base pointer */
-#define USBHSH ((USBHSH_Type *)USBHSH_BASE)
-/** Peripheral USBHSH base pointer */
-#define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS)
-/** Array initializer of USBHSH peripheral base addresses */
-#define USBHSH_BASE_ADDRS \
- { \
- USBHSH_BASE \
- }
-/** Array initializer of USBHSH peripheral base pointers */
-#define USBHSH_BASE_PTRS \
- { \
- USBHSH \
- }
-/** Array initializer of USBHSH peripheral base addresses */
-#define USBHSH_BASE_ADDRS_NS \
- { \
- USBHSH_BASE_NS \
- }
-/** Array initializer of USBHSH peripheral base pointers */
-#define USBHSH_BASE_PTRS_NS \
- { \
- USBHSH_NS \
- }
+ /** Peripheral USBHSH base address */
+ #define USBHSH_BASE (0x500A3000u)
+ /** Peripheral USBHSH base address */
+ #define USBHSH_BASE_NS (0x400A3000u)
+ /** Peripheral USBHSH base pointer */
+ #define USBHSH ((USBHSH_Type *)USBHSH_BASE)
+ /** Peripheral USBHSH base pointer */
+ #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS)
+ /** Array initializer of USBHSH peripheral base addresses */
+ #define USBHSH_BASE_ADDRS { USBHSH_BASE }
+ /** Array initializer of USBHSH peripheral base pointers */
+ #define USBHSH_BASE_PTRS { USBHSH }
+ /** Array initializer of USBHSH peripheral base addresses */
+ #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS }
+ /** Array initializer of USBHSH peripheral base pointers */
+ #define USBHSH_BASE_PTRS_NS { USBHSH_NS }
#else
-/** Peripheral USBHSH base address */
-#define USBHSH_BASE (0x400A3000u)
-/** Peripheral USBHSH base pointer */
-#define USBHSH ((USBHSH_Type *)USBHSH_BASE)
-/** Array initializer of USBHSH peripheral base addresses */
-#define USBHSH_BASE_ADDRS \
- { \
- USBHSH_BASE \
- }
-/** Array initializer of USBHSH peripheral base pointers */
-#define USBHSH_BASE_PTRS \
- { \
- USBHSH \
- }
+ /** Peripheral USBHSH base address */
+ #define USBHSH_BASE (0x400A3000u)
+ /** Peripheral USBHSH base pointer */
+ #define USBHSH ((USBHSH_Type *)USBHSH_BASE)
+ /** Array initializer of USBHSH peripheral base addresses */
+ #define USBHSH_BASE_ADDRS { USBHSH_BASE }
+ /** Array initializer of USBHSH peripheral base pointers */
+ #define USBHSH_BASE_PTRS { USBHSH }
#endif
/** Interrupt vectors for the USBHSH peripheral type */
-#define USBHSH_IRQS \
- { \
- USB1_IRQn \
- }
-#define USBHSH_NEEDCLK_IRQS \
- { \
- USB1_NEEDCLK_IRQn \
- }
+#define USBHSH_IRQS { USB1_IRQn }
+#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
/*!
* @}
*/ /* end of group USBHSH_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- USBPHY Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -28588,40 +28138,39 @@ typedef struct
*/
/** USBPHY - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
- __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
- __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
- __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
- __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
- __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
- __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
- __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
- __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
- __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
- __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
- __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
- __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
- __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
- __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
- __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
- __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
- uint8_t RESERVED_0[92];
- __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
- __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
- __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
- __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
- uint8_t RESERVED_1[16];
- __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
- __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
- __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
- __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
- uint8_t RESERVED_2[48];
- __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */
- __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
- __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
- __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
+typedef struct {
+ __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
+ __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
+ __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
+ __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
+ __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
+ __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
+ __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
+ __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
+ __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
+ __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
+ __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
+ __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
+ __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
+ __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
+ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
+ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
+ __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
+ uint8_t RESERVED_0[92];
+ __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
+ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
+ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
+ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
+ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
+ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
+ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
+ uint8_t RESERVED_2[48];
+ __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */
+ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
+ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
+ __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
} USBPHY_Type;
/* ----------------------------------------------------------------------------
@@ -28635,354 +28184,365 @@ typedef struct
/*! @name PWD - USB PHY Power-Down Register */
/*! @{ */
-#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
-#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
+
+#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
/*! TXPWDFS
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
*/
-#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
-#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
-#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
+#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
+
+#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
*/
-#define USBPHY_PWD_TXPWDIBIAS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
-#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
-#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
+#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
+
+#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
*/
-#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
-#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
-#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
+#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
+
+#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
/*! RXPWDENV
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
*/
-#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
-#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
-#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
+#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
+
+#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed differential receiver.
*/
-#define USBPHY_PWD_RXPWD1PT1(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
-#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
-#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
+#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
+
+#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed differential receive
*/
-#define USBPHY_PWD_RXPWDDIFF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
-#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
-#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
+#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
+
+#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
/*! RXPWDRX
* 0b0..Normal operation.
* 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
*/
-#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
+#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
/*! @} */
/*! @name PWD_SET - USB PHY Power-Down Register */
/*! @{ */
-#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
-#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
+
+#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
/*! TXPWDFS
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
*/
-#define USBPHY_PWD_SET_TXPWDFS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
-#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
-#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
+#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
+
+#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
*/
-#define USBPHY_PWD_SET_TXPWDIBIAS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
-#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
-#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
+#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
+
+#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
*/
-#define USBPHY_PWD_SET_TXPWDV2I(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
-#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
-#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
+#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
+
+#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
/*! RXPWDENV
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
*/
-#define USBPHY_PWD_SET_RXPWDENV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
-#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
-#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
+#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
+
+#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed differential receiver.
*/
-#define USBPHY_PWD_SET_RXPWD1PT1(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
-#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
-#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
+#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
+
+#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed differential receive
*/
-#define USBPHY_PWD_SET_RXPWDDIFF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
-#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
-#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
+#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
+
+#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
/*! RXPWDRX
* 0b0..Normal operation.
* 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
*/
-#define USBPHY_PWD_SET_RXPWDRX(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
+#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
/*! @} */
/*! @name PWD_CLR - USB PHY Power-Down Register */
/*! @{ */
-#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
-#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
+
+#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
/*! TXPWDFS
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
*/
-#define USBPHY_PWD_CLR_TXPWDFS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
-#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
-#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
+#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
+
+#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
*/
-#define USBPHY_PWD_CLR_TXPWDIBIAS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
-#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
-#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
+#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
+
+#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
*/
-#define USBPHY_PWD_CLR_TXPWDV2I(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
-#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
-#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
+#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
+
+#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
/*! RXPWDENV
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
*/
-#define USBPHY_PWD_CLR_RXPWDENV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
-#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
-#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
+#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
+
+#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed differential receiver.
*/
-#define USBPHY_PWD_CLR_RXPWD1PT1(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
-#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
-#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
+#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
+
+#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed differential receive
*/
-#define USBPHY_PWD_CLR_RXPWDDIFF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
-#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
-#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
+#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
+
+#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
/*! RXPWDRX
* 0b0..Normal operation.
* 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
*/
-#define USBPHY_PWD_CLR_RXPWDRX(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
+#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
/*! @} */
/*! @name PWD_TOG - USB PHY Power-Down Register */
/*! @{ */
-#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
-#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
+
+#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
+#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
/*! TXPWDFS
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the
*/
-#define USBPHY_PWD_TOG_TXPWDFS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
-#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
-#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
+#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
+
+#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the
*/
-#define USBPHY_PWD_TOG_TXPWDIBIAS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
-#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
-#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
+#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
+
+#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
+#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
*/
-#define USBPHY_PWD_TOG_TXPWDV2I(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
-#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
-#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
+#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
+
+#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
+#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
/*! RXPWDENV
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
*/
-#define USBPHY_PWD_TOG_RXPWDENV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
-#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
-#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
+#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
+
+#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
+#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed differential receiver.
*/
-#define USBPHY_PWD_TOG_RXPWD1PT1(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
-#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
-#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
+#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
+
+#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
+#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed differential receive
*/
-#define USBPHY_PWD_TOG_RXPWDDIFF(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
-#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
-#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
+#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
+
+#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
+#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
/*! RXPWDRX
* 0b0..Normal operation.
* 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
*/
-#define USBPHY_PWD_TOG_RXPWDRX(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
+#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
/*! @} */
/*! @name TX - USB PHY Transmitter Control Register */
/*! @{ */
-#define USBPHY_TX_D_CAL_MASK (0xFU)
-#define USBPHY_TX_D_CAL_SHIFT (0U)
+
+#define USBPHY_TX_D_CAL_MASK (0xFU)
+#define USBPHY_TX_D_CAL_SHIFT (0U)
/*! D_CAL
* 0b0000..Maximum current, approximately 19% above nominal.
* 0b0111..Nominal
* 0b1111..Minimum current, approximately 19% below nominal.
*/
-#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
-#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
-#define USBPHY_TX_TXCAL45DM_SHIFT (8U)
-#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
-#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U)
-#define USBPHY_TX_TXENCAL45DN_SHIFT (13U)
-#define USBPHY_TX_TXENCAL45DN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK)
-#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
-#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
-#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
-#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U)
-#define USBPHY_TX_TXENCAL45DP_SHIFT (21U)
-#define USBPHY_TX_TXENCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK)
+#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
+
+#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
+
+#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_TXENCAL45DN_SHIFT (13U)
+#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK)
+
+#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
+
+#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_TXENCAL45DP_SHIFT (21U)
+#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK)
/*! @} */
/*! @name TX_SET - USB PHY Transmitter Control Register */
/*! @{ */
-#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
-#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
+
+#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
+#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
/*! D_CAL
* 0b0000..Maximum current, approximately 19% above nominal.
* 0b0111..Nominal
* 0b1111..Minimum current, approximately 19% below nominal.
*/
-#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
-#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
-#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
-#define USBPHY_TX_SET_TXCAL45DM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
-#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U)
-#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U)
-#define USBPHY_TX_SET_TXENCAL45DN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK)
-#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
-#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
-#define USBPHY_TX_SET_TXCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
-#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U)
-#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U)
-#define USBPHY_TX_SET_TXENCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK)
+#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
+
+#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
+
+#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U)
+#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK)
+
+#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
+
+#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U)
+#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK)
/*! @} */
/*! @name TX_CLR - USB PHY Transmitter Control Register */
/*! @{ */
-#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
-#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
+
+#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
+#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
/*! D_CAL
* 0b0000..Maximum current, approximately 19% above nominal.
* 0b0111..Nominal
* 0b1111..Minimum current, approximately 19% below nominal.
*/
-#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
-#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
-#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
-#define USBPHY_TX_CLR_TXCAL45DM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
-#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U)
-#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U)
-#define USBPHY_TX_CLR_TXENCAL45DN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK)
-#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
-#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
-#define USBPHY_TX_CLR_TXCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
-#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U)
-#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U)
-#define USBPHY_TX_CLR_TXENCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK)
+#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
+
+#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
+
+#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U)
+#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK)
+
+#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
+
+#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U)
+#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK)
/*! @} */
/*! @name TX_TOG - USB PHY Transmitter Control Register */
/*! @{ */
-#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
-#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
+
+#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
+#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
/*! D_CAL
* 0b0000..Maximum current, approximately 19% above nominal.
* 0b0111..Nominal
* 0b1111..Minimum current, approximately 19% below nominal.
*/
-#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
-#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
-#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
-#define USBPHY_TX_TOG_TXCAL45DM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
-#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U)
-#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U)
-#define USBPHY_TX_TOG_TXENCAL45DN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK)
-#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
-#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
-#define USBPHY_TX_TOG_TXCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
-#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U)
-#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U)
-#define USBPHY_TX_TOG_TXENCAL45DP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK)
+#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
+
+#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
+#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
+#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
+
+#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U)
+#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U)
+#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK)
+
+#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
+#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
+#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
+
+#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U)
+#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U)
+#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK)
/*! @} */
/*! @name RX - USB PHY Receiver Control Register */
/*! @{ */
-#define USBPHY_RX_ENVADJ_MASK (0x7U)
-#define USBPHY_RX_ENVADJ_SHIFT (0U)
+
+#define USBPHY_RX_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_ENVADJ_SHIFT (0U)
/*! ENVADJ
* 0b000..Trip-Level Voltage is 0.1000 V
* 0b001..Trip-Level Voltage is 0.1125 V
@@ -28993,9 +28553,10 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
-#define USBPHY_RX_DISCONADJ_MASK (0x70U)
-#define USBPHY_RX_DISCONADJ_SHIFT (4U)
+#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
+
+#define USBPHY_RX_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_DISCONADJ_SHIFT (4U)
/*! DISCONADJ
* 0b000..Trip-Level Voltage is 0.56875 V
* 0b001..Trip-Level Voltage is 0.55000 V
@@ -29006,20 +28567,22 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
-#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
-#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
+#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
+
+#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS
* 0b0..Normal operation.
* 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
*/
-#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
+#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
/*! @} */
/*! @name RX_SET - USB PHY Receiver Control Register */
/*! @{ */
-#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
-#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
+
+#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
/*! ENVADJ
* 0b000..Trip-Level Voltage is 0.1000 V
* 0b001..Trip-Level Voltage is 0.1125 V
@@ -29030,10 +28593,10 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_SET_ENVADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
-#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
-#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
+#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
+
+#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
/*! DISCONADJ
* 0b000..Trip-Level Voltage is 0.56875 V
* 0b001..Trip-Level Voltage is 0.55000 V
@@ -29044,22 +28607,22 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_SET_DISCONADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
-#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
-#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
+#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
+
+#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS
* 0b0..Normal operation.
* 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
*/
-#define USBPHY_RX_SET_RXDBYPASS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
+#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
/*! @} */
/*! @name RX_CLR - USB PHY Receiver Control Register */
/*! @{ */
-#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
-#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
+
+#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
/*! ENVADJ
* 0b000..Trip-Level Voltage is 0.1000 V
* 0b001..Trip-Level Voltage is 0.1125 V
@@ -29070,10 +28633,10 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_CLR_ENVADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
-#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
-#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
+#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
+
+#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
/*! DISCONADJ
* 0b000..Trip-Level Voltage is 0.56875 V
* 0b001..Trip-Level Voltage is 0.55000 V
@@ -29084,22 +28647,22 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_CLR_DISCONADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
-#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
-#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
+#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
+
+#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS
* 0b0..Normal operation.
* 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
*/
-#define USBPHY_RX_CLR_RXDBYPASS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
+#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
/*! @} */
/*! @name RX_TOG - USB PHY Receiver Control Register */
/*! @{ */
-#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
-#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
+
+#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
+#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
/*! ENVADJ
* 0b000..Trip-Level Voltage is 0.1000 V
* 0b001..Trip-Level Voltage is 0.1125 V
@@ -29110,10 +28673,10 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_TOG_ENVADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
-#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
-#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
+#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
+
+#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
+#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
/*! DISCONADJ
* 0b000..Trip-Level Voltage is 0.56875 V
* 0b001..Trip-Level Voltage is 0.55000 V
@@ -29124,505 +28687,494 @@ typedef struct
* 0b110..reserved
* 0b111..reserved
*/
-#define USBPHY_RX_TOG_DISCONADJ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
-#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
-#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
+#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
+
+#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
+#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS
* 0b0..Normal operation.
* 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
*/
-#define USBPHY_RX_TOG_RXDBYPASS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
+#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
/*! @} */
/*! @name CTRL - USB PHY General Control Register */
/*! @{ */
-#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
-#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
-#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
-#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
-#define USBPHY_CTRL_ENIRQHOSTDISCON(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
-#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
-#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
-#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
-#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
-#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
+
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
+
+#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
+#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
+#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
+
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
+
+#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
/*! ENDEVPLUGINDET
* 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
* 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
*/
-#define USBPHY_CTRL_ENDEVPLUGINDET(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
-#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
-#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
-#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
-#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
-#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
-#define USBPHY_CTRL_RESUMEIRQSTICKY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
-#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
-#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
-#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
-#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
-#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
-#define USBPHY_CTRL_RESUME_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
-#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
-#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
-#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
-#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
-#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
-#define USBPHY_CTRL_ENUTMILEVEL2(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
-#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
-#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
-#define USBPHY_CTRL_ENUTMILEVEL3(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
-#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
-#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
-#define USBPHY_CTRL_ENIRQWAKEUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
-#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
-#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
-#define USBPHY_CTRL_WAKEUP_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
-#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
-#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
-#define USBPHY_CTRL_AUTORESUME_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
-#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
-#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
-#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
-#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
-#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
-#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
-#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
-#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
-#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
-#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
-#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
-#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
-#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
-#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
-#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK)
-#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U)
-#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U)
-#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK)
-#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
-#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
-#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
-#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
-#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
-#define USBPHY_CTRL_UTMI_SUSPENDM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
-#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
-#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
-#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
-#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
-#define USBPHY_CTRL_SFTRST_SHIFT (31U)
-#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
+#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
+
+#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
+#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
+#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
+
+#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
+#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
+#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
+
+#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
+#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
+#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
+
+#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
+#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
+#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
+
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
+
+#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
+
+#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
+
+#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
+#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
+#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
+
+#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
+#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
+#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
+
+#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
+
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
+
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
+
+#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
+#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
+#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
+
+#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
+#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
+#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
+
+#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
+#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
+#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK)
+
+#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U)
+#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U)
+#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK)
+
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
+
+#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
+
+#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
+
+#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - USB PHY General Control Register */
/*! @{ */
-#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
+
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & \
- USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
-#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
-#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
-#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
+
+#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
+#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
+#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
+
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
-#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & \
- USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
-#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
-#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
+
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
/*! ENDEVPLUGINDET
* 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
* 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
*/
-#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
-#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
+
+#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
-#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & \
- USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
-#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
-#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
-#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
-#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
-#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
-#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
-#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
-#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
-#define USBPHY_CTRL_SET_RESUME_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
-#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
-#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
-#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
-#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
-#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
-#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
-#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
-#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
-#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
-#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
-#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
-#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
-#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
-#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
-#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
-#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
-#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
-#define USBPHY_CTRL_SET_AUTORESUME_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
-#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
-#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
-#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
-#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
-#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
-#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
-#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
-#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
+#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
+
+#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
+#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
+#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
+
+#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
+#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
+#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
+
+#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
+#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
+#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
+
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
+
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
+
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
+
+#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
+#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
+#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
+
+#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
+#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
+#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
+
+#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
+
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
+
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
+
+#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
+#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
+#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
+
+#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
+#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
+#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
+
#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & \
- USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK)
-#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U)
-#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U)
-#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK)
-#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
-#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
-#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
-#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
-#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
-#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
-#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
-#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
-#define USBPHY_CTRL_SET_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
-#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
-#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
-#define USBPHY_CTRL_SET_SFTRST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK)
+
+#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U)
+#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U)
+#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK)
+
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
+
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
+
+#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
+
+#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - USB PHY General Control Register */
/*! @{ */
-#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
+
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & \
- USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
-#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
-#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
-#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
+
+#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
+#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
+#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
+
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
-#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & \
- USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
-#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
-#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
+
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
/*! ENDEVPLUGINDET
* 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
* 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
*/
-#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
-#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
+
+#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
-#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & \
- USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
-#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
-#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
-#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
-#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
-#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
-#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
-#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
-#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
-#define USBPHY_CTRL_CLR_RESUME_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
-#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
-#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
-#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
-#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
-#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
-#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
-#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
-#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
-#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
-#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
-#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
-#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
-#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
-#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
-#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
-#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
-#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
-#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
+
+#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
+#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
+#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
+
+#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
+#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
+#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
+
+#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
+#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
+#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
+
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
+
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
+
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
+
+#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
+#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
+#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
+
+#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
+#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
+#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
+
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
+
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
+
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
+
+#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
+#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
+#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
+
+#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
+#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
+#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
+
#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & \
- USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK)
-#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U)
-#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U)
-#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK)
-#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
-#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
-#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
-#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
-#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
-#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
-#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
-#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
-#define USBPHY_CTRL_CLR_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
-#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
-#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
-#define USBPHY_CTRL_CLR_SFTRST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK)
+
+#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U)
+#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U)
+#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK)
+
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
+
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
+
+#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
+
+#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - USB PHY General Control Register */
/*! @{ */
-#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
+
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & \
- USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
-#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
-#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
-#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
+
+#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
+#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
+#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
+
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
-#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & \
- USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
-#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
-#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
+
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
/*! ENDEVPLUGINDET
* 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
* 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
*/
-#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
-#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
+
+#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
-#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & \
- USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
-#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
-#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
-#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
-#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
-#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
-#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
-#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
-#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
-#define USBPHY_CTRL_TOG_RESUME_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
-#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
-#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
-#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
-#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
-#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
-#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
-#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
-#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
-#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
-#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
-#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
-#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
-#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
-#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
-#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
-#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
-#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
-#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
+
+#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
+#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
+#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
+
+#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
+#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
+#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
+
+#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
+#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
+#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
+
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
+
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
+
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
+
+#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
+#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
+#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
+
+#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
+#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
+#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
+
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
+
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
+
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
+
+#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
+#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
+#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
+
+#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
+#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
+#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
+
#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & \
- USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK)
-#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U)
-#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U)
-#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK)
-#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
-#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
-#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
-#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
-#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
-#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
-#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
-#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
-#define USBPHY_CTRL_TOG_CLKGATE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
-#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
-#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
-#define USBPHY_CTRL_TOG_SFTRST(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK)
+
+#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U)
+#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U)
+#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK)
+
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
+
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
+
+#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
+#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
+#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
+
+#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
+#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
+#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name STATUS - USB PHY Status Register */
/*! @{ */
-#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U)
-#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U)
-#define USBPHY_STATUS_OK_STATUS_3V(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK)
+
+#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U)
+#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U)
+#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK)
+
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
/*! HOSTDISCONDETECT_STATUS
* 0b0..USB cable disconnect has not been detected at the local host
* 0b1..USB cable disconnect has been detected at the local host
*/
-#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & \
- USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
-#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
-#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
+
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
/*! DEVPLUGIN_STATUS
* 0b0..No attachment to a USB host is detected
* 0b1..Cable attachment to a USB host is detected
*/
-#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
-#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
-#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
-#define USBPHY_STATUS_RESUME_STATUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
+
+#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
+#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
+#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
/*! @} */
/*! @name PLL_SIC - USB PHY PLL Control/Status Register */
/*! @{ */
-#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
-#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
-#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
-#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
-#define USBPHY_PLL_SIC_PLL_POWER(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
-#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
-#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
-#define USBPHY_PLL_SIC_PLL_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
-#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U)
-#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U)
+
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
+
+#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
+
+#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL
* 0b0..Selects PLL_POWER to control the reference bias
* 0b1..Selects REFBIAS_PWD to control the reference bias
*/
-#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
-#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U)
-#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U)
-#define USBPHY_PLL_SIC_REFBIAS_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
-#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U)
-#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U)
-#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
-#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U)
-#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
+
+#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U)
+#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
+
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U)
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL
* 0b000..Divide by 13
* 0b001..Divide by 15
@@ -29633,56 +29185,54 @@ typedef struct
* 0b110..Divide by 30
* 0b111..Divide by 240
*/
-#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
-#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U)
-#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U)
-#define USBPHY_PLL_SIC_PLL_PREDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK)
-#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
-#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
+
+#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U)
+#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U)
+#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK)
+
+#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK
* 0b0..PLL is not currently locked
* 0b1..PLL is currently locked
*/
-#define USBPHY_PLL_SIC_PLL_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
/*! @} */
/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
/*! @{ */
-#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
+
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & \
- USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
-#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
-#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
-#define USBPHY_PLL_SIC_SET_PLL_POWER(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
-#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
-#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
-#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
-#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
+
+#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
+
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL
* 0b0..Selects PLL_POWER to control the reference bias
* 0b1..Selects REFBIAS_PWD to control the reference bias
*/
-#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & \
- USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
-#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U)
-#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U)
-#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
-#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U)
-#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U)
-#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
-#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U)
-#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
+
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U)
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
+
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U)
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL
* 0b000..Divide by 13
* 0b001..Divide by 15
@@ -29693,56 +29243,54 @@ typedef struct
* 0b110..Divide by 30
* 0b111..Divide by 240
*/
-#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
-#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U)
-#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U)
-#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK)
-#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
-#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
+
+#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U)
+#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U)
+#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK)
+
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK
* 0b0..PLL is not currently locked
* 0b1..PLL is currently locked
*/
-#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
/*! @} */
/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
/*! @{ */
-#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
+
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & \
- USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
-#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
-#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
-#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
-#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
-#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
-#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
-#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
+
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
+
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL
* 0b0..Selects PLL_POWER to control the reference bias
* 0b1..Selects REFBIAS_PWD to control the reference bias
*/
-#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & \
- USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
-#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U)
-#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U)
-#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
-#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U)
-#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U)
-#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
-#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U)
-#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
+
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U)
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
+
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U)
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL
* 0b000..Divide by 13
* 0b001..Divide by 15
@@ -29753,56 +29301,54 @@ typedef struct
* 0b110..Divide by 30
* 0b111..Divide by 240
*/
-#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
-#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U)
-#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U)
-#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK)
-#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
-#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
+
+#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U)
+#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U)
+#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK)
+
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK
* 0b0..PLL is not currently locked
* 0b1..PLL is currently locked
*/
-#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
/*! @} */
/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
/*! @{ */
-#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
+
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & \
- USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
-#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
-#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
-#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
-#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
-#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
-#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
-#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
+
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
+
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL
* 0b0..Selects PLL_POWER to control the reference bias
* 0b1..Selects REFBIAS_PWD to control the reference bias
*/
-#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & \
- USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
-#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U)
-#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U)
-#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
-#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U)
-#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U)
-#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
-#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U)
-#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
+
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U)
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
+
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U)
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U)
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
+
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL
* 0b000..Divide by 13
* 0b001..Divide by 15
@@ -29813,24 +29359,24 @@ typedef struct
* 0b110..Divide by 30
* 0b111..Divide by 240
*/
-#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
-#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U)
-#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U)
-#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK)
-#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
-#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
+
+#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U)
+#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U)
+#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK)
+
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK
* 0b0..PLL is not currently locked
* 0b1..PLL is currently locked
*/
-#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
/*! @{ */
+
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH
@@ -29843,47 +29389,40 @@ typedef struct
* 0b110..4.6V
* 0b111..4.7V
*/
-#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN
- * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and
- * SESSEND (Default) 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
*/
-#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
-#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
-#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
-#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
-#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL
* 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
* 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
*/
-#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL
@@ -29892,73 +29431,64 @@ typedef struct
* 0b10..Use the Session Valid comparator results for signal reported to the USB controller
* 0b11..Reserved, do not use
*/
-#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
-#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
-#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U)
/*! EXT_ID_OVERRIDE_EN
* 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN.
* 0b1..Select the external ID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
/*! EXT_VBUS_OVERRIDE_EN
* 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN.
* 0b1..Select the external VBUS VALID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID
* 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
* 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
*/
-#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U)
-#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK)
-#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK)
+
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS
* 0b000..Powers down the VBUS_VALID comparator
* 0b111..Enables the VBUS_VALID comparator (default)
*/
-#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS
* 0b0..VBUS discharge resistor is disabled (Default)
* 0b1..VBUS discharge resistor is enabled
*/
-#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
/*! @{ */
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH
@@ -29971,47 +29501,40 @@ typedef struct
* 0b110..4.6V
* 0b111..4.7V
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN
- * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and
- * SESSEND (Default) 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
-#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
-#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
-#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL
* 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
* 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL
@@ -30020,73 +29543,64 @@ typedef struct
* 0b10..Use the Session Valid comparator results for signal reported to the USB controller
* 0b11..Reserved, do not use
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
-#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
-#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U)
/*! EXT_ID_OVERRIDE_EN
* 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN.
* 0b1..Select the external ID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
/*! EXT_VBUS_OVERRIDE_EN
* 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN.
* 0b1..Select the external VBUS VALID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID
* 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
* 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U)
-#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS
* 0b000..Powers down the VBUS_VALID comparator
* 0b111..Enables the VBUS_VALID comparator (default)
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS
* 0b0..VBUS discharge resistor is disabled (Default)
* 0b1..VBUS discharge resistor is enabled
*/
-#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
/*! @{ */
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH
@@ -30099,47 +29613,40 @@ typedef struct
* 0b110..4.6V
* 0b111..4.7V
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN
- * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and
- * SESSEND (Default) 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL
* 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
* 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL
@@ -30148,73 +29655,64 @@ typedef struct
* 0b10..Use the Session Valid comparator results for signal reported to the USB controller
* 0b11..Reserved, do not use
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U)
/*! EXT_ID_OVERRIDE_EN
* 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN.
* 0b1..Select the external ID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
/*! EXT_VBUS_OVERRIDE_EN
* 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN.
* 0b1..Select the external VBUS VALID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID
* 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
* 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U)
-#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS
* 0b000..Powers down the VBUS_VALID comparator
* 0b111..Enables the VBUS_VALID comparator (default)
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS
* 0b0..VBUS discharge resistor is disabled (Default)
* 0b1..VBUS discharge resistor is enabled
*/
-#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
/*! @{ */
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH
@@ -30227,47 +29725,40 @@ typedef struct
* 0b110..4.6V
* 0b111..4.7V
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN
- * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and
- * SESSEND (Default) 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL
* 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
* 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL
@@ -30276,211 +29767,183 @@ typedef struct
* 0b10..Use the Session Valid comparator results for signal reported to the USB controller
* 0b11..Reserved, do not use
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U)
/*! EXT_ID_OVERRIDE_EN
* 0b0..Select the muxed value chosen using ID_OVERRIDE_EN.
* 0b1..Select the external ID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U)
/*! EXT_VBUS_OVERRIDE_EN
* 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN.
* 0b1..Select the external VBUS VALID value.
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID
* 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
* 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U)
-#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS
* 0b000..Powers down the VBUS_VALID comparator
* 0b111..Enables the VBUS_VALID comparator (default)
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
+
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS
* 0b0..VBUS discharge resistor is disabled (Default)
* 0b1..VBUS discharge resistor is enabled
*/
-#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & \
- USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
/*! @} */
/*! @name ANACTRL - USB PHY Analog Control Register */
/*! @{ */
-#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U)
-#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U)
-#define USBPHY_ANACTRL_LVI_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK)
-#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
-#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
-#define USBPHY_ANACTRL_PFD_CLK_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
-#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
-#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
+
+#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U)
+#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U)
+#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK)
+
+#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
+#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
+
+#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN
* 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
* 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
*/
-#define USBPHY_ANACTRL_DEV_PULLDOWN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name ANACTRL_SET - USB PHY Analog Control Register */
/*! @{ */
-#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U)
-#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U)
-#define USBPHY_ANACTRL_SET_LVI_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK)
-#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
-#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
-#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
-#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
-#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
+
+#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U)
+#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U)
+#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK)
+
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
+
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN
* 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
* 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
*/
-#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name ANACTRL_CLR - USB PHY Analog Control Register */
/*! @{ */
-#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U)
-#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U)
-#define USBPHY_ANACTRL_CLR_LVI_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK)
-#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
-#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
-#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
-#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
-#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
+
+#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U)
+#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U)
+#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK)
+
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
+
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN
* 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
* 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
*/
-#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name ANACTRL_TOG - USB PHY Analog Control Register */
/*! @{ */
-#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U)
-#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U)
-#define USBPHY_ANACTRL_TOG_LVI_EN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK)
-#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
-#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
-#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
-#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
-#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
+
+#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U)
+#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U)
+#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK)
+
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
+
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN
* 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
* 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
*/
-#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) \
- (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group USBPHY_Register_Masks */
+
/* USBPHY - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral USBPHY base address */
-#define USBPHY_BASE (0x50038000u)
-/** Peripheral USBPHY base address */
-#define USBPHY_BASE_NS (0x40038000u)
-/** Peripheral USBPHY base pointer */
-#define USBPHY ((USBPHY_Type *)USBPHY_BASE)
-/** Peripheral USBPHY base pointer */
-#define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS)
-/** Array initializer of USBPHY peripheral base addresses */
-#define USBPHY_BASE_ADDRS \
- { \
- USBPHY_BASE \
- }
-/** Array initializer of USBPHY peripheral base pointers */
-#define USBPHY_BASE_PTRS \
- { \
- USBPHY \
- }
-/** Array initializer of USBPHY peripheral base addresses */
-#define USBPHY_BASE_ADDRS_NS \
- { \
- USBPHY_BASE_NS \
- }
-/** Array initializer of USBPHY peripheral base pointers */
-#define USBPHY_BASE_PTRS_NS \
- { \
- USBPHY_NS \
- }
+ /** Peripheral USBPHY base address */
+ #define USBPHY_BASE (0x50038000u)
+ /** Peripheral USBPHY base address */
+ #define USBPHY_BASE_NS (0x40038000u)
+ /** Peripheral USBPHY base pointer */
+ #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
+ /** Peripheral USBPHY base pointer */
+ #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS)
+ /** Array initializer of USBPHY peripheral base addresses */
+ #define USBPHY_BASE_ADDRS { USBPHY_BASE }
+ /** Array initializer of USBPHY peripheral base pointers */
+ #define USBPHY_BASE_PTRS { USBPHY }
+ /** Array initializer of USBPHY peripheral base addresses */
+ #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS }
+ /** Array initializer of USBPHY peripheral base pointers */
+ #define USBPHY_BASE_PTRS_NS { USBPHY_NS }
#else
-/** Peripheral USBPHY base address */
-#define USBPHY_BASE (0x40038000u)
-/** Peripheral USBPHY base pointer */
-#define USBPHY ((USBPHY_Type *)USBPHY_BASE)
-/** Array initializer of USBPHY peripheral base addresses */
-#define USBPHY_BASE_ADDRS \
- { \
- USBPHY_BASE \
- }
-/** Array initializer of USBPHY peripheral base pointers */
-#define USBPHY_BASE_PTRS \
- { \
- USBPHY \
- }
+ /** Peripheral USBPHY base address */
+ #define USBPHY_BASE (0x40038000u)
+ /** Peripheral USBPHY base pointer */
+ #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
+ /** Array initializer of USBPHY peripheral base addresses */
+ #define USBPHY_BASE_ADDRS { USBPHY_BASE }
+ /** Array initializer of USBPHY peripheral base pointers */
+ #define USBPHY_BASE_PTRS { USBPHY }
#endif
/** Interrupt vectors for the USBPHY peripheral type */
-#define USBPHY_IRQS \
- { \
- USB1_PHY_IRQn \
- }
+#define USBPHY_IRQS { USB1_PHY_IRQn }
/*!
* @}
*/ /* end of group USBPHY_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- UTICK Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -30491,13 +29954,12 @@ typedef struct
*/
/** UTICK - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
- __IO uint32_t STAT; /**< Status register., offset: 0x4 */
- __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
- __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
- __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
+ __IO uint32_t STAT; /**< Status register., offset: 0x4 */
+ __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
+ __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
+ __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
} UTICK_Type;
/* ----------------------------------------------------------------------------
@@ -30511,185 +29973,181 @@ typedef struct
/*! @name CTRL - Control register. */
/*! @{ */
-#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
-#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
+
+#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer
* clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer.
*/
-#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
-#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
-#define UTICK_CTRL_REPEAT_SHIFT (31U)
+#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+
+#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT (31U)
/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously.
*/
-#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
/*! @} */
/*! @name STAT - Status register. */
/*! @{ */
-#define UTICK_STAT_INTR_MASK (0x1U)
-#define UTICK_STAT_INTR_SHIFT (0U)
+
+#define UTICK_STAT_INTR_MASK (0x1U)
+#define UTICK_STAT_INTR_SHIFT (0U)
/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any
* value to this register clears this flag.
*/
-#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
-#define UTICK_STAT_ACTIVE_MASK (0x2U)
-#define UTICK_STAT_ACTIVE_SHIFT (1U)
+#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+
+#define UTICK_STAT_ACTIVE_MASK (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT (1U)
/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active.
*/
-#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
/*! @} */
/*! @name CFG - Capture configuration register. */
/*! @{ */
-#define UTICK_CFG_CAPEN0_MASK (0x1U)
-#define UTICK_CFG_CAPEN0_SHIFT (0U)
+
+#define UTICK_CFG_CAPEN0_MASK (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT (0U)
/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled.
*/
-#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
-#define UTICK_CFG_CAPEN1_MASK (0x2U)
-#define UTICK_CFG_CAPEN1_SHIFT (1U)
+#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+
+#define UTICK_CFG_CAPEN1_MASK (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT (1U)
/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled.
*/
-#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
-#define UTICK_CFG_CAPEN2_MASK (0x4U)
-#define UTICK_CFG_CAPEN2_SHIFT (2U)
+#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+
+#define UTICK_CFG_CAPEN2_MASK (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT (2U)
/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled.
*/
-#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
-#define UTICK_CFG_CAPEN3_MASK (0x8U)
-#define UTICK_CFG_CAPEN3_SHIFT (3U)
+#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+
+#define UTICK_CFG_CAPEN3_MASK (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT (3U)
/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled.
*/
-#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
-#define UTICK_CFG_CAPPOL0_MASK (0x100U)
-#define UTICK_CFG_CAPPOL0_SHIFT (8U)
+#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+
+#define UTICK_CFG_CAPPOL0_MASK (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT (8U)
/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture.
*/
-#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
-#define UTICK_CFG_CAPPOL1_MASK (0x200U)
-#define UTICK_CFG_CAPPOL1_SHIFT (9U)
+#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+
+#define UTICK_CFG_CAPPOL1_MASK (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT (9U)
/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture.
*/
-#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
-#define UTICK_CFG_CAPPOL2_MASK (0x400U)
-#define UTICK_CFG_CAPPOL2_SHIFT (10U)
+#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+
+#define UTICK_CFG_CAPPOL2_MASK (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT (10U)
/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture.
*/
-#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
-#define UTICK_CFG_CAPPOL3_MASK (0x800U)
-#define UTICK_CFG_CAPPOL3_SHIFT (11U)
+#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+
+#define UTICK_CFG_CAPPOL3_MASK (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT (11U)
/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture.
*/
-#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
/*! @} */
/*! @name CAPCLR - Capture clear register. */
/*! @{ */
-#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
-#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
+
+#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value.
*/
-#define UTICK_CAPCLR_CAPCLR0(x) \
- (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
-#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
-#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
+#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+
+#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value.
*/
-#define UTICK_CAPCLR_CAPCLR1(x) \
- (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
-#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
-#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
+#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+
+#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value.
*/
-#define UTICK_CAPCLR_CAPCLR2(x) \
- (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
-#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
-#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
+#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+
+#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value.
*/
-#define UTICK_CAPCLR_CAPCLR3(x) \
- (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
/*! @} */
/*! @name CAP - Capture register . */
/*! @{ */
-#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
-#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
+
+#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower
* than the actual value of the Micro-tick Timer at the moment of the capture event.
*/
-#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
-#define UTICK_CAP_VALID_MASK (0x80000000U)
-#define UTICK_CAP_VALID_SHIFT (31U)
+#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+
+#define UTICK_CAP_VALID_MASK (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT (31U)
/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related
* UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register.
*/
-#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
/*! @} */
/* The count of UTICK_CAP */
-#define UTICK_CAP_COUNT (4U)
+#define UTICK_CAP_COUNT (4U)
+
/*!
* @}
*/ /* end of group UTICK_Register_Masks */
+
/* UTICK - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral UTICK0 base address */
-#define UTICK0_BASE (0x5000E000u)
-/** Peripheral UTICK0 base address */
-#define UTICK0_BASE_NS (0x4000E000u)
-/** Peripheral UTICK0 base pointer */
-#define UTICK0 ((UTICK_Type *)UTICK0_BASE)
-/** Peripheral UTICK0 base pointer */
-#define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS)
-/** Array initializer of UTICK peripheral base addresses */
-#define UTICK_BASE_ADDRS \
- { \
- UTICK0_BASE \
- }
-/** Array initializer of UTICK peripheral base pointers */
-#define UTICK_BASE_PTRS \
- { \
- UTICK0 \
- }
-/** Array initializer of UTICK peripheral base addresses */
-#define UTICK_BASE_ADDRS_NS \
- { \
- UTICK0_BASE_NS \
- }
-/** Array initializer of UTICK peripheral base pointers */
-#define UTICK_BASE_PTRS_NS \
- { \
- UTICK0_NS \
- }
+ /** Peripheral UTICK0 base address */
+ #define UTICK0_BASE (0x5000E000u)
+ /** Peripheral UTICK0 base address */
+ #define UTICK0_BASE_NS (0x4000E000u)
+ /** Peripheral UTICK0 base pointer */
+ #define UTICK0 ((UTICK_Type *)UTICK0_BASE)
+ /** Peripheral UTICK0 base pointer */
+ #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS)
+ /** Array initializer of UTICK peripheral base addresses */
+ #define UTICK_BASE_ADDRS { UTICK0_BASE }
+ /** Array initializer of UTICK peripheral base pointers */
+ #define UTICK_BASE_PTRS { UTICK0 }
+ /** Array initializer of UTICK peripheral base addresses */
+ #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS }
+ /** Array initializer of UTICK peripheral base pointers */
+ #define UTICK_BASE_PTRS_NS { UTICK0_NS }
#else
-/** Peripheral UTICK0 base address */
-#define UTICK0_BASE (0x4000E000u)
-/** Peripheral UTICK0 base pointer */
-#define UTICK0 ((UTICK_Type *)UTICK0_BASE)
-/** Array initializer of UTICK peripheral base addresses */
-#define UTICK_BASE_ADDRS \
- { \
- UTICK0_BASE \
- }
-/** Array initializer of UTICK peripheral base pointers */
-#define UTICK_BASE_PTRS \
- { \
- UTICK0 \
- }
+ /** Peripheral UTICK0 base address */
+ #define UTICK0_BASE (0x4000E000u)
+ /** Peripheral UTICK0 base pointer */
+ #define UTICK0 ((UTICK_Type *)UTICK0_BASE)
+ /** Array initializer of UTICK peripheral base addresses */
+ #define UTICK_BASE_ADDRS { UTICK0_BASE }
+ /** Array initializer of UTICK peripheral base pointers */
+ #define UTICK_BASE_PTRS { UTICK0 }
#endif
/** Interrupt vectors for the UTICK peripheral type */
-#define UTICK_IRQS \
- { \
- UTICK0_IRQn \
- }
+#define UTICK_IRQS { UTICK0_IRQn }
/*!
* @}
*/ /* end of group UTICK_Peripheral_Access_Layer */
+
/* ----------------------------------------------------------------------------
-- WWDT Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -30700,19 +30158,14 @@ typedef struct
*/
/** WWDT - Register Layout Typedef */
-typedef struct
-{
- __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog
- Timer., offset: 0x0 */
- __IO uint32_t
- TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
- __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the
- Watchdog timer with the value contained in TC., offset: 0x8 */
- __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the
- Watchdog timer., offset: 0xC */
- uint8_t RESERVED_0[4];
- __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
- __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
+typedef struct {
+ __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+ __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+ __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+ __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+ __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
} WWDT_Type;
/* ----------------------------------------------------------------------------
@@ -30726,175 +30179,165 @@ typedef struct
/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
/*! @{ */
-#define WWDT_MOD_WDEN_MASK (0x1U)
-#define WWDT_MOD_WDEN_SHIFT (0U)
+
+#define WWDT_MOD_WDEN_MASK (0x1U)
+#define WWDT_MOD_WDEN_SHIFT (0U)
/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the
* watchdog timer will run permanently.
* 0b0..Stop. The watchdog timer is stopped.
* 0b1..Run. The watchdog timer is running.
*/
-#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
-#define WWDT_MOD_WDRESET_MASK (0x2U)
-#define WWDT_MOD_WDRESET_SHIFT (1U)
+#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+
+#define WWDT_MOD_WDRESET_MASK (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT (1U)
/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.
* 0b0..Interrupt. A watchdog time-out will not cause a chip reset.
* 0b1..Reset. A watchdog time-out will cause a chip reset.
*/
-#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
-#define WWDT_MOD_WDTOF_MASK (0x4U)
-#define WWDT_MOD_WDTOF_SHIFT (2U)
+#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+
+#define WWDT_MOD_WDTOF_MASK (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT (2U)
/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by
* events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a
* chip reset if WDRESET = 1.
*/
-#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
-#define WWDT_MOD_WDINT_MASK (0x8U)
-#define WWDT_MOD_WDINT_SHIFT (3U)
+#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+
+#define WWDT_MOD_WDINT_MASK (0x8U)
+#define WWDT_MOD_WDINT_SHIFT (3U)
/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT.
* Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the
* WARNINT value is equal to the value of the TV register. This can occur if the value of
* WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0.
*/
-#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
-#define WWDT_MOD_WDPROTECT_MASK (0x10U)
-#define WWDT_MOD_WDPROTECT_SHIFT (4U)
+#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+
+#define WWDT_MOD_WDPROTECT_MASK (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT (4U)
/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
* 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.
- * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of
- * WDWARNINT and WDWINDOW.
+ * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.
*/
-#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
/*! @} */
/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
/*! @{ */
-#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
-#define WWDT_TC_COUNT_SHIFT (0U)
+
+#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT (0U)
/*! COUNT - Watchdog time-out value.
*/
-#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
/*! @} */
-/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog
- * timer with the value contained in TC. */
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
/*! @{ */
-#define WWDT_FEED_FEED_MASK (0xFFU)
-#define WWDT_FEED_FEED_SHIFT (0U)
+
+#define WWDT_FEED_FEED_MASK (0xFFU)
+#define WWDT_FEED_FEED_SHIFT (0U)
/*! FEED - Feed value should be 0xAA followed by 0x55.
*/
-#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
/*! @} */
/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
/*! @{ */
-#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
-#define WWDT_TV_COUNT_SHIFT (0U)
+
+#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT (0U)
/*! COUNT - Counter timer value.
*/
-#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
/*! @} */
/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
/*! @{ */
-#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
-#define WWDT_WARNINT_WARNINT_SHIFT (0U)
+
+#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT (0U)
/*! WARNINT - Watchdog warning interrupt compare value.
*/
-#define WWDT_WARNINT_WARNINT(x) \
- (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
/*! @} */
/*! @name WINDOW - Watchdog Window compare value. */
/*! @{ */
-#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
-#define WWDT_WINDOW_WINDOW_SHIFT (0U)
+
+#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT (0U)
/*! WINDOW - Watchdog window value.
*/
-#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
/*! @} */
+
/*!
* @}
*/ /* end of group WWDT_Register_Masks */
+
/* WWDT - Peripheral instance base addresses */
#if (__ARM_FEATURE_CMSE & 0x2)
-/** Peripheral WWDT base address */
-#define WWDT_BASE (0x5000C000u)
-/** Peripheral WWDT base address */
-#define WWDT_BASE_NS (0x4000C000u)
-/** Peripheral WWDT base pointer */
-#define WWDT ((WWDT_Type *)WWDT_BASE)
-/** Peripheral WWDT base pointer */
-#define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS)
-/** Array initializer of WWDT peripheral base addresses */
-#define WWDT_BASE_ADDRS \
- { \
- WWDT_BASE \
- }
-/** Array initializer of WWDT peripheral base pointers */
-#define WWDT_BASE_PTRS \
- { \
- WWDT \
- }
-/** Array initializer of WWDT peripheral base addresses */
-#define WWDT_BASE_ADDRS_NS \
- { \
- WWDT_BASE_NS \
- }
-/** Array initializer of WWDT peripheral base pointers */
-#define WWDT_BASE_PTRS_NS \
- { \
- WWDT_NS \
- }
+ /** Peripheral WWDT base address */
+ #define WWDT_BASE (0x5000C000u)
+ /** Peripheral WWDT base address */
+ #define WWDT_BASE_NS (0x4000C000u)
+ /** Peripheral WWDT base pointer */
+ #define WWDT ((WWDT_Type *)WWDT_BASE)
+ /** Peripheral WWDT base pointer */
+ #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS)
+ /** Array initializer of WWDT peripheral base addresses */
+ #define WWDT_BASE_ADDRS { WWDT_BASE }
+ /** Array initializer of WWDT peripheral base pointers */
+ #define WWDT_BASE_PTRS { WWDT }
+ /** Array initializer of WWDT peripheral base addresses */
+ #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS }
+ /** Array initializer of WWDT peripheral base pointers */
+ #define WWDT_BASE_PTRS_NS { WWDT_NS }
#else
-/** Peripheral WWDT base address */
-#define WWDT_BASE (0x4000C000u)
-/** Peripheral WWDT base pointer */
-#define WWDT ((WWDT_Type *)WWDT_BASE)
-/** Array initializer of WWDT peripheral base addresses */
-#define WWDT_BASE_ADDRS \
- { \
- WWDT_BASE \
- }
-/** Array initializer of WWDT peripheral base pointers */
-#define WWDT_BASE_PTRS \
- { \
- WWDT \
- }
+ /** Peripheral WWDT base address */
+ #define WWDT_BASE (0x4000C000u)
+ /** Peripheral WWDT base pointer */
+ #define WWDT ((WWDT_Type *)WWDT_BASE)
+ /** Array initializer of WWDT peripheral base addresses */
+ #define WWDT_BASE_ADDRS { WWDT_BASE }
+ /** Array initializer of WWDT peripheral base pointers */
+ #define WWDT_BASE_PTRS { WWDT }
#endif
/** Interrupt vectors for the WWDT peripheral type */
-#define WWDT_IRQS \
- { \
- WDT_BOD_IRQn \
- }
+#define WWDT_IRQS { WDT_BOD_IRQn }
/*!
* @}
*/ /* end of group WWDT_Peripheral_Access_Layer */
+
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
-#if (__ARMCC_VERSION >= 6010050)
-#pragma clang diagnostic pop
-#else
-#pragma pop
-#endif
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #else
+ #pragma pop
+ #endif
#elif defined(__GNUC__)
-/* leave anonymous unions enabled */
+ /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
-#pragma language = default
+ #pragma language=default
#else
-#error Not supported compiler type
+ #error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
+
/* ----------------------------------------------------------------------------
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
---------------------------------------------------------------------------- */
@@ -30905,11 +30348,11 @@ typedef struct
*/
#if defined(__ARMCC_VERSION)
-#if (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header
-#endif
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
#elif defined(__IAR_SYSTEMS_ICC__)
-#pragma system_include
+ #pragma system_include
#endif
/**
@@ -30918,19 +30361,20 @@ typedef struct
* @param value Value of the bit field.
* @return Masked and shifted value.
*/
-#define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK))
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
* @brief Mask and right-shift a register value to extract a bit field value.
* @param field Name of the register bit field.
* @param value Value of the register.
* @return Masked and shifted bit field value.
*/
-#define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT))
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
/*!
* @}
*/ /* end of group Bit_Field_Generic_Macros */
+
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
@@ -30941,7 +30385,7 @@ typedef struct
*/
/** High Speed SPI (Flexcomm 8) interrupt name */
-#define LSPI_HS_IRQn FLEXCOMM8_IRQn
+#define LSPI_HS_IRQn FLEXCOMM8_IRQn
/*!
* @brief Get the chip value.
@@ -30954,11 +30398,11 @@ static inline uint32_t Chip_GetVersion(void)
deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK;
- if (0UL == deviceRevision) /* A0 device revision is 0 */
+ if(0UL == deviceRevision) /* A0 device revision is 0 */
{
return 0x0;
}
- else if (1UL == deviceRevision) /* A1 device revision is 1 */
+ else if(1UL == deviceRevision) /* A1 device revision is 1 */
{
return 0x1;
}
@@ -30968,8 +30412,11 @@ static inline uint32_t Chip_GetVersion(void)
}
}
+
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
-#endif /* _LPC55S69_CM33_CORE0_H_ */
+
+#endif /* _LPC55S69_CM33_CORE0_H_ */
+
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
index 5380e9f41..2ea266b99 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/LPC55S69_cm33_core0_features.h
@@ -1,13 +1,13 @@
/*
** ###################################################################
** Version: rev. 1.1, 2019-05-16
-** Build: b190719
+** Build: b210318
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2019 NXP
+** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -75,7 +75,7 @@
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
/* @brief PUF availability on the SoC. */
#define FSL_FEATURE_SOC_PUF_COUNT (1)
-/* @brief RNG1 availability on the SoC. */
+/* @brief LPC_RNG1 availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -146,16 +146,22 @@
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
/* @brief Temperature sensor parameter Alpha. */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
+/* @brief the buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
/* CASPER module features */
/* @brief Base address of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
-/* @brief Interleaving of the CASPER dedicated RAM */
+/* @brief SW interleaving of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
/* @brief CASPER dedicated RAM offset */
#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
+/* CTIMER module features */
+
+/* No feature definitions */
+
/* DMA module features */
/* @brief Number of channels */
@@ -168,71 +174,71 @@
/* FLEXCOMM module features */
/* @brief FLEXCOMM0 USART INDEX 0 */
-#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
/* @brief FLEXCOMM0 SPI INDEX 0 */
-#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
/* @brief FLEXCOMM0 I2C INDEX 0 */
-#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
/* @brief FLEXCOMM0 I2S INDEX 0 */
-#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
/* @brief FLEXCOMM1 USART INDEX 1 */
-#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
/* @brief FLEXCOMM1 SPI INDEX 1 */
-#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
/* @brief FLEXCOMM1 I2C INDEX 1 */
-#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
/* @brief FLEXCOMM1 I2S INDEX 1 */
-#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
/* @brief FLEXCOMM2 USART INDEX 2 */
-#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
/* @brief FLEXCOMM2 SPI INDEX 2 */
-#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
/* @brief FLEXCOMM2 I2C INDEX 2 */
-#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
/* @brief FLEXCOMM2 I2S INDEX 2 */
-#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
/* @brief FLEXCOMM3 USART INDEX 3 */
-#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
/* @brief FLEXCOMM3 SPI INDEX 3 */
-#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
/* @brief FLEXCOMM3 I2C INDEX 3 */
-#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
/* @brief FLEXCOMM3 I2S INDEX 3 */
-#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
/* @brief FLEXCOMM4 USART INDEX 4 */
-#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
/* @brief FLEXCOMM4 SPI INDEX 4 */
-#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
/* @brief FLEXCOMM4 I2C INDEX 4 */
-#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
/* @brief FLEXCOMM4 I2S INDEX 4 */
-#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
+#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
/* @brief FLEXCOMM5 USART INDEX 5 */
-#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
/* @brief FLEXCOMM5 SPI INDEX 5 */
-#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
/* @brief FLEXCOMM5 I2C INDEX 5 */
-#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
/* @brief FLEXCOMM5 I2S INDEX 5 */
-#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
+#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
/* @brief FLEXCOMM6 USART INDEX 6 */
-#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
/* @brief FLEXCOMM6 SPI INDEX 6 */
-#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
/* @brief FLEXCOMM6 I2C INDEX 6 */
-#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
/* @brief FLEXCOMM6 I2S INDEX 6 */
-#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
/* @brief FLEXCOMM7 USART INDEX 7 */
-#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
/* @brief FLEXCOMM7 SPI INDEX 7 */
-#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
/* @brief FLEXCOMM7 I2C INDEX 7 */
-#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
/* @brief FLEXCOMM7 I2S INDEX 7 */
-#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
-#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
@@ -245,7 +251,7 @@
/* @brief I2S support dual channel transfer. */
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
-/* @brief I2S has DMIC interconnection. */
+/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
/* IOCON module features */
@@ -261,7 +267,7 @@
/* MRT module features */
/* @brief number of channels. */
-#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
/* PINT module features */
@@ -273,6 +279,13 @@
/* @brief Has WAKEINT_CTRL register. */
#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
+/* PMC module features */
+
+/* @brief UTICK does not support PD configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief WDT OSC does not support PD configure. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
/* POWERLIB module features */
/* @brief Powerlib API is different with other LPC series devices. */
@@ -281,7 +294,7 @@
/* POWERQUAD module features */
/* @brief Sine and Cossine fix errata */
-#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
+#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
/* PUF module features */
@@ -290,6 +303,10 @@
/* @brief the shift status value */
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
+/* RTC module features */
+
+/* No feature definitions */
+
/* SCT module features */
/* @brief Number of events */
@@ -319,8 +336,6 @@
/* SYSCON module features */
-/* @brief Pointer to ROM IAP entry functions */
-#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
/* @brief Flash page size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
/* @brief Flash sector size in bytes */
@@ -334,6 +349,10 @@
/* @brief Starter register discontinuous. */
#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+/* SYSCTL1 module features */
+
+/* No feature definitions */
+
/* USB module features */
/* @brief Size of the USB dedicated RAM */
@@ -374,16 +393,23 @@
/* @brief USBHSH version */
#define FSL_FEATURE_USBHSH_VERSION (300)
-/* UTICK module features */
+/* USBPHY module features */
-/* @brief UTICK does not support PD configure. */
-#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBPHY_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBPHY_EP_NUM (6)
/* WWDT module features */
+/* @brief Has no RESET register. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
/* @brief WWDT does not support oscillator lock. */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
-/* @brief WWDT does not support power down configure */
-#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */
+
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c
index 28657eb2a..fa15e4b7b 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.c
@@ -11,7 +11,7 @@
**
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
-** Build: b190830
+** Build: b200418
**
** Abstract:
** Provides a system configuration function and a global variable that
@@ -19,7 +19,7 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2019 NXP
+** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -60,15 +60,15 @@
/* Get predivider (N) from PLL0 NDEC setting */
static uint32_t findPll0PreDiv(void)
{
- uint32_t preDiv = 1;
+ uint32_t preDiv = 1UL;
/* Direct input is not used? */
- if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL)
{
preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
- if (preDiv == 0)
+ if (preDiv == 0UL)
{
- preDiv = 1;
+ preDiv = 1UL;
}
}
return preDiv;
@@ -79,19 +79,19 @@ static uint32_t findPll0PostDiv(void)
{
uint32_t postDiv = 1;
- if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL)
{
- if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL)
{
postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
}
else
{
- postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
+ postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
}
- if (postDiv == 0)
+ if (postDiv == 0UL)
{
- postDiv = 2;
+ postDiv = 2UL;
}
}
return postDiv;
@@ -100,24 +100,25 @@ static uint32_t findPll0PostDiv(void)
/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
static float findPll0MMult(void)
{
- float mMult = 1;
+ float mMult = 1.0F;
float mMult_fract;
uint32_t mMult_int;
- if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
+ if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL)
{
- mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
+ mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT);
}
else
{
- mMult_int =
- ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
- mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / (1 << PLL_SSCG_MD_INT_P));
+ mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U);
+ mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
+ mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) /
+ (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P));
mMult = (float)mMult_int + mMult_fract;
}
- if (mMult == 0)
+ if (mMult == 0.0F)
{
- mMult = 1;
+ mMult = 1.0F;
}
return mMult;
}
@@ -125,15 +126,15 @@ static float findPll0MMult(void)
/* Get predivider (N) from PLL1 NDEC setting */
static uint32_t findPll1PreDiv(void)
{
- uint32_t preDiv = 1;
+ uint32_t preDiv = 1UL;
/* Direct input is not used? */
- if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL)
{
preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
- if (preDiv == 0)
+ if (preDiv == 0UL)
{
- preDiv = 1;
+ preDiv = 1UL;
}
}
return preDiv;
@@ -142,21 +143,21 @@ static uint32_t findPll1PreDiv(void)
/* Get postdivider (P) from PLL1 PDEC setting */
static uint32_t findPll1PostDiv(void)
{
- uint32_t postDiv = 1;
+ uint32_t postDiv = 1UL;
- if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL)
{
- if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL)
{
postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
}
else
{
- postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
+ postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
}
- if (postDiv == 0)
+ if (postDiv == 0UL)
{
- postDiv = 2;
+ postDiv = 2UL;
}
}
return postDiv;
@@ -165,13 +166,13 @@ static uint32_t findPll1PostDiv(void)
/* Get multiplier (M) from PLL1 MDEC settings */
static uint32_t findPll1MMult(void)
{
- uint32_t mMult = 1;
+ uint32_t mMult = 1UL;
mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
- if (mMult == 0)
+ if (mMult == 0UL)
{
- mMult = 1;
+ mMult = 1UL;
}
return mMult;
}
@@ -180,51 +181,53 @@ static uint32_t findPll1MMult(void)
/*! brief Return Frequency of FRO 12MHz
* return Frequency of FRO 12MHz
*/
-static uint32_t CLOCK_GetFro12MFreq(void)
+static uint32_t GetFro12MFreq(void)
{
- return (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
+ return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U;
}
/* Get FRO 1M Clk */
/*! brief Return Frequency of FRO 1MHz
* return Frequency of FRO 1MHz
*/
-static uint32_t CLOCK_GetFro1MFreq(void)
+static uint32_t GetFro1MFreq(void)
{
- return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
+ return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U;
}
/* Get EXT OSC Clk */
/*! brief Return Frequency of External Clock
* return Frequency of External Clock. If no external clock is used returns 0.
*/
-static uint32_t CLOCK_GetExtClkFreq(void)
+static uint32_t GetExtClkFreq(void)
{
- return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;
+ return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U;
}
/* Get HF FRO Clk */
/*! brief Return Frequency of High-Freq output of FRO
* return Frequency of High-Freq output of FRO
*/
-static uint32_t CLOCK_GetFroHfFreq(void)
+static uint32_t GetFroHfFreq(void)
{
- return (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
+ return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U;
}
/* Get RTC OSC Clk */
/*! brief Return Frequency of 32kHz osc
* return Frequency of 32kHz osc
*/
-static uint32_t CLOCK_GetOsc32KFreq(void)
+static uint32_t GetOsc32KFreq(void)
{
- return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?
+ return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ?
CLK_RTC_32K_CLK :
- ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ?
+ ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ?
CLK_RTC_32K_CLK :
0U;
}
+
+
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
@@ -235,47 +238,45 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-- SystemInit()
---------------------------------------------------------------------------- */
-__attribute__((weak)) void SystemInit(void)
-{
+__attribute__((weak)) void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
- SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
-#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Normal mode */
-#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */
+ #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
- SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
-#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- SCB_NS->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
-#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+ SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */
+#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
- SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
+ SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
#if defined(__MCUXPRESSO)
- extern void (*const g_pfnVectors[])(void);
- SCB->VTOR = (uint32_t)&g_pfnVectors;
+ extern void(*const g_pfnVectors[]) (void);
+ SCB->VTOR = (uint32_t) &g_pfnVectors;
#else
extern void *__Vectors;
- SCB->VTOR = (uint32_t)&__Vectors;
+ SCB->VTOR = (uint32_t) &__Vectors;
#endif
SYSCON->TRACECLKDIV = 0;
/* Optionally enable RAM banks that may be off by default at reset */
#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
- SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK |
- SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
+ SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK
+ | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
#endif
- SystemInitHook();
+ SystemInitHook();
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
-void SystemCoreClockUpdate(void)
-{
+void SystemCoreClockUpdate (void) {
uint32_t clkRate = 0;
uint32_t prediv, postdiv;
- float workRate;
+ uint64_t workRate;
uint64_t workRate1;
switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
@@ -284,16 +285,16 @@ void SystemCoreClockUpdate(void)
switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
- clkRate = CLOCK_GetFro12MFreq();
+ clkRate = GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
- clkRate = CLOCK_GetExtClkFreq();
+ clkRate = GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
- clkRate = CLOCK_GetFro1MFreq();
+ clkRate = GetFro1MFreq();
break;
default: /* = 0x03 = FRO 96 MHz (fro_hf) */
- clkRate = CLOCK_GetFroHfFreq();
+ clkRate = GetFroHfFreq();
break;
}
break;
@@ -301,81 +302,78 @@ void SystemCoreClockUpdate(void)
switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
- clkRate = CLOCK_GetFro12MFreq();
+ clkRate = GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
- clkRate = CLOCK_GetExtClkFreq();
+ clkRate = GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
- clkRate = CLOCK_GetFro1MFreq();
+ clkRate = GetFro1MFreq();
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
- clkRate = CLOCK_GetOsc32KFreq();
+ clkRate = GetOsc32KFreq();
break;
default:
+ clkRate = 0UL;
break;
}
- if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) &&
- (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) &&
- ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) &&
- ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
+ if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL))
{
- prediv = findPll0PreDiv();
+ prediv = findPll0PreDiv();
postdiv = findPll0PostDiv();
/* Adjust input clock */
clkRate = clkRate / prediv;
/* MDEC used for rate */
- workRate = (float)clkRate * (float)findPll0MMult();
- clkRate = (uint32_t)(workRate / ((float)postdiv));
+ workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult();
+ clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
}
break;
case 0x02: /* PLL1 clock (pll1_clk)*/
switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
- clkRate = CLOCK_GetFro12MFreq();
+ clkRate = GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
- clkRate = CLOCK_GetExtClkFreq();
+ clkRate = GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
- clkRate = CLOCK_GetFro1MFreq();
+ clkRate = GetFro1MFreq();
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
- clkRate = CLOCK_GetOsc32KFreq();
+ clkRate = GetOsc32KFreq();
break;
default:
+ clkRate = 0UL;
break;
}
- if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) &&
- (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) &&
- ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))
+ if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL))
{
/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
- prediv = findPll1PreDiv();
+ prediv = findPll1PreDiv();
postdiv = findPll1PostDiv();
/* Adjust input clock */
clkRate = clkRate / prediv;
/* MDEC used for rate */
workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();
- clkRate = workRate1 / ((uint64_t)postdiv);
+ clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv));
}
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
- clkRate = CLOCK_GetOsc32KFreq();
+ clkRate = GetOsc32KFreq();
break;
default:
+ clkRate = 0UL;
break;
}
- SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
+ SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
-__attribute__((weak)) void SystemInitHook(void)
-{
- /* Void implementation of the weak function. */
+__attribute__ ((weak)) void SystemInitHook (void) {
+ /* Void implementation of the weak function. */
}
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h
index 25204afcd..7ef9ccb41 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/device/system_LPC55S69_cm33_core0.h
@@ -11,7 +11,7 @@
**
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
-** Build: b190830
+** Build: b200418
**
** Abstract:
** Provides a system configuration function and a global variable that
@@ -19,7 +19,7 @@
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2019 NXP
+** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -49,7 +49,7 @@
*/
#ifndef _SYSTEM_LPC55S69_cm33_core0_H_
-#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */
+#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
@@ -57,12 +57,13 @@ extern "C" {
#include
-#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
-#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
-#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
-#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
-#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
-#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */
+
/**
* @brief System clock frequency (core clock)
@@ -82,7 +83,7 @@ extern uint32_t SystemCoreClock;
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
-void SystemInit(void);
+void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
@@ -91,7 +92,7 @@ void SystemInit(void);
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
-void SystemCoreClockUpdate(void);
+void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
@@ -103,10 +104,10 @@ void SystemCoreClockUpdate(void);
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
-void SystemInitHook(void);
+void SystemInitHook (void);
#ifdef __cplusplus
}
#endif
-#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */
+#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c
index 85a057eb5..f008866d0 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2017 - 2019 , NXP
+ * Copyright 2017 - 2020 , NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -26,16 +26,16 @@
#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */
#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P)
-#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
-#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P)
-#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */
-#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */
+#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P)
#define PLL_MIN_CCO_FREQ_MHZ (275000000U)
#define PLL_MAX_CCO_FREQ_MHZ (550000000U)
-#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */
-#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */
-#define PLL_MIN_IN_SSMODE (3000000U)
+#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */
+#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */
+#define PLL_MIN_IN_SSMODE (3000000U)
#define PLL_MAX_IN_SSMODE \
(100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */
@@ -48,12 +48,12 @@
/* PLL0 SSCG control1 */
#define PLL0_SSCG_MD_FRACT_P 0U
-#define PLL0_SSCG_MD_INT_P 25U
+#define PLL0_SSCG_MD_INT_P 25U
#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P)
-#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P)
+#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P)
#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M)
-#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M)
+#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M)
/* Saved value of PLL output rate, computed whenever needed to save run-time
computation on each call to retrive the PLL rate. */
@@ -202,17 +202,26 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool
volatile uint32_t *pClkDiv;
pClkDiv = &(SYSCON->SYSTICKCLKDIV0);
- if (reset)
+ if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7))
{
- pClkDiv[(uint8_t)div_name] = 1UL << 29U;
- }
- if (divided_by_value == 0U) /*!< halt */
- {
- pClkDiv[(uint8_t)div_name] = 1UL << 30U;
+ /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */
+ ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] =
+ SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value);
}
else
{
- pClkDiv[(uint8_t)div_name] = (divided_by_value - 1U);
+ if (reset)
+ {
+ ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 29U;
+ }
+ if (divided_by_value == 0U) /*!< halt */
+ {
+ ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U;
+ }
+ else
+ {
+ ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U);
+ }
}
}
@@ -379,12 +388,14 @@ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)
/* Set EXT OSC Clk */
/**
* brief Initialize the external osc clock to given frequency.
+ * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz.
+ * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz.
* param iFreq : Desired frequency (must be equal to exact rate in Hz)
* return returns success or fail status.
*/
status_t CLOCK_SetupExtClocking(uint32_t iFreq)
{
- if (iFreq >= 32000000U)
+ if (iFreq > 32000000U)
{
return kStatus_Fail;
}
@@ -935,7 +946,7 @@ uint32_t CLOCK_GetSystickClkFreq(uint32_t id)
switch (SYSCON->SYSTICKCLKSELX[id])
{
case 0U:
- freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U);
+ freq = CLOCK_GetCoreSysClkFreq() / ((((volatile uint32_t *)pSystickClkDiv)[(uint32_t)id] & 0xffU) + 1U);
break;
case 1U:
freq = CLOCK_GetFro1MFreq();
@@ -1478,8 +1489,8 @@ uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup)
/* Get the input clock frequency of PLL. */
clkRate = CLOCK_GetPLL0InClockRate();
- if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) &&
- ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) &&
+ if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) &&
+ ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) &&
((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) &&
((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL))
{
@@ -1769,7 +1780,7 @@ pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)
}
/* Update current programmed PLL rate var */
- s_Pll0_Freq = pSetup->pllRate;
+ s_Pll1_Freq = pSetup->pllRate;
return kStatus_PLL_Success;
}
@@ -1871,7 +1882,7 @@ bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq)
/* Turn ON FRO HF */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
/* Enable FRO 96MHz output */
- ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
+ ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
/* Select FRO 96 or 48 MHz */
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
}
@@ -1974,6 +1985,9 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
{
volatile uint32_t i;
+ uint32_t phyPllDiv = 0U;
+ uint16_t multiplier = 0U;
+ bool ret = true;
POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);
POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);
@@ -1992,17 +2006,67 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1);
SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1);
- USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;
- USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06);
- USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK;
- USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0
- USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK;
- USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK;
+ USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;
- USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;
- USBPHY->PWD_SET = 0x0;
+ multiplier = (uint16_t)(480000000UL / freq);
- return true;
+ switch (multiplier)
+ {
+ case 15U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
+ break;
+ }
+ case 16U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
+ break;
+ }
+ case 20U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
+ break;
+ }
+ case 24U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U);
+ break;
+ }
+ case 25U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U);
+ break;
+ }
+ case 30U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U);
+ break;
+ }
+ case 40U:
+ {
+ phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U);
+ break;
+ }
+ default:
+ {
+ ret = false;
+ break;
+ }
+ }
+
+ if (ret)
+ {
+ USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv;
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK;
+ USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK;
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK;
+
+ USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;
+ USBPHY->PWD_SET = 0x0;
+ }
+
+ return ret;
}
/* Enable USB DEVICE HIGH SPEED clock */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h
index ce7e2065d..7e2f534c6 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2017 - 2019 , NXP
+ * Copyright 2017 - 2021 , NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -21,8 +21,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief CLOCK driver version 2.3.1. */
-#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+/*! @brief CLOCK driver version 2.3.6. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6))
/*@}*/
/*! @brief Configure whether driver controls clock
@@ -293,9 +293,9 @@
------------------------------------------------------------------------------*/
#define CLK_GATE_REG_OFFSET_SHIFT 8U
-#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
-#define CLK_GATE_BIT_SHIFT_SHIFT 0U
-#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
@@ -311,103 +311,198 @@
/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
typedef enum _clock_ip_name
{
- kCLOCK_IpInvalid = 0U,
- kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
- kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
- kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
- kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
- kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
- kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
- kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
- kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
- kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
- kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
- kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
- kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
- kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
- kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
- kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
- kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
- kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
- kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
- kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
- kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
- kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
- kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
- kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
- kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
- kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
- kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
- kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
- kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
- kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
- kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
- kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
- kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
- kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
- kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
- kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
- kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
- kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
- kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
- kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
- kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
- kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
- kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
- kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
- kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
- kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
- kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
- kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
- kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
- kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
- kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
- kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
- kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
- kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
- kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
- kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
- kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
- kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
- kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
- kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
- kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
- kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
- kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
- kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
- kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
- kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
- kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
- kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
- kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
- kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
- kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
- kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),
- kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
- kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),
- kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
- kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
- kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
- kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
- kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
- kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
- kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),
- kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
- kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
- kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
- kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
- kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
- kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
- kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
- kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
- kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),
- kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),
- kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),
- kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),
- kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),
- kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),
- kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),
- kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)
+ kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
+ kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */
+
+ kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */
+
+ kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */
+
+ kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */
+
+ kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */
+
+ kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */
+
+ kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */
+
+ kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */
+
+ kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */
+
+ kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */
+
+ kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */
+
+ kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */
+
+ kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */
+
+ kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */
+
+ kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */
+
+ kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */
+
+ kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */
+
+ kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */
+
+ kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */
+
+ kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */
+
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */
+
+ kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */
+
+ kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */
+
+ kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */
+
+ kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */
+
+ kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */
+
+ kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */
+
+ kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */
+
+ kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */
+
+ kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */
+
+ kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */
+
+ kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */
+
+ kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */
+
+ kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */
+
+ kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */
+
+ kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */
+
+ kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */
+
+ kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */
+
+ kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */
+
+ kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */
+
+ kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */
+
+ kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */
+
+ kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */
+
+ kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */
+
+ kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */
+
+ kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */
+
+ kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */
+
+ kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */
+
+ kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */
+
+ kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */
+
+ kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */
+
+ kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */
+
+ kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */
+
+ kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */
+
+ kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */
+
+ kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */
+
+ kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */
+
+ kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */
+
+ kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */
+
+ kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */
+
+ kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */
+
+ kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */
+
+ kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */
+
+ kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */
+
+ kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */
+
+ kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */
+
+ kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */
+
+ kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */
+
+ kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */
+
+ kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */
+
+ kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */
+
+ kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */
+
+ kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */
+
+ kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */
+
+ kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */
+
+ kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */
+
+ kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */
+
+ kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */
+
+ kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */
+
+ kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */
+
+ kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */
+
+ kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */
+
+ kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */
+
+ kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */
+
+ kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */
+
+ kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */
+
+ kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */
+
+ kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */
+
+ kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */
+
+ kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */
+
+ kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */
+
+ kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */
+
+ kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */
+
+ kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */
+
+ kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */
+
+ kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */
} clock_ip_name_t;
/*! @brief Peripherals clock source definition. */
@@ -441,269 +536,435 @@ typedef enum _clock_name
#define CLK_ATTACH_ID(mux, sel, pos) \
((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U))
-#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
+#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U)
#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U))
-#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
+#define GET_ID_ITEM(connection) ((connection)&0xFFFU)
#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)
-#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
-#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
-#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
+#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU)
+#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U))
+#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)
#define CM_SYSTICKCLKSEL0 0U
#define CM_SYSTICKCLKSEL1 1U
-#define CM_TRACECLKSEL 2U
-#define CM_CTIMERCLKSEL0 3U
-#define CM_CTIMERCLKSEL1 4U
-#define CM_CTIMERCLKSEL2 5U
-#define CM_CTIMERCLKSEL3 6U
-#define CM_CTIMERCLKSEL4 7U
-#define CM_MAINCLKSELA 8U
-#define CM_MAINCLKSELB 9U
-#define CM_CLKOUTCLKSEL 10U
-#define CM_PLL0CLKSEL 12U
-#define CM_PLL1CLKSEL 13U
+#define CM_TRACECLKSEL 2U
+#define CM_CTIMERCLKSEL0 3U
+#define CM_CTIMERCLKSEL1 4U
+#define CM_CTIMERCLKSEL2 5U
+#define CM_CTIMERCLKSEL3 6U
+#define CM_CTIMERCLKSEL4 7U
+#define CM_MAINCLKSELA 8U
+#define CM_MAINCLKSELB 9U
+#define CM_CLKOUTCLKSEL 10U
+#define CM_PLL0CLKSEL 12U
+#define CM_PLL1CLKSEL 13U
#define CM_ADCASYNCCLKSEL 17U
-#define CM_USB0CLKSEL 18U
-#define CM_FXCOMCLKSEL0 20U
-#define CM_FXCOMCLKSEL1 21U
-#define CM_FXCOMCLKSEL2 22U
-#define CM_FXCOMCLKSEL3 23U
-#define CM_FXCOMCLKSEL4 24U
-#define CM_FXCOMCLKSEL5 25U
-#define CM_FXCOMCLKSEL6 26U
-#define CM_FXCOMCLKSEL7 27U
-#define CM_HSLSPICLKSEL 28U
-#define CM_MCLKCLKSEL 32U
-#define CM_SCTCLKSEL 36U
-#define CM_SDIOCLKSEL 38U
+#define CM_USB0CLKSEL 18U
+#define CM_FXCOMCLKSEL0 20U
+#define CM_FXCOMCLKSEL1 21U
+#define CM_FXCOMCLKSEL2 22U
+#define CM_FXCOMCLKSEL3 23U
+#define CM_FXCOMCLKSEL4 24U
+#define CM_FXCOMCLKSEL5 25U
+#define CM_FXCOMCLKSEL6 26U
+#define CM_FXCOMCLKSEL7 27U
+#define CM_HSLSPICLKSEL 28U
+#define CM_MCLKCLKSEL 32U
+#define CM_SCTCLKSEL 36U
+#define CM_SDIOCLKSEL 38U
#define CM_RTCOSC32KCLKSEL 63U
+/*!
+ * @brief The enumerator of clock attach Id.
+ */
typedef enum _clock_attach_id
{
- kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),
- kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),
- kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),
- kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),
- kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),
- kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),
- kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),
-
- kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),
- kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),
- kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),
- kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),
- kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),
- kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),
- kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),
- kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),
-
- kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),
- kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),
- kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),
- kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),
- kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),
-
- kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
- kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
- kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
- kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
-
- kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
- kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
- kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),
- kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),
- kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
-
- kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
- kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
- kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
- kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
- kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
- kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),
- kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),
- kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
-
- kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
- kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
- kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
- kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
- kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
- kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),
- kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),
- kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
-
- kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
- kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
- kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
- kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
- kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
- kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),
- kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),
- kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
-
- kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
- kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
- kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
- kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
- kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
- kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),
- kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),
- kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
-
- kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
- kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
- kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
- kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
- kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
- kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),
- kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),
- kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
-
- kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
- kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
- kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
- kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
- kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
- kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),
- kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),
- kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
-
- kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
- kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
- kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
- kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
- kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
- kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),
- kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),
- kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
-
- kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
- kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
- kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
- kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
- kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
- kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),
- kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),
- kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
-
- kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),
- kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),
- kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),
- kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),
- kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),
- kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),
- kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),
-
- kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
- kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
- kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
-
- kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
- kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
- kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
- kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
- kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),
- kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
-
- kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
- kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
- kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
- kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),
- kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
-
- kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),
- kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),
-
- kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),
- kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),
- kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),
- kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),
-
- kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),
- kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),
- kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),
- kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),
-
- kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0),
- kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),
- kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),
- kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),
-
- kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),
- kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),
- kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),
- kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),
- kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),
-
- kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),
- kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),
- kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),
- kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),
- kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),
- kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),
- kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),
-
- kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),
- kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),
- kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),
- kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),
- kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),
- kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),
- kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),
-
- kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),
- kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),
- kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),
- kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),
- kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),
- kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),
- kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),
-
- kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),
- kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),
- kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),
- kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),
- kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),
- kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),
- kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),
-
- kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),
- kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),
- kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),
- kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),
- kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),
- kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),
- kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),
- kNONE_to_NONE = (int)0x80000000U,
+ kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */
+
+ kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */
+
+ kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */
+
+ kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */
+
+ kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */
+
+ kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */
+
+ kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */
+
+ kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */
+
+ kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */
+
+ kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */
+
+ kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */
+
+ kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */
+
+ kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */
+
+ kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */
+
+ kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */
+
+ kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */
+
+ kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */
+
+ kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */
+
+ kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */
+
+ kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */
+
+ kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */
+
+ kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */
+
+ kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */
+
+ kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */
+
+ kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */
+
+ kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */
+
+ kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */
+
+ kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */
+
+ kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */
+
+ kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */
+
+ kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */
+
+ kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */
+
+ kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */
+
+ kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */
+
+ kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */
+
+ kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */
+
+ kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */
+
+ kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */
+
+ kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */
+
+ kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */
+
+ kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */
+
+ kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */
+
+ kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */
+
+ kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */
+
+ kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */
+
+ kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */
+
+ kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */
+
+ kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */
+
+ kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */
+
+ kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */
+
+ kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */
+
+ kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */
+
+ kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */
+
+ kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */
+
+ kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */
+
+ kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */
+
+ kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */
+
+ kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */
+
+ kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */
+
+ kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */
+
+ kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */
+
+ kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */
+
+ kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */
+
+ kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */
+
+ kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */
+
+ kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */
+
+ kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */
+
+ kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */
+
+ kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */
+
+ kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */
+
+ kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */
+
+ kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */
+
+ kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */
+
+ kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */
+
+ kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */
+
+ kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */
+
+ kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */
+
+ kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */
+
+ kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */
+
+ kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */
+
+ kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */
+
+ kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */
+
+ kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */
+
+ kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */
+
+ kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */
+
+ kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */
+
+ kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */
+
+ kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */
+
+ kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */
+
+ kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */
+
+ kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */
+
+ kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */
+
+ kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */
+
+ kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */
+
+ kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */
+
+ kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */
+
+ kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */
+
+ kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */
+
+ kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */
+
+ kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */
+
+ kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */
+
+ kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */
+
+ kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */
+
+ kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */
+
+ kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */
+
+ kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */
+
+ kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */
+
+ kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */
+
+ kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */
+
+ kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */
+
+ kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */
+
+ kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */
+
+ kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */
+
+ kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */
+
+ kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */
+
+ kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */
+
+ kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */
+
+ kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */
+
+ kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */
+
+ kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */
+
+ kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */
+
+ kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */
+
+ kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */
+
+ kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */
+
+ kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */
+
+ kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */
+
+ kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */
+
+ kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */
+
+ kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */
+
+ kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */
+
+ kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */
+
+ kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */
+
+ kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */
+
+ kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */
+
+ kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */
+
+ kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */
+
+ kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */
+
+ kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */
+
+ kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */
+
+ kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */
+
+ kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */
+
+ kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */
+
+ kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */
+
+ kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */
+
+ kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */
+
+ kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */
+
+ kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */
+
+ kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */
+
+ kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */
+
+ kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */
+
+ kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */
+
+ kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */
+
+ kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */
+
+ kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */
+
+ kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */
+
+ kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */
+
+ kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */
+
+ kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */
+
+ kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */
+
+ kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */
+
+ kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */
+
+ kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */
+
+ kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */
+
+ kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */
+
+ kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */
+
+ kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */
+
+ kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */
+
+ kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */
+
+ kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */
+
} clock_attach_id_t;
-/* Clock dividers */
+/*! @brief Clock dividers */
typedef enum _clock_div_name
{
- kCLOCK_DivSystickClk0 = 0,
- kCLOCK_DivSystickClk1 = 1,
- kCLOCK_DivArmTrClkDiv = 2,
- kCLOCK_DivFlexFrg0 = 8,
- kCLOCK_DivFlexFrg1 = 9,
- kCLOCK_DivFlexFrg2 = 10,
- kCLOCK_DivFlexFrg3 = 11,
- kCLOCK_DivFlexFrg4 = 12,
- kCLOCK_DivFlexFrg5 = 13,
- kCLOCK_DivFlexFrg6 = 14,
- kCLOCK_DivFlexFrg7 = 15,
- kCLOCK_DivAhbClk = 32,
- kCLOCK_DivClkOut = 33,
- kCLOCK_DivFrohfClk = 34,
- kCLOCK_DivWdtClk = 35,
- kCLOCK_DivAdcAsyncClk = 37,
- kCLOCK_DivUsb0Clk = 38,
- kCLOCK_DivMClk = 43,
- kCLOCK_DivSctClk = 45,
- kCLOCK_DivSdioClk = 47,
- kCLOCK_DivPll0Clk = 49
+ kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */
+
+ kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */
+
+ kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */
+
+ kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */
+
+ kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */
+
+ kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */
+
+ kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */
+
+ kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */
+
+ kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */
+
+ kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */
+
+ kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */
+
+ kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */
+
+ kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */
+
+ kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */
+
+ kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */
+
+ kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */
+
+ kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */
+
+ kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */
+
+ kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */
+
+ kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */
+
+ kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */
} clock_div_name_t;
/*******************************************************************************
@@ -716,7 +977,7 @@ extern "C" {
/**
* @brief Enable the clock for specific IP.
- * @param name : Clock to be enabled.
+ * @param clk : Clock to be enabled.
* @return Nothing
*/
static inline void CLOCK_EnableClock(clock_ip_name_t clk)
@@ -726,7 +987,7 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk)
}
/**
* @brief Disable the clock for specific IP.
- * @param name : Clock to be Disabled.
+ * @param clk : Clock to be Disabled.
* @return Nothing
*/
static inline void CLOCK_DisableClock(clock_ip_name_t clk)
@@ -738,7 +999,7 @@ static inline void CLOCK_DisableClock(clock_ip_name_t clk)
* @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
* Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
* enabled.
- * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
+ * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
* @return returns success or fail status.
*/
status_t CLOCK_SetupFROClocking(uint32_t iFreq);
@@ -804,7 +1065,7 @@ void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);
/**
* @brief Set the flexcomm output frequency.
* @param id : flexcomm instance id
- * freq : output frequency
+ * @param freq : output frequency
* @return 0 : the frequency range is out of range.
* 1 : switch successfully.
*/
@@ -996,7 +1257,7 @@ void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);
* automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
* are not used.
#include
-#if defined(__ICCARM__)
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
#include
#endif
-/*
- * For CMSIS pack RTE.
- * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
- * of the related element for all selected software components.
- */
-#ifdef _RTE_
-#include "RTE_Components.h"
-#endif
-
#include "fsl_device_registers.h"
/*!
@@ -35,6 +26,15 @@
* @{
*/
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
/*******************************************************************************
* Definitions
******************************************************************************/
@@ -47,8 +47,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief common driver version 2.2.2. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
/* Debug console type definition. */
@@ -62,6 +62,7 @@
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
/*! @brief Status group numbers. */
enum _status_groups
@@ -139,6 +140,10 @@ enum _status_groups
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
+ kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
+ kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
+ kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
+ kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
@@ -162,34 +167,39 @@ enum _status_groups
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
- kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
+ kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
+ kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
+ kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
+ kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
+ kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
+ kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
+ kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
+ kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
};
-/*! @brief Generic status return codes. */
+/*! \public
+ * @brief Generic status return codes.
+ */
enum
{
- kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
- kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
- kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
- kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
- kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
- kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
- kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
+ kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
-/*
- * Macro guard for whether to use default weak IRQ implementation in drivers
+/*!
+ * @name Min/max macros
+ * @{
*/
-#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
-#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
-#endif
-
-/*! @name Min/max macros */
-/* @{ */
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
@@ -215,192 +225,6 @@ typedef int32_t status_t;
#endif
/* @} */
-/*! @name Timer utilities */
-/* @{ */
-/*! Macro to convert a microsecond period to raw count value */
-#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
-/*! Macro to convert a raw count value to microsecond */
-#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
-
-/*! Macro to convert a millisecond period to raw count value */
-#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
-/*! Macro to convert a raw count value to millisecond */
-#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
-/* @} */
-
-/*! @name Alignment variable definition macros */
-/* @{ */
-#if (defined(__ICCARM__))
-/**
- * Workaround to disable MISRA C message suppress warnings for IAR compiler.
- * http:/ /supp.iar.com/Support/?note=24725
- */
-_Pragma("diag_suppress=Pm120")
-#define SDK_PRAGMA(x) _Pragma(#x)
- _Pragma("diag_error=Pm120")
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
-#endif
-#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
-#endif
-#elif defined(__GNUC__)
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
-#endif
-#else
-#error Toolchain not supported
-#define SDK_ALIGN(var, alignbytes) var
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) var
-#endif
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) var
-#endif
-#endif
-
-/*! Macro to change a value to a given size aligned value */
-#define SDK_SIZEALIGN(var, alignbytes) \
- ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
-/* @} */
-
-/*! @name Non-cacheable region definition macros */
-/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
- * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
- * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
- * will be initialized to zero in system startup.
- */
-/* @{ */
-#if (defined(__ICCARM__))
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-#endif
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
- __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
-#if(defined(__CC_ARM))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
-#else
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
-#endif
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#endif
-#elif(defined(__XCC__))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
- __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
-#elif(defined(__GNUC__))
-/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
- * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
- */
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
- __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
-#endif
-#else
-#error Toolchain not supported.
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
-#endif
-/* @} */
-
-/*! @name Time sensitive region */
-/* @{ */
-#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
-#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-#else
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#else
-#error Toolchain not supported.
-#endif
-#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
-/* @} */
-
-/*! @name Ram Function */
-#if (defined(__ICCARM__))
-#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif(defined(__GNUC__))
-#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-/* @} */
-
/*! @name Suppress fallthrough warning macro */
/* For switch case code block, if case section ends without "break;" statement, there wil be
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
@@ -415,229 +239,41 @@ _Pragma("diag_suppress=Pm120")
#endif
/* @} */
-#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-void DefaultISR(void);
-#endif
-/*
- * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
- * defined in previous of this file.
- */
-#include "fsl_clock.h"
-
-/*
- * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
- */
-#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
-#include "fsl_reset.h"
-#endif
-
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
- extern "C"
-{
-#endif
-
- /*!
- * @brief Enable specific interrupt.
- *
- * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
- * levels. For example, there are NVIC and intmux. Here the interrupts connected
- * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
- * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
- * to NVIC first then routed to core.
- *
- * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
- * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- *
- * @param interrupt The IRQ number.
- * @retval kStatus_Success Interrupt enabled successfully
- * @retval kStatus_Fail Failed to enable the interrupt
- */
- static inline status_t EnableIRQ(IRQn_Type interrupt)
- {
- if (NotAvail_IRQn == interrupt)
- {
- return kStatus_Fail;
- }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
- if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
- {
- return kStatus_Fail;
- }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
- GIC_EnableIRQ(interrupt);
-#else
- NVIC_EnableIRQ(interrupt);
-#endif
- return kStatus_Success;
- }
-
- /*!
- * @brief Disable specific interrupt.
- *
- * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
- * levels. For example, there are NVIC and intmux. Here the interrupts connected
- * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
- * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
- * to NVIC first then routed to core.
- *
- * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
- * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- *
- * @param interrupt The IRQ number.
- * @retval kStatus_Success Interrupt disabled successfully
- * @retval kStatus_Fail Failed to disable the interrupt
- */
- static inline status_t DisableIRQ(IRQn_Type interrupt)
- {
- if (NotAvail_IRQn == interrupt)
- {
- return kStatus_Fail;
- }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
- if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
- {
- return kStatus_Fail;
- }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
- GIC_DisableIRQ(interrupt);
-#else
- NVIC_DisableIRQ(interrupt);
-#endif
- return kStatus_Success;
- }
-
- /*!
- * @brief Disable the global IRQ
- *
- * Disable the global interrupt and return the current primask register. User is required to provided the primask
- * register for the EnableGlobalIRQ().
- *
- * @return Current primask value.
- */
- static inline uint32_t DisableGlobalIRQ(void)
- {
-#if defined (__XCC__)
- return 0;
-#else
-#if defined(CPSR_I_Msk)
- uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
-
- __disable_irq();
-
- return cpsr;
-#else
- uint32_t regPrimask = __get_PRIMASK();
-
- __disable_irq();
-
- return regPrimask;
-#endif
-#endif
- }
-
- /*!
- * @brief Enable the global IRQ
- *
- * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
- * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
- * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
- *
- * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
- * DisableGlobalIRQ().
- */
- static inline void EnableGlobalIRQ(uint32_t primask)
- {
-#if defined (__XCC__)
-#else
-#if defined(CPSR_I_Msk)
- __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
-#else
- __set_PRIMASK(primask);
+extern "C" {
#endif
-#endif
- }
-
-#if defined(ENABLE_RAM_VECTOR_TABLE)
- /*!
- * @brief install IRQ handler
- *
- * @param irq IRQ number
- * @param irqHandler IRQ handler address
- * @return The old IRQ handler address
- */
- uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-#endif /* ENABLE_RAM_VECTOR_TABLE. */
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
- /*!
- * @brief Enable specific interrupt for wake-up from deep-sleep mode.
- *
- * Enable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
- *
- * @param interrupt The IRQ number.
- */
- void EnableDeepSleepIRQ(IRQn_Type interrupt);
-
- /*!
- * @brief Disable specific interrupt for wake-up from deep-sleep mode.
- *
- * Disable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
- *
- * @param interrupt The IRQ number.
- */
- void DisableDeepSleepIRQ(IRQn_Type interrupt);
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
- /*!
- * @brief Allocate memory with given alignment and aligned size.
- *
- * This is provided to support the dynamically allocated memory
- * used in cache-able region.
- * @param size The length required to malloc.
- * @param alignbytes The alignment size.
- * @retval The allocated memory.
- */
- void *SDK_Malloc(size_t size, size_t alignbytes);
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
- /*!
- * @brief Free memory.
- *
- * @param ptr The memory to be release.
- */
- void SDK_Free(void *ptr);
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
- /*!
- * @brief Delay at least for some time.
- * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
- * if precise delay count was needed, please implement a new delay function with hardware timer.
- *
- * @param delay_us Delay time in unit of microsecond.
- * @param coreClock_Hz Core clock frequency with Hz.
- */
- void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
+/*!
+* @brief Delay at least for some time.
+* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+* if precise delay count was needed, please implement a new delay function with hardware timer.
+*
+* @param delayTime_us Delay time in unit of microsecond.
+* @param coreClock_Hz Core clock frequency with Hz.
+*/
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}
@@ -645,4 +281,12 @@ void DefaultISR(void);
/*! @} */
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XCC__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
#endif /* _FSL_COMMON_H_ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
new file mode 100644
index 000000000..e77a265ce
--- /dev/null
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common_arm"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+ extern uint32_t Image$$VECTOR_ROM$$Base[];
+ extern uint32_t Image$$VECTOR_RAM$$Base[];
+ extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+ extern uint32_t __VECTOR_TABLE[];
+ extern uint32_t __VECTOR_RAM[];
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+ uint32_t n;
+ uint32_t ret;
+ uint32_t irqMaskValue;
+
+ irqMaskValue = DisableGlobalIRQ();
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+ {
+ /* Copy the vector table from ROM to RAM */
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+ {
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+ }
+ /* Point the VTOR to the position of vector table */
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;
+ }
+
+ ret = __VECTOR_RAM[(int32_t)irq + 16];
+ /* make sure the __VECTOR_RAM is noncachable */
+ __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+
+ EnableGlobalIRQ(irqMaskValue);
+
+ return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+
+/*
+ * When the SYSCON STARTER registers are discontinuous, these functions are
+ * implemented in fsl_power.c.
+ */
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ uint32_t index = 0;
+
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERSET[index] = 1UL << intNumber;
+ (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+ uint32_t intNumber = (uint32_t)interrupt;
+
+ (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+ uint32_t index = 0;
+
+ while (intNumber >= 32u)
+ {
+ index++;
+ intNumber -= 32u;
+ }
+
+ SYSCON->STARTERCLR[index] = 1UL << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
+/* Use WDT. */
+static void enableCpuCycleCounter(void)
+{
+ /* Make sure the DWT trace fucntion is enabled. */
+ if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
+ {
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+ }
+
+ /* CYCCNT not supported on this device. */
+ assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
+
+ /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
+ if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
+ {
+ DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+ }
+}
+
+static uint32_t getCpuCycleCount(void)
+{
+ return DWT->CYCCNT;
+}
+#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+/* Use software loop. */
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+ SUBS R0, R0, #1
+ CMP R0, #0
+ BNE loop
+ BX LR
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+ __ASM volatile(" MOV R0, %0" : : "r"(count));
+ __ASM volatile(
+ "loop: \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+ " SUB R0, R0, #1 \n"
+#else
+ " SUBS R0, R0, #1 \n"
+#endif
+ " CMP R0, #0 \n"
+
+ " BNE loop \n"
+ :
+ :
+ : "r0");
+}
+#endif /* defined(__CC_ARM) */
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+
+/*!
+ * @brief Delay at least for some time.
+ * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
+ * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
+ * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ * up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
+ *
+ * @param delayTime_us Delay time in unit of microsecond.
+ * @param coreClock_Hz Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+{
+ uint64_t count;
+
+ if (delayTime_us > 0U)
+ {
+ count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+
+ assert(count <= UINT32_MAX);
+
+#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
+
+ enableCpuCycleCounter();
+ /* Calculate the count ticks. */
+ count += getCpuCycleCount();
+
+ if (count > UINT32_MAX)
+ {
+ count -= UINT32_MAX;
+ /* Wait for cyccnt overflow. */
+ while (count < getCpuCycleCount())
+ {
+ }
+ }
+
+ /* Wait for cyccnt reach count value. */
+ while (count > getCpuCycleCount())
+ {
+ }
+#else
+ /* Divide value may be different in various environment to ensure delay is precise.
+ * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+ * two instructions in one period, through test here set divide 1.5. Other M cores use
+ * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
+ * not matter because other instructions outside while loop is enough to fill the time.
+ */
+#if (__CORTEX_M == 7)
+ count = count / 3U * 2U;
+#else
+ count = count / 4U;
+#endif
+ DelayLoop((uint32_t)count);
+#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+ }
+}
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h
new file mode 100644
index 000000000..8b28aa888
--- /dev/null
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.h
@@ -0,0 +1,660 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_ARM_H_
+#define _FSL_COMMON_ARM_H_
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*! @name Atomic modification
+ *
+ * These macros are used for atomic access, such as read-modify-write
+ * to the peripheral registers.
+ *
+ * - SDK_ATOMIC_LOCAL_ADD
+ * - SDK_ATOMIC_LOCAL_SET
+ * - SDK_ATOMIC_LOCAL_CLEAR
+ * - SDK_ATOMIC_LOCAL_TOGGLE
+ * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
+ *
+ * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * means the address of the peripheral register or variable you want to modify
+ * atomically, the parameter @c clearBits is the bits to clear, the parameter
+ * @c setBits it the bits to set.
+ * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this:
+ *
+ * @code
+ volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR;
+
+ SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02);
+ @endcode
+ *
+ * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result,
+ * register bit1:bit0 = 0b10.
+ *
+ * @note For the platforms don't support exclusive load and store, these macros
+ * disable the global interrupt to pretect the modification.
+ *
+ * @note These macros only guarantee the local processor atomic operations. For
+ * the multi-processor devices, use hardware semaphore such as SEMA42 to
+ * guarantee exclusive access if necessary.
+ *
+ * @{
+ */
+
+/* clang-format off */
+#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1)))
+/* clang-format on */
+
+/* If the LDREX and STREX are supported, use them. */
+#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \
+ do \
+ { \
+ (val) = __LDREXB(addr); \
+ (ops); \
+ } while (0UL != __STREXB((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \
+ do \
+ { \
+ (val) = __LDREXH(addr); \
+ (ops); \
+ } while (0UL != __STREXH((val), (addr)))
+
+#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \
+ do \
+ { \
+ (val) = __LDREXW(addr); \
+ (ops); \
+ } while (0UL != __STREXW((val), (addr)))
+
+static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val);
+}
+
+static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val);
+}
+
+static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits);
+}
+
+static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits);
+}
+
+static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits)
+{
+ uint8_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits)
+{
+ uint16_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits)
+{
+ uint32_t s_val;
+
+ _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits);
+}
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd1Byte((volatile uint8_t*)(volatile void*)(addr), (val)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t*)(volatile void*)(addr), (val)) : \
+ _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void*)(addr), (val))))
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
+ _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClear2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
+ _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle1Byte((volatile uint8_t*)(volatile void*)(addr), (bits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalToggle2Byte((volatile uint16_t*)(volatile void*)(addr), (bits)) : \
+ _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void*)(addr), (bits))))
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+ ((1UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t*)(volatile void*)(addr), (clearBits), (setBits)) : \
+ ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t*)(volatile void*)(addr), (clearBits), (setBits)) : \
+ _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void*)(addr), (clearBits), (setBits))))
+#else
+
+#define SDK_ATOMIC_LOCAL_ADD(addr, val) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) += (val); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_SET(addr, bits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) |= (bits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) &= ~(bits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) ^= (bits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
+ do { \
+ uint32_t s_atomicOldInt; \
+ s_atomicOldInt = DisableGlobalIRQ(); \
+ *(addr) = (*(addr) & ~(clearBits)) | (setBits); \
+ EnableGlobalIRQ(s_atomicOldInt); \
+ } while (0)
+
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000000U / (clockFreqInHz))
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count) * 1000U / (clockFreqInHz))
+/* @} */
+
+/*! @name ISR exit barrier
+ * @{
+ *
+ * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ * exception return operation might vector to incorrect interrupt.
+ * For Cortex-M7, if core speed much faster than peripheral register write speed,
+ * the peripheral interrupt flags may be still set after exiting ISR, this results to
+ * the same error similar with errata 83869.
+ */
+#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
+#define SDK_ISR_EXIT_BARRIER __DSB()
+#else
+#define SDK_ISR_EXIT_BARRIER
+#endif
+
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/*
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+_Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported
+#endif
+
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+ ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+
+#if (defined(__ICCARM__))
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if(defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#error Toolchain not supported.
+#endif
+
+#else
+
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes)
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes)
+
+#endif
+
+/* @} */
+
+/*!
+ * @name Time sensitive region
+ * @{
+ */
+#if (defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
+
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+
+#else /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+void DefaultISR(void);
+#endif
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+ status_t status = kStatus_Success;
+
+ if (NotAvail_IRQn == interrupt)
+ {
+ status = kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ status = kStatus_Fail;
+ }
+#endif
+
+ else
+ {
+#if defined(__GIC_PRIO_BITS)
+ GIC_EnableIRQ(interrupt);
+#else
+ NVIC_EnableIRQ(interrupt);
+#endif
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+ status_t status = kStatus_Success;
+
+ if (NotAvail_IRQn == interrupt)
+ {
+ status = kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ status = kStatus_Fail;
+ }
+#endif
+
+ else
+ {
+#if defined(__GIC_PRIO_BITS)
+ GIC_DisableIRQ(interrupt);
+#else
+ NVIC_DisableIRQ(interrupt);
+#endif
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#if defined(CPSR_I_Msk)
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+ __disable_irq();
+
+ return cpsr;
+#else
+ uint32_t regPrimask = __get_PRIMASK();
+
+ __disable_irq();
+
+ return regPrimask;
+#endif
+}
+
+/*!
+ * @brief Enable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#if defined(CPSR_I_Msk)
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+ __set_PRIMASK(primask);
+#endif
+}
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+/*
+ * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
+ * powerlib should be used instead of these functions.
+ */
+#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_POWERLIB_EXTEND */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @} */
+
+#endif /* _FSL_COMMON_ARM_H_ */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c
index 8f57c8118..7a21a1ce0 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c
@@ -40,18 +40,18 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T
* Variables
******************************************************************************/
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS;
+
/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
-static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)];
/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
-static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)];
/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
-/*! @brief Array to map FLEXCOMM instance number to base address. */
-static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
-
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief IDs of clock for each FLEXCOMM module */
static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
@@ -103,7 +103,7 @@ uint32_t FLEXCOMM_GetInstance(void *base)
}
}
- assert(i < FSL_FEATURE_SOC_FLEXCOMM_COUNT);
+ assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT);
return i;
}
@@ -157,7 +157,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
* mode */
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle)
{
uint32_t instance;
@@ -166,246 +166,247 @@ void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *ha
/* Clear handler first to avoid execution of the handler with wrong handle */
s_flexcommIrqHandler[instance] = NULL;
- s_flexcommHandle[instance] = handle;
+ s_flexcommHandle[instance] = flexcommHandle;
s_flexcommIrqHandler[instance] = handler;
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ SDK_ISR_EXIT_BARRIER;
}
/* IRQ handler functions overloading weak symbols in the startup */
#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void);
void FLEXCOMM0_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[0]);
- s_flexcommIrqHandler[0]((uint32_t *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM0);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void);
void FLEXCOMM1_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[1]);
- s_flexcommIrqHandler[1]((uint32_t *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM1);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void);
void FLEXCOMM2_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[2]);
- s_flexcommIrqHandler[2]((uint32_t *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM2);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void);
void FLEXCOMM3_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[3]);
- s_flexcommIrqHandler[3]((uint32_t *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM3);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void);
void FLEXCOMM4_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[4]);
- s_flexcommIrqHandler[4]((uint32_t *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM4);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void);
void FLEXCOMM5_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[5]);
- s_flexcommIrqHandler[5]((uint32_t *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM5);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void);
void FLEXCOMM6_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[6]);
- s_flexcommIrqHandler[6]((uint32_t *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM6);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void);
void FLEXCOMM7_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[7]);
- s_flexcommIrqHandler[7]((uint32_t *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM7);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void);
void FLEXCOMM8_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[8]);
- s_flexcommIrqHandler[8]((uint32_t *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM8);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void);
void FLEXCOMM9_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[9]);
- s_flexcommIrqHandler[9]((uint32_t *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM9);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void);
void FLEXCOMM10_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[10]);
- s_flexcommIrqHandler[10]((uint32_t *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM10);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void);
void FLEXCOMM11_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[11]);
- s_flexcommIrqHandler[11]((uint32_t *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM11);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void);
void FLEXCOMM12_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[12]);
- s_flexcommIrqHandler[12]((uint32_t *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM12);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void);
void FLEXCOMM13_DriverIRQHandler(void)
{
- assert(s_flexcommIrqHandler[13]);
- s_flexcommIrqHandler[13]((uint32_t *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ uint32_t instance;
+
+ /* Look up instance number */
+ instance = FLEXCOMM_GetInstance(FLEXCOMM13);
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void);
void FLEXCOMM14_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM14);
- assert(s_flexcommIrqHandler[instance]);
- s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void);
void FLEXCOMM15_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM15);
- assert(s_flexcommIrqHandler[instance]);
- s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
#if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void);
void FLEXCOMM16_DriverIRQHandler(void)
{
uint32_t instance;
/* Look up instance number */
instance = FLEXCOMM_GetInstance(FLEXCOMM16);
- assert(s_flexcommIrqHandler[instance]);
- s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
- exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
- __DSB();
-#endif
+ assert(s_flexcommIrqHandler[instance] != NULL);
+ s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+ SDK_ISR_EXIT_BARRIER;
}
#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h
index cf5b6ef99..f96086fde 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h
@@ -53,7 +53,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
* mode */
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);
#if defined(__cplusplus)
}
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.c
index 388834440..be100d5e9 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -28,10 +28,27 @@ static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
/*******************************************************************************
* Prototypes
************ ******************************************************************/
+/*!
+ * @brief Enable GPIO port clock.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param port GPIO port number.
+ */
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port);
/*******************************************************************************
* Code
******************************************************************************/
+static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ assert(port < ARRAY_SIZE(s_gpioClockName));
+
+ /* Upgate the GPIO clock */
+ CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
/*!
* brief Initializes the GPIO peripheral.
*
@@ -42,12 +59,8 @@ static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
*/
void GPIO_PortInit(GPIO_Type *base, uint32_t port)
{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
- assert(port < ARRAY_SIZE(s_gpioClockName));
+ GPIO_EnablePortClock(base, port);
- /* Upgate the GPIO clock */
- CLOCK_EnableClock(s_gpioClockName[port]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
/* Reset the GPIO module */
RESET_PeripheralReset(s_gpioResets[port]);
@@ -83,6 +96,8 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port)
*/
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
{
+ GPIO_EnablePortClock(base, port);
+
if (config->pinDirection == kGPIO_DigitalInput)
{
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
@@ -113,7 +128,7 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
/*!
- * @brief Configures the gpio pin interrupt.
+ * @brief Set the configuration of pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number
@@ -122,9 +137,9 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
*/
void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
{
- base->INTEDG[port] = base->INTEDG[port] | ((uint32_t)config->mode << pin);
+ base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin);
- base->INTPOL[port] = base->INTPOL[port] | ((uint32_t)config->polarity << pin);
+ base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin);
}
/*!
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.h
index 05a0e93fc..50a33f892 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_gpio.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -25,7 +25,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPC GPIO driver version. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
/*@}*/
/*! @brief LPC GPIO direction definition */
@@ -50,10 +50,10 @@ typedef struct _gpio_pin_config
#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
#define GPIO_PIN_INT_LEVEL 0x00U
-#define GPIO_PIN_INT_EDGE 0x01U
+#define GPIO_PIN_INT_EDGE 0x01U
#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
-#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
/*! @brief GPIO Pin Interrupt enable mode */
typedef enum _gpio_pin_enable_mode
@@ -268,7 +268,7 @@ static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
/*!
- * @brief Configures the gpio pin interrupt.
+ * @brief Set the configuration of pin interrupt.
*
* @param base GPIO base pointer.
* @param port GPIO port number
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_iocon.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_iocon.h
index cf0cbd132..e705e91f6 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_iocon.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_iocon.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -29,8 +29,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief IOCON driver version 2.1.1. */
-#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief IOCON driver version. */
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
/*@}*/
/**
@@ -38,53 +38,57 @@
*/
typedef struct _iocon_group
{
- uint32_t port : 8; /* Pin port */
- uint32_t pin : 8; /* Pin number */
- uint32_t ionumber : 8; /* IO number */
- uint32_t modefunc : 16; /* Function and mode */
+ uint8_t port; /* Pin port */
+ uint8_t pin; /* Pin number */
+ uint8_t ionumber; /* IO number */
+ uint16_t modefunc; /* Function and mode */
} iocon_group_t;
/**
* @brief IOCON function and mode selection definitions
* @note See the User Manual for specific modes and functions supported by the various pins.
*/
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
-#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
-#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
-#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
-#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
-#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
-#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
-#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
-#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
-#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
-#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
+#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
+#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
+#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */
+
#if defined(IOCON_PIO_MODE_SHIFT)
-#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
-#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
#endif
#if defined(IOCON_PIO_I2CSLEW_SHIFT)
#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
+#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
+#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */
#endif
#if defined(IOCON_PIO_EGP_SHIFT)
#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
+#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
+#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */
#endif
#if defined(IOCON_PIO_SLEW_SHIFT)
#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
-#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
+#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
#endif
#if defined(IOCON_PIO_INVERT_SHIFT)
@@ -99,11 +103,11 @@ typedef struct _iocon_group
#if defined(IOCON_PIO_FILTEROFF_SHIFT)
#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
-#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
#endif
#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
-#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
#endif
@@ -113,7 +117,7 @@ typedef struct _iocon_group
#if defined(IOCON_PIO_I2CFILTER_SHIFT)
#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
-#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */
#endif
#if defined(IOCON_PIO_ASW_SHIFT)
@@ -127,7 +131,7 @@ typedef struct _iocon_group
#if defined(IOCON_PIO_ECS_SHIFT)
#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */
-#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */
+#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */
#endif
#if defined(IOCON_PIO_S_MODE_SHIFT)
@@ -150,83 +154,6 @@ typedef struct _iocon_group
<< IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
#endif
-#else
-#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
-#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
-#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
-#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
-#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
-#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
-#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
-#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
-
-#if defined(IOCON_PIO_MODE_SHIFT)
-#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
-#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
-#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
-#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
-#endif
-
-#if defined(IOCON_PIO_I2CSLEW_SHIFT)
-#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
-#endif
-
-#if defined(IOCON_PIO_EGP_SHIFT)
-#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
-#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
-#endif
-
-#if defined(IOCON_PIO_INVERT_SHIFT)
-#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
-#endif
-
-#if defined(IOCON_PIO_DIGIMODE_SHIFT)
-#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
-#define IOCON_DIGITAL_EN \
- (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
-#endif
-
-#if defined(IOCON_PIO_FILTEROFF_SHIFT)
-#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
-#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
-#endif
-
-#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
-#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
-#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
-#endif
-
-#if defined(IOCON_PIO_OD_SHIFT)
-#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
-#endif
-
-#if defined(IOCON_PIO_I2CFILTER_SHIFT)
-#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
-#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */
-#endif
-
-#if defined(IOCON_PIO_S_MODE_SHIFT)
-#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
-#define IOCON_S_MODE_1CLK \
- (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
- */
-#define IOCON_S_MODE_2CLK \
- (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
- */
-#define IOCON_S_MODE_3CLK \
- (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
- */
-#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
-#endif
-
-#if defined(IOCON_PIO_CLK_DIV_SHIFT)
-#define IOCON_CLKDIV(div) \
- ((div) \
- << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
-#endif
-
-#endif
#if defined(__cplusplus)
extern "C" {
#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h
index 381d9007f..ab0996302 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_power.h
@@ -71,7 +71,7 @@ typedef enum pd_bits
kPDRUNCFG_ForceUnsigned = 0x80000000U,
} pd_bit_t;
-/*@brief BOD VBAT level */
+/*! @brief BOD VBAT level */
typedef enum _power_bod_vbat_level
{
kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
@@ -102,7 +102,7 @@ typedef enum _power_bod_vbat_level
kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
} power_bod_vbat_level_t;
-/*@brief BOD Hysteresis control */
+/*! @brief BOD Hysteresis control */
typedef enum _power_bod_hyst
{
kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
@@ -111,7 +111,7 @@ typedef enum _power_bod_hyst
kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
} power_bod_hyst_t;
-/*@brief BOD core level */
+/*! @brief BOD core level */
typedef enum _power_bod_core_level
{
kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
@@ -124,6 +124,49 @@ typedef enum _power_bod_core_level
kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
} power_bod_core_level_t;
+/**
+ * @brief Device Reset Causes
+ */
+typedef enum _power_device_reset_cause
+{
+ kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */
+ kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */
+ kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */
+ kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */
+ kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */
+ kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */
+ kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */
+ /* Reset causes in DEEP-POWER-DOWN low power mode */
+ kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */
+ kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */
+ kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */
+ kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish
+ which of these 2 events occured first) */
+ kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to
+ distinguish which of these 2 events occured first) */
+ kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to
+ distinguish which of these 2 events occured first) */
+ kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish
+ which of these 3 events occured first) */
+ /* Miscallenous */
+ kRESET_CAUSE_NOT_RELEVANT =
+ 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */
+ kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an
+ application point of view. */
+} power_device_reset_cause_t;
+
+/**
+ * @brief Device Boot Modes
+ */
+typedef enum _power_device_boot_mode
+{
+ kBOOT_MODE_POWER_UP =
+ 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */
+ kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */
+ kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */
+ kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */
+} power_device_boot_mode_t;
+
/**
* @brief SRAM instances retention control during low power modes
*/
@@ -163,44 +206,44 @@ typedef enum _power_bod_core_level
/**
* @brief Low Power Modes Wake up sources
*/
-#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
-#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
-#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
-#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
-#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
-#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
-#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
-#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
-#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
+#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
+#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
+#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
+#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
+#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
+#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
+#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
+#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
+#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
// reserved (1ULL << 25)
// reserved (1ULL << 26)
-#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
-#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */
-#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
-#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
+#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */
+#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
+#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
// reserved (1ULL << 39)
// reserved (1ULL << 40)
// reserved (1ULL << 41)
@@ -209,19 +252,19 @@ typedef enum _power_bod_core_level
// reserved (1ULL << 44)
// reserved (1ULL << 45)
// reserved (1ULL << 46)
-#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
-#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_SEC_VIO (1ULL << 53)
-#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
-#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
-#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */
-#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */
-#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
-#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_SEC_VIO (1ULL << 53)
+#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
+#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
+#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */
+#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */
+#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
+#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60)
// reserved WAKEUP_PVTVF0_RED (1ULL << 61)
// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62)
@@ -245,7 +288,7 @@ typedef enum _power_bod_core_level
LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */
#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
-#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
+#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
/**
* @brief Wake up I/O sources
*/
@@ -254,9 +297,9 @@ typedef enum _power_bod_core_level
#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
-#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
-#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
-#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
+#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
+#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
+#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */
@@ -274,7 +317,7 @@ typedef enum _power_bod_core_level
(1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */
#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */
-#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
+#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */
#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \
12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */
@@ -293,6 +336,27 @@ typedef enum _power_bod_core_level
#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \
(1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */
+#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \
+ (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/
+#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \
+ (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */
+#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \
+ (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */
+#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \
+ (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */
+#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \
+ (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \
+ disable/enable mask, 0: disable, 1: enable */
+#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \
+ (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \
+ disable/enable mask, 0: disable, 1: enable */
+#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \
+ (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \
+ disable/enable mask, 0: disable, 1: enable */
+#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \
+ (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \
+ disable/enable mask, 0: disable, 1: enable */
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -359,7 +423,6 @@ static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod
/*!
* @brief API to enable deep sleep bit in the ARM Core.
*
- * @param none
* @return none
*/
static inline void POWER_EnableDeepSleep(void)
@@ -370,7 +433,6 @@ static inline void POWER_EnableDeepSleep(void)
/*!
* @brief API to disable deep sleep bit in the ARM Core.
*
- * @param none
* @return none
*/
static inline void POWER_DisableDeepSleep(void)
@@ -383,7 +445,7 @@ static inline void POWER_DisableDeepSleep(void)
* This MUST BE EXECUTED outside the Flash:
* either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
* preferable to have all functions defined in this file implemented in ROM.
- * @param None
+ *
* @return Nothing
*/
void POWER_CycleCpuAndFlash(void);
@@ -481,17 +543,16 @@ void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
/*!
* @brief Power Library API to return the library version.
*
- * @param none
* @return version number of the power library
*/
uint32_t POWER_GetLibVersion(void);
/**
* @brief Sets board-specific trim values for 16MHz XTAL
- * @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
- * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
+ * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
+ * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
* becomes 120
- * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
+ * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF
* becomes 120
* @return none
* @note Following default Values can be used:
@@ -521,7 +582,7 @@ extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100,
int32_t pi32_32kfXtalNPcbParCappF_x100);
/**
* @brief Enables and sets LDO for 16MHz XTAL
- * @param none
+ *
* @return none
*/
extern void POWER_SetXtal16mhzLdo(void);
@@ -533,6 +594,27 @@ extern void POWER_SetXtal16mhzLdo(void);
* @return none
*/
extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);
+
+/**
+ * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes.
+ * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type.
+ * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type.
+ * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0].
+
+ * @return Nothing
+ *
+ * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!!
+ * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!!
+ * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!!
+ * - 1. p_wakeupio_cause is NOT ACCURATE
+ * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when
+ * several wake-up sources are enabled during DEEP-POWER-DOWN
+ * (like enabling wake-up on RTC and Falling edge wake-up pins)
+ *
+ */
+void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause,
+ power_device_boot_mode_t *p_boot_mode,
+ uint32_t *p_wakeupio_cause);
#ifdef __cplusplus
}
#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h
index 5d8015bb4..200a0f42c 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_reset.h
@@ -16,7 +16,7 @@
#include "fsl_device_registers.h"
/*!
- * @addtogroup ksdk_common
+ * @addtogroup reset
* @{
*/
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c
index ef7805672..1bbf23587 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -64,7 +64,7 @@ uint32_t USART_GetInstance(USART_Type *base)
}
}
- assert(i < FSL_FEATURE_SOC_USART_COUNT);
+ assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT);
return i;
}
@@ -142,7 +142,7 @@ void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uin
handle->rxRingBufferHead = 0U;
handle->rxRingBufferTail = 0U;
/* ring buffer is ready we can start receiving data */
- base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+ base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
}
/*!
@@ -233,13 +233,28 @@ status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t src
base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |
- USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK;
+ USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) |
+ USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK;
/* Setup baudrate */
- result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
- if (kStatus_Success != result)
+ if (config->enableMode32k)
{
- return result;
+ if ((9600U % config->baudRate_Bps) == 0U)
+ {
+ base->BRG = 9600U / config->baudRate_Bps;
+ }
+ else
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+ }
+ else
+ {
+ result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
}
/* Setting continuous Clock configuration. used for synchronous mode. */
USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
@@ -292,18 +307,20 @@ void USART_GetDefaultConfig(usart_config_t *config)
(void)memset(config, 0, sizeof(*config));
/* Set always all members ! */
- config->baudRate_Bps = 115200U;
- config->parityMode = kUSART_ParityDisabled;
- config->stopBitCount = kUSART_OneStopBit;
- config->bitCountPerChar = kUSART_8BitsPerChar;
- config->loopback = false;
- config->enableRx = false;
- config->enableTx = false;
- config->txWatermark = kUSART_TxFifo0;
- config->rxWatermark = kUSART_RxFifo1;
- config->syncMode = kUSART_SyncModeDisabled;
- config->enableContinuousSCLK = false;
- config->clockPolarity = kUSART_RxSampleOnFallingEdge;
+ config->baudRate_Bps = 115200U;
+ config->parityMode = kUSART_ParityDisabled;
+ config->stopBitCount = kUSART_OneStopBit;
+ config->bitCountPerChar = kUSART_8BitsPerChar;
+ config->loopback = false;
+ config->enableRx = false;
+ config->enableTx = false;
+ config->enableMode32k = false;
+ config->txWatermark = kUSART_TxFifo0;
+ config->rxWatermark = kUSART_RxFifo1;
+ config->syncMode = kUSART_SyncModeDisabled;
+ config->enableContinuousSCLK = false;
+ config->clockPolarity = kUSART_RxSampleOnFallingEdge;
+ config->enableHardwareFlowControl = false;
}
/*!
@@ -328,7 +345,7 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
uint32_t osrval, brgval, diff, baudrate;
/* check arguments */
- assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+ assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)));
if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))
{
return kStatus_InvalidArgument;
@@ -357,7 +374,7 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
continue;
}
baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));
- diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+ diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
if (diff < best_diff)
{
best_diff = diff;
@@ -366,6 +383,15 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
}
}
+ /* Check to see if actual baud rate is within 3% of desired baud rate
+ * based on the best calculated OSR and BRG value */
+ baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U));
+ diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+ if (diff > ((baudrate_Bps / 100U) * 3U))
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+
/* value over range */
if (best_brgval > 0xFFFFU)
{
@@ -379,6 +405,93 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
return kStatus_Success;
}
+/*!
+ * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source.
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * param base USART peripheral base address.
+ * param baudRate_Bps USART baudrate to be set..
+ * param enableMode32k true is 32k mode, false is normal mode.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz)
+{
+ status_t result = kStatus_Success;
+ base->CFG &= ~(USART_CFG_ENABLE_MASK);
+ if (enableMode32k)
+ {
+ base->CFG |= USART_CFG_MODE32K_MASK;
+ if ((9600U % baudRate_Bps) == 0U)
+ {
+ base->BRG = 9600U / baudRate_Bps - 1U;
+ }
+ else
+ {
+ return kStatus_USART_BaudrateNotSupport;
+ }
+ }
+ else
+ {
+ base->CFG &= ~(USART_CFG_MODE32K_MASK);
+ result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+ }
+ base->CFG |= USART_CFG_ENABLE_MASK;
+ return result;
+}
+
+/*!
+ * brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * param base USART peripheral base address.
+ * param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable)
+{
+ assert(base != NULL);
+
+ uint32_t temp = 0U;
+
+ if (enable)
+ {
+ /* Set USART 9-bit mode, disable parity. */
+ temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK);
+ temp |= (uint32_t)USART_CFG_DATALEN(0x2U);
+ base->CFG = temp;
+ }
+ else
+ {
+ /* Set USART to 8-bit mode. */
+ base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK);
+ base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U);
+ }
+}
+
+/*!
+ * brief Transmit an address frame in 9-bit data mode.
+ *
+ * param base USART peripheral base address.
+ * param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address)
+{
+ assert(base != NULL);
+ base->FIFOWR = ((uint32_t)address | 0x100UL);
+}
+
/*!
* brief Writes to the TX register using a blocking method.
*
@@ -388,33 +501,62 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
* param base USART peripheral base address.
* param data Start address of the data to write.
* param length Size of the data to write.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_InvalidArgument Invalid argument.
+ * retval kStatus_Success Successfully wrote all data.
*/
-void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
{
/* Check arguments */
assert(!((NULL == base) || (NULL == data)));
+#if UART_RETRY_TIMES
+ uint32_t waitTimes;
+#endif
if ((NULL == base) || (NULL == data))
{
- return;
+ return kStatus_InvalidArgument;
}
/* Check whether txFIFO is enabled */
if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
{
- return;
+ return kStatus_InvalidArgument;
}
for (; length > 0U; length--)
{
/* Loop until txFIFO get some space for new data */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U))
+#else
while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+#endif
{
}
+#if UART_RETRY_TIMES
+ if (0U == waitTimes)
+ {
+ return kStatus_USART_Timeout;
+ }
+#endif
base->FIFOWR = *data;
data++;
}
/* Wait to finish transfer */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U))
+#else
while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (0U == waitTimes)
{
+ return kStatus_USART_Timeout;
}
+#endif
+ return kStatus_Success;
}
/*!
@@ -430,12 +572,16 @@ void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
* retval kStatus_USART_ParityError Noise error happened while receiving data.
* retval kStatus_USART_NoiseError Framing error happened while receiving data.
* retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
* retval kStatus_Success Successfully received all data.
*/
status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
{
uint32_t statusFlag;
status_t status = kStatus_Success;
+#if UART_RETRY_TIMES
+ uint32_t waitTimes;
+#endif
/* check arguments */
assert(!((NULL == base) || (NULL == data)));
@@ -452,9 +598,21 @@ status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
for (; length > 0U; length--)
{
/* loop until rxFIFO have some data to read */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U))
+#else
while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (waitTimes == 0U)
{
+ status = kStatus_USART_Timeout;
+ break;
}
+#endif
/* check rxFIFO statusFlag */
if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
{
@@ -570,8 +728,8 @@ status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle,
return kStatus_InvalidArgument;
}
/* Check xfer members */
- assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
- if ((0U == xfer->dataSize) || (NULL == xfer->data))
+ assert(!((0U == xfer->dataSize) || (NULL == xfer->txData)));
+ if ((0U == xfer->dataSize) || (NULL == xfer->txData))
{
return kStatus_InvalidArgument;
}
@@ -583,12 +741,16 @@ status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle,
}
else
{
- handle->txData = xfer->data;
+ /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the
+ * handle value. */
+ uint32_t interruptMask = USART_GetEnabledInterrupts(base);
+ USART_DisableInterrupts(base, interruptMask);
+ handle->txData = xfer->txData;
handle->txDataSize = xfer->dataSize;
handle->txDataSizeAll = xfer->dataSize;
handle->txState = (uint8_t)kUSART_TxBusy;
- /* Enable transmiter interrupt. */
- base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+ /* Enable transmiter interrupt and the previously disabled interrupt. */
+ USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable);
}
return kStatus_Success;
}
@@ -616,10 +778,9 @@ void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
}
/*!
- * brief Get the number of bytes that have been written to USART TX register.
+ * brief Get the number of bytes that have been sent out to bus.
*
- * This function gets the number of bytes that have been written to USART TX
- * register by interrupt method.
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
*
* param base USART peripheral base address.
* param handle USART handle pointer.
@@ -638,7 +799,8 @@ status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, ui
return kStatus_NoTransferInProgress;
}
- *count = handle->txDataSizeAll - handle->txDataSize;
+ *count = handle->txDataSizeAll - handle->txDataSize -
+ ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
return kStatus_Success;
}
@@ -681,7 +843,7 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base,
size_t bytesToReceive;
/* How many bytes currently have received. */
size_t bytesCurrentReceived;
- uint32_t regPrimask = 0U;
+ uint32_t interruptMask = 0U;
/* Check arguments */
assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
@@ -690,12 +852,18 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base,
return kStatus_InvalidArgument;
}
/* Check xfer members */
- assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
- if ((0U == xfer->dataSize) || (NULL == xfer->data))
+ assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData)));
+ if ((0U == xfer->dataSize) || (NULL == xfer->rxData))
{
return kStatus_InvalidArgument;
}
+ /* Enable address detect when address match is enabled. */
+ if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U)
+ {
+ base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+ }
+
/* How to get data:
1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
to uart handle, enable interrupt to store received data to xfer->data. When
@@ -717,7 +885,9 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base,
if (handle->rxRingBuffer != NULL)
{
/* Disable IRQ, protect ring buffer. */
- regPrimask = DisableGlobalIRQ();
+ interruptMask = USART_GetEnabledInterrupts(base);
+ USART_DisableInterrupts(base, interruptMask);
+
/* How many bytes in RX ring buffer currently. */
bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
if (bytesToCopy != 0U)
@@ -727,7 +897,7 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base,
/* Copy data from ring buffer to user memory. */
for (i = 0U; i < bytesToCopy; i++)
{
- xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+ xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
/* Wrap to 0. Not use modulo (%) because it might be large and slow. */
if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
{
@@ -743,13 +913,13 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base,
if (bytesToReceive != 0U)
{
/* No data in ring buffer, save the request to UART handle. */
- handle->rxData = xfer->data + bytesCurrentReceived;
+ handle->rxData = xfer->rxData + bytesCurrentReceived;
handle->rxDataSize = bytesToReceive;
- handle->rxDataSizeAll = bytesToReceive;
+ handle->rxDataSizeAll = xfer->dataSize;
handle->rxState = (uint8_t)kUSART_RxBusy;
}
- /* Enable IRQ if previously enabled. */
- EnableGlobalIRQ(regPrimask);
+ /* Re-enable IRQ. */
+ USART_EnableInterrupts(base, interruptMask);
/* Call user callback since all data are received. */
if (0U == bytesToReceive)
{
@@ -762,13 +932,19 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base,
/* Ring buffer not used. */
else
{
- handle->rxData = xfer->data + bytesCurrentReceived;
+ /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up
+ * the handle value. */
+ interruptMask = USART_GetEnabledInterrupts(base);
+ USART_DisableInterrupts(base, interruptMask);
+ handle->rxData = xfer->rxData + bytesCurrentReceived;
handle->rxDataSize = bytesToReceive;
handle->rxDataSizeAll = bytesToReceive;
handle->rxState = (uint8_t)kUSART_RxBusy;
/* Enable RX interrupt. */
- base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+ base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK;
+ /* Re-enable IRQ. */
+ USART_EnableInterrupts(base, interruptMask);
}
/* Return the how many bytes have read. */
if (receivedBytes != NULL)
@@ -869,6 +1045,8 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
/* Receive data */
if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))
{
+ /* Clear address detect when RXFIFO has data. */
+ base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
/* Receive to app bufffer if app buffer is present */
if (handle->rxDataSize != 0U)
{
@@ -941,19 +1119,20 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
if (!sendEnabled)
{
base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
- handle->txState = (uint8_t)kUSART_TxIdle;
- base->INTENSET |= USART_INTENSET_TXIDLEEN_MASK;
+ base->INTENSET = USART_INTENSET_TXIDLEEN_MASK;
}
}
}
/* Tx idle and the interrupt is enabled. */
- if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) &&
- (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)) && (handle->txState == (uint8_t)kUSART_TxIdle))
+ if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)))
{
+ /* Set txState to idle only when all data has been sent out to bus. */
+ handle->txState = (uint8_t)kUSART_TxIdle;
/* Disable tx idle interrupt */
- base->INTENCLR |= USART_INTENCLR_TXIDLECLR_MASK;
+ base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK;
+
/* Trigger callback. */
if (handle->callback != NULL)
{
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h
index 74f37f232..68467e7e2 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_usart.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -21,13 +21,18 @@
/*! @name Driver version */
/*@{*/
-/*! @brief USART driver version 2.1.1. */
-#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief USART driver version. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
/*@}*/
#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+/*! @brief Retry times for waiting flag. */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */
+#endif
+
/*! @brief Error codes for the USART driver. */
enum
{
@@ -43,6 +48,7 @@ enum
kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
kStatus_USART_BaudrateNotSupport =
MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+ kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */
};
/*! @brief USART synchronous mode. */
@@ -145,6 +151,8 @@ typedef struct _usart_config
bool enableRx; /*!< Enable RX */
bool enableTx; /*!< Enable TX */
bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */
+ bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */
+ bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */
usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */
@@ -154,7 +162,16 @@ typedef struct _usart_config
/*! @brief USART transfer structure. */
typedef struct _usart_transfer
{
- uint8_t *data; /*!< The buffer of data to be transfer.*/
+ /*
+ * Use separate TX and RX data pointer, because TX data is const data.
+ * The member data is kept for backward compatibility.
+ */
+ union
+ {
+ uint8_t *data; /*!< The buffer of data to be transfer.*/
+ uint8_t *rxData; /*!< The buffer to receive data. */
+ const uint8_t *txData; /*!< The buffer of data to be sent. */
+ };
size_t dataSize; /*!< The byte count to be transfer. */
} usart_transfer_t;
@@ -167,12 +184,12 @@ typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *hand
/*! @brief USART handle structure. */
struct _usart_handle
{
- uint8_t *volatile txData; /*!< Address of remaining data to send. */
- volatile size_t txDataSize; /*!< Size of the remaining data to send. */
- size_t txDataSizeAll; /*!< Size of the data to send out. */
- uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
- volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
- size_t rxDataSizeAll; /*!< Size of the data to receive. */
+ const uint8_t *volatile txData; /*!< Address of remaining data to send. */
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+ size_t txDataSizeAll; /*!< Size of the data to send out. */
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */
uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
size_t rxRingBufferSize; /*!< Size of the ring buffer. */
@@ -275,6 +292,77 @@ void USART_GetDefaultConfig(usart_config_t *config);
*/
status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+/*!
+ * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * @param base USART peripheral base address.
+ * @param baudRate_Bps USART baudrate to be set..
+ * @param enableMode32k true is 32k mode, false is normal mode.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * @param base USART peripheral base address.
+ * @param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable);
+
+/*!
+ * @brief Set the USART slave address.
+ *
+ * This function configures the address for USART module that works as slave in 9-bit data mode. When the address
+ * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is
+ * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This
+ * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded.
+ * To un-address a slave, just send an address frame with unmatched address.
+ *
+ * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the
+ * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats.
+ *
+ * @param base USART peripheral base address.
+ * @param address USART slave address.
+ */
+static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address)
+{
+ /* Configure match address. */
+ base->ADDR = (uint32_t)address;
+}
+
+/*!
+ * @brief Enable the USART match address feature.
+ *
+ * @param base USART peripheral base address.
+ * @param match true to enable match address, false to disable.
+ */
+static inline void USART_EnableMatchAddress(USART_Type *base, bool match)
+{
+ /* Configure match address enable bit. */
+ if (match)
+ {
+ base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK;
+ base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+ }
+ else
+ {
+ base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK;
+ base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
+ }
+}
+
/* @} */
/*!
@@ -469,6 +557,30 @@ static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)
base->CTL &= ~USART_CTL_CLRCCONRX_MASK;
}
}
+
+/*!
+ * @brief Sets the rx FIFO watermark.
+ *
+ * @param base USART peripheral base address.
+ * @param water Rx FIFO watermark.
+ */
+static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water)
+{
+ assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT));
+ base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water);
+}
+
+/*!
+ * @brief Sets the tx FIFO watermark.
+ *
+ * @param base USART peripheral base address.
+ * @param water Tx FIFO watermark.
+ */
+static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water)
+{
+ assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT));
+ base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water);
+}
/* @} */
/*!
@@ -504,6 +616,36 @@ static inline uint8_t USART_ReadByte(USART_Type *base)
return (uint8_t)base->FIFORD;
}
+/*!
+ * @brief Gets the rx FIFO data count.
+ *
+ * @param base USART peripheral base address.
+ * @return rx FIFO data count.
+ */
+static inline uint8_t USART_GetRxFifoCount(USART_Type *base)
+{
+ return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT);
+}
+
+/*!
+ * @brief Gets the tx FIFO data count.
+ *
+ * @param base USART peripheral base address.
+ * @return tx FIFO data count.
+ */
+static inline uint8_t USART_GetTxFifoCount(USART_Type *base)
+{
+ return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
+}
+
+/*!
+ * @brief Transmit an address frame in 9-bit data mode.
+ *
+ * @param base USART peripheral base address.
+ * @param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address);
+
/*!
* @brief Writes to the TX register using a blocking method.
*
@@ -513,8 +655,11 @@ static inline uint8_t USART_ReadByte(USART_Type *base)
* @param base USART peripheral base address.
* @param data Start address of the data to write.
* @param length Size of the data to write.
+ * @retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ * @retval kStatus_Success Successfully wrote all data.
*/
-void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
/*!
* @brief Read RX data register using a blocking method.
@@ -529,6 +674,7 @@ void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
* @retval kStatus_USART_ParityError Noise error happened while receiving data.
* @retval kStatus_USART_NoiseError Framing error happened while receiving data.
* @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_USART_Timeout Transmission timed out and was aborted.
* @retval kStatus_Success Successfully received all data.
*/
status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
@@ -630,10 +776,9 @@ size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
/*!
- * @brief Get the number of bytes that have been written to USART TX register.
+ * @brief Get the number of bytes that have been sent out to bus.
*
- * This function gets the number of bytes that have been written to USART TX
- * register by interrupt method.
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
*
* @param base USART peripheral base address.
* @param handle USART handle pointer.
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a
index 2cb80203d..92d25dfc5 100644
Binary files a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a and b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi.a differ
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a
index 8d1610c73..b0adb7d3e 100644
Binary files a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a and b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_hardabi_s.a differ
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a
index dfd3c9088..7df8627e6 100644
Binary files a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a and b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi.a differ
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a
index 1ab7b0f9c..79b7e6e61 100644
Binary files a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a and b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/libs/libpower_softabi_s.a differ
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c
index be4729157..0ac5d0cbb 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/source/semihost_hardfault.c
@@ -4,29 +4,18 @@
// to hang application when debugger not connected.
//
// ****************************************************************************
-// Copyright 2017-2020 NXP
+// Copyright 2017-2021 NXP
// All rights reserved.
//
-// Software that is described herein is for illustrative purposes only
-// which provides customers with programming information regarding the
-// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any
-// warranties of any kind, and NXP Semiconductors and its licensor disclaim any
-// and all warranties, express or implied, including all implied warranties of
-// merchantability, fitness for a particular purpose and non-infringement of
-// intellectual property rights. NXP Semiconductors assumes no responsibility
-// or liability for the use of the software, conveys no license or rights under
-// any patent, copyright, mask work right, or any other intellectual property
-// rights in or to any products. NXP Semiconductors reserves the right to make
-// changes in the software without notification. NXP Semiconductors also makes
-// no representation or warranty that such application will be suitable for the
-// specified use without further testing or modification.
+// NXP Confidential. This software is owned or controlled by NXP and may only be
+// used strictly in accordance with the applicable license terms.
//
-// Permission to use, copy, modify, and distribute this software and its
-// documentation is hereby granted, under NXP Semiconductors' and its
-// licensor's relevant copyrights in the software, without fee, provided that it
-// is used in conjunction with NXP Semiconductors microcontrollers. This
-// copyright, permission, and disclaimer notice must appear in all copies of
-// this code.
+// By expressly accepting such terms or by downloading, installing, activating
+// and/or otherwise using the software, you are agreeing that you have read, and
+// that you agree to comply with and are bound by, such license terms.
+//
+// If you do not agree to be bound by the applicable license terms, then you may not
+// retain, install, activate or otherwise use the software.
// ****************************************************************************
//
// ===== DESCRIPTION =====
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_lpc55s69_cm33_core0.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_lpc55s69_cm33_core0.c
index ac375b718..c6b7bdc57 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_lpc55s69_cm33_core0.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_lpc55s69_cm33_core0.c
@@ -1,10 +1,10 @@
//*****************************************************************************
// LPC55S69_cm33_core0 startup code for use with MCUXpresso IDE
//
-// Version : 230919
+// Version : 010621
//*****************************************************************************
//
-// Copyright 2016-2019 NXP
+// Copyright 2016-2021 NXP
// All rights reserved.
//
// SPDX-License-Identifier: BSD-3-Clause
@@ -44,6 +44,7 @@ extern "C" {
// by the linker when "Enable Code Read Protect" selected.
// See crp.h header for more information
//*****************************************************************************
+
//*****************************************************************************
// Declaration of external SystemInit function
//*****************************************************************************
@@ -224,6 +225,7 @@ extern void _vStackTop(void);
// External declaration for LPC MCU vector table checksum from Linker Script
//*****************************************************************************
WEAK extern void __valid_user_code_checksum();
+extern void _vStackBase(void);
//*****************************************************************************
//*****************************************************************************
@@ -234,6 +236,9 @@ WEAK extern void __valid_user_code_checksum();
// The vector table.
// This relies on the linker script to place at correct location in memory.
//*****************************************************************************
+
+
+
extern void (* const g_pfnVectors[])(void);
extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
@@ -319,6 +324,7 @@ void (* const g_pfnVectors[])(void) = {
DMA1_IRQHandler, // 74: DMA1 interrupt
FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM)
+
}; /* End of g_pfnVectors */
//*****************************************************************************
@@ -361,12 +367,24 @@ extern unsigned int __bss_section_table_end;
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
-__attribute__ ((section(".after_vectors.reset")))
+__attribute__ ((naked, section(".after_vectors.reset")))
void ResetISR(void) {
+
// Disable interrupts
__asm volatile ("cpsid i");
+ // Config VTOR & MSPLIM register
+ __asm volatile ("LDR R0, =0xE000ED08 \n"
+ "STR %0, [R0] \n"
+ "LDR R1, [%0] \n"
+ "MSR MSP, R1 \n"
+ "MSR MSPLIM, %1 \n"
+ :
+ : "r"(g_pfnVectors), "r"(_vStackBase)
+ : "r0", "r1");
+
+
#if defined (__USE_CMSIS)
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c
index c53b9fe07..d2cbe28ef 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_assert.c
@@ -14,7 +14,12 @@
#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
void __aeabi_assert(const char *failedExpr, const char *file, int line)
{
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#else
+ (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+#endif
+
for (;;)
{
__BKPT(0);
@@ -24,7 +29,7 @@ void __aeabi_assert(const char *failedExpr, const char *file, int line)
#if defined(__REDLIB__)
void __assertion_failed(char *failedExpr)
{
- PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+ (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr);
for (;;)
{
__BKPT(0);
@@ -33,7 +38,8 @@ void __assertion_failed(char *failedExpr)
#else
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+ (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line,
+ func);
for (;;)
{
__BKPT(0);
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c
index 4ac0b5883..790610fba 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.c
@@ -1,38 +1,10 @@
/*
- * This is a modified version of the file printf.c, which was distributed
- * by Motorola as part of the M5407C3BOOT.zip package used to initialize
- * the M5407C3 evaluation board.
+ * Copyright 2017-2018, 2020 NXP
+ * All rights reserved.
*
- * Copyright:
- * 1999-2000 MOTOROLA, INC. All Rights Reserved.
- * You are hereby granted a copyright license to use, modify, and
- * distribute the SOFTWARE so long as this entire notice is
- * retained without alteration in any modified and/or redistributed
- * versions, and that such modified versions are clearly identified
- * as such. No licenses are granted by implication, estoppel or
- * otherwise under any patents or trademarks of Motorola, Inc. This
- * software is provided on an "AS IS" basis and without warranty.
- *
- * To the maximum extent permitted by applicable law, MOTOROLA
- * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
- * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
- * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
- * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
- * ACCOMPANYING WRITTEN MATERIALS.
- *
- * To the maximum extent permitted by applicable law, IN NO EVENT
- * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
- * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
- * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
- * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
- *
- * Motorola assumes no responsibility for the maintenance and support
- * of this software
-
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
+ *
*/
#include
@@ -40,956 +12,1576 @@
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
#include
#endif
-
-#ifdef FSL_RTOS_FREE_RTOS
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "task.h"
-#endif
-
-#include "fsl_debug_console_conf.h"
-#include "fsl_str.h"
-
-#include "fsl_common.h"
-#include "serial_manager.h"
-
+#include
#include "fsl_debug_console.h"
+#include "fsl_adapter_uart.h"
+
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
+#if defined(__CC_ARM)
+#pragma diag_suppress 1256
+#endif /* __CC_ARM */
/*******************************************************************************
* Definitions
******************************************************************************/
-#ifndef NDEBUG
-#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
-#undef assert
-#define assert(n)
-#endif
-#endif
-
-#if SDK_DEBUGCONSOLE
-#define DEBUG_CONSOLE_FUNCTION_PREFIX
-#else
-#define DEBUG_CONSOLE_FUNCTION_PREFIX static
-#endif
-
-/*! @brief character backspace ASCII value */
-#define DEBUG_CONSOLE_BACKSPACE 127U
-
-/* lock definition */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
-
-static SemaphoreHandle_t s_debugConsoleReadSemaphore;
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
-static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
-#endif
-
-#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
-
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
-static volatile uint8_t s_debugConsoleReadWaitSemaphore;
-#endif
-
-#else
-
-#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
-
-/*! @brief get current runing environment is ISR or not */
-#ifdef __CA7_REV
-#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
-#else
-#define IS_RUNNING_IN_ISR() __get_IPSR()
-#endif /* __CA7_REV */
-
-/* semaphore definition */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
-
-/* mutex semaphore */
-/* clang-format off */
-#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
-#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \
- do \
- { \
- if(NULL != mutex) \
- { \
- vSemaphoreDelete(mutex); \
- mutex = NULL; \
- } \
- } while(0)
-
-#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
-{ \
- if (IS_RUNNING_IN_ISR() == 0U) \
- { \
- (void)xSemaphoreGive(mutex); \
- } \
-}
-
-#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \
-{ \
- if (IS_RUNNING_IN_ISR() == 0U) \
- { \
- (void)xSemaphoreTake(mutex, portMAX_DELAY); \
- } \
-}
-
-#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
-{ \
- if (IS_RUNNING_IN_ISR() == 0U) \
- { \
- result = xSemaphoreTake(mutex, 0U); \
- } \
- else \
- { \
- result = 1U; \
- } \
-}
-
-/* Binary semaphore */
-#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
-#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \
- do \
- { \
- if(NULL != binary) \
- { \
- vSemaphoreDelete(binary); \
- binary = NULL; \
- } \
- } while(0)
-#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY))
-#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL))
-
-#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
-
-#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)
-#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)
-#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
-#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)
-#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
-
-#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)
-#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary)
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
- { \
- while (!binary) \
- { \
- } \
- binary = false; \
- }
-#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
-#else
-#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
-#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
-#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
-/* clang-format on */
-
-/* add other implementation here
- *such as :
- * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)
- */
-#else
+/*! @brief This definition is maximum line that debugconsole can scanf each time.*/
+#define IO_MAXLINE 20U
-#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.
+/*! @brief The overflow value.*/
+#ifndef HUGE_VAL
+#define HUGE_VAL (99.e99)
+#endif /* HUGE_VAL */
-#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
-
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-/* receive state structure */
-typedef struct _debug_console_write_ring_buffer
+/*! @brief State structure storing debug console. */
+typedef struct DebugConsoleState
{
- uint32_t ringBufferSize;
- volatile uint32_t ringHead;
- volatile uint32_t ringTail;
- uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];
-} debug_console_write_ring_buffer_t;
-#endif
+ uint8_t uartHandleBuffer[HAL_UART_HANDLE_SIZE];
+ hal_uart_status_t (*putChar)(hal_uart_handle_t handle,
+ const uint8_t *data,
+ size_t length); /*!< put char function pointer */
+ hal_uart_status_t (*getChar)(hal_uart_handle_t handle,
+ uint8_t *data,
+ size_t length); /*!< get char function pointer */
+ serial_port_type_t type; /*!< The initialized port of the debug console. */
+} debug_console_state_t;
+
+/*! @brief Type of KSDK printf function pointer. */
+typedef int (*PUTCHAR_FUNC)(int a);
+
+#if PRINTF_ADVANCED_ENABLE
+/*! @brief Specification modifier flags for printf. */
+enum _debugconsole_printf_flag
+{
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
+};
+#endif /* PRINTF_ADVANCED_ENABLE */
-typedef struct _debug_console_state_struct
+/*! @brief Specification modifier flags for scanf. */
+enum _debugconsole_scanf_flag
{
- uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];
- serial_handle_t serialHandle; /*!< serial manager handle */
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
- debug_console_write_ring_buffer_t writeRingBuffer;
- uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];
-#endif
- uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];
- uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];
-} debug_console_state_struct_t;
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
+#if SCANF_ADVANCED_ENABLE
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
+#endif /*SCANF_FLOAT_ENABLE */
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
+};
/*******************************************************************************
* Variables
******************************************************************************/
-
-/*! @brief Debug console state information. */
-#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0))
-AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState);
-#else
-static debug_console_state_struct_t s_debugConsoleState;
-#endif
-serial_handle_t g_serialHandle; /*!< serial manager handle */
+/*! @brief Debug UART state information. */
+static debug_console_state_t s_debugConsole;
/*******************************************************************************
* Prototypes
******************************************************************************/
-/*!
- * @brief This is a printf call back function which is used to relocate the log to buffer
- * or print the log immediately when the local buffer is full.
- *
- * @param[in] buf Buffer to store log.
- * @param[in] indicator Buffer index.
- * @param[in] val Target character to store.
- * @param[in] len length of the character
- *
- */
#if SDK_DEBUGCONSOLE
-static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len);
-#endif
-
-status_t DbgConsole_ReadOneCharacter(uint8_t *ch);
-int DbgConsole_SendData(uint8_t *ch, size_t size);
-int DbgConsole_SendDataReliable(uint8_t *ch, size_t size);
-int DbgConsole_ReadLine(uint8_t *buf, size_t size);
-int DbgConsole_ReadCharacter(uint8_t *ch);
+static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap);
+static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr);
+#endif /* SDK_DEBUGCONSOLE */
-#if ((SDK_DEBUGCONSOLE > 0U) || \
- ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
- (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
-DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void);
-#endif
/*******************************************************************************
* Code
******************************************************************************/
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
-
-static void DbgConsole_SerialManagerTxCallback(void *callbackParam,
- serial_manager_callback_message_t *message,
- serial_manager_status_t status)
-{
- debug_console_state_struct_t *ioState;
- uint32_t sendDataLength;
-
- if ((NULL == callbackParam) || (NULL == message))
- {
- return;
- }
-
- ioState = (debug_console_state_struct_t *)callbackParam;
-
- ioState->writeRingBuffer.ringTail += message->length;
- if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)
- {
- ioState->writeRingBuffer.ringTail = 0U;
- }
-
- if (kStatus_SerialManager_Success == status)
- {
- if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)
- {
- if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)
- {
- sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;
- }
- else
- {
- sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;
- }
-
- (void)SerialManager_WriteNonBlocking(
- ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),
- &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength);
- }
- }
- else if (kStatus_SerialManager_Canceled == status)
- {
- ioState->writeRingBuffer.ringTail = 0U;
- ioState->writeRingBuffer.ringHead = 0U;
- }
- else
- {
- /*MISRA rule 16.4*/
- }
-}
-
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
-
-static void DbgConsole_SerialManagerRxCallback(void *callbackParam,
- serial_manager_callback_message_t *message,
- serial_manager_status_t status)
-{
- if ((NULL == callbackParam) || (NULL == message))
- {
- return;
- }
-
- if (kStatus_SerialManager_Notify == status)
- {
- }
- else if (kStatus_SerialManager_Success == status)
- {
- /* release s_debugConsoleReadWaitSemaphore from RX callback */
- DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);
- }
- else
- {
- /*MISRA rule 16.4*/
- }
-}
-#endif
-
-#endif
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
-status_t DbgConsole_ReadOneCharacter(uint8_t *ch)
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
{
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ hal_uart_config_t usrtConfig;
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
- (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
- return kStatus_Fail;
-#else
- status_t status = (status_t)kStatus_SerialManager_Error;
-
-/* recieve one char every time */
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- status = (status_t)SerialManager_ReadNonBlocking(
- ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
-#else
- status = (status_t)SerialManager_ReadBlocking(
- ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);
-#endif
- if ((status_t)kStatus_SerialManager_Success != status)
+ if (kSerialPort_Uart != device)
{
- return (status_t)kStatus_Fail;
+ return kStatus_Fail;
}
- /* wait s_debugConsoleReadWaitSemaphore from RX callback */
- DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);
- return (status_t)kStatus_Success;
+ /* Set debug console to initialized to avoid duplicated initialized operation. */
+ s_debugConsole.type = device;
+
+ usrtConfig.srcClock_Hz = clkSrcFreq;
+ usrtConfig.baudRate_Bps = baudRate;
+ usrtConfig.parityMode = kHAL_UartParityDisabled;
+ usrtConfig.stopBitCount = kHAL_UartOneStopBit;
+ usrtConfig.enableRx = 1U;
+ usrtConfig.enableTx = 1U;
+ usrtConfig.enableRxRTS = 0U;
+ usrtConfig.enableTxCTS = 0U;
+ usrtConfig.instance = instance;
+#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
+ usrtConfig.txFifoWatermark = 0U;
+ usrtConfig.rxFifoWatermark = 0U;
#endif
+ /* Enable clock and initial UART module follow user configure structure. */
+ (void)HAL_UartInit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], &usrtConfig);
+ /* Set the function pointer for send and receive for this kind of device. */
+ s_debugConsole.putChar = HAL_UartSendBlocking;
+ s_debugConsole.getChar = HAL_UartReceiveBlocking;
-#else
-
- return (status_t)kStatus_Fail;
-
-#endif
+ return kStatus_Success;
}
-#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
-static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
{
- /* Due to scanf take \n and \r as end of string,should not echo */
- if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar))
+ if (kSerialPort_None == s_debugConsole.type)
{
- /* recieve one char every time */
- if (1 != DbgConsole_SendDataReliable(ch, 1U))
- {
- return (status_t)kStatus_Fail;
- }
+ return kStatus_Success;
}
- if ((!isGetChar) && (index != NULL))
- {
- if (DEBUG_CONSOLE_BACKSPACE == *ch)
- {
- if ((*index >= 2))
- {
- *index -= 2;
- }
- else
- {
- *index = 0;
- }
- }
- }
+ (void)HAL_UartDeinit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]);
+
+ s_debugConsole.type = kSerialPort_None;
- return (status_t)kStatus_Success;
+ return kStatus_Success;
}
-#endif
+#endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */
-int DbgConsole_SendData(uint8_t *ch, size_t size)
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *fmt_s, ...)
{
- status_t status = (status_t)kStatus_SerialManager_Error;
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- uint32_t sendDataLength;
- int txBusy = 0;
-#endif
- assert(NULL != ch);
- assert(0 != size);
+ va_list ap;
+ int result;
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- uint32_t regPrimask = DisableGlobalIRQ();
- if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
- {
- txBusy = 1;
- sendDataLength =
- (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
- s_debugConsoleState.writeRingBuffer.ringTail) %
- s_debugConsoleState.writeRingBuffer.ringBufferSize;
- }
- else
- {
- sendDataLength = 0U;
- }
- sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1;
- if (sendDataLength < size)
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
{
- EnableGlobalIRQ(regPrimask);
return -1;
}
- for (int i = 0; i < (int)size; i++)
- {
- s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];
- if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)
- {
- s_debugConsoleState.writeRingBuffer.ringHead = 0U;
- }
- }
-
- status = (status_t)kStatus_SerialManager_Success;
-
- if (txBusy == 0)
- {
- if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)
- {
- sendDataLength =
- s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;
- }
- else
- {
- sendDataLength =
- s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;
- }
+ va_start(ap, fmt_s);
+ result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, ap);
+ va_end(ap);
- status = (status_t)SerialManager_WriteNonBlocking(
- ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
- &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],
- sendDataLength);
- }
- EnableGlobalIRQ(regPrimask);
-#else
- status = (status_t)SerialManager_WriteBlocking(
- ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
-#endif
- return (((status_t)kStatus_Success == status) ? (int)size : -1);
+ return result;
}
-int DbgConsole_SendDataReliable(uint8_t *ch, size_t size)
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
{
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
-#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
- status_t status = kStatus_SerialManager_Error;
- uint32_t sendDataLength;
- uint32_t totalLength = size;
- int sentLength;
-#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
-#else
- status_t status = kStatus_SerialManager_Error;
-#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
-
- assert(NULL != ch);
- assert(0 != size);
-
- if (NULL == g_serialHandle)
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
{
- return 0;
+ return -1;
}
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1);
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
-
-#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))
- do
- {
- uint32_t regPrimask = DisableGlobalIRQ();
- if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
- {
- sendDataLength =
- (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -
- s_debugConsoleState.writeRingBuffer.ringTail) %
- s_debugConsoleState.writeRingBuffer.ringBufferSize;
- }
- else
- {
- sendDataLength = 0U;
- }
- sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U;
-
- if (sendDataLength > 0U)
- {
- if (sendDataLength > totalLength)
- {
- sendDataLength = totalLength;
- }
-
- sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength);
- if (sentLength > 0)
- {
- totalLength = totalLength - (uint32_t)sentLength;
- }
- }
- EnableGlobalIRQ(regPrimask);
-
- if (totalLength != 0U)
- {
- status = DbgConsole_Flush();
- if ((status_t)kStatus_Success != status)
- {
- break;
- }
- }
- } while (totalLength != 0U);
- return (status_t)(uint32_t)((uint32_t)size - totalLength);
-#else
- return DbgConsole_SendData(ch, size);
-#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */
-
-#else
- status = (status_t)SerialManager_WriteBlocking(
- ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);
- return (((status_t)kStatus_Success == status) ? (int)size : -1);
-#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+ return 1;
}
-int DbgConsole_ReadLine(uint8_t *buf, size_t size)
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *fmt_ptr, ...)
{
- int i = 0;
-
- assert(buf != NULL);
+ /* Plus one to store end of string char */
+ char temp_buf[IO_MAXLINE + 1];
+ va_list ap;
+ int32_t i;
+ char result;
- if (NULL == g_serialHandle)
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
{
return -1;
}
+ va_start(ap, fmt_ptr);
+ temp_buf[0] = '\0';
- /* take mutex lock function */
- DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
-
- do
+ i = 0;
+ while (true)
{
- /* recieve one char every time */
- if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
+ if (i >= (int32_t)IO_MAXLINE)
{
- /* release mutex lock function */
- DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
- i = -1;
break;
}
-#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
- (void)DbgConsole_EchoCharacter(&buf[i], false, &i);
-#endif
- /* analysis data */
- if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i]))
+
+ result = (char)DbgConsole_Getchar();
+ temp_buf[i] = result;
+
+ if ((result == '\r') || (result == '\n'))
{
/* End of Line. */
- if (0 == i)
+ if (i == 0)
{
- buf[i] = (uint8_t)'\0';
- continue;
+ temp_buf[i] = '\0';
+ i = -1;
}
else
{
break;
}
}
+
i++;
- } while (i < (int)size);
+ }
- /* get char should not add '\0'*/
- if (i == (int)size)
+ if (i == (int32_t)IO_MAXLINE)
{
- buf[i] = (uint8_t)'\0';
+ temp_buf[i] = '\0';
}
else
{
- buf[i + 1] = (uint8_t)'\0';
+ temp_buf[i + 1] = '\0';
}
+ result = (char)DbgConsole_ScanfFormattedData(temp_buf, fmt_ptr, ap);
+ va_end(ap);
- /* release mutex lock function */
- DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-
- return i;
+ return (int)result;
}
-int DbgConsole_ReadCharacter(uint8_t *ch)
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
{
- int ret;
-
- assert(ch);
-
- if (NULL == g_serialHandle)
+ char ch;
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
{
return -1;
}
-
- /* take mutex lock function */
- DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
- /* read one character */
- if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
+ while (kStatus_HAL_UartSuccess !=
+ s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1))
{
- ret = 1;
-#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
- (void)DbgConsole_EchoCharacter(ch, true, NULL);
-#endif
- }
- else
- {
- ret = -1;
+ return -1;
}
- /* release mutex lock function */
- DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-
- return ret;
+ return (int)ch;
}
-#if SDK_DEBUGCONSOLE
-static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len)
+/*************Code for process formatted data*******************************/
+/*!
+ * @brief Scanline function which ignores white spaces.
+ *
+ * @param[in] s The address of the string pointer to update.
+ * @return String without white spaces.
+ */
+static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s)
{
- int i = 0;
+ uint8_t count = 0;
+ char c;
- for (i = 0; i < len; i++)
+ c = **s;
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
{
- if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
- {
- (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));
- *indicator = 0;
- }
+ count++;
+ (*s)++;
+ c = **s;
+ }
+ return count;
+}
- buf[*indicator] = dbgVal;
- (*indicator)++;
+/*!
+ * @brief This function puts padding character.
+ *
+ * @param[in] c Padding character.
+ * @param[in] curlen Length of current formatted string .
+ * @param[in] width Width of expected formatted string.
+ * @param[in] count Number of characters.
+ * @param[in] func_ptr Function to put character out.
+ */
+static void DbgConsole_PrintfPaddingCharacter(
+ char c, int32_t curlen, int32_t width, int32_t *count, PUTCHAR_FUNC func_ptr)
+{
+ int32_t i;
+
+ for (i = curlen; i < width; i++)
+ {
+ (void)func_ptr(c);
+ (*count)++;
}
}
-#endif
-/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+/*!
+ * @brief Converts a radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] neg Polarity of the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] use_caps Used to identify %x/X output format.
-#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
-/* See fsl_debug_console.h for documentation of this function. */
-status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)
+ * @return Length of the converted string.
+ */
+static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
{
- serial_manager_config_t serialConfig;
- status_t status = (status_t)kStatus_SerialManager_Error;
-
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- serial_port_uart_config_t uartConfig = {
- .instance = instance,
- .clockRate = clkSrcFreq,
- .baudRate = baudRate,
- .parityMode = kSerialManager_UartParityDisabled,
- .stopBitCount = kSerialManager_UartOneStopBit,
- .enableRx = 1,
- .enableTx = 1,
- };
-#endif
+#if PRINTF_ADVANCED_ENABLE
+ int64_t a;
+ int64_t b;
+ int64_t c;
+
+ uint64_t ua;
+ uint64_t ub;
+ uint64_t uc;
+#else
+ int32_t a;
+ int32_t b;
+ int32_t c;
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- serial_port_usb_cdc_config_t usbCdcConfig = {
- .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,
- };
-#endif
+ uint32_t ua;
+ uint32_t ub;
+ uint32_t uc;
+#endif /* PRINTF_ADVANCED_ENABLE */
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- serial_port_swo_config_t swoConfig = {
- .clockRate = clkSrcFreq,
- .baudRate = baudRate,
- .port = instance,
- .protocol = kSerialManager_SwoProtocolNrz,
- };
-#endif
+ int32_t nlen;
+ char *nstrp;
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = {
- .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance,
- };
-#endif
- serialConfig.type = device;
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0];
- serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+
+#if !(PRINTF_ADVANCED_ENABLE > 0)
+ neg = 0;
#endif
- if (kSerialPort_Uart == device)
+ if (0 != neg)
{
-#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
- serialConfig.portConfig = &uartConfig;
+#if PRINTF_ADVANCED_ENABLE
+ a = *(int64_t *)nump;
#else
- return status;
-#endif
- }
- else if (kSerialPort_UsbCdc == device)
- {
-#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
- serialConfig.portConfig = &usbCdcConfig;
+ a = *(int32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (a == 0)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (a != 0)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ b = (int64_t)a / (int64_t)radix;
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);
+ if (c < 0)
+ {
+ c = (int64_t)'0' - c;
+ }
#else
- return status;
-#endif
+ b = a / radix;
+ c = a - (b * radix);
+ if (c < 0)
+ {
+ c = (int32_t)'0' - c;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
+ }
}
- else if (kSerialPort_Swo == device)
+ else
{
-#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
- serialConfig.portConfig = &swoConfig;
+#if PRINTF_ADVANCED_ENABLE
+ ua = *(uint64_t *)nump;
#else
- return status;
-#endif
- }
- else if (kSerialPort_UsbCdcVirtual == device)
- {
-#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
- serialConfig.portConfig = &usbCdcVirtualConfig;
+ ua = *(uint32_t *)nump;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (ua == 0U)
+ {
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
+ }
+ while (ua != 0U)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ ub = (uint64_t)ua / (uint64_t)radix;
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
#else
- return status;
-#endif
- }
- else
- {
- return status;
- }
-
- (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState));
-
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;
-#endif
+ ub = ua / (uint32_t)radix;
+ uc = ua - (ub * (uint32_t)radix);
+#endif /* PRINTF_ADVANCED_ENABLE */
- s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];
- status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);
-
- assert(kStatus_SerialManager_Success == status);
+ if (uc < 10U)
+ {
+ uc = uc + '0';
+ }
+ else
+ {
+ uc = uc - 10U + (use_caps ? 'A' : 'a');
+ }
+ ua = ub;
+ *nstrp++ = (char)uc;
+ ++nlen;
+ }
+ }
+ return nlen;
+}
- DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
- DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
-#endif
+#if PRINTF_FLOAT_ENABLE
+/*!
+ * @brief Converts a floating radix number to a string and return its length.
+ *
+ * @param[in] numstr Converted string of the number.
+ * @param[in] nump Pointer to the number.
+ * @param[in] radix The radix to be converted to.
+ * @param[in] precision_width Specify the precision width.
+ * @return Length of the converted string.
+ */
+static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr,
+ void *nump,
+ int32_t radix,
+ uint32_t precision_width)
+{
+ int32_t a;
+ int32_t b;
+ int32_t c;
+ uint32_t i;
+ double fa;
+ double dc;
+ double fb;
+ double r;
+ double fractpart;
+ double intpart;
+
+ int32_t nlen;
+ char *nstrp;
+ nlen = 0;
+ nstrp = numstr;
+ *nstrp++ = '\0';
+ r = *(double *)nump;
+ if (0.0 == r)
{
- status = (status_t)SerialManager_OpenWriteHandle(
- s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
- assert(kStatus_SerialManager_Success == status);
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
- DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);
-#endif
+ *nstrp = '0';
+ ++nlen;
+ return nlen;
}
-
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ fractpart = modf((double)r, (double *)&intpart);
+ /* Process fractional part. */
+ for (i = 0; i < precision_width; i++)
{
- status = (status_t)SerialManager_OpenReadHandle(
- s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
- assert(kStatus_SerialManager_Success == status);
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),
- DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);
-#endif
- }
-#endif
-
- g_serialHandle = s_debugConsoleState.serialHandle;
-
- return kStatus_Success;
-}
-
-/* See fsl_debug_console.h for documentation of this function. */
-status_t DbgConsole_Deinit(void)
-{
+ fractpart *= (double)radix;
+ }
+ if (r >= 0.0)
{
- if (s_debugConsoleState.serialHandle != NULL)
+ fa = fractpart + (double)0.5;
+ if (fa >= pow((double)10, (double)precision_width))
{
- (void)SerialManager_CloseWriteHandle(
- ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
+ intpart++;
}
}
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
+ else
{
- if (s_debugConsoleState.serialHandle != NULL)
+ fa = fractpart - (double)0.5;
+ if (fa <= -pow((double)10, (double)precision_width))
{
- (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));
+ intpart--;
}
}
-#endif
- if (s_debugConsoleState.serialHandle)
+ for (i = 0; i < precision_width; i++)
{
- if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle))
+ fb = fa / (double)radix;
+ dc = (fa - (double)(int64_t)fb * (double)radix);
+ c = (int32_t)dc;
+ if (c < 0)
+ {
+ c = (int32_t)'0' - c;
+ }
+ else
{
- s_debugConsoleState.serialHandle = NULL;
- g_serialHandle = NULL;
+ c = c + '0';
}
+ fa = fb;
+ *nstrp++ = (char)c;
+ ++nlen;
}
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
- DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
-#endif
- DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-
- return (status_t)kStatus_Success;
-}
-#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
-
-#if ((SDK_DEBUGCONSOLE > 0U) || \
- ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \
- (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))))
-DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
-{
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
-
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)
-
- if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ *nstrp++ = (char)'.';
+ ++nlen;
+ a = (int32_t)intpart;
+ if (a == 0)
{
- return (status_t)kStatus_Fail;
+ *nstrp++ = '0';
+ ++nlen;
}
-
-#else
-
- while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)
+ else
{
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
- if (0U == IS_RUNNING_IN_ISR())
+ while (a != 0)
{
- if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState())
+ b = (int32_t)a / (int32_t)radix;
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);
+ if (c < 0)
{
- vTaskDelay(1);
+ c = (int32_t)'0' - c;
}
+ else
+ {
+ c = c + '0';
+ }
+ a = b;
+ *nstrp++ = (char)c;
+ ++nlen;
}
- else
- {
- return (status_t)kStatus_Fail;
- }
-#endif
- }
-
-#endif
-
-#endif
- return (status_t)kStatus_Success;
-}
-#endif
-
-#if SDK_DEBUGCONSOLE
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Printf(const char *formatString, ...)
-{
- va_list ap;
- int logLength = 0, dbgResult = 0;
- char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
-
- if (NULL == g_serialHandle)
- {
- return 0;
}
-
- va_start(ap, formatString);
- /* format print log first */
- logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
- /* print log */
- dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
-
- va_end(ap);
-
- return dbgResult;
-}
-
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Putchar(int ch)
-{
- /* print char */
- return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U);
+ return nlen;
}
+#endif /* PRINTF_FLOAT_ENABLE */
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Scanf(char *formatString, ...)
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] func_ptr Function to put character out.
+ * @param[in] fmt_ptr Format string for printf.
+ * @param[in] args_ptr Arguments to printf.
+ *
+ * @return Number of characters
+ */
+static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap)
{
- va_list ap;
- int formatResult;
- char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'};
-
- /* scanf log */
- (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
- /* get va_list */
- va_start(ap, formatString);
- /* format scanf log */
- formatResult = StrFormatScanf(scanfBuf, formatString, ap);
-
- va_end(ap);
+ /* va_list ap; */
+ const char *p;
+ char c;
+
+ char vstr[33];
+ char *vstrp = NULL;
+ int32_t vlen = 0;
+
+ bool done;
+ int32_t count = 0;
+
+ uint32_t field_width;
+ uint32_t precision_width;
+ char *sval;
+ int32_t cval;
+ bool use_caps;
+ uint8_t radix = 0;
+
+#if PRINTF_ADVANCED_ENABLE
+ uint32_t flags_used;
+ char schar;
+ bool dschar;
+ int64_t ival;
+ uint64_t uval = 0;
+ bool valid_precision_width;
+#else
+ int32_t ival;
+ uint32_t uval = 0;
+#endif /* PRINTF_ADVANCED_ENABLE */
- return formatResult;
-}
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_BlockingPrintf(const char *formatString, ...)
-{
- va_list ap;
- status_t status = (status_t)kStatus_SerialManager_Error;
- int logLength = 0, dbgResult = 0;
- char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'};
+#if PRINTF_FLOAT_ENABLE
+ double fval;
+#endif /* PRINTF_FLOAT_ENABLE */
- if (NULL == g_serialHandle)
+ /* Start parsing apart the format string and display appropriate formats and data. */
+ p = fmt;
+ while (true)
{
- return 0;
- }
+ if ('\0' == *p)
+ {
+ break;
+ }
+ c = *p;
+ /*
+ * All formats begin with a '%' marker. Special chars like
+ * '\n' or '\t' are normally converted to the appropriate
+ * character by the __compiler__. Thus, no need for this
+ * routine to account for the '\' character.
+ */
+ if (c != '%')
+ {
+ (void)func_ptr(c);
+ count++;
+ p++;
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
+ continue;
+ }
- va_start(ap, formatString);
- /* format print log first */
- logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
+ use_caps = true;
-#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
- SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));
-#endif
- /* print log */
- status =
- (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),
- (uint8_t *)printBuf, (size_t)logLength);
- dbgResult = (((status_t)kStatus_Success == status) ? (int)logLength : -1);
- va_end(ap);
+#if PRINTF_ADVANCED_ENABLE
+ /* First check for specification modifier flags. */
+ flags_used = 0;
+ done = false;
+ while (!done)
+ {
+ switch (*++p)
+ {
+ case '-':
+ flags_used |= (uint32_t)kPRINTF_Minus;
+ break;
+ case '+':
+ flags_used |= (uint32_t)kPRINTF_Plus;
+ break;
+ case ' ':
+ flags_used |= (uint32_t)kPRINTF_Space;
+ break;
+ case '0':
+ flags_used |= (uint32_t)kPRINTF_Zero;
+ break;
+ case '#':
+ flags_used |= (uint32_t)kPRINTF_Pound;
+ break;
+ default:
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ break;
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
- return dbgResult;
+ /* Next check for minimum field width. */
+ field_width = 0;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ field_width = (field_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ field_width = (uint32_t)va_arg(ap, uint32_t);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ /* Next check for the width and precision field separator. */
+#if (PRINTF_ADVANCED_ENABLE || PRINTF_FLOAT_ENABLE)
+ precision_width = 6U; /* MISRA C-2012 Rule 2.2 */
+#endif
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = false;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ if (*++p == '.')
+ {
+ /* Must get precision field width, if present. */
+ precision_width = 0U;
+ done = false;
+ while (!done)
+ {
+ c = *++p;
+ if ((c >= '0') && (c <= '9'))
+ {
+ precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0');
+#if PRINTF_ADVANCED_ENABLE
+ valid_precision_width = true;
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if PRINTF_ADVANCED_ENABLE
+ else if (c == '*')
+ {
+ precision_width = (uint32_t)va_arg(ap, uint32_t);
+ valid_precision_width = true;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ done = true;
+ }
+ }
+ }
+ else
+ {
+ /* We've gone one char too far. */
+ --p;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ /*
+ * Check for the length modifier.
+ */
+ switch (/* c = */ *++p)
+ {
+ case 'h':
+ if (*++p != 'h')
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthShortInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthChar;
+ }
+ break;
+ case 'l':
+ if (*++p != 'l')
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthLongInt;
+ --p;
+ }
+ else
+ {
+ flags_used |= (uint32_t)kPRINTF_LengthLongLongInt;
+ }
+ break;
+ default:
+ /* we've gone one char too far */
+ --p;
+ break;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ /* Now we're ready to examine the format. */
+ c = *++p;
+ {
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
+ (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+ if ((c == 'd') || (c == 'i'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+ {
+ ival = (int64_t)va_arg(ap, int64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ ival = (int32_t)va_arg(ap, int32_t);
+ }
+ vlen = DbgConsole_ConvertRadixNumToString(vstr, &ival, 1, 10, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (ival < 0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = '\0';
+ }
+ }
+ }
+ dschar = false;
+ /* Do the ZERO pad. */
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+ }
+ }
+ /* The string was built in reverse order, now display in correct order. */
+ if ((!dschar) && ('\0' != schar))
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+
+#if PRINTF_FLOAT_ENABLE
+ if ((c == 'f') || (c == 'F'))
+ {
+ fval = (double)va_arg(ap, double);
+ vlen = DbgConsole_ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ if (fval < 0.0)
+ {
+ schar = '-';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Plus))
+ {
+ schar = '+';
+ ++vlen;
+ }
+ else
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Space))
+ {
+ schar = ' ';
+ ++vlen;
+ }
+ else
+ {
+ schar = '\0';
+ }
+ }
+ }
+ dschar = false;
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ if ('\0' != schar)
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+ dschar = true;
+ }
+ }
+ if ((!dschar) && ('\0' != schar))
+ {
+ (void)func_ptr(schar);
+ count++;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#endif /* PRINTF_FLOAT_ENABLE */
+ if ((c == 'X') || (c == 'x'))
+ {
+ if (c == 'x')
+ {
+ use_caps = false;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps);
+ vstrp = &vstr[vlen];
+
+#if PRINTF_ADVANCED_ENABLE
+ dschar = false;
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ (void)func_ptr('0');
+ (void)func_ptr((use_caps ? 'X' : 'x'));
+ count += 2;
+ /*vlen += 2;*/
+ dschar = true;
+ }
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ vlen += 2;
+ }
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ if (0U != (flags_used & (uint32_t)kPRINTF_Pound))
+ {
+ (void)func_ptr('0');
+ (void)func_ptr(use_caps ? 'X' : 'x');
+ count += 2;
+
+ dschar = true;
+ }
+ }
+ }
+
+ if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (!dschar))
+ {
+ (void)func_ptr('0');
+ (void)func_ptr(use_caps ? 'X' : 'x');
+ count += 2;
+ vlen += 2;
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt))
+ {
+ uval = (uint64_t)va_arg(ap, uint64_t);
+ }
+ else
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ uval = (uint32_t)va_arg(ap, uint32_t);
+ }
+ switch (c)
+ {
+ case 'o':
+ radix = 8;
+ break;
+ case 'b':
+ radix = 2;
+ break;
+ case 'p':
+ radix = 16;
+ break;
+ case 'u':
+ radix = 10;
+ break;
+ default:
+ /* MISRA C-2012 Rule 16.4 */
+ break;
+ }
+ vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, (int32_t)radix, use_caps);
+ vstrp = &vstr[vlen];
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_Zero))
+ {
+ DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr);
+ vlen = (int32_t)field_width;
+ }
+ else
+ {
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+#if !PRINTF_ADVANCED_ENABLE
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+#endif /* !PRINTF_ADVANCED_ENABLE */
+ if (vstrp != NULL)
+ {
+ while ('\0' != *vstrp)
+ {
+ (void)func_ptr(*vstrp--);
+ count++;
+ }
+ }
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ else if (c == 'c')
+ {
+ cval = (int32_t)va_arg(ap, uint32_t);
+ (void)func_ptr(cval);
+ count++;
+ }
+ else if (c == 's')
+ {
+ sval = (char *)va_arg(ap, char *);
+ if (NULL != sval)
+ {
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ vlen = (int32_t)precision_width;
+ }
+ else
+ {
+ vlen = (int32_t)strlen(sval);
+ }
+#else
+ vlen = (int32_t)strlen(sval);
+#endif /* PRINTF_ADVANCED_ENABLE */
+#if PRINTF_ADVANCED_ENABLE
+ if (0U == (flags_used & (uint32_t)kPRINTF_Minus))
+#endif /* PRINTF_ADVANCED_ENABLE */
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+
+#if PRINTF_ADVANCED_ENABLE
+ if (valid_precision_width)
+ {
+ while (('\0' != *sval) && (vlen > 0))
+ {
+ (void)func_ptr(*sval++);
+ count++;
+ vlen--;
+ }
+ /* In case that vlen sval is shorter than vlen */
+ vlen = (int32_t)precision_width - vlen;
+ }
+ else
+ {
+#endif /* PRINTF_ADVANCED_ENABLE */
+ while ('\0' != *sval)
+ {
+ (void)func_ptr(*sval++);
+ count++;
+ }
+#if PRINTF_ADVANCED_ENABLE
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+#if PRINTF_ADVANCED_ENABLE
+ if (0U != (flags_used & (uint32_t)kPRINTF_Minus))
+ {
+ DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr);
+ }
+#endif /* PRINTF_ADVANCED_ENABLE */
+ }
+ }
+ else
+ {
+ (void)func_ptr(c);
+ count++;
+ }
+ }
+ p++;
+ }
+ return count;
}
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-status_t DbgConsole_TryGetchar(char *ch)
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr)
{
-#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
- uint32_t length = 0;
- status_t status = (status_t)kStatus_Fail;
-
- assert(ch);
-
- if (NULL == g_serialHandle)
+ uint8_t base;
+ int8_t neg;
+ /* Identifier for the format string. */
+ char *c = format;
+ char temp;
+ char *buf;
+ /* Flag telling the conversion specification. */
+ uint32_t flag = 0;
+ /* Filed width for the matching input streams. */
+ uint32_t field_width;
+ /* How many arguments are assigned except the suppress. */
+ uint32_t nassigned = 0;
+ bool match_failure = false;
+ /* How many characters are read from the input streams. */
+ uint32_t n_decode = 0;
+
+ int32_t val;
+
+ const char *s;
+ /* Identifier for the input string. */
+ const char *p = line_ptr;
+
+#if SCANF_FLOAT_ENABLE
+ double fnum = 0.0;
+#endif /* SCANF_FLOAT_ENABLE */
+
+ /* Return EOF error before any conversion. */
+ if (*p == '\0')
{
- return kStatus_Fail;
+ return -1;
}
- /* take mutex lock function */
- DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
-
- if (kStatus_SerialManager_Success ==
- SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
- &length))
+ /* Decode directives. */
+ while (('\0' != (*c)) && ('\0' != (*p)))
{
- if (length != 0U)
+ /* Ignore all white-spaces in the format strings. */
+ if (0U != DbgConsole_ScanIgnoreWhiteSpace((const char **)(void *)&c))
{
-#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
- (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL);
-#endif
- status = (status_t)kStatus_Success;
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
}
- }
- /* release mutex lock function */
- DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
- return status;
-#else
- return (status_t)kStatus_Fail;
-#endif
-}
-#endif
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
+ {
+ /* Ordinary characters. */
+ c++;
+ if (*p == *c)
+ {
+ n_decode++;
+ p++;
+ c++;
+ }
+ else
+ {
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
+ * However, it is deserted now. */
+ break;
+ }
+ }
+ else
+ {
+ /* convernsion specification */
+ c++;
+ /* Reset. */
+ flag = 0;
+ field_width = 0;
+ base = 0;
+
+ /* Loop to get full conversion specification. */
+ while (('\0' != *c) && (0U == (flag & (uint32_t)kSCANF_DestMask)))
+ {
+ switch (*c)
+ {
+#if SCANF_ADVANCED_ENABLE
+ case '*':
+ if (0U != (flag & (uint32_t)kSCANF_Suppress))
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ flag |= (uint32_t)kSCANF_Suppress;
+ c++;
+ break;
+ case 'h':
+ if (0U != (flag & (uint32_t)kSCANF_LengthMask))
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ if (c[1] == 'h')
+ {
+ flag |= (uint32_t)kSCANF_LengthChar;
+ c++;
+ }
+ else
+ {
+ flag |= (uint32_t)kSCANF_LengthShortInt;
+ }
+ c++;
+ break;
+ case 'l':
+ if (0U != (flag & (uint32_t)kSCANF_LengthMask))
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ if (c[1] == 'l')
+ {
+ flag |= (uint32_t)kSCANF_LengthLongLongInt;
+ c++;
+ }
+ else
+ {
+ flag |= (uint32_t)kSCANF_LengthLongInt;
+ }
+ c++;
+ break;
+#endif /* SCANF_ADVANCED_ENABLE */
+#if SCANF_FLOAT_ENABLE
+ case 'L':
+ if (flag & (uint32_t)kSCANF_LengthMask)
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ flag |= (uint32_t)kSCANF_LengthLongLongDouble;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ if (0U != field_width)
+ {
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ do
+ {
+ field_width = field_width * 10U + ((uint32_t)*c - (uint32_t)'0');
+ c++;
+ } while ((*c >= '0') && (*c <= '9'));
+ break;
+ case 'd':
+ base = 10;
+ flag |= (uint32_t)kSCANF_TypeSinged;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'u':
+ base = 10;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'o':
+ base = 8;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'x':
+ case 'X':
+ base = 16;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+ case 'i':
+ base = 0;
+ flag |= (uint32_t)kSCANF_DestInt;
+ c++;
+ break;
+#if SCANF_FLOAT_ENABLE
+ case 'a':
+ case 'A':
+ case 'e':
+ case 'E':
+ case 'f':
+ case 'F':
+ case 'g':
+ case 'G':
+ flag |= kSCANF_DestFloat;
+ c++;
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ case 'c':
+ flag |= (uint32_t)kSCANF_DestChar;
+ if (0U == field_width)
+ {
+ field_width = 1;
+ }
+ c++;
+ break;
+ case 's':
+ flag |= (uint32_t)kSCANF_DestString;
+ c++;
+ break;
+ default:
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+
+ /* Match failure. */
+ if (match_failure)
+ {
+ return (int)nassigned;
+ }
+ }
-/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Getchar(void)
-{
- uint8_t ch = 0U;
+ if (0U == (flag & (uint32_t)kSCANF_DestMask))
+ {
+ /* Format strings are exhausted. */
+ return (int)nassigned;
+ }
- /* Get char */
- (void)DbgConsole_ReadCharacter(&ch);
+ if (0U == field_width)
+ {
+ /* Large than length of a line. */
+ field_width = 99;
+ }
- return (int)ch;
-}
+ /* Matching strings in input streams and assign to argument. */
+ switch (flag & (uint32_t)kSCANF_DestMask)
+ {
+ case (uint32_t)kSCANF_DestChar:
+ s = (const char *)p;
+ buf = va_arg(args_ptr, char *);
+ while (((field_width--) > 0U) && ('\0' != *p))
+ {
+ if (0U == (flag & (uint32_t)kSCANF_Suppress))
+ {
+ *buf++ = *p++;
+ }
+ else
+ {
+ p++;
+ }
+ n_decode++;
+ }
+
+ if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p))
+ {
+ nassigned++;
+ }
+ break;
+ case (uint32_t)kSCANF_DestString:
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ s = p;
+ buf = va_arg(args_ptr, char *);
+ while ((field_width-- > 0U) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))
+ {
+ if (0U != (flag & (uint32_t)kSCANF_Suppress))
+ {
+ p++;
+ }
+ else
+ {
+ *buf++ = *p++;
+ }
+ n_decode++;
+ }
+
+ if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p))
+ {
+ /* Add NULL to end of string. */
+ *buf = '\0';
+ nassigned++;
+ }
+ break;
+ case (uint32_t)kSCANF_DestInt:
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ s = p;
+ val = 0;
+ if ((base == 0U) || (base == 16U))
+ {
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
+ {
+ base = 16U;
+ if (field_width >= 1U)
+ {
+ p += 2;
+ n_decode += 2U;
+ field_width -= 2U;
+ }
+ }
+ }
+
+ if (base == 0U)
+ {
+ if (s[0] == '0')
+ {
+ base = 8U;
+ }
+ else
+ {
+ base = 10U;
+ }
+ }
+
+ neg = 1;
+ switch (*p)
+ {
+ case '-':
+ neg = -1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ case '+':
+ neg = 1;
+ n_decode++;
+ p++;
+ field_width--;
+ break;
+ default:
+ /* MISRA C-2012 Rule 16.4 */
+ break;
+ }
+
+ while ((field_width-- > 0U) && (*p > '\0'))
+ {
+ if ((*p <= '9') && (*p >= '0'))
+ {
+ temp = *p - '0' + (char)0;
+ }
+ else if ((*p <= 'f') && (*p >= 'a'))
+ {
+ temp = *p - 'a' + (char)10;
+ }
+ else if ((*p <= 'F') && (*p >= 'A'))
+ {
+ temp = *p - 'A' + (char)10;
+ }
+ else
+ {
+ temp = (char)base;
+ }
+
+ if ((uint8_t)temp >= base)
+ {
+ break;
+ }
+ else
+ {
+ val = (int32_t)base * val + (int32_t)temp;
+ }
+ p++;
+ n_decode++;
+ }
+ val *= neg;
+ if (0U == (flag & (uint32_t)kSCANF_Suppress))
+ {
+#if SCANF_ADVANCED_ENABLE
+ switch (flag & (uint32_t)kSCANF_LengthMask)
+ {
+ case (uint32_t)kSCANF_LengthChar:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed char *) = (signed char)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
+ }
+ break;
+ case (uint32_t)kSCANF_LengthShortInt:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed short *) = (signed short)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
+ }
+ break;
+ case (uint32_t)kSCANF_LengthLongInt:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
+ }
+ break;
+ case (uint32_t)kSCANF_LengthLongLongInt:
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
+ }
+ break;
+ default:
+ /* The default type is the type int. */
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+ break;
+ }
+#else
+ /* The default type is the type int. */
+ if (0U != (flag & (uint32_t)kSCANF_TypeSinged))
+ {
+ *va_arg(args_ptr, signed int *) = (signed int)val;
+ }
+ else
+ {
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
+ }
+#endif /* SCANF_ADVANCED_ENABLE */
+ nassigned++;
+ }
+ break;
+#if SCANF_FLOAT_ENABLE
+ case (uint32_t)kSCANF_DestFloat:
+ n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p);
+ fnum = strtod(p, (char **)&s);
+
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
+ {
+ break;
+ }
+
+ n_decode += (int)(s) - (int)(p);
+ p = s;
+ if (0U == (flag & (uint32_t)kSCANF_Suppress))
+ {
+ if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble))
+ {
+ *va_arg(args_ptr, double *) = fnum;
+ }
+ else
+ {
+ *va_arg(args_ptr, float *) = (float)fnum;
+ }
+ nassigned++;
+ }
+ break;
+#endif /* SCANF_FLOAT_ENABLE */
+ default:
+ /* Match failure. */
+ match_failure = true;
+ break;
+ }
+ /* Match failure. */
+ if (match_failure)
+ {
+ return (int)nassigned;
+ }
+ }
+ }
+ return (int)nassigned;
+}
#endif /* SDK_DEBUGCONSOLE */
/*************Code to support toolchain's printf, scanf *******************************/
@@ -997,55 +1589,60 @@ int DbgConsole_Getchar(void)
#if (defined(__ICCARM__))
#if defined(SDK_DEBUGCONSOLE_UART)
#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size);
size_t __write(int handle, const unsigned char *buffer, size_t size)
{
- if (buffer == 0)
+ size_t ret;
+ if (NULL == buffer)
{
/*
* This means that we should flush internal buffers. Since we don't we just return.
* (Remember, "handle" == -1 means that all handles should be flushed.)
*/
- return 0;
+ ret = (size_t)0;
}
-
- /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
- if ((handle != 1) && (handle != 2))
+ else if ((handle != 1) && (handle != 2))
{
- return ((size_t)-1);
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure.
+ */
+ ret = (size_t)-1;
}
-
- /* Send data. */
- DbgConsole_SendDataReliable((uint8_t *)buffer, size);
-
- return size;
+ else if (kSerialPort_None == s_debugConsole.type)
+ {
+ /* Do nothing if the debug UART is not initialized. */
+ ret = (size_t)-1;
+ }
+ else
+ {
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size);
+ ret = size;
+ }
+ return ret;
}
#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size);
size_t __read(int handle, unsigned char *buffer, size_t size)
{
- uint8_t ch = 0U;
- int actualSize = 0U;
-
+ size_t ret;
/* This function only reads from "standard in", for all other file handles it returns failure. */
if (handle != 0)
{
- return ((size_t)-1);
+ ret = ((size_t)-1);
}
-
- /* Receive data.*/
- for (; size > 0; size--)
+ else if (kSerialPort_None == s_debugConsole.type)
{
- DbgConsole_ReadCharacter(&ch);
- if (ch == 0)
- {
- break;
- }
-
- *buffer++ = ch;
- actualSize++;
+ /* Do nothing if the debug UART is not initialized. */
+ ret = ((size_t)-1);
}
-
- return actualSize;
+ else
+ {
+ /* Receive data. */
+ (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size);
+ ret = size;
+ }
+ return ret;
}
#endif /* SDK_DEBUGCONSOLE_UART */
@@ -1055,7 +1652,7 @@ size_t __read(int handle, unsigned char *buffer, size_t size)
#if (defined(SDK_DEBUGCONSOLE_UART))
int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
{
- if (buffer == 0)
+ if (NULL == buffer)
{
/* return -1 if error. */
return -1;
@@ -1067,8 +1664,14 @@ int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
return -1;
}
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
/* Send data. */
- DbgConsole_SendDataReliable((uint8_t *)buffer, size);
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
return 0;
}
@@ -1076,13 +1679,18 @@ int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
int __attribute__((weak)) __sys_readc(void)
{
char tmp;
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
/* Receive data. */
- DbgConsole_ReadCharacter((uint8_t *)&tmp);
+ s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)&tmp, sizeof(tmp));
return tmp;
}
-#endif
+#endif /* SDK_DEBUGCONSOLE_UART */
/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
@@ -1107,18 +1715,29 @@ FILE __stdin;
#pragma weak fputc
int fputc(int ch, FILE *f)
{
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
/* Send data. */
- return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1);
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1);
+ return 1;
}
#pragma weak fgetc
int fgetc(FILE *f)
{
char ch;
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
/* Receive data. */
- DbgConsole_ReadCharacter((uint8_t *)&ch);
-
+ s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1);
return ch;
}
@@ -1140,7 +1759,8 @@ void _sys_exit(int returncode)
void _ttywrch(int ch)
{
char ench = ch;
- DbgConsole_SendDataReliable((uint8_t *)(&ench), 1);
+ /* Send data. */
+ s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ench), 1);
}
char *_sys_command_string(char *cmd, int len)
@@ -1149,6 +1769,58 @@ char *_sys_command_string(char *cmd, int len)
}
#endif /* SDK_DEBUGCONSOLE_UART */
+/* These function __write_r and __read_r are used to support Xtensa Clang toolchain to printf and scanf */
+#elif defined(__XTENSA__) && defined(__XT_CLANG__)
+#if defined(SDK_DEBUGCONSOLE_UART)
+
+int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size);
+int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size)
+{
+ if (NULL == buffer)
+ {
+ /* return -1 if error. */
+ return -1;
+ }
+
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+ if ((handle != 1) && (handle != 2))
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Send data. */
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+
+ return size;
+}
+
+int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size);
+int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size)
+{
+ /* This function only reads from "standard in", for all other file handles it returns failure. */
+ if (handle != 0)
+ {
+ return -1;
+ }
+
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
+ /* Receive data. */
+ (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+ return size;
+}
+#endif /* SDK_DEBUGCONSOLE_UART */
+
/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
#elif (defined(__GNUC__))
@@ -1157,7 +1829,7 @@ char *_sys_command_string(char *cmd, int len)
int __attribute__((weak)) _write(int handle, char *buffer, int size);
int __attribute__((weak)) _write(int handle, char *buffer, int size)
{
- if (buffer == NULL)
+ if (NULL == buffer)
{
/* return -1 if error. */
return -1;
@@ -1169,8 +1841,14 @@ int __attribute__((weak)) _write(int handle, char *buffer, int size)
return -1;
}
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
+ {
+ return -1;
+ }
+
/* Send data. */
- (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size);
+ (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
return size;
}
@@ -1178,33 +1856,21 @@ int __attribute__((weak)) _write(int handle, char *buffer, int size)
int __attribute__((weak)) _read(int handle, char *buffer, int size);
int __attribute__((weak)) _read(int handle, char *buffer, int size)
{
- uint8_t ch = 0U;
- int actualSize = 0;
-
/* This function only reads from "standard in", for all other file handles it returns failure. */
if (handle != 0)
{
return -1;
}
- /* Receive data. */
- for (; size > 0; size--)
+ /* Do nothing if the debug UART is not initialized. */
+ if (kSerialPort_None == s_debugConsole.type)
{
- if (DbgConsole_ReadCharacter(&ch) < 0)
- {
- break;
- }
-
- *buffer++ = (char)ch;
- actualSize++;
-
- if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r'))
- {
- break;
- }
+ return -1;
}
- return (actualSize > 0) ? actualSize : -1;
+ /* Receive data. */
+ (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size);
+ return size;
}
#endif
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h
index 30b03e7d2..755b434fe 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h
@@ -1,8 +1,8 @@
/*
- * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
* All rights reserved.
*
+ *
* SPDX-License-Identifier: BSD-3-Clause
*
* Debug console shall provide input and output functions to scan and print formatted data.
@@ -23,9 +23,8 @@
#define _FSL_DEBUGCONSOLE_H_
#include "fsl_common.h"
-#include "serial_manager.h"
-/*!
+/*
* @addtogroup debugconsole
* @{
*/
@@ -34,24 +33,40 @@
* Definitions
******************************************************************************/
-extern serial_handle_t g_serialHandle; /*!< serial manager handle */
-
/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
-#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
-#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
-/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
- * to be redefined in project setting.
- */
+/*! @brief Definition to select sdk or toolchain printf, scanf. */
#ifndef SDK_DEBUGCONSOLE
-#define SDK_DEBUGCONSOLE 1U
+#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK
#endif
#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
#include
#endif
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
*
* if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
@@ -64,18 +79,24 @@ extern serial_handle_t g_serialHandle; /*!< serial manager handle */
#define PUTCHAR
#define GETCHAR
#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
-#define PRINTF DbgConsole_Printf
-#define SCANF DbgConsole_Scanf
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
#define PUTCHAR DbgConsole_Putchar
#define GETCHAR DbgConsole_Getchar
-#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
- */
-#define PRINTF printf
-#define SCANF scanf
+#elif SDK_DEBUGCONSOLE == \
+ DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ */
+#define PRINTF printf
+#define SCANF scanf
#define PUTCHAR putchar
#define GETCHAR getchar
#endif /* SDK_DEBUGCONSOLE */
+typedef enum _serial_port_type
+{
+ kSerialPort_None = 0U, /*!< Serial port is none */
+ kSerialPort_Uart = 1U, /*!< Serial port UART */
+} serial_port_type_t;
+
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -91,20 +112,25 @@ extern "C" {
/*!
* @brief Initializes the peripheral used for debug messages.
*
- * Call this function to enable debug log messages to be output via the specified peripheral
- * initialized by the serial manager module.
+ * Call this function to enable debug log messages to be output via the specified peripheral,
+ * frequency of peripheral source clock, and base address at the specified baud rate.
* After this function has returned, stdout and stdin are connected to the selected peripheral.
*
- * @param instance The instance of the module.
+ * @param instance The instance of the module.If the device is kSerialPort_Uart,
+ * the instance is UART peripheral instance. The UART hardware peripheral
+ * type is determined by UART adapter. For example, if the instance is 1,
+ * if the lpuart_adapter.c is added to the current project, the UART periheral
+ * is LPUART1.
+ * If the uart_adapter.c is added to the current project, the UART periheral
+ * is UART1.
* @param baudRate The desired baud rate in bits per second.
* @param device Low level device type for the debug console, can be one of the following.
- * @arg kSerialPort_Uart,
- * @arg kSerialPort_UsbCdc
- * @arg kSerialPort_UsbCdcVirtual.
+ * @arg kSerialPort_Uart.
* @param clkSrcFreq Frequency of peripheral source clock.
*
* @return Indicates whether initialization was successful or not.
* @retval kStatus_Success Execution successfully
+ * @retval kStatus_Fail Execution failure
*/
status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
@@ -112,11 +138,12 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t
* @brief De-initializes the peripheral used for debug messages.
*
* Call this function to disable debug log messages to be output via the specified peripheral
- * initialized by the serial manager module.
+ * base address and at the specified baud rate.
*
* @return Indicates whether de-initialization was successful or not.
*/
status_t DbgConsole_Deinit(void);
+
#else
/*!
* Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
@@ -141,6 +168,7 @@ static inline status_t DbgConsole_Deinit(void)
{
return (status_t)kStatus_Fail;
}
+
#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
#if SDK_DEBUGCONSOLE
@@ -149,10 +177,10 @@ static inline status_t DbgConsole_Deinit(void)
*
* Call this function to write a formatted output to the standard output stream.
*
- * @param formatString Format control string.
+ * @param fmt_s Format control string.
* @return Returns the number of characters printed or a negative value if an error occurs.
*/
-int DbgConsole_Printf(const char *formatString, ...);
+int DbgConsole_Printf(const char *fmt_s, ...);
/*!
* @brief Writes a character to stdout.
@@ -169,68 +197,20 @@ int DbgConsole_Putchar(int ch);
*
* Call this function to read formatted data from the standard input stream.
*
- * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
- * other tasks will not be scheduled), the function cannot be used when the
- * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
- * And an error is returned when the function called in this case. The suggestion
- * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
- *
- * @param formatString Format control string.
+ * @param fmt_ptr Format control string.
* @return Returns the number of fields successfully converted and assigned.
*/
-int DbgConsole_Scanf(char *formatString, ...);
+int DbgConsole_Scanf(char *fmt_ptr, ...);
/*!
* @brief Reads a character from standard input.
*
* Call this function to read a character from standard input.
*
- * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
- * other tasks will not be scheduled), the function cannot be used when the
- * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
- * And an error is returned when the function called in this case. The suggestion
- * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
- *
* @return Returns the character read.
*/
int DbgConsole_Getchar(void);
-/*!
- * @brief Writes formatted output to the standard output stream with the blocking mode.
- *
- * Call this function to write a formatted output to the standard output stream with the blocking mode.
- * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
- * or not.
- * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
- *
- * @param formatString Format control string.
- * @return Returns the number of characters printed or a negative value if an error occurs.
- */
-int DbgConsole_BlockingPrintf(const char *formatString, ...);
-
-/*!
- * @brief Debug console flush.
- *
- * Call this function to wait the tx buffer empty.
- * If interrupt transfer is using, make sure the global IRQ is enable before call this function
- * This function should be called when
- * 1, before enter power down mode
- * 2, log is required to print to terminal immediately
- * @return Indicates whether wait idle was successful or not.
- */
-status_t DbgConsole_Flush(void);
-
-#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
-/*!
- * @brief Debug console try to get char
- * This function provides a API which will not block current task, if character is
- * available return it, otherwise return fail.
- * @param ch the address of char to receive
- * @return Indicates get char was successful or not.
- */
-status_t DbgConsole_TryGetchar(char *ch);
-#endif
-
#endif /* SDK_DEBUGCONSOLE */
/*! @} */
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.c b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.c
deleted file mode 100644
index c4d1a0c79..000000000
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/utilities/fsl_str.c
+++ /dev/null
@@ -1,1324 +0,0 @@
-/*
- * Copyright 2017 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-#include
-#include
-#include
-#include "fsl_str.h"
-#include "fsl_debug_console_conf.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief The overflow value.*/
-#ifndef HUGE_VAL
-#define HUGE_VAL (99.e99)
-#endif /* HUGE_VAL */
-
-#if PRINTF_ADVANCED_ENABLE
-/*! @brief Specification modifier flags for printf. */
-enum _debugconsole_printf_flag
-{
- kPRINTF_Minus = 0x01U, /*!< Minus FLag. */
- kPRINTF_Plus = 0x02U, /*!< Plus Flag. */
- kPRINTF_Space = 0x04U, /*!< Space Flag. */
- kPRINTF_Zero = 0x08U, /*!< Zero Flag. */
- kPRINTF_Pound = 0x10U, /*!< Pound Flag. */
- kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */
- kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */
- kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */
- kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */
-};
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-/*! @brief Specification modifier flags for scanf. */
-enum _debugconsole_scanf_flag
-{
- kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */
- kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */
- kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */
- kSCANF_DestString = 0x8U, /*!< Destination String FLag. */
- kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */
- kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */
- kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */
- kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */
-#if SCANF_ADVANCED_ENABLE
- kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */
- kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */
- kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */
- kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */
-#endif /* SCANF_ADVANCED_ENABLE */
-#if SCANF_FLOAT_ENABLE
- kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */
-#endif /*PRINTF_FLOAT_ENABLE */
- kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */
-};
-
-/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */
-#if defined(__CC_ARM)
-#pragma diag_suppress 1256
-#endif /* __CC_ARM */
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Scanline function which ignores white spaces.
- *
- * @param[in] s The address of the string pointer to update.
- * @return String without white spaces.
- */
-static uint32_t ScanIgnoreWhiteSpace(const char **s);
-
-/*!
- * @brief Converts a radix number to a string and return its length.
- *
- * @param[in] numstr Converted string of the number.
- * @param[in] nump Pointer to the number.
- * @param[in] neg Polarity of the number.
- * @param[in] radix The radix to be converted to.
- * @param[in] use_caps Used to identify %x/X output format.
-
- * @return Length of the converted string.
- */
-static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);
-
-#if PRINTF_FLOAT_ENABLE
-/*!
- * @brief Converts a floating radix number to a string and return its length.
- *
- * @param[in] numstr Converted string of the number.
- * @param[in] nump Pointer to the number.
- * @param[in] radix The radix to be converted to.
- * @param[in] precision_width Specify the precision width.
-
- * @return Length of the converted string.
- */
-static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);
-#endif /* PRINTF_FLOAT_ENABLE */
-
-/*!
- *
- */
-double modf(double input_dbl, double *intpart_ptr);
-
-/*************Code for process formatted data*******************************/
-
-static uint32_t ScanIgnoreWhiteSpace(const char **s)
-{
- uint8_t count = 0;
- uint8_t c;
-
- c = **s;
- while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))
- {
- count++;
- (*s)++;
- c = **s;
- }
- return count;
-}
-
-static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)
-{
-#if PRINTF_ADVANCED_ENABLE
- int64_t a;
- int64_t b;
- int64_t c;
-
- uint64_t ua;
- uint64_t ub;
- uint64_t uc;
-#else
- int32_t a;
- int32_t b;
- int32_t c;
-
- uint32_t ua;
- uint32_t ub;
- uint32_t uc;
-#endif /* PRINTF_ADVANCED_ENABLE */
-
- int32_t nlen;
- char *nstrp;
-
- nlen = 0;
- nstrp = numstr;
- *nstrp++ = '\0';
-
- if (neg)
- {
-#if PRINTF_ADVANCED_ENABLE
- a = *(int64_t *)nump;
-#else
- a = *(int32_t *)nump;
-#endif /* PRINTF_ADVANCED_ENABLE */
- if (a == 0)
- {
- *nstrp = '0';
- ++nlen;
- return nlen;
- }
- while (a != 0)
- {
-#if PRINTF_ADVANCED_ENABLE
- b = (int64_t)a / (int64_t)radix;
- c = (int64_t)a - ((int64_t)b * (int64_t)radix);
- if (c < 0)
- {
- uc = (uint64_t)c;
- c = (int64_t)(~uc) + 1 + '0';
- }
-#else
- b = a / radix;
- c = a - (b * radix);
- if (c < 0)
- {
- uc = (uint32_t)c;
- c = (uint32_t)(~uc) + 1 + '0';
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- else
- {
- c = c + '0';
- }
- a = b;
- *nstrp++ = (char)c;
- ++nlen;
- }
- }
- else
- {
-#if PRINTF_ADVANCED_ENABLE
- ua = *(uint64_t *)nump;
-#else
- ua = *(uint32_t *)nump;
-#endif /* PRINTF_ADVANCED_ENABLE */
- if (ua == 0)
- {
- *nstrp = '0';
- ++nlen;
- return nlen;
- }
- while (ua != 0)
- {
-#if PRINTF_ADVANCED_ENABLE
- ub = (uint64_t)ua / (uint64_t)radix;
- uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);
-#else
- ub = ua / (uint32_t)radix;
- uc = ua - (ub * (uint32_t)radix);
-#endif /* PRINTF_ADVANCED_ENABLE */
-
- if (uc < 10)
- {
- uc = uc + '0';
- }
- else
- {
- uc = uc - 10 + (use_caps ? 'A' : 'a');
- }
- ua = ub;
- *nstrp++ = (char)uc;
- ++nlen;
- }
- }
- return nlen;
-}
-
-#if PRINTF_FLOAT_ENABLE
-static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)
-{
- int32_t a;
- int32_t b;
- int32_t c;
- int32_t i;
- uint32_t uc;
- double fa;
- double dc;
- double fb;
- double r;
- double fractpart;
- double intpart;
-
- int32_t nlen;
- char *nstrp;
- nlen = 0;
- nstrp = numstr;
- *nstrp++ = '\0';
- r = *(double *)nump;
- if (!r)
- {
- *nstrp = '0';
- ++nlen;
- return nlen;
- }
- fractpart = modf((double)r, (double *)&intpart);
- /* Process fractional part. */
- for (i = 0; i < precision_width; i++)
- {
- fractpart *= radix;
- }
- if (r >= 0)
- {
- fa = fractpart + (double)0.5;
- if (fa >= pow(10, precision_width))
- {
- intpart++;
- }
- }
- else
- {
- fa = fractpart - (double)0.5;
- if (fa <= -pow(10, precision_width))
- {
- intpart--;
- }
- }
- for (i = 0; i < precision_width; i++)
- {
- fb = fa / (int32_t)radix;
- dc = (fa - (int64_t)fb * (int32_t)radix);
- c = (int32_t)dc;
- if (c < 0)
- {
- uc = (uint32_t)c;
- c = (int32_t)(~uc) + 1 + '0';
- }
- else
- {
- c = c + '0';
- }
- fa = fb;
- *nstrp++ = (char)c;
- ++nlen;
- }
- *nstrp++ = (char)'.';
- ++nlen;
- a = (int32_t)intpart;
- if (a == 0)
- {
- *nstrp++ = '0';
- ++nlen;
- }
- else
- {
- while (a != 0)
- {
- b = (int32_t)a / (int32_t)radix;
- c = (int32_t)a - ((int32_t)b * (int32_t)radix);
- if (c < 0)
- {
- uc = (uint32_t)c;
- c = (int32_t)(~uc) + 1 + '0';
- }
- else
- {
- c = c + '0';
- }
- a = b;
- *nstrp++ = (char)c;
- ++nlen;
- }
- }
- return nlen;
-}
-#endif /* PRINTF_FLOAT_ENABLE */
-
-/*!
- * brief This function outputs its parameters according to a formatted string.
- *
- * note I/O is performed by calling given function pointer using following
- * (*func_ptr)(c);
- *
- * param[in] fmt_ptr Format string for printf.
- * param[in] args_ptr Arguments to printf.
- * param[in] buf pointer to the buffer
- * param cb print callback function pointer
- *
- * return Number of characters to be print
- */
-int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)
-{
- /* va_list ap; */
- char *p;
- int32_t c;
-
- char vstr[33];
- char *vstrp = NULL;
- int32_t vlen = 0;
-
- int32_t done;
- int32_t count = 0;
-
- uint32_t field_width;
- uint32_t precision_width;
- char *sval;
- int32_t cval;
- bool use_caps;
- uint8_t radix = 0;
-
-#if PRINTF_ADVANCED_ENABLE
- uint32_t flags_used;
- int32_t schar, dschar;
- int64_t ival;
- uint64_t uval = 0;
- bool valid_precision_width;
-#else
- int32_t ival;
- uint32_t uval = 0;
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-#if PRINTF_FLOAT_ENABLE
- double fval;
-#endif /* PRINTF_FLOAT_ENABLE */
-
- /* Start parsing apart the format string and display appropriate formats and data. */
- for (p = (char *)fmt; (c = *p) != 0; p++)
- {
- /*
- * All formats begin with a '%' marker. Special chars like
- * '\n' or '\t' are normally converted to the appropriate
- * character by the __compiler__. Thus, no need for this
- * routine to account for the '\' character.
- */
- if (c != '%')
- {
- cb(buf, &count, c, 1);
- /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */
- continue;
- }
-
- use_caps = true;
-
-#if PRINTF_ADVANCED_ENABLE
- /* First check for specification modifier flags. */
- flags_used = 0;
- done = false;
- while (!done)
- {
- switch (*++p)
- {
- case '-':
- flags_used |= kPRINTF_Minus;
- break;
- case '+':
- flags_used |= kPRINTF_Plus;
- break;
- case ' ':
- flags_used |= kPRINTF_Space;
- break;
- case '0':
- flags_used |= kPRINTF_Zero;
- break;
- case '#':
- flags_used |= kPRINTF_Pound;
- break;
- default:
- /* We've gone one char too far. */
- --p;
- done = true;
- break;
- }
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
-
- /* Next check for minimum field width. */
- field_width = 0;
- done = false;
- while (!done)
- {
- c = *++p;
- if ((c >= '0') && (c <= '9'))
- {
- field_width = (field_width * 10) + (c - '0');
- }
-#if PRINTF_ADVANCED_ENABLE
- else if (c == '*')
- {
- field_width = (uint32_t)va_arg(ap, uint32_t);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- else
- {
- /* We've gone one char too far. */
- --p;
- done = true;
- }
- }
- /* Next check for the width and precision field separator. */
- precision_width = 6;
-#if PRINTF_ADVANCED_ENABLE
- valid_precision_width = false;
-#endif /* PRINTF_ADVANCED_ENABLE */
- if (*++p == '.')
- {
- /* Must get precision field width, if present. */
- precision_width = 0;
- done = false;
- while (!done)
- {
- c = *++p;
- if ((c >= '0') && (c <= '9'))
- {
- precision_width = (precision_width * 10) + (c - '0');
-#if PRINTF_ADVANCED_ENABLE
- valid_precision_width = true;
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-#if PRINTF_ADVANCED_ENABLE
- else if (c == '*')
- {
- precision_width = (uint32_t)va_arg(ap, uint32_t);
- valid_precision_width = true;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- else
- {
- /* We've gone one char too far. */
- --p;
- done = true;
- }
- }
- }
- else
- {
- /* We've gone one char too far. */
- --p;
- }
-#if PRINTF_ADVANCED_ENABLE
- /*
- * Check for the length modifier.
- */
- switch (/* c = */ *++p)
- {
- case 'h':
- if (*++p != 'h')
- {
- flags_used |= kPRINTF_LengthShortInt;
- --p;
- }
- else
- {
- flags_used |= kPRINTF_LengthChar;
- }
- break;
- case 'l':
- if (*++p != 'l')
- {
- flags_used |= kPRINTF_LengthLongInt;
- --p;
- }
- else
- {
- flags_used |= kPRINTF_LengthLongLongInt;
- }
- break;
- default:
- /* we've gone one char too far */
- --p;
- break;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- /* Now we're ready to examine the format. */
- c = *++p;
- {
- if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||
- (c == 'b') || (c == 'p') || (c == 'u'))
- {
- if ((c == 'd') || (c == 'i'))
- {
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_LengthLongLongInt)
- {
- ival = (int64_t)va_arg(ap, int64_t);
- }
- else
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- ival = (int32_t)va_arg(ap, int32_t);
- }
- vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);
- vstrp = &vstr[vlen];
-#if PRINTF_ADVANCED_ENABLE
- if (ival < 0)
- {
- schar = '-';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Plus)
- {
- schar = '+';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Space)
- {
- schar = ' ';
- ++vlen;
- }
- else
- {
- schar = 0;
- }
- }
- }
- dschar = false;
- /* Do the ZERO pad. */
- if (flags_used & kPRINTF_Zero)
- {
- if (schar)
- {
- cb(buf, &count, schar, 1);
- }
- dschar = true;
-
- cb(buf, &count, '0', field_width - vlen);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- cb(buf, &count, ' ', field_width - vlen);
- if (schar)
- {
- cb(buf, &count, schar, 1);
- }
- dschar = true;
- }
- }
- /* The string was built in reverse order, now display in correct order. */
- if ((!dschar) && schar)
- {
- cb(buf, &count, schar, 1);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-
-#if PRINTF_FLOAT_ENABLE
- if ((c == 'f') || (c == 'F'))
- {
- fval = (double)va_arg(ap, double);
- vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);
- vstrp = &vstr[vlen];
-
-#if PRINTF_ADVANCED_ENABLE
- if (fval < 0)
- {
- schar = '-';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Plus)
- {
- schar = '+';
- ++vlen;
- }
- else
- {
- if (flags_used & kPRINTF_Space)
- {
- schar = ' ';
- ++vlen;
- }
- else
- {
- schar = 0;
- }
- }
- }
- dschar = false;
- if (flags_used & kPRINTF_Zero)
- {
- if (schar)
- {
- cb(buf, &count, schar, 1);
- }
- dschar = true;
- cb(buf, &count, '0', field_width - vlen);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- cb(buf, &count, ' ', field_width - vlen);
- if (schar)
- {
- cb(buf, &count, schar, 1);
- }
- dschar = true;
- }
- }
- if ((!dschar) && schar)
- {
- cb(buf, &count, schar, 1);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-#endif /* PRINTF_FLOAT_ENABLE */
- if ((c == 'X') || (c == 'x'))
- {
- if (c == 'x')
- {
- use_caps = false;
- }
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_LengthLongLongInt)
- {
- uval = (uint64_t)va_arg(ap, uint64_t);
- }
- else
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- uval = (uint32_t)va_arg(ap, uint32_t);
- }
- vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);
- vstrp = &vstr[vlen];
-
-#if PRINTF_ADVANCED_ENABLE
- dschar = false;
- if (flags_used & kPRINTF_Zero)
- {
- if (flags_used & kPRINTF_Pound)
- {
- cb(buf, &count, '0', 1);
- cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
- dschar = true;
- }
- cb(buf, &count, '0', field_width - vlen);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- if (flags_used & kPRINTF_Pound)
- {
- vlen += 2;
- }
- cb(buf, &count, ' ', field_width - vlen);
- if (flags_used & kPRINTF_Pound)
- {
- cb(buf, &count, '0', 1);
- cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
- dschar = true;
- }
- }
- }
-
- if ((flags_used & kPRINTF_Pound) && (!dschar))
- {
- cb(buf, &count, '0', 1);
- cb(buf, &count, (use_caps ? 'X' : 'x'), 1);
- vlen += 2;
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
- if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))
- {
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_LengthLongLongInt)
- {
- uval = (uint64_t)va_arg(ap, uint64_t);
- }
- else
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- uval = (uint32_t)va_arg(ap, uint32_t);
- }
-
- if (c == 'o')
- {
- radix = 8;
- }
- else if (c == 'b')
- {
- radix = 2;
- }
- else if (c == 'p')
- {
- radix = 16;
- }
- else
- {
- radix = 10;
- }
-
- vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);
- vstrp = &vstr[vlen];
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_Zero)
- {
- cb(buf, &count, '0', field_width - vlen);
- vlen = field_width;
- }
- else
- {
- if (!(flags_used & kPRINTF_Minus))
- {
- cb(buf, &count, ' ', field_width - vlen);
- }
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
-#if !PRINTF_ADVANCED_ENABLE
- cb(buf, &count, ' ', field_width - vlen);
-#endif /* !PRINTF_ADVANCED_ENABLE */
- if (vstrp != NULL)
- {
- while (*vstrp)
- {
- cb(buf, &count, *vstrp--, 1);
- }
- }
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_Minus)
- {
- cb(buf, &count, ' ', field_width - vlen);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
- else if (c == 'c')
- {
- cval = (char)va_arg(ap, uint32_t);
- cb(buf, &count, cval, 1);
- }
- else if (c == 's')
- {
- sval = (char *)va_arg(ap, char *);
- if (sval)
- {
-#if PRINTF_ADVANCED_ENABLE
- if (valid_precision_width)
- {
- vlen = precision_width;
- }
- else
- {
- vlen = strlen(sval);
- }
-#else
- vlen = strlen(sval);
-#endif /* PRINTF_ADVANCED_ENABLE */
-#if PRINTF_ADVANCED_ENABLE
- if (!(flags_used & kPRINTF_Minus))
-#endif /* PRINTF_ADVANCED_ENABLE */
- {
- cb(buf, &count, ' ', field_width - vlen);
- }
-
-#if PRINTF_ADVANCED_ENABLE
- if (valid_precision_width)
- {
- while ((*sval) && (vlen > 0))
- {
- cb(buf, &count, *sval++, 1);
- vlen--;
- }
- /* In case that vlen sval is shorter than vlen */
- vlen = precision_width - vlen;
- }
- else
- {
-#endif /* PRINTF_ADVANCED_ENABLE */
- while (*sval)
- {
- cb(buf, &count, *sval++, 1);
- }
-#if PRINTF_ADVANCED_ENABLE
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
-
-#if PRINTF_ADVANCED_ENABLE
- if (flags_used & kPRINTF_Minus)
- {
- cb(buf, &count, ' ', field_width - vlen);
- }
-#endif /* PRINTF_ADVANCED_ENABLE */
- }
- }
- else
- {
- cb(buf, &count, c, 1);
- }
- }
- }
-
- return count;
-}
-
-/*!
- * brief Converts an input line of ASCII characters based upon a provided
- * string format.
- *
- * param[in] line_ptr The input line of ASCII data.
- * param[in] format Format first points to the format string.
- * param[in] args_ptr The list of parameters.
- *
- * return Number of input items converted and assigned.
- * retval IO_EOF When line_ptr is empty string "".
- */
-int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)
-{
- uint8_t base;
- int8_t neg;
- /* Identifier for the format string. */
- char *c = format;
- char temp;
- char *buf;
- /* Flag telling the conversion specification. */
- uint32_t flag = 0;
- /* Filed width for the matching input streams. */
- uint32_t field_width;
- /* How many arguments are assigned except the suppress. */
- uint32_t nassigned = 0;
- /* How many characters are read from the input streams. */
- uint32_t n_decode = 0;
-
- int32_t val;
-
- const char *s;
- /* Identifier for the input string. */
- const char *p = line_ptr;
-
-#if SCANF_FLOAT_ENABLE
- double fnum = 0.0;
-#endif /* SCANF_FLOAT_ENABLE */
- /* Return EOF error before any conversion. */
- if (*p == '\0')
- {
- return -1;
- }
-
- /* Decode directives. */
- while ((*c) && (*p))
- {
- /* Ignore all white-spaces in the format strings. */
- if (ScanIgnoreWhiteSpace((const char **)&c))
- {
- n_decode += ScanIgnoreWhiteSpace(&p);
- }
- else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))
- {
- /* Ordinary characters. */
- c++;
- if (*p == *c)
- {
- n_decode++;
- p++;
- c++;
- }
- else
- {
- /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.
- * However, it is deserted now. */
- break;
- }
- }
- else
- {
- /* convernsion specification */
- c++;
- /* Reset. */
- flag = 0;
- field_width = 0;
- base = 0;
-
- /* Loop to get full conversion specification. */
- while ((*c) && (!(flag & kSCANF_DestMask)))
- {
- switch (*c)
- {
-#if SCANF_ADVANCED_ENABLE
- case '*':
- if (flag & kSCANF_Suppress)
- {
- /* Match failure. */
- return nassigned;
- }
- flag |= kSCANF_Suppress;
- c++;
- break;
- case 'h':
- if (flag & kSCANF_LengthMask)
- {
- /* Match failure. */
- return nassigned;
- }
-
- if (c[1] == 'h')
- {
- flag |= kSCANF_LengthChar;
- c++;
- }
- else
- {
- flag |= kSCANF_LengthShortInt;
- }
- c++;
- break;
- case 'l':
- if (flag & kSCANF_LengthMask)
- {
- /* Match failure. */
- return nassigned;
- }
-
- if (c[1] == 'l')
- {
- flag |= kSCANF_LengthLongLongInt;
- c++;
- }
- else
- {
- flag |= kSCANF_LengthLongInt;
- }
- c++;
- break;
-#endif /* SCANF_ADVANCED_ENABLE */
-#if SCANF_FLOAT_ENABLE
- case 'L':
- if (flag & kSCANF_LengthMask)
- {
- /* Match failure. */
- return nassigned;
- }
- flag |= kSCANF_LengthLongLongDouble;
- c++;
- break;
-#endif /* SCANF_FLOAT_ENABLE */
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- if (field_width)
- {
- /* Match failure. */
- return nassigned;
- }
- do
- {
- field_width = field_width * 10 + *c - '0';
- c++;
- } while ((*c >= '0') && (*c <= '9'));
- break;
- case 'd':
- base = 10;
- flag |= kSCANF_TypeSinged;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'u':
- base = 10;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'o':
- base = 8;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'x':
- case 'X':
- base = 16;
- flag |= kSCANF_DestInt;
- c++;
- break;
- case 'i':
- base = 0;
- flag |= kSCANF_DestInt;
- c++;
- break;
-#if SCANF_FLOAT_ENABLE
- case 'a':
- case 'A':
- case 'e':
- case 'E':
- case 'f':
- case 'F':
- case 'g':
- case 'G':
- flag |= kSCANF_DestFloat;
- c++;
- break;
-#endif /* SCANF_FLOAT_ENABLE */
- case 'c':
- flag |= kSCANF_DestChar;
- if (!field_width)
- {
- field_width = 1;
- }
- c++;
- break;
- case 's':
- flag |= kSCANF_DestString;
- c++;
- break;
- default:
- return nassigned;
- }
- }
-
- if (!(flag & kSCANF_DestMask))
- {
- /* Format strings are exhausted. */
- return nassigned;
- }
-
- if (!field_width)
- {
- /* Large than length of a line. */
- field_width = 99;
- }
-
- /* Matching strings in input streams and assign to argument. */
- switch (flag & kSCANF_DestMask)
- {
- case kSCANF_DestChar:
- s = (const char *)p;
- buf = va_arg(args_ptr, char *);
- while ((field_width--) && (*p))
- {
- if (!(flag & kSCANF_Suppress))
- {
- *buf++ = *p++;
- }
- else
- {
- p++;
- }
- n_decode++;
- }
-
- if ((!(flag & kSCANF_Suppress)) && (s != p))
- {
- nassigned++;
- }
- break;
- case kSCANF_DestString:
- n_decode += ScanIgnoreWhiteSpace(&p);
- s = p;
- buf = va_arg(args_ptr, char *);
- while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&
- (*p != '\r') && (*p != '\v') && (*p != '\f'))
- {
- if (flag & kSCANF_Suppress)
- {
- p++;
- }
- else
- {
- *buf++ = *p++;
- }
- n_decode++;
- }
-
- if ((!(flag & kSCANF_Suppress)) && (s != p))
- {
- /* Add NULL to end of string. */
- *buf = '\0';
- nassigned++;
- }
- break;
- case kSCANF_DestInt:
- n_decode += ScanIgnoreWhiteSpace(&p);
- s = p;
- val = 0;
- if ((base == 0) || (base == 16))
- {
- if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))
- {
- base = 16;
- if (field_width >= 1)
- {
- p += 2;
- n_decode += 2;
- field_width -= 2;
- }
- }
- }
-
- if (base == 0)
- {
- if (s[0] == '0')
- {
- base = 8;
- }
- else
- {
- base = 10;
- }
- }
-
- neg = 1;
- switch (*p)
- {
- case '-':
- neg = -1;
- n_decode++;
- p++;
- field_width--;
- break;
- case '+':
- neg = 1;
- n_decode++;
- p++;
- field_width--;
- break;
- default:
- break;
- }
-
- while ((*p) && (field_width--))
- {
- if ((*p <= '9') && (*p >= '0'))
- {
- temp = *p - '0';
- }
- else if ((*p <= 'f') && (*p >= 'a'))
- {
- temp = *p - 'a' + 10;
- }
- else if ((*p <= 'F') && (*p >= 'A'))
- {
- temp = *p - 'A' + 10;
- }
- else
- {
- temp = base;
- }
-
- if (temp >= base)
- {
- break;
- }
- else
- {
- val = base * val + temp;
- }
- p++;
- n_decode++;
- }
- val *= neg;
- if (!(flag & kSCANF_Suppress))
- {
-#if SCANF_ADVANCED_ENABLE
- switch (flag & kSCANF_LengthMask)
- {
- case kSCANF_LengthChar:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed char *) = (signed char)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned char *) = (unsigned char)val;
- }
- break;
- case kSCANF_LengthShortInt:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed short *) = (signed short)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned short *) = (unsigned short)val;
- }
- break;
- case kSCANF_LengthLongInt:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed long int *) = (signed long int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;
- }
- break;
- case kSCANF_LengthLongLongInt:
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed long long int *) = (signed long long int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;
- }
- break;
- default:
- /* The default type is the type int. */
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed int *) = (signed int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
- }
- break;
- }
-#else
- /* The default type is the type int. */
- if (flag & kSCANF_TypeSinged)
- {
- *va_arg(args_ptr, signed int *) = (signed int)val;
- }
- else
- {
- *va_arg(args_ptr, unsigned int *) = (unsigned int)val;
- }
-#endif /* SCANF_ADVANCED_ENABLE */
- nassigned++;
- }
- break;
-#if SCANF_FLOAT_ENABLE
- case kSCANF_DestFloat:
- n_decode += ScanIgnoreWhiteSpace(&p);
- fnum = strtod(p, (char **)&s);
-
- if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))
- {
- break;
- }
-
- n_decode += (int)(s) - (int)(p);
- p = s;
- if (!(flag & kSCANF_Suppress))
- {
- if (flag & kSCANF_LengthLongLongDouble)
- {
- *va_arg(args_ptr, double *) = fnum;
- }
- else
- {
- *va_arg(args_ptr, float *) = (float)fnum;
- }
- nassigned++;
- }
- break;
-#endif /* SCANF_FLOAT_ENABLE */
- default:
- return nassigned;
- }
- }
- }
- return nassigned;
-}
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h
index 07da887da..2641e1b48 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject
index a2eef507f..d85e820da 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject
@@ -1,8 +1,8 @@
-
-
+
+
-
-
-
-
-
+
+
+
+
+
-
-
-
+
+
-
+
-
-
-
+
+
-
-
-
+
+
-
-
+
-
+
-
-
-
+
+
-
+
-
+
-
+
-
+
-
-
+
@@ -313,20 +356,14 @@
-
-
-
-
-
+
-
+
@@ -334,8 +371,8 @@
SDK_2.x_LPCXpresso55S69
FreeRTOSDemo_ns
- 2.7.1
- platform.drivers.lpc_iocon.LPC55S69;platform.drivers.common.LPC55S69;platform.drivers.clock.LPC55S69;platform.drivers.power.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.Include_core_cm33.LPC55S69;platform.Include_common.LPC55S69;platform.Include_dsp.LPC55S69;platform.drivers.reset.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;platform.utilities.assert.LPC55S69;utility.debug_console.LPC55S69;component.serial_manager.LPC55S69;component.lists.LPC55S69;component.usart_adapter.LPC55S69;component.serial_manager_uart.LPC55S69;platform.utilities.misc_utilities.LPC55S69;FreeRTOSDemo_ns;
+ 2.10.0
+ utility.debug_console_lite.LPC55S69;platform.utilities.assert_lite.LPC55S69;platform.drivers.lpc_iocon.LPC55S69;platform.drivers.common.LPC55S69;platform.drivers.power.LPC55S69;platform.drivers.reset.LPC55S69;platform.drivers.clock.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;component.usart_adapter.LPC55S69;component.lists.LPC55S69;CMSIS_Include_core_cm.LPC55S69;platform.utilities.misc_utilities.LPC55S69;platform.devices.LPC55S69_system.LPC55S69;FreeRTOSDemo_ns;
lpcxpresso55s69
LPC55S69JBD100
cm33
@@ -349,7 +386,7 @@
<info chip="LPC55S69" name="LPC55S69">
<chip>
<name>LPC55S69</name>
-<family>LPC55xx</family>
+<family>LPC55S6x</family>
<vendor>NXP</vendor>
<memory can_program="true" id="Flash" is_ro="true" size="608" type="Flash"/>
<memory id="RAM" size="304" type="RAM"/>
@@ -370,4 +407,4 @@
+
\ No newline at end of file
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project
index aeed0946a..ab84a178b 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.project
@@ -6,6 +6,11 @@
FreeRTOSDemo_s
+
+ org.eclipse.xtext.ui.shared.xtextBuilder
+
+
+
org.eclipse.cdt.managedbuilder.core.genmakebuilder
clean,full,incremental,
@@ -24,6 +29,7 @@
com.nxp.mcuxpresso.core.datamodels.sdkNature
org.eclipse.cdt.managedbuilder.core.managedBuildNature
org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+ org.eclipse.xtext.ui.shared.xtextNature
-
-
+
+
-
-
-
-
-
+
+
+
+
+
-
-
-
+
+
-
+
-
-
-
+
+
-
-
-
+
+
-
-
+
-
+
-
-
-
+
+
-
+
-
+
-
+
-
-
+
@@ -311,20 +352,14 @@
-
-
-
-
-
+
-
+
@@ -332,8 +367,8 @@
SDK_2.x_LPCXpresso55S69
FreeRTOSDemo_s
- 2.7.1
- platform.drivers.power_s.LPC55S69;platform.drivers.common.LPC55S69;platform.drivers.clock.LPC55S69;platform.drivers.power.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.Include_core_cm33.LPC55S69;platform.Include_common.LPC55S69;platform.Include_dsp.LPC55S69;platform.drivers.reset.LPC55S69;platform.drivers.lpc_iocon.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;platform.utilities.assert.LPC55S69;utility.debug_console.LPC55S69;component.serial_manager.LPC55S69;component.lists.LPC55S69;component.usart_adapter.LPC55S69;component.serial_manager_uart.LPC55S69;platform.utilities.misc_utilities.LPC55S69;FreeRTOSDemo_s;
+ 2.10.0
+ platform.drivers.clock.LPC55S69;platform.drivers.power_s.LPC55S69;platform.drivers.common.LPC55S69;utility.debug_console_lite.LPC55S69;platform.utilities.assert_lite.LPC55S69;platform.drivers.lpc_iocon.LPC55S69;platform.drivers.reset.LPC55S69;platform.devices.LPC55S69_CMSIS.LPC55S69;platform.devices.LPC55S69_startup.LPC55S69;platform.drivers.flexcomm_usart.LPC55S69;platform.drivers.flexcomm.LPC55S69;platform.drivers.lpc_gpio.LPC55S69;component.usart_adapter.LPC55S69;component.lists.LPC55S69;CMSIS_Include_core_cm.LPC55S69;platform.utilities.misc_utilities.LPC55S69;platform.devices.LPC55S69_system.LPC55S69;FreeRTOSDemo_s;
lpcxpresso55s69
LPC55S69JBD100
cm33
@@ -347,7 +382,7 @@
<info chip="LPC55S69" name="LPC55S69">
<chip>
<name>LPC55S69</name>
-<family>LPC55xx</family>
+<family>LPC55S6x</family>
<vendor>NXP</vendor>
<memory can_program="true" id="Flash" is_ro="true" size="608" type="Flash"/>
<memory id="RAM" size="304" type="RAM"/>
@@ -367,5 +402,6 @@
</infoList>
</TargetConfig>
+
+
\ No newline at end of file
diff --git a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project
index 812a800cd..fd3bc7a8e 100644
--- a/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project
+++ b/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.project
@@ -5,6 +5,11 @@
+
+ org.eclipse.xtext.ui.shared.xtextBuilder
+
+
+
org.eclipse.cdt.managedbuilder.core.genmakebuilder
clean,full,incremental,
@@ -23,6 +28,7 @@
com.nxp.mcuxpresso.core.datamodels.sdkNature
org.eclipse.cdt.managedbuilder.core.managedBuildNature
org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+ org.eclipse.xtext.ui.shared.xtextNature
@@ -81,228 +81,228 @@ Changes from V4.0.2
#include "BlockQ.h"
#include "print.h"
-#define blckqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE )
-#define blckqNUM_TASK_SETS ( 3 )
+#define blckqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE )
+#define blckqNUM_TASK_SETS ( 3 )
/* Structure used to pass parameters to the blocking queue tasks. */
typedef struct BLOCKING_QUEUE_PARAMETERS
{
- QueueHandle_t xQueue; /*< The queue to be used by the task. */
- TickType_t xBlockTime; /*< The block time to use on queue reads/writes. */
- volatile short *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
+ QueueHandle_t xQueue; /*< The queue to be used by the task. */
+ TickType_t xBlockTime; /*< The block time to use on queue reads/writes. */
+ volatile short * psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
} xBlockingQueueParameters;
/* Task function that creates an incrementing number and posts it on a queue. */
-static void vBlockingQueueProducer( void *pvParameters );
+static void vBlockingQueueProducer( void * pvParameters );
-/* Task function that removes the incrementing number from a queue and checks that
-it is the expected number. */
-static void vBlockingQueueConsumer( void *pvParameters );
+/* Task function that removes the incrementing number from a queue and checks that
+ * it is the expected number. */
+static void vBlockingQueueConsumer( void * pvParameters );
-/* Variables which are incremented each time an item is removed from a queue, and
-found to be the expected value.
-These are used to check that the tasks are still running. */
+/* Variables which are incremented each time an item is removed from a queue, and
+ * found to be the expected value.
+ * These are used to check that the tasks are still running. */
static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
-/* Variable which are incremented each time an item is posted on a queue. These
-are used to check that the tasks are still running. */
+/* Variable which are incremented each time an item is posted on a queue. These
+ * are used to check that the tasks are still running. */
static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
/*-----------------------------------------------------------*/
void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )
{
-xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
-xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
-xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
-const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;
-const TickType_t xBlockTime = ( TickType_t ) 1000 / portTICK_PERIOD_MS;
-const TickType_t xDontBlock = ( TickType_t ) 0;
+ xBlockingQueueParameters * pxQueueParameters1, * pxQueueParameters2;
+ xBlockingQueueParameters * pxQueueParameters3, * pxQueueParameters4;
+ xBlockingQueueParameters * pxQueueParameters5, * pxQueueParameters6;
+ const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;
+ const TickType_t xBlockTime = ( TickType_t ) 1000 / portTICK_PERIOD_MS;
+ const TickType_t xDontBlock = ( TickType_t ) 0;
+
+ /* Create the first two tasks as described at the top of the file. */
- /* Create the first two tasks as described at the top of the file. */
-
- /* First create the structure used to pass parameters to the consumer tasks. */
- pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ /* First create the structure used to pass parameters to the consumer tasks. */
+ pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- /* Create the queue used by the first two tasks to pass the incrementing number.
- Pass a pointer to the queue in the parameter structure. */
- pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+ /* Create the queue used by the first two tasks to pass the incrementing number.
+ * Pass a pointer to the queue in the parameter structure. */
+ pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
- /* The consumer is created first so gets a block time as described above. */
- pxQueueParameters1->xBlockTime = xBlockTime;
+ /* The consumer is created first so gets a block time as described above. */
+ pxQueueParameters1->xBlockTime = xBlockTime;
- /* Pass in the variable that this task is going to increment so we can check it
- is still running. */
- pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
-
- /* Create the structure used to pass parameters to the producer task. */
- pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ /* Pass in the variable that this task is going to increment so we can check it
+ * is still running. */
+ pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
- /* Pass the queue to this task also, using the parameter structure. */
- pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
+ /* Create the structure used to pass parameters to the producer task. */
+ pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- /* The producer is not going to block - as soon as it posts the consumer will
- wake and remove the item so the producer should always have room to post. */
- pxQueueParameters2->xBlockTime = xDontBlock;
+ /* Pass the queue to this task also, using the parameter structure. */
+ pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
- /* Pass in the variable that this task is going to increment so we can check
- it is still running. */
- pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
+ /* The producer is not going to block - as soon as it posts the consumer will
+ * wake and remove the item so the producer should always have room to post. */
+ pxQueueParameters2->xBlockTime = xDontBlock;
+ /* Pass in the variable that this task is going to increment so we can check
+ * it is still running. */
+ pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
- /* Note the producer has a lower priority than the consumer when the tasks are
- spawned. */
- xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
- xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
-
+ /* Note the producer has a lower priority than the consumer when the tasks are
+ * spawned. */
+ xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
+ xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
- /* Create the second two tasks as described at the top of the file. This uses
- the same mechanism but reverses the task priorities. */
- pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
- pxQueueParameters3->xBlockTime = xDontBlock;
- pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
- pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
- pxQueueParameters4->xBlockTime = xBlockTime;
- pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
+ /* Create the second two tasks as described at the top of the file. This uses
+ * the same mechanism but reverses the task priorities. */
- xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
+ pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+ pxQueueParameters3->xBlockTime = xDontBlock;
+ pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
+ pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
+ pxQueueParameters4->xBlockTime = xBlockTime;
+ pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
+ xTaskCreate( vBlockingQueueProducer, "QProdB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vBlockingQueueConsumer, "QConsB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
- /* Create the last two tasks as described above. The mechanism is again just
- the same. This time both parameter structures are given a block time. */
- pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
- pxQueueParameters5->xBlockTime = xBlockTime;
- pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
- pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
- pxQueueParameters6->xBlockTime = xBlockTime;
- pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
- xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
+ /* Create the last two tasks as described above. The mechanism is again just
+ * the same. This time both parameter structures are given a block time. */
+ pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+ pxQueueParameters5->xBlockTime = xBlockTime;
+ pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
+
+ pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
+ pxQueueParameters6->xBlockTime = xBlockTime;
+ pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
+
+ xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
-static void vBlockingQueueProducer( void *pvParameters )
+static void vBlockingQueueProducer( void * pvParameters )
{
-unsigned short usValue = 0;
-xBlockingQueueParameters *pxQueueParameters;
-const char * const pcTaskStartMsg = "Blocking queue producer started.\r\n";
-const char * const pcTaskErrorMsg = "Could not post on blocking queue\r\n";
-short sErrorEverOccurred = pdFALSE;
-
- pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
- {
- vPrintDisplayMessage( &pcTaskErrorMsg );
- sErrorEverOccurred = pdTRUE;
- }
- else
- {
- /* We have successfully posted a message, so increment the variable
- used to check we are still running. */
- if( sErrorEverOccurred == pdFALSE )
- {
- ( *pxQueueParameters->psCheckVariable )++;
- }
-
- /* Increment the variable we are going to post next time round. The
- consumer will expect the numbers to follow in numerical order. */
- ++usValue;
- }
- }
+ unsigned short usValue = 0;
+ xBlockingQueueParameters * pxQueueParameters;
+ const char * const pcTaskStartMsg = "Blocking queue producer started.\r\n";
+ const char * const pcTaskErrorMsg = "Could not post on blocking queue\r\n";
+ short sErrorEverOccurred = pdFALSE;
+
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ if( xQueueSendToBack( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
+ {
+ vPrintDisplayMessage( &pcTaskErrorMsg );
+ sErrorEverOccurred = pdTRUE;
+ }
+ else
+ {
+ /* We have successfully posted a message, so increment the variable
+ * used to check we are still running. */
+ if( sErrorEverOccurred == pdFALSE )
+ {
+ ( *pxQueueParameters->psCheckVariable )++;
+ }
+
+ /* Increment the variable we are going to post next time round. The
+ * consumer will expect the numbers to follow in numerical order. */
+ ++usValue;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void vBlockingQueueConsumer( void *pvParameters )
+static void vBlockingQueueConsumer( void * pvParameters )
{
-unsigned short usData, usExpectedValue = 0;
-xBlockingQueueParameters *pxQueueParameters;
-const char * const pcTaskStartMsg = "Blocking queue consumer started.\r\n";
-const char * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n";
-short sErrorEverOccurred = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
-
- for( ;; )
- {
- if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
- {
- if( usData != usExpectedValue )
- {
- vPrintDisplayMessage( &pcTaskErrorMsg );
-
- /* Catch-up. */
- usExpectedValue = usData;
-
- sErrorEverOccurred = pdTRUE;
- }
- else
- {
- /* We have successfully received a message, so increment the
- variable used to check we are still running. */
- if( sErrorEverOccurred == pdFALSE )
- {
- ( *pxQueueParameters->psCheckVariable )++;
- }
-
- /* Increment the value we expect to remove from the queue next time
- round. */
- ++usExpectedValue;
- }
- }
- }
+ unsigned short usData, usExpectedValue = 0;
+ xBlockingQueueParameters * pxQueueParameters;
+ const char * const pcTaskStartMsg = "Blocking queue consumer started.\r\n";
+ const char * const pcTaskErrorMsg = "Incorrect value received on blocking queue.\r\n";
+ short sErrorEverOccurred = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+ for( ; ; )
+ {
+ if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
+ {
+ if( usData != usExpectedValue )
+ {
+ vPrintDisplayMessage( &pcTaskErrorMsg );
+
+ /* Catch-up. */
+ usExpectedValue = usData;
+
+ sErrorEverOccurred = pdTRUE;
+ }
+ else
+ {
+ /* We have successfully received a message, so increment the
+ * variable used to check we are still running. */
+ if( sErrorEverOccurred == pdFALSE )
+ {
+ ( *pxQueueParameters->psCheckVariable )++;
+ }
+
+ /* Increment the value we expect to remove from the queue next time
+ * round. */
+ ++usExpectedValue;
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreBlockingQueuesStillRunning( void )
{
-static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
-static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
-portBASE_TYPE xReturn = pdPASS, xTasks;
-
- /* Not too worried about mutual exclusion on these variables as they are 16
- bits and we are only reading them. We also only care to see if they have
- changed or not.
-
- Loop through each check variable and return pdFALSE if any are found not
- to have changed since the last call. */
-
- for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
- {
- if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
- {
- xReturn = pdFALSE;
- }
- sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
-
-
- if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
- {
- xReturn = pdFALSE;
- }
- sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
- }
-
- return xReturn;
+ static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
+ static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( short ) 0, ( short ) 0, ( short ) 0 };
+ portBASE_TYPE xReturn = pdPASS, xTasks;
+
+ /* Not too worried about mutual exclusion on these variables as they are 16
+ * bits and we are only reading them. We also only care to see if they have
+ * changed or not.
+ *
+ * Loop through each check variable and return pdFALSE if any are found not
+ * to have changed since the last call. */
+
+ for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
+ {
+ if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
+ {
+ xReturn = pdFALSE;
+ }
+
+ sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
+
+ if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
+ {
+ xReturn = pdFALSE;
+ }
+
+ sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
+ }
+
+ return xReturn;
}
-
diff --git a/Demo/Common/Full/PollQ.c b/Demo/Common/Full/PollQ.c
index 493c9f62e..584a0712b 100644
--- a/Demo/Common/Full/PollQ.c
+++ b/Demo/Common/Full/PollQ.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -27,24 +27,24 @@
/**
- * This is a very simple queue test. See the BlockQ. c documentation for a more
+ * This is a very simple queue test. See the BlockQ. c documentation for a more
* comprehensive version.
*
- * Creates two tasks that communicate over a single queue. One task acts as a
- * producer, the other a consumer.
+ * Creates two tasks that communicate over a single queue. One task acts as a
+ * producer, the other a consumer.
*
- * The producer loops for three iteration, posting an incrementing number onto the
- * queue each cycle. It then delays for a fixed period before doing exactly the
+ * The producer loops for three iteration, posting an incrementing number onto the
+ * queue each cycle. It then delays for a fixed period before doing exactly the
* same again.
*
- * The consumer loops emptying the queue. Each item removed from the queue is
- * checked to ensure it contains the expected value. When the queue is empty it
+ * The consumer loops emptying the queue. Each item removed from the queue is
+ * checked to ensure it contains the expected value. When the queue is empty it
* blocks for a fixed period, then does the same again.
*
- * All queue access is performed without blocking. The consumer completely empties
- * the queue each time it runs so the producer should never find the queue full.
+ * All queue access is performed without blocking. The consumer completely empties
+ * the queue each time it runs so the producer should never find the queue full.
*
- * An error is flagged if the consumer obtains an unexpected value or the producer
+ * An error is flagged if the consumer obtains an unexpected value or the producer
* find the queue is full.
*
* \page PollQC pollQ.c
@@ -53,11 +53,11 @@
*/
/*
-Changes from V2.0.0
-
- + Delay periods are now specified using variables and constants of
- TickType_t rather than unsigned long.
-*/
+ * Changes from V2.0.0
+ *
+ + Delay periods are now specified using variables and constants of
+ + TickType_t rather than unsigned long.
+ */
#include
@@ -70,13 +70,13 @@ Changes from V2.0.0
/* Demo program include files. */
#include "PollQ.h"
-#define pollqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE )
+#define pollqSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE )
/* The task that posts the incrementing number onto the queue. */
-static void vPolledQueueProducer( void *pvParameters );
+static void vPolledQueueProducer( void * pvParameters );
/* The task that empties the queue. */
-static void vPolledQueueConsumer( void *pvParameters );
+static void vPolledQueueConsumer( void * pvParameters );
/* Variables that are used to check that the tasks are still running with no errors. */
static volatile short sPollingConsumerCount = 0, sPollingProducerCount = 0;
@@ -84,137 +84,139 @@ static volatile short sPollingConsumerCount = 0, sPollingProducerCount = 0;
void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )
{
-static QueueHandle_t xPolledQueue;
-const unsigned portBASE_TYPE uxQueueSize = 10;
+ static QueueHandle_t xPolledQueue;
+ const unsigned portBASE_TYPE uxQueueSize = 10;
- /* Create the queue used by the producer and consumer. */
- xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
+ /* Create the queue used by the producer and consumer. */
+ xPolledQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );
- /* Spawn the producer and consumer. */
- xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
- xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
+ /* Spawn the producer and consumer. */
+ xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
+ xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, NULL );
}
/*-----------------------------------------------------------*/
-static void vPolledQueueProducer( void *pvParameters )
+static void vPolledQueueProducer( void * pvParameters )
{
-unsigned short usValue = 0, usLoop;
-QueueHandle_t *pxQueue;
-const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS;
-const unsigned short usNumToProduce = 3;
-const char * const pcTaskStartMsg = "Polled queue producer started.\r\n";
-const char * const pcTaskErrorMsg = "Could not post on polled queue.\r\n";
-short sError = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The queue being used is passed in as the parameter. */
- pxQueue = ( QueueHandle_t * ) pvParameters;
-
- for( ;; )
- {
- for( usLoop = 0; usLoop < usNumToProduce; ++usLoop )
- {
- /* Send an incrementing number on the queue without blocking. */
- if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( TickType_t ) 0 ) != pdPASS )
- {
- /* We should never find the queue full - this is an error. */
- vPrintDisplayMessage( &pcTaskErrorMsg );
- sError = pdTRUE;
- }
- else
- {
- if( sError == pdFALSE )
- {
- /* If an error has ever been recorded we stop incrementing the
- check variable. */
- ++sPollingProducerCount;
- }
-
- /* Update the value we are going to post next time around. */
- ++usValue;
- }
- }
-
- /* Wait before we start posting again to ensure the consumer runs and
- empties the queue. */
- vTaskDelay( xDelay );
- }
+ unsigned short usValue = 0, usLoop;
+ QueueHandle_t * pxQueue;
+ const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS;
+ const unsigned short usNumToProduce = 3;
+ const char * const pcTaskStartMsg = "Polled queue producer started.\r\n";
+ const char * const pcTaskErrorMsg = "Could not post on polled queue.\r\n";
+ short sError = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The queue being used is passed in as the parameter. */
+ pxQueue = ( QueueHandle_t * ) pvParameters;
+
+ for( ; ; )
+ {
+ for( usLoop = 0; usLoop < usNumToProduce; ++usLoop )
+ {
+ /* Send an incrementing number on the queue without blocking. */
+ if( xQueueSendToBack( *pxQueue, ( void * ) &usValue, ( TickType_t ) 0 ) != pdPASS )
+ {
+ /* We should never find the queue full - this is an error. */
+ vPrintDisplayMessage( &pcTaskErrorMsg );
+ sError = pdTRUE;
+ }
+ else
+ {
+ if( sError == pdFALSE )
+ {
+ /* If an error has ever been recorded we stop incrementing the
+ * check variable. */
+ ++sPollingProducerCount;
+ }
+
+ /* Update the value we are going to post next time around. */
+ ++usValue;
+ }
+ }
+
+ /* Wait before we start posting again to ensure the consumer runs and
+ * empties the queue. */
+ vTaskDelay( xDelay );
+ }
}
/*-----------------------------------------------------------*/
-static void vPolledQueueConsumer( void *pvParameters )
+static void vPolledQueueConsumer( void * pvParameters )
{
-unsigned short usData, usExpectedValue = 0;
-QueueHandle_t *pxQueue;
-const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS;
-const char * const pcTaskStartMsg = "Polled queue consumer started.\r\n";
-const char * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n";
-short sError = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The queue being used is passed in as the parameter. */
- pxQueue = ( QueueHandle_t * ) pvParameters;
-
- for( ;; )
- {
- /* Loop until the queue is empty. */
- while( uxQueueMessagesWaiting( *pxQueue ) )
- {
- if( xQueueReceive( *pxQueue, &usData, ( TickType_t ) 0 ) == pdPASS )
- {
- if( usData != usExpectedValue )
- {
- /* This is not what we expected to receive so an error has
- occurred. */
- vPrintDisplayMessage( &pcTaskErrorMsg );
- sError = pdTRUE;
- /* Catch-up to the value we received so our next expected value
- should again be correct. */
- usExpectedValue = usData;
- }
- else
- {
- if( sError == pdFALSE )
- {
- /* Only increment the check variable if no errors have
- occurred. */
- ++sPollingConsumerCount;
- }
- }
- ++usExpectedValue;
- }
- }
-
- /* Now the queue is empty we block, allowing the producer to place more
- items in the queue. */
- vTaskDelay( xDelay );
- }
+ unsigned short usData, usExpectedValue = 0;
+ QueueHandle_t * pxQueue;
+ const TickType_t xDelay = ( TickType_t ) 200 / portTICK_PERIOD_MS;
+ const char * const pcTaskStartMsg = "Polled queue consumer started.\r\n";
+ const char * const pcTaskErrorMsg = "Incorrect value received on polled queue.\r\n";
+ short sError = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The queue being used is passed in as the parameter. */
+ pxQueue = ( QueueHandle_t * ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Loop until the queue is empty. */
+ while( uxQueueMessagesWaiting( *pxQueue ) )
+ {
+ if( xQueueReceive( *pxQueue, &usData, ( TickType_t ) 0 ) == pdPASS )
+ {
+ if( usData != usExpectedValue )
+ {
+ /* This is not what we expected to receive so an error has
+ * occurred. */
+ vPrintDisplayMessage( &pcTaskErrorMsg );
+ sError = pdTRUE;
+
+ /* Catch-up to the value we received so our next expected value
+ * should again be correct. */
+ usExpectedValue = usData;
+ }
+ else
+ {
+ if( sError == pdFALSE )
+ {
+ /* Only increment the check variable if no errors have
+ * occurred. */
+ ++sPollingConsumerCount;
+ }
+ }
+
+ ++usExpectedValue;
+ }
+ }
+
+ /* Now the queue is empty we block, allowing the producer to place more
+ * items in the queue. */
+ vTaskDelay( xDelay );
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running with no errors. */
portBASE_TYPE xArePollingQueuesStillRunning( void )
{
-static short sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0;
-portBASE_TYPE xReturn;
-
- if( ( sLastPollingConsumerCount == sPollingConsumerCount ) ||
- ( sLastPollingProducerCount == sPollingProducerCount )
- )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- sLastPollingConsumerCount = sPollingConsumerCount;
- sLastPollingProducerCount = sPollingProducerCount;
-
- return xReturn;
+ static short sLastPollingConsumerCount = 0, sLastPollingProducerCount = 0;
+ portBASE_TYPE xReturn;
+
+ if( ( sLastPollingConsumerCount == sPollingConsumerCount ) ||
+ ( sLastPollingProducerCount == sPollingProducerCount )
+ )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ sLastPollingConsumerCount = sPollingConsumerCount;
+ sLastPollingProducerCount = sPollingProducerCount;
+
+ return xReturn;
}
diff --git a/Demo/Common/Full/comtest.c b/Demo/Common/Full/comtest.c
index ae731a6e9..233f25b3e 100644
--- a/Demo/Common/Full/comtest.c
+++ b/Demo/Common/Full/comtest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,73 +19,72 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/**
- * Creates two tasks that operate on an interrupt driven serial port. A loopback
- * connector should be used so that everything that is transmitted is also received.
- * The serial port does not use any flow control. On a standard 9way 'D' connector
+ * Creates two tasks that operate on an interrupt driven serial port. A loopback
+ * connector should be used so that everything that is transmitted is also received.
+ * The serial port does not use any flow control. On a standard 9way 'D' connector
* pins two and three should be connected together.
*
- * The first task repeatedly sends a string to a queue, character at a time. The
- * serial port interrupt will empty the queue and transmit the characters. The
+ * The first task repeatedly sends a string to a queue, character at a time. The
+ * serial port interrupt will empty the queue and transmit the characters. The
* task blocks for a pseudo random period before resending the string.
*
- * The second task blocks on a queue waiting for a character to be received.
- * Characters received by the serial port interrupt routine are posted onto the
- * queue - unblocking the task making it ready to execute. If this is then the
- * highest priority task ready to run it will run immediately - with a context
- * switch occurring at the end of the interrupt service routine. The task
- * receiving characters is spawned with a higher priority than the task
+ * The second task blocks on a queue waiting for a character to be received.
+ * Characters received by the serial port interrupt routine are posted onto the
+ * queue - unblocking the task making it ready to execute. If this is then the
+ * highest priority task ready to run it will run immediately - with a context
+ * switch occurring at the end of the interrupt service routine. The task
+ * receiving characters is spawned with a higher priority than the task
* transmitting the characters.
*
- * With the loop back connector in place, one task will transmit a string and the
- * other will immediately receive it. The receiving task knows the string it
+ * With the loop back connector in place, one task will transmit a string and the
+ * other will immediately receive it. The receiving task knows the string it
* expects to receive so can detect an error.
*
* This also creates a third task. This is used to test semaphore usage from an
- * ISR and does nothing interesting.
- *
+ * ISR and does nothing interesting.
+ *
* \page ComTestC comtest.c
* \ingroup DemoFiles
*
@@ -61,143 +60,143 @@ Changes from V2.0.0
#include "death.h"
#include "print.h"
-#define deathSTACK_SIZE ( ( unsigned short ) 512 )
+#define deathSTACK_SIZE ( ( unsigned short ) 512 )
-/* The task originally created which is responsible for periodically dynamically
-creating another four tasks. */
-static void vCreateTasks( void *pvParameters );
+/* The task originally created which is responsible for periodically dynamically
+ * creating another four tasks. */
+static void vCreateTasks( void * pvParameters );
/* The task function of the dynamically created tasks. */
-static void vSuicidalTask( void *pvParameters );
+static void vSuicidalTask( void * pvParameters );
-/* A variable which is incremented every time the dynamic tasks are created. This
-is used to check that the task is still running. */
+/* A variable which is incremented every time the dynamic tasks are created. This
+ * is used to check that the task is still running. */
static volatile short sCreationCount = 0;
-/* Used to store the number of tasks that were originally running so the creator
-task can tell if any of the suicidal tasks have failed to die. */
+/* Used to store the number of tasks that were originally running so the creator
+ * task can tell if any of the suicidal tasks have failed to die. */
static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;
static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 5;
-/* Used to store a handle to the tasks that should be killed by a suicidal task,
-before it kills itself. */
+/* Used to store a handle to the tasks that should be killed by a suicidal task,
+ * before it kills itself. */
TaskHandle_t xCreatedTask1, xCreatedTask2;
/*-----------------------------------------------------------*/
void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )
{
-unsigned portBASE_TYPE *puxPriority;
+ unsigned portBASE_TYPE * puxPriority;
- /* Create the Creator tasks - passing in as a parameter the priority at which
- the suicidal tasks should be created. */
- puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );
- *puxPriority = uxPriority;
+ /* Create the Creator tasks - passing in as a parameter the priority at which
+ * the suicidal tasks should be created. */
+ puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );
+ *puxPriority = uxPriority;
- xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );
+ xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );
- /* Record the number of tasks that are running now so we know if any of the
- suicidal tasks have failed to be killed. */
- uxTasksRunningAtStart = uxTaskGetNumberOfTasks();
+ /* Record the number of tasks that are running now so we know if any of the
+ * suicidal tasks have failed to be killed. */
+ uxTasksRunningAtStart = uxTaskGetNumberOfTasks();
}
/*-----------------------------------------------------------*/
-static void vSuicidalTask( void *pvParameters )
+static void vSuicidalTask( void * pvParameters )
{
-portDOUBLE d1, d2;
-TaskHandle_t xTaskToKill;
-const TickType_t xDelay = ( TickType_t ) 500 / portTICK_PERIOD_MS;
-
- if( pvParameters != NULL )
- {
- /* This task is periodically created four times. Tow created tasks are
- passed a handle to the other task so it can kill it before killing itself.
- The other task is passed in null. */
- xTaskToKill = *( TaskHandle_t* )pvParameters;
- }
- else
- {
- xTaskToKill = NULL;
- }
-
- for( ;; )
- {
- /* Do something random just to use some stack and registers. */
- d1 = 2.4;
- d2 = 89.2;
- d2 *= d1;
- vTaskDelay( xDelay );
-
- if( xTaskToKill != NULL )
- {
- /* Make sure the other task has a go before we delete it. */
- vTaskDelay( ( TickType_t ) 0 );
- /* Kill the other task that was created by vCreateTasks(). */
- vTaskDelete( xTaskToKill );
- /* Kill ourselves. */
- vTaskDelete( NULL );
- }
- }
-}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */
+ portDOUBLE d1, d2;
+ TaskHandle_t xTaskToKill;
+ const TickType_t xDelay = ( TickType_t ) 500 / portTICK_PERIOD_MS;
+
+ if( pvParameters != NULL )
+ {
+ /* This task is periodically created four times. Tow created tasks are
+ * passed a handle to the other task so it can kill it before killing itself.
+ * The other task is passed in null. */
+ xTaskToKill = *( TaskHandle_t * ) pvParameters;
+ }
+ else
+ {
+ xTaskToKill = NULL;
+ }
+
+ for( ; ; )
+ {
+ /* Do something random just to use some stack and registers. */
+ d1 = 2.4;
+ d2 = 89.2;
+ d2 *= d1;
+ vTaskDelay( xDelay );
+
+ if( xTaskToKill != NULL )
+ {
+ /* Make sure the other task has a go before we delete it. */
+ vTaskDelay( ( TickType_t ) 0 );
+ /* Kill the other task that was created by vCreateTasks(). */
+ vTaskDelete( xTaskToKill );
+ /* Kill ourselves. */
+ vTaskDelete( NULL );
+ }
+ }
+} /*lint !e818 !e550 Function prototype must be as per standard for task functions. */
/*-----------------------------------------------------------*/
-static void vCreateTasks( void *pvParameters )
+static void vCreateTasks( void * pvParameters )
{
-const TickType_t xDelay = ( TickType_t ) 1000 / portTICK_PERIOD_MS;
-unsigned portBASE_TYPE uxPriority;
-const char * const pcTaskStartMsg = "Create task started.\r\n";
+ const TickType_t xDelay = ( TickType_t ) 1000 / portTICK_PERIOD_MS;
+ unsigned portBASE_TYPE uxPriority;
+ const char * const pcTaskStartMsg = "Create task started.\r\n";
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
- uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;
- vPortFree( pvParameters );
+ uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;
+ vPortFree( pvParameters );
- for( ;; )
- {
- /* Just loop round, delaying then creating the four suicidal tasks. */
- vTaskDelay( xDelay );
+ for( ; ; )
+ {
+ /* Just loop round, delaying then creating the four suicidal tasks. */
+ vTaskDelay( xDelay );
- xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 );
- xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL );
+ xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask1 );
+ xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask1, uxPriority, NULL );
- xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 );
- xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL );
+ xTaskCreate( vSuicidalTask, "SUICIDE1", deathSTACK_SIZE, NULL, uxPriority, &xCreatedTask2 );
+ xTaskCreate( vSuicidalTask, "SUICIDE2", deathSTACK_SIZE, &xCreatedTask2, uxPriority, NULL );
- ++sCreationCount;
- }
+ ++sCreationCount;
+ }
}
/*-----------------------------------------------------------*/
-/* This is called to check that the creator task is still running and that there
-are not any more than four extra tasks. */
+/* This is called to check that the creator task is still running and that there
+ * are not any more than four extra tasks. */
portBASE_TYPE xIsCreateTaskStillRunning( void )
{
-static short sLastCreationCount = 0;
-short sReturn = pdTRUE;
-unsigned portBASE_TYPE uxTasksRunningNow;
-
- if( sLastCreationCount == sCreationCount )
- {
- sReturn = pdFALSE;
- }
-
- uxTasksRunningNow = uxTaskGetNumberOfTasks();
-
- if( uxTasksRunningNow < uxTasksRunningAtStart )
- {
- sReturn = pdFALSE;
- }
- else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
- {
- sReturn = pdFALSE;
- }
- else
- {
- /* Everything is okay. */
- }
-
- return sReturn;
+ static short sLastCreationCount = 0;
+ short sReturn = pdTRUE;
+ unsigned portBASE_TYPE uxTasksRunningNow;
+
+ if( sLastCreationCount == sCreationCount )
+ {
+ sReturn = pdFALSE;
+ }
+
+ sLastCreationCount = sCreationCount;
+
+ uxTasksRunningNow = uxTaskGetNumberOfTasks();
+
+ if( uxTasksRunningNow < uxTasksRunningAtStart )
+ {
+ sReturn = pdFALSE;
+ }
+ else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
+ {
+ sReturn = pdFALSE;
+ }
+ else
+ {
+ /* Everything is okay. */
+ }
+
+ return sReturn;
}
-
-
diff --git a/Demo/Common/Full/dynamic.c b/Demo/Common/Full/dynamic.c
index c0c4e32e7..31a3d4d6e 100644
--- a/Demo/Common/Full/dynamic.c
+++ b/Demo/Common/Full/dynamic.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,31 +26,31 @@
*/
/**
- * The first test creates three tasks - two counter tasks (one continuous count
- * and one limited count) and one controller. A "count" variable is shared
- * between all three tasks. The two counter tasks should never be in a "ready"
- * state at the same time. The controller task runs at the same priority as
- * the continuous count task, and at a lower priority than the limited count
+ * The first test creates three tasks - two counter tasks (one continuous count
+ * and one limited count) and one controller. A "count" variable is shared
+ * between all three tasks. The two counter tasks should never be in a "ready"
+ * state at the same time. The controller task runs at the same priority as
+ * the continuous count task, and at a lower priority than the limited count
* task.
*
* One counter task loops indefinitely, incrementing the shared count variable
* on each iteration. To ensure it has exclusive access to the variable it
- * raises it's priority above that of the controller task before each
+ * raises it's priority above that of the controller task before each
* increment, lowering it again to it's original priority before starting the
* next iteration.
*
* The other counter task increments the shared count variable on each
* iteration of it's loop until the count has reached a limit of 0xff - at
- * which point it suspends itself. It will not start a new loop until the
- * controller task has made it "ready" again by calling vTaskResume ().
- * This second counter task operates at a higher priority than controller
- * task so does not need to worry about mutual exclusion of the counter
+ * which point it suspends itself. It will not start a new loop until the
+ * controller task has made it "ready" again by calling vTaskResume ().
+ * This second counter task operates at a higher priority than controller
+ * task so does not need to worry about mutual exclusion of the counter
* variable.
*
* The controller task is in two sections. The first section controls and
- * monitors the continuous count task. When this section is operational the
- * limited count task is suspended. Likewise, the second section controls
- * and monitors the limited count task. When this section is operational the
+ * monitors the continuous count task. When this section is operational the
+ * limited count task is suspended. Likewise, the second section controls
+ * and monitors the limited count task. When this section is operational the
* continuous count task is suspended.
*
* In the first section the controller task first takes a copy of the shared
@@ -60,11 +60,11 @@
* the continuous count task will execute and increment the shared variable.
* When the controller task wakes it checks that the continuous count task
* has executed by comparing the copy of the shared variable with its current
- * value. This time, to ensure mutual exclusion, the scheduler itself is
- * suspended with a call to vTaskSuspendAll (). This is for demonstration
+ * value. This time, to ensure mutual exclusion, the scheduler itself is
+ * suspended with a call to vTaskSuspendAll (). This is for demonstration
* purposes only and is not a recommended technique due to its inefficiency.
*
- * After a fixed number of iterations the controller task suspends the
+ * After a fixed number of iterations the controller task suspends the
* continuous count task, and moves on to its second section.
*
* At the start of the second section the shared variable is cleared to zero.
@@ -76,7 +76,7 @@
* a check on the shared variable to ensure everything is as expected.
*
*
- * The second test consists of a couple of very simple tasks that post onto a
+ * The second test consists of a couple of very simple tasks that post onto a
* queue while the scheduler is suspended. This test was added to test parts
* of the scheduler not exercised by the first test.
*
@@ -91,20 +91,20 @@
*/
/*
-Changes from V2.0.0
-
- + Delay periods are now specified using variables and constants of
- TickType_t rather than unsigned long.
- + Added a second, simple test that uses the functions
- vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask().
-
-Changes from V3.1.1
-
- + Added a third simple test that uses the vTaskPrioritySet() function
- while the scheduler is suspended.
- + Modified the controller task slightly to test the calling of
- vTaskResumeAll() while the scheduler is suspended.
-*/
+ * Changes from V2.0.0
+ *
+ + Delay periods are now specified using variables and constants of
+ + TickType_t rather than unsigned long.
+ + Added a second, simple test that uses the functions
+ + vQueueReceiveWhenSuspendedTask() and vQueueSendWhenSuspendedTask().
+ +
+ + Changes from V3.1.1
+ +
+ + Added a third simple test that uses the vTaskPrioritySet() function
+ + while the scheduler is suspended.
+ + Modified the controller task slightly to test the calling of
+ + vTaskResumeAll() while the scheduler is suspended.
+ */
#include
@@ -127,42 +127,42 @@ static void vContinuousIncrementTask( void * pvParameters );
static void vCounterControlTask( void * pvParameters );
/* The simple test functions that check sending and receiving while the
-scheduler is suspended. */
-static void vQueueReceiveWhenSuspendedTask( void *pvParameters );
-static void vQueueSendWhenSuspendedTask( void *pvParameters );
+ * scheduler is suspended. */
+static void vQueueReceiveWhenSuspendedTask( void * pvParameters );
+static void vQueueSendWhenSuspendedTask( void * pvParameters );
/* The simple test functions that check raising and lowering of task priorities
-while the scheduler is suspended. */
-static void prvChangePriorityWhenSuspendedTask( void *pvParameters );
-static void prvChangePriorityHelperTask( void *pvParameters );
+ * while the scheduler is suspended. */
+static void prvChangePriorityWhenSuspendedTask( void * pvParameters );
+static void prvChangePriorityHelperTask( void * pvParameters );
/* Demo task specific constants. */
-#define priSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE )
-#define priSLEEP_TIME ( ( TickType_t ) 50 )
-#define priLOOPS ( 5 )
-#define priMAX_COUNT ( ( unsigned long ) 0xff )
-#define priNO_BLOCK ( ( TickType_t ) 0 )
-#define priSUSPENDED_QUEUE_LENGTH ( 1 )
+#define priSTACK_SIZE ( ( unsigned short ) configMINIMAL_STACK_SIZE )
+#define priSLEEP_TIME ( ( TickType_t ) 50 )
+#define priLOOPS ( 5 )
+#define priMAX_COUNT ( ( unsigned long ) 0xff )
+#define priNO_BLOCK ( ( TickType_t ) 0 )
+#define priSUSPENDED_QUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/* Handles to the two counter tasks. These could be passed in as parameters
-to the controller task to prevent them having to be file scope. */
+ * to the controller task to prevent them having to be file scope. */
static TaskHandle_t xContinuousIncrementHandle, xLimitedIncrementHandle, xChangePriorityWhenSuspendedHandle;
-/* The shared counter variable. This is passed in as a parameter to the two
-counter variables for demonstration purposes. */
+/* The shared counter variable. This is passed in as a parameter to the two
+ * counter variables for demonstration purposes. */
static unsigned long ulCounter;
/* Variable used in a similar way by the test that checks the raising and
-lowering of task priorities while the scheduler is suspended. */
+ * lowering of task priorities while the scheduler is suspended. */
static unsigned long ulPrioritySetCounter;
/* Variables used to check that the tasks are still operating without error.
-Each complete iteration of the controller task increments this variable
-provided no errors have been found. The variable maintaining the same value
-is therefore indication of an error. */
+ * Each complete iteration of the controller task increments this variable
+ * provided no errors have been found. The variable maintaining the same value
+ * is therefore indication of an error. */
static unsigned short usCheckVariable = ( unsigned short ) 0;
static portBASE_TYPE xSuspendedQueueSendError = pdFALSE;
static portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;
@@ -172,49 +172,50 @@ static portBASE_TYPE xPriorityRaiseWhenSuspendedError = pdFALSE;
QueueHandle_t xSuspendedTestQueue;
/*-----------------------------------------------------------*/
+
/*
* Start the seven tasks as described at the top of the file.
* Note that the limited count task is given a higher priority.
*/
void vStartDynamicPriorityTasks( void )
{
- xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) );
- xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
- xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
- xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL );
- xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle );
+ xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) );
+ xTaskCreate( vContinuousIncrementTask, "CONT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
+ xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
+ xTaskCreate( vCounterControlTask, "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_SEND", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RECV", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvChangePriorityWhenSuspendedTask, "1st_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY + 1, NULL );
+ xTaskCreate( prvChangePriorityHelperTask, "2nd_P_CHANGE", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, &xChangePriorityWhenSuspendedHandle );
}
/*-----------------------------------------------------------*/
/*
* Just loops around incrementing the shared variable until the limit has been
- * reached. Once the limit has been reached it suspends itself.
+ * reached. Once the limit has been reached it suspends itself.
*/
static void vLimitedIncrementTask( void * pvParameters )
{
-unsigned long *pulCounter;
-
- /* Take a pointer to the shared variable from the parameters passed into
- the task. */
- pulCounter = ( unsigned long * ) pvParameters;
-
- /* This will run before the control task, so the first thing it does is
- suspend - the control task will resume it when ready. */
- vTaskSuspend( NULL );
-
- for( ;; )
- {
- /* Just count up to a value then suspend. */
- ( *pulCounter )++;
-
- if( *pulCounter >= priMAX_COUNT )
- {
- vTaskSuspend( NULL );
- }
- }
+ unsigned long * pulCounter;
+
+ /* Take a pointer to the shared variable from the parameters passed into
+ * the task. */
+ pulCounter = ( unsigned long * ) pvParameters;
+
+ /* This will run before the control task, so the first thing it does is
+ * suspend - the control task will resume it when ready. */
+ vTaskSuspend( NULL );
+
+ for( ; ; )
+ {
+ /* Just count up to a value then suspend. */
+ ( *pulCounter )++;
+
+ if( *pulCounter >= priMAX_COUNT )
+ {
+ vTaskSuspend( NULL );
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -224,29 +225,29 @@ unsigned long *pulCounter;
*/
static void vContinuousIncrementTask( void * pvParameters )
{
-unsigned long *pulCounter;
-unsigned portBASE_TYPE uxOurPriority;
-
- /* Take a pointer to the shared variable from the parameters passed into
- the task. */
- pulCounter = ( unsigned long * ) pvParameters;
-
- /* Query our priority so we can raise it when exclusive access to the
- shared variable is required. */
- uxOurPriority = uxTaskPriorityGet( NULL );
-
- for( ;; )
- {
- /* Raise our priority above the controller task to ensure a context
- switch does not occur while we are accessing this variable. */
- vTaskPrioritySet( NULL, uxOurPriority + 1 );
- ( *pulCounter )++;
- vTaskPrioritySet( NULL, uxOurPriority );
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
- }
+ unsigned long * pulCounter;
+ unsigned portBASE_TYPE uxOurPriority;
+
+ /* Take a pointer to the shared variable from the parameters passed into
+ * the task. */
+ pulCounter = ( unsigned long * ) pvParameters;
+
+ /* Query our priority so we can raise it when exclusive access to the
+ * shared variable is required. */
+ uxOurPriority = uxTaskPriorityGet( NULL );
+
+ for( ; ; )
+ {
+ /* Raise our priority above the controller task to ensure a context
+ * switch does not occur while we are accessing this variable. */
+ vTaskPrioritySet( NULL, uxOurPriority + 1 );
+ ( *pulCounter )++;
+ vTaskPrioritySet( NULL, uxOurPriority );
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
@@ -255,324 +256,320 @@ unsigned portBASE_TYPE uxOurPriority;
*/
static void vCounterControlTask( void * pvParameters )
{
-unsigned long ulLastCounter;
-short sLoops;
-short sError = pdFALSE;
-const char * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n";
-const char * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n";
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- /* Start with the counter at zero. */
- ulCounter = ( unsigned long ) 0;
-
- /* First section : */
-
- /* Check the continuous count task is running. */
- for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
- {
- /* Suspend the continuous count task so we can take a mirror of the
- shared variable without risk of corruption. */
- vTaskSuspend( xContinuousIncrementHandle );
- ulLastCounter = ulCounter;
- vTaskResume( xContinuousIncrementHandle );
-
- /* Now delay to ensure the other task has processor time. */
- vTaskDelay( priSLEEP_TIME );
-
- /* Check the shared variable again. This time to ensure mutual
- exclusion the whole scheduler will be locked. This is just for
- demo purposes! */
- vTaskSuspendAll();
- {
- if( ulLastCounter == ulCounter )
- {
- /* The shared variable has not changed. There is a problem
- with the continuous count task so flag an error. */
- sError = pdTRUE;
- xTaskResumeAll();
- vPrintDisplayMessage( &pcTaskFailMsg );
- vTaskSuspendAll();
- }
- }
- xTaskResumeAll();
- }
-
-
- /* Second section: */
-
- /* Suspend the continuous counter task so it stops accessing the shared variable. */
- vTaskSuspend( xContinuousIncrementHandle );
-
- /* Reset the variable. */
- ulCounter = ( unsigned long ) 0;
-
- /* Resume the limited count task which has a higher priority than us.
- We should therefore not return from this call until the limited count
- task has suspended itself with a known value in the counter variable.
- The scheduler suspension is not necessary but is included for test
- purposes. */
- vTaskSuspendAll();
- vTaskResume( xLimitedIncrementHandle );
- xTaskResumeAll();
-
- /* Does the counter variable have the expected value? */
- if( ulCounter != priMAX_COUNT )
- {
- sError = pdTRUE;
- vPrintDisplayMessage( &pcTaskFailMsg );
- }
-
- if( sError == pdFALSE )
- {
- /* If no errors have occurred then increment the check variable. */
- portENTER_CRITICAL();
- usCheckVariable++;
- portEXIT_CRITICAL();
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Resume the continuous count task and do it all again. */
- vTaskResume( xContinuousIncrementHandle );
- }
+ unsigned long ulLastCounter;
+ short sLoops;
+ short sError = pdFALSE;
+ const char * const pcTaskStartMsg = "Priority manipulation tasks started.\r\n";
+ const char * const pcTaskFailMsg = "Priority manipulation Task Failed\r\n";
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ /* Start with the counter at zero. */
+ ulCounter = ( unsigned long ) 0;
+
+ /* First section : */
+
+ /* Check the continuous count task is running. */
+ for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
+ {
+ /* Suspend the continuous count task so we can take a mirror of the
+ * shared variable without risk of corruption. */
+ vTaskSuspend( xContinuousIncrementHandle );
+ ulLastCounter = ulCounter;
+ vTaskResume( xContinuousIncrementHandle );
+
+ /* Now delay to ensure the other task has processor time. */
+ vTaskDelay( priSLEEP_TIME );
+
+ /* Check the shared variable again. This time to ensure mutual
+ * exclusion the whole scheduler will be locked. This is just for
+ * demo purposes! */
+ vTaskSuspendAll();
+ {
+ if( ulLastCounter == ulCounter )
+ {
+ /* The shared variable has not changed. There is a problem
+ * with the continuous count task so flag an error. */
+ sError = pdTRUE;
+ xTaskResumeAll();
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ vTaskSuspendAll();
+ }
+ }
+ xTaskResumeAll();
+ }
+
+ /* Second section: */
+
+ /* Suspend the continuous counter task so it stops accessing the shared variable. */
+ vTaskSuspend( xContinuousIncrementHandle );
+
+ /* Reset the variable. */
+ ulCounter = ( unsigned long ) 0;
+
+ /* Resume the limited count task which has a higher priority than us.
+ * We should therefore not return from this call until the limited count
+ * task has suspended itself with a known value in the counter variable.
+ * The scheduler suspension is not necessary but is included for test
+ * purposes. */
+ vTaskSuspendAll();
+ vTaskResume( xLimitedIncrementHandle );
+ xTaskResumeAll();
+
+ /* Does the counter variable have the expected value? */
+ if( ulCounter != priMAX_COUNT )
+ {
+ sError = pdTRUE;
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If no errors have occurred then increment the check variable. */
+ portENTER_CRITICAL();
+ usCheckVariable++;
+ portEXIT_CRITICAL();
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Resume the continuous count task and do it all again. */
+ vTaskResume( xContinuousIncrementHandle );
+ }
}
/*-----------------------------------------------------------*/
-static void vQueueSendWhenSuspendedTask( void *pvParameters )
+static void vQueueSendWhenSuspendedTask( void * pvParameters )
{
-static unsigned long ulValueToSend = ( unsigned long ) 0;
-const char * const pcTaskStartMsg = "Queue send while suspended task started.\r\n";
-const char * const pcTaskFailMsg = "Queue send while suspended failed.\r\n";
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- vTaskSuspendAll();
- {
- /* We must not block while the scheduler is suspended! */
- if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
- {
- if( xSuspendedQueueSendError == pdFALSE )
- {
- xTaskResumeAll();
- vPrintDisplayMessage( &pcTaskFailMsg );
- vTaskSuspendAll();
- }
-
- xSuspendedQueueSendError = pdTRUE;
- }
- }
- xTaskResumeAll();
-
- vTaskDelay( priSLEEP_TIME );
-
- ++ulValueToSend;
- }
+ static unsigned long ulValueToSend = ( unsigned long ) 0;
+ const char * const pcTaskStartMsg = "Queue send while suspended task started.\r\n";
+ const char * const pcTaskFailMsg = "Queue send while suspended failed.\r\n";
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ vTaskSuspendAll();
+ {
+ /* We must not block while the scheduler is suspended! */
+ if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
+ {
+ if( xSuspendedQueueSendError == pdFALSE )
+ {
+ xTaskResumeAll();
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ vTaskSuspendAll();
+ }
+
+ xSuspendedQueueSendError = pdTRUE;
+ }
+ }
+ xTaskResumeAll();
+
+ vTaskDelay( priSLEEP_TIME );
+
+ ++ulValueToSend;
+ }
}
/*-----------------------------------------------------------*/
-static void vQueueReceiveWhenSuspendedTask( void *pvParameters )
+static void vQueueReceiveWhenSuspendedTask( void * pvParameters )
{
-static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue;
-const char * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n";
-const char * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n";
-portBASE_TYPE xGotValue;
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- do
- {
- /* Suspending the scheduler here is fairly pointless and
- undesirable for a normal application. It is done here purely
- to test the scheduler. The inner xTaskResumeAll() should
- never return pdTRUE as the scheduler is still locked by the
- outer call. */
- vTaskSuspendAll();
- {
- vTaskSuspendAll();
- {
- xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
- }
- if( xTaskResumeAll() )
- {
- xSuspendedQueueReceiveError = pdTRUE;
- }
- }
- xTaskResumeAll();
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- } while( xGotValue == pdFALSE );
-
- if( ulReceivedValue != ulExpectedValue )
- {
- if( xSuspendedQueueReceiveError == pdFALSE )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- }
- xSuspendedQueueReceiveError = pdTRUE;
- }
-
- ++ulExpectedValue;
- }
+ static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue;
+ const char * const pcTaskStartMsg = "Queue receive while suspended task started.\r\n";
+ const char * const pcTaskFailMsg = "Queue receive while suspended failed.\r\n";
+ portBASE_TYPE xGotValue;
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ do
+ {
+ /* Suspending the scheduler here is fairly pointless and
+ * undesirable for a normal application. It is done here purely
+ * to test the scheduler. The inner xTaskResumeAll() should
+ * never return pdTRUE as the scheduler is still locked by the
+ * outer call. */
+ vTaskSuspendAll();
+ {
+ vTaskSuspendAll();
+ {
+ xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
+ }
+
+ if( xTaskResumeAll() )
+ {
+ xSuspendedQueueReceiveError = pdTRUE;
+ }
+ }
+ xTaskResumeAll();
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ } while( xGotValue == pdFALSE );
+
+ if( ulReceivedValue != ulExpectedValue )
+ {
+ if( xSuspendedQueueReceiveError == pdFALSE )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ }
+
+ xSuspendedQueueReceiveError = pdTRUE;
+ }
+
+ ++ulExpectedValue;
+ }
}
/*-----------------------------------------------------------*/
-static void prvChangePriorityWhenSuspendedTask( void *pvParameters )
+static void prvChangePriorityWhenSuspendedTask( void * pvParameters )
{
-const char * const pcTaskStartMsg = "Priority change when suspended task started.\r\n";
-const char * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n";
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- /* Start with the counter at 0 so we know what the counter should be
- when we check it next. */
- ulPrioritySetCounter = ( unsigned long ) 0;
-
- /* Resume the helper task. At this time it has a priority lower than
- ours so no context switch should occur. */
- vTaskResume( xChangePriorityWhenSuspendedHandle );
-
- /* Check to ensure the task just resumed has not executed. */
- portENTER_CRITICAL();
- {
- if( ulPrioritySetCounter != ( unsigned long ) 0 )
- {
- xPriorityRaiseWhenSuspendedError = pdTRUE;
- vPrintDisplayMessage( &pcTaskFailMsg );
- }
- }
- portEXIT_CRITICAL();
-
- /* Now try raising the priority while the scheduler is suspended. */
- vTaskSuspendAll();
- {
- vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) );
-
- /* Again, even though the helper task has a priority greater than
- ours, it should not have executed yet because the scheduler is
- suspended. */
- portENTER_CRITICAL();
- {
- if( ulPrioritySetCounter != ( unsigned long ) 0 )
- {
- xPriorityRaiseWhenSuspendedError = pdTRUE;
- vPrintDisplayMessage( &pcTaskFailMsg );
- }
- }
- portEXIT_CRITICAL();
- }
- xTaskResumeAll();
-
- /* Now the scheduler has been resumed the helper task should
- immediately preempt us and execute. When it executes it will increment
- the ulPrioritySetCounter exactly once before suspending itself.
-
- We should now always find the counter set to 1. */
- portENTER_CRITICAL();
- {
- if( ulPrioritySetCounter != ( unsigned long ) 1 )
- {
- xPriorityRaiseWhenSuspendedError = pdTRUE;
- vPrintDisplayMessage( &pcTaskFailMsg );
- }
- }
- portEXIT_CRITICAL();
-
- /* Delay until we try this again. */
- vTaskDelay( priSLEEP_TIME * 2 );
-
- /* Set the priority of the helper task back ready for the next
- execution of this task. */
- vTaskSuspendAll();
- vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY );
- xTaskResumeAll();
- }
+ const char * const pcTaskStartMsg = "Priority change when suspended task started.\r\n";
+ const char * const pcTaskFailMsg = "Priority change when suspended task failed.\r\n";
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ /* Start with the counter at 0 so we know what the counter should be
+ * when we check it next. */
+ ulPrioritySetCounter = ( unsigned long ) 0;
+
+ /* Resume the helper task. At this time it has a priority lower than
+ * ours so no context switch should occur. */
+ vTaskResume( xChangePriorityWhenSuspendedHandle );
+
+ /* Check to ensure the task just resumed has not executed. */
+ portENTER_CRITICAL();
+ {
+ if( ulPrioritySetCounter != ( unsigned long ) 0 )
+ {
+ xPriorityRaiseWhenSuspendedError = pdTRUE;
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ }
+ }
+ portEXIT_CRITICAL();
+
+ /* Now try raising the priority while the scheduler is suspended. */
+ vTaskSuspendAll();
+ {
+ vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, ( configMAX_PRIORITIES - 1 ) );
+
+ /* Again, even though the helper task has a priority greater than
+ * ours, it should not have executed yet because the scheduler is
+ * suspended. */
+ portENTER_CRITICAL();
+ {
+ if( ulPrioritySetCounter != ( unsigned long ) 0 )
+ {
+ xPriorityRaiseWhenSuspendedError = pdTRUE;
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ }
+ }
+ portEXIT_CRITICAL();
+ }
+ xTaskResumeAll();
+
+ /* Now the scheduler has been resumed the helper task should
+ * immediately preempt us and execute. When it executes it will increment
+ * the ulPrioritySetCounter exactly once before suspending itself.
+ *
+ * We should now always find the counter set to 1. */
+ portENTER_CRITICAL();
+ {
+ if( ulPrioritySetCounter != ( unsigned long ) 1 )
+ {
+ xPriorityRaiseWhenSuspendedError = pdTRUE;
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ }
+ }
+ portEXIT_CRITICAL();
+
+ /* Delay until we try this again. */
+ vTaskDelay( priSLEEP_TIME * 2 );
+
+ /* Set the priority of the helper task back ready for the next
+ * execution of this task. */
+ vTaskSuspendAll();
+ vTaskPrioritySet( xChangePriorityWhenSuspendedHandle, tskIDLE_PRIORITY );
+ xTaskResumeAll();
+ }
}
/*-----------------------------------------------------------*/
-static void prvChangePriorityHelperTask( void *pvParameters )
+static void prvChangePriorityHelperTask( void * pvParameters )
{
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* This is the helper task for prvChangePriorityWhenSuspendedTask().
- It has it's priority raised and lowered. When it runs it simply
- increments the counter then suspends itself again. This allows
- prvChangePriorityWhenSuspendedTask() to know how many times it has
- executed. */
- ulPrioritySetCounter++;
- vTaskSuspend( NULL );
- }
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* This is the helper task for prvChangePriorityWhenSuspendedTask().
+ * It has it's priority raised and lowered. When it runs it simply
+ * increments the counter then suspends itself again. This allows
+ * prvChangePriorityWhenSuspendedTask() to know how many times it has
+ * executed. */
+ ulPrioritySetCounter++;
+ vTaskSuspend( NULL );
+ }
}
/*-----------------------------------------------------------*/
/* Called to check that all the created tasks are still running without error. */
portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )
{
-/* Keep a history of the check variables so we know if it has been incremented
-since the last call. */
-static unsigned short usLastTaskCheck = ( unsigned short ) 0;
-portBASE_TYPE xReturn = pdTRUE;
-
- /* Check the tasks are still running by ensuring the check variable
- is still incrementing. */
-
- if( usCheckVariable == usLastTaskCheck )
- {
- /* The check has not incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- if( xSuspendedQueueSendError == pdTRUE )
- {
- xReturn = pdFALSE;
- }
-
- if( xSuspendedQueueReceiveError == pdTRUE )
- {
- xReturn = pdFALSE;
- }
-
- if( xPriorityRaiseWhenSuspendedError == pdTRUE )
- {
- xReturn = pdFALSE;
- }
-
- usLastTaskCheck = usCheckVariable;
- return xReturn;
+/* Keep a history of the check variables so we know if it has been incremented
+ * since the last call. */
+ static unsigned short usLastTaskCheck = ( unsigned short ) 0;
+ portBASE_TYPE xReturn = pdTRUE;
+
+ /* Check the tasks are still running by ensuring the check variable
+ * is still incrementing. */
+
+ if( usCheckVariable == usLastTaskCheck )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ if( xSuspendedQueueSendError == pdTRUE )
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( xSuspendedQueueReceiveError == pdTRUE )
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( xPriorityRaiseWhenSuspendedError == pdTRUE )
+ {
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck = usCheckVariable;
+ return xReturn;
}
-
-
-
-
diff --git a/Demo/Common/Full/events.c b/Demo/Common/Full/events.c
index 2f8791e4f..704432f84 100644
--- a/Demo/Common/Full/events.c
+++ b/Demo/Common/Full/events.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -60,309 +60,310 @@
#include "print.h"
/* Demo specific constants. */
-#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE )
-#define evtNUM_TASKS ( 4 )
-#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 )
-#define evtNO_DELAY 0
+#define evtSTACK_SIZE ( ( unsigned portBASE_TYPE ) configMINIMAL_STACK_SIZE )
+#define evtNUM_TASKS ( 4 )
+#define evtQUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 3 )
+#define evtNO_DELAY 0
/* Just indexes used to uniquely identify the tasks. Note that two tasks are
-'highest' priority. */
-#define evtHIGHEST_PRIORITY_INDEX_2 3
-#define evtHIGHEST_PRIORITY_INDEX_1 2
-#define evtMEDIUM_PRIORITY_INDEX 1
-#define evtLOWEST_PRIORITY_INDEX 0
+ * 'highest' priority. */
+#define evtHIGHEST_PRIORITY_INDEX_2 3
+#define evtHIGHEST_PRIORITY_INDEX_1 2
+#define evtMEDIUM_PRIORITY_INDEX 1
+#define evtLOWEST_PRIORITY_INDEX 0
/* Each event task increments one of these counters each time it reads data
-from the queue. */
+ * from the queue. */
static volatile portBASE_TYPE xTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };
-/* Each time the controlling task posts onto the queue it increments the
-expected count of the task that it expected to read the data from the queue
-(i.e. the task with the highest priority that should be blocked on the queue).
-
-xExpectedTaskCounters are incremented from the controlling task, and
-xTaskCounters are incremented from the individual event tasks - therefore
-comparing xTaskCounters to xExpectedTaskCounters shows whether or not the
-correct task was unblocked by the post. */
+/* Each time the controlling task posts onto the queue it increments the
+ * expected count of the task that it expected to read the data from the queue
+ * (i.e. the task with the highest priority that should be blocked on the queue).
+ *
+ * xExpectedTaskCounters are incremented from the controlling task, and
+ * xTaskCounters are incremented from the individual event tasks - therefore
+ * comparing xTaskCounters to xExpectedTaskCounters shows whether or not the
+ * correct task was unblocked by the post. */
static portBASE_TYPE xExpectedTaskCounters[ evtNUM_TASKS ] = { 0, 0, 0, 0 };
/* Handles to the four event tasks. These are required to suspend and resume
-the tasks. */
+ * the tasks. */
static TaskHandle_t xCreatedTasks[ evtNUM_TASKS ];
/* The single queue onto which the controlling task posts, and the four event
-tasks block. */
+ * tasks block. */
static QueueHandle_t xQueue;
/* Flag used to indicate whether or not an error has occurred at any time.
-An error is either the queue being full when not expected, or an unexpected
-task reading data from the queue. */
+ * An error is either the queue being full when not expected, or an unexpected
+ * task reading data from the queue. */
static portBASE_TYPE xHealthStatus = pdPASS;
/*-----------------------------------------------------------*/
/* Function that implements the event task. This is created four times. */
-static void prvMultiEventTask( void *pvParameters );
+static void prvMultiEventTask( void * pvParameters );
/* Function that implements the controlling task. */
-static void prvEventControllerTask( void *pvParameters );
-
-/* This is a utility function that posts data to the queue, then compares
-xExpectedTaskCounters with xTaskCounters to ensure everything worked as
-expected.
+static void prvEventControllerTask( void * pvParameters );
-The event tasks all have higher priorities the controlling task. Therefore
-the controlling task will always get preempted between writhing to the queue
-and checking the task counters.
-
-@param xExpectedTask The index to the task that the controlling task thinks
- should be the highest priority task waiting for data, and
- therefore the task that will unblock.
-
-@param xIncrement The number of items that should be written to the queue.
-*/
-static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement );
+/* This is a utility function that posts data to the queue, then compares
+ * xExpectedTaskCounters with xTaskCounters to ensure everything worked as
+ * expected.
+ *
+ * The event tasks all have higher priorities the controlling task. Therefore
+ * the controlling task will always get preempted between writhing to the queue
+ * and checking the task counters.
+ *
+ * @param xExpectedTask The index to the task that the controlling task thinks
+ * should be the highest priority task waiting for data, and
+ * therefore the task that will unblock.
+ *
+ * @param xIncrement The number of items that should be written to the queue.
+ */
+static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask,
+ portBASE_TYPE xIncrement );
/* This is just incremented each cycle of the controlling tasks function so
-the main application can ensure the test is still running. */
+ * the main application can ensure the test is still running. */
static portBASE_TYPE xCheckVariable = 0;
/*-----------------------------------------------------------*/
void vStartMultiEventTasks( void )
{
- /* Create the queue to be used for all the communications. */
- xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) );
-
- /* Start the controlling task. This has the idle priority to ensure it is
- always preempted by the event tasks. */
- xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
- /* Start the four event tasks. Note that two have priority 3, one
- priority 2 and the other priority 1. */
- xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) );
- xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) );
- xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) );
- xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) );
+ /* Create the queue to be used for all the communications. */
+ xQueue = xQueueCreate( evtQUEUE_LENGTH, ( unsigned portBASE_TYPE ) sizeof( unsigned portBASE_TYPE ) );
+
+ /* Start the controlling task. This has the idle priority to ensure it is
+ * always preempted by the event tasks. */
+ xTaskCreate( prvEventControllerTask, "EvntCTRL", evtSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+ /* Start the four event tasks. Note that two have priority 3, one
+ * priority 2 and the other priority 1. */
+ xTaskCreate( prvMultiEventTask, "Event0", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 0 ] ), 1, &( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] ) );
+ xTaskCreate( prvMultiEventTask, "Event1", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 1 ] ), 2, &( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] ) );
+ xTaskCreate( prvMultiEventTask, "Event2", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 2 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] ) );
+ xTaskCreate( prvMultiEventTask, "Event3", evtSTACK_SIZE, ( void * ) &( xTaskCounters[ 3 ] ), 3, &( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] ) );
}
/*-----------------------------------------------------------*/
-static void prvMultiEventTask( void *pvParameters )
+static void prvMultiEventTask( void * pvParameters )
{
-portBASE_TYPE *pxCounter;
-unsigned portBASE_TYPE uxDummy;
-const char * const pcTaskStartMsg = "Multi event task started.\r\n";
-
- /* The variable this task will increment is passed in as a parameter. */
- pxCounter = ( portBASE_TYPE * ) pvParameters;
-
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- /* Block on the queue. */
- if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) )
- {
- /* We unblocked by reading the queue - so simply increment
- the counter specific to this task instance. */
- ( *pxCounter )++;
- }
- else
- {
- xHealthStatus = pdFAIL;
- }
- }
+ portBASE_TYPE * pxCounter;
+ unsigned portBASE_TYPE uxDummy;
+ const char * const pcTaskStartMsg = "Multi event task started.\r\n";
+
+ /* The variable this task will increment is passed in as a parameter. */
+ pxCounter = ( portBASE_TYPE * ) pvParameters;
+
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ /* Block on the queue. */
+ if( xQueueReceive( xQueue, &uxDummy, portMAX_DELAY ) )
+ {
+ /* We unblocked by reading the queue - so simply increment
+ * the counter specific to this task instance. */
+ ( *pxCounter )++;
+ }
+ else
+ {
+ xHealthStatus = pdFAIL;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvEventControllerTask( void *pvParameters )
+static void prvEventControllerTask( void * pvParameters )
{
-const char * const pcTaskStartMsg = "Multi event controller task started.\r\n";
-portBASE_TYPE xDummy = 0;
-
- /* Just to stop warnings. */
- ( void ) pvParameters;
-
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- for( ;; )
- {
- /* All tasks are blocked on the queue. When a message is posted one of
- the two tasks that share the highest priority should unblock to read
- the queue. The next message written should unblock the other task with
- the same high priority, and so on in order. No other task should
- unblock to read data as they have lower priorities. */
-
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
-
- /* For the rest of these tests we don't need the second 'highest'
- priority task - so it is suspended. */
- vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
-
-
-
- /* Now suspend the other highest priority task. The medium priority
- task will then be the task with the highest priority that remains
- blocked on the queue. */
- vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
-
- /* This time, when we post onto the queue we will expect the medium
- priority task to unblock and preempt us. */
- prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
-
- /* Now try resuming the highest priority task while the scheduler is
- suspended. The task should start executing as soon as the scheduler
- is resumed - therefore when we post to the queue again, the highest
- priority task should again preempt us. */
- vTaskSuspendAll();
- vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
- xTaskResumeAll();
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
-
- /* Now we are going to suspend the high and medium priority tasks. The
- low priority task should then preempt us. Again the task suspension is
- done with the whole scheduler suspended just for test purposes. */
- vTaskSuspendAll();
- vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
- vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
- xTaskResumeAll();
- prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
-
- /* Do the same basic test another few times - selectively suspending
- and resuming tasks and each time calling prvCheckTaskCounters() passing
- to the function the number of the task we expected to be unblocked by
- the post. */
-
- vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
-
- vTaskSuspendAll(); /* Just for test. */
- vTaskSuspendAll(); /* Just for test. */
- vTaskSuspendAll(); /* Just for even more test. */
- vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
- xTaskResumeAll();
- xTaskResumeAll();
- xTaskResumeAll();
- prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
-
- vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
- prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
-
- vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
- prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
-
- /* Now a slight change, first suspend all tasks. */
- vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
- vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
- vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
-
- /* Now when we resume the low priority task and write to the queue 3
- times. We expect the low priority task to service the queue three
- times. */
- vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
- prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH );
-
- /* Again suspend all tasks (only the low priority task is not suspended
- already). */
- vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
-
- /* This time we are going to suspend the scheduler, resume the low
- priority task, then resume the high priority task. In this state we
- will write to the queue three times. When the scheduler is resumed
- we expect the high priority task to service all three messages. */
- vTaskSuspendAll();
- {
- vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
- vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
-
- for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ )
- {
- if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
- {
- xHealthStatus = pdFAIL;
- }
- }
-
- /* The queue should not have been serviced yet!. The scheduler
- is still suspended. */
- if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
- {
- xHealthStatus = pdFAIL;
- }
- }
- xTaskResumeAll();
-
- /* We should have been preempted by resuming the scheduler - so by the
- time we are running again we expect the high priority task to have
- removed three items from the queue. */
- xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH;
- if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
- {
- xHealthStatus = pdFAIL;
- }
-
- /* The medium priority and second high priority tasks are still
- suspended. Make sure to resume them before starting again. */
- vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
- vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
-
- /* Just keep incrementing to show the task is still executing. */
- xCheckVariable++;
- }
+ const char * const pcTaskStartMsg = "Multi event controller task started.\r\n";
+ portBASE_TYPE xDummy = 0;
+
+ /* Just to stop warnings. */
+ ( void ) pvParameters;
+
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ for( ; ; )
+ {
+ /* All tasks are blocked on the queue. When a message is posted one of
+ * the two tasks that share the highest priority should unblock to read
+ * the queue. The next message written should unblock the other task with
+ * the same high priority, and so on in order. No other task should
+ * unblock to read data as they have lower priorities. */
+
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_2, 1 );
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+
+ /* For the rest of these tests we don't need the second 'highest'
+ * priority task - so it is suspended. */
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
+
+
+
+ /* Now suspend the other highest priority task. The medium priority
+ * task will then be the task with the highest priority that remains
+ * blocked on the queue. */
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+
+ /* This time, when we post onto the queue we will expect the medium
+ * priority task to unblock and preempt us. */
+ prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
+
+ /* Now try resuming the highest priority task while the scheduler is
+ * suspended. The task should start executing as soon as the scheduler
+ * is resumed - therefore when we post to the queue again, the highest
+ * priority task should again preempt us. */
+ vTaskSuspendAll();
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+ xTaskResumeAll();
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+
+ /* Now we are going to suspend the high and medium priority tasks. The
+ * low priority task should then preempt us. Again the task suspension is
+ * done with the whole scheduler suspended just for test purposes. */
+ vTaskSuspendAll();
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+ vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+ xTaskResumeAll();
+ prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
+
+ /* Do the same basic test another few times - selectively suspending
+ * and resuming tasks and each time calling prvCheckTaskCounters() passing
+ * to the function the number of the task we expected to be unblocked by
+ * the post. */
+
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+
+ vTaskSuspendAll(); /* Just for test. */
+ vTaskSuspendAll(); /* Just for test. */
+ vTaskSuspendAll(); /* Just for even more test. */
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+ xTaskResumeAll();
+ xTaskResumeAll();
+ xTaskResumeAll();
+ prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, 1 );
+
+ vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+ prvCheckTaskCounters( evtMEDIUM_PRIORITY_INDEX, 1 );
+
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+ prvCheckTaskCounters( evtHIGHEST_PRIORITY_INDEX_1, 1 );
+
+ /* Now a slight change, first suspend all tasks. */
+ vTaskSuspend( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+ vTaskSuspend( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+ vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+
+ /* Now when we resume the low priority task and write to the queue 3
+ * times. We expect the low priority task to service the queue three
+ * times. */
+ vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+ prvCheckTaskCounters( evtLOWEST_PRIORITY_INDEX, evtQUEUE_LENGTH );
+
+ /* Again suspend all tasks (only the low priority task is not suspended
+ * already). */
+ vTaskSuspend( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+
+ /* This time we are going to suspend the scheduler, resume the low
+ * priority task, then resume the high priority task. In this state we
+ * will write to the queue three times. When the scheduler is resumed
+ * we expect the high priority task to service all three messages. */
+ vTaskSuspendAll();
+ {
+ vTaskResume( xCreatedTasks[ evtLOWEST_PRIORITY_INDEX ] );
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_1 ] );
+
+ for( xDummy = 0; xDummy < evtQUEUE_LENGTH; xDummy++ )
+ {
+ if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
+ {
+ xHealthStatus = pdFAIL;
+ }
+ }
+
+ /* The queue should not have been serviced yet!. The scheduler
+ * is still suspended. */
+ if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
+ {
+ xHealthStatus = pdFAIL;
+ }
+ }
+ xTaskResumeAll();
+
+ /* We should have been preempted by resuming the scheduler - so by the
+ * time we are running again we expect the high priority task to have
+ * removed three items from the queue. */
+ xExpectedTaskCounters[ evtHIGHEST_PRIORITY_INDEX_1 ] += evtQUEUE_LENGTH;
+
+ if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
+ {
+ xHealthStatus = pdFAIL;
+ }
+
+ /* The medium priority and second high priority tasks are still
+ * suspended. Make sure to resume them before starting again. */
+ vTaskResume( xCreatedTasks[ evtMEDIUM_PRIORITY_INDEX ] );
+ vTaskResume( xCreatedTasks[ evtHIGHEST_PRIORITY_INDEX_2 ] );
+
+ /* Just keep incrementing to show the task is still executing. */
+ xCheckVariable++;
+ }
}
/*-----------------------------------------------------------*/
-static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask, portBASE_TYPE xIncrement )
+static void prvCheckTaskCounters( portBASE_TYPE xExpectedTask,
+ portBASE_TYPE xIncrement )
{
-portBASE_TYPE xDummy = 0;
-
- /* Write to the queue the requested number of times. The data written is
- not important. */
- for( xDummy = 0; xDummy < xIncrement; xDummy++ )
- {
- if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
- {
- /* Did not expect to ever find the queue full. */
- xHealthStatus = pdFAIL;
- }
- }
-
- /* All the tasks blocked on the queue have a priority higher than the
- controlling task. Writing to the queue will therefore have caused this
- task to be preempted. By the time this line executes the event task will
- have executed and incremented its counter. Increment the expected counter
- to the same value. */
- ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement;
-
- /* Check the actual counts and expected counts really are the same. */
- if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
- {
- /* The counters were not the same. This means a task we did not expect
- to unblock actually did unblock. */
- xHealthStatus = pdFAIL;
- }
+ portBASE_TYPE xDummy = 0;
+
+ /* Write to the queue the requested number of times. The data written is
+ * not important. */
+ for( xDummy = 0; xDummy < xIncrement; xDummy++ )
+ {
+ if( xQueueSend( xQueue, &xDummy, evtNO_DELAY ) != pdTRUE )
+ {
+ /* Did not expect to ever find the queue full. */
+ xHealthStatus = pdFAIL;
+ }
+ }
+
+ /* All the tasks blocked on the queue have a priority higher than the
+ * controlling task. Writing to the queue will therefore have caused this
+ * task to be preempted. By the time this line executes the event task will
+ * have executed and incremented its counter. Increment the expected counter
+ * to the same value. */
+ ( xExpectedTaskCounters[ xExpectedTask ] ) += xIncrement;
+
+ /* Check the actual counts and expected counts really are the same. */
+ if( memcmp( ( void * ) xExpectedTaskCounters, ( void * ) xTaskCounters, sizeof( xExpectedTaskCounters ) ) )
+ {
+ /* The counters were not the same. This means a task we did not expect
+ * to unblock actually did unblock. */
+ xHealthStatus = pdFAIL;
+ }
}
/*-----------------------------------------------------------*/
portBASE_TYPE xAreMultiEventTasksStillRunning( void )
{
-static portBASE_TYPE xPreviousCheckVariable = 0;
-
- /* Called externally to periodically check that this test is still
- operational. */
-
- if( xPreviousCheckVariable == xCheckVariable )
- {
- xHealthStatus = pdFAIL;
- }
-
- xPreviousCheckVariable = xCheckVariable;
-
- return xHealthStatus;
-}
+ static portBASE_TYPE xPreviousCheckVariable = 0;
+ /* Called externally to periodically check that this test is still
+ * operational. */
+ if( xPreviousCheckVariable == xCheckVariable )
+ {
+ xHealthStatus = pdFAIL;
+ }
+
+ xPreviousCheckVariable = xCheckVariable;
+
+ return xHealthStatus;
+}
diff --git a/Demo/Common/Full/flash.c b/Demo/Common/Full/flash.c
index eb1fc6f56..f5a52246c 100644
--- a/Demo/Common/Full/flash.c
+++ b/Demo/Common/Full/flash.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -27,13 +27,13 @@
/**
- * Creates eight tasks, each of which flash an LED at a different rate. The first
+ * Creates eight tasks, each of which flash an LED at a different rate. The first
* LED flashes every 125ms, the second every 250ms, the third every 375ms, etc.
*
- * The LED flash tasks provide instant visual feedback. They show that the scheduler
+ * The LED flash tasks provide instant visual feedback. They show that the scheduler
* is still operational.
*
- * The PC port uses the standard parallel port for outputs, the Flashlite 186 port
+ * The PC port uses the standard parallel port for outputs, the Flashlite 186 port
* uses IO port F.
*
* \page flashC flash.c
@@ -42,16 +42,16 @@
*/
/*
-Changes from V2.0.0
-
- + Delay periods are now specified using variables and constants of
- TickType_t rather than unsigned long.
-
-Changes from V2.1.1
-
- + The stack size now uses configMINIMAL_STACK_SIZE.
- + String constants made file scope to decrease stack depth on 8051 port.
-*/
+ * Changes from V2.0.0
+ *
+ + Delay periods are now specified using variables and constants of
+ + TickType_t rather than unsigned long.
+ +
+ + Changes from V2.1.1
+ +
+ + The stack size now uses configMINIMAL_STACK_SIZE.
+ + String constants made file scope to decrease stack depth on 8051 port.
+ */
#include
@@ -64,18 +64,18 @@ Changes from V2.1.1
#include "flash.h"
#include "print.h"
-#define ledSTACK_SIZE configMINIMAL_STACK_SIZE
+#define ledSTACK_SIZE configMINIMAL_STACK_SIZE
/* Structure used to pass parameters to the LED tasks. */
typedef struct LED_PARAMETERS
{
- unsigned portBASE_TYPE uxLED; /*< The output the task should use. */
- TickType_t xFlashRate; /*< The rate at which the LED should flash. */
+ unsigned portBASE_TYPE uxLED; /*< The output the task should use. */
+ TickType_t xFlashRate; /*< The rate at which the LED should flash. */
} xLEDParameters;
-/* The task that is created eight times - each time with a different xLEDParaemtes
-structure passed in as the parameter. */
-static void vLEDFlashTask( void *pvParameters );
+/* The task that is created eight times - each time with a different xLEDParaemtes
+ * structure passed in as the parameter. */
+static void vLEDFlashTask( void * pvParameters );
/* String to print if USE_STDIO is defined. */
const char * const pcTaskStartMsg = "LED flash task started.\r\n";
@@ -84,45 +84,44 @@ const char * const pcTaskStartMsg = "LED flash task started.\r\n";
void vStartLEDFlashTasks( unsigned portBASE_TYPE uxPriority )
{
-unsigned portBASE_TYPE uxLEDTask;
-xLEDParameters *pxLEDParameters;
-const unsigned portBASE_TYPE uxNumOfLEDs = 8;
-const TickType_t xFlashRate = 125;
-
- /* Create the eight tasks. */
- for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask )
- {
- /* Create and complete the structure used to pass parameters to the next
- created task. */
- pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) );
- pxLEDParameters->uxLED = uxLEDTask;
- pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( TickType_t ) uxLEDTask ) );
- pxLEDParameters->xFlashRate /= portTICK_PERIOD_MS;
-
- /* Spawn the task. */
- xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( TaskHandle_t * ) NULL );
- }
+ unsigned portBASE_TYPE uxLEDTask;
+ xLEDParameters * pxLEDParameters;
+ const unsigned portBASE_TYPE uxNumOfLEDs = 8;
+ const TickType_t xFlashRate = 125;
+
+ /* Create the eight tasks. */
+ for( uxLEDTask = 0; uxLEDTask < uxNumOfLEDs; ++uxLEDTask )
+ {
+ /* Create and complete the structure used to pass parameters to the next
+ * created task. */
+ pxLEDParameters = ( xLEDParameters * ) pvPortMalloc( sizeof( xLEDParameters ) );
+ pxLEDParameters->uxLED = uxLEDTask;
+ pxLEDParameters->xFlashRate = ( xFlashRate + ( xFlashRate * ( TickType_t ) uxLEDTask ) );
+ pxLEDParameters->xFlashRate /= portTICK_PERIOD_MS;
+
+ /* Spawn the task. */
+ xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, ( void * ) pxLEDParameters, uxPriority, ( TaskHandle_t * ) NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void vLEDFlashTask( void *pvParameters )
+static void vLEDFlashTask( void * pvParameters )
{
-xLEDParameters *pxParameters;
+ xLEDParameters * pxParameters;
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
- pxParameters = ( xLEDParameters * ) pvParameters;
+ pxParameters = ( xLEDParameters * ) pvParameters;
- for(;;)
- {
- /* Delay for half the flash period then turn the LED on. */
- vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 );
- vParTestToggleLED( pxParameters->uxLED );
+ for( ; ; )
+ {
+ /* Delay for half the flash period then turn the LED on. */
+ vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 );
+ vParTestToggleLED( pxParameters->uxLED );
- /* Delay for half the flash period then turn the LED off. */
- vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 );
- vParTestToggleLED( pxParameters->uxLED );
- }
+ /* Delay for half the flash period then turn the LED off. */
+ vTaskDelay( pxParameters->xFlashRate / ( TickType_t ) 2 );
+ vParTestToggleLED( pxParameters->uxLED );
+ }
}
-
diff --git a/Demo/Common/Full/flop.c b/Demo/Common/Full/flop.c
index 382ad0a47..3d43a46b7 100644
--- a/Demo/Common/Full/flop.c
+++ b/Demo/Common/Full/flop.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,22 +26,22 @@
*/
/*
-Changes from V1.2.3
-
- + The created tasks now include calls to tskYIELD(), allowing them to be used
- with the cooperative scheduler.
-*/
+ * Changes from V1.2.3
+ *
+ + The created tasks now include calls to tskYIELD(), allowing them to be used
+ + with the cooperative scheduler.
+ */
/**
- * Creates eight tasks, each of which loops continuously performing an (emulated)
+ * Creates eight tasks, each of which loops continuously performing an (emulated)
* floating point calculation.
*
- * All the tasks run at the idle priority and never block or yield. This causes
- * all eight tasks to time slice with the idle task. Running at the idle priority
+ * All the tasks run at the idle priority and never block or yield. This causes
+ * all eight tasks to time slice with the idle task. Running at the idle priority
* means that these tasks will get pre-empted any time another task is ready to run
- * or a time slice occurs. More often than not the pre-emption will occur mid
- * calculation, creating a good test of the schedulers context switch mechanism - a
- * calculation producing an unexpected result could be a symptom of a corruption in
+ * or a time slice occurs. More often than not the pre-emption will occur mid
+ * calculation, creating a good test of the schedulers context switch mechanism - a
+ * calculation producing an unexpected result could be a symptom of a corruption in
* the context of a task.
*
* \page FlopC flop.c
@@ -60,272 +60,271 @@ Changes from V1.2.3
/* Demo program include files. */
#include "flop.h"
-#define mathSTACK_SIZE ( ( unsigned short ) 512 )
-#define mathNUMBER_OF_TASKS ( 8 )
+#define mathSTACK_SIZE ( ( unsigned short ) 512 )
+#define mathNUMBER_OF_TASKS ( 8 )
-/* Four tasks, each of which performs a different floating point calculation.
-Each of the four is created twice. */
-static void vCompetingMathTask1( void *pvParameters );
-static void vCompetingMathTask2( void *pvParameters );
-static void vCompetingMathTask3( void *pvParameters );
-static void vCompetingMathTask4( void *pvParameters );
+/* Four tasks, each of which performs a different floating point calculation.
+ * Each of the four is created twice. */
+static void vCompetingMathTask1( void * pvParameters );
+static void vCompetingMathTask2( void * pvParameters );
+static void vCompetingMathTask3( void * pvParameters );
+static void vCompetingMathTask4( void * pvParameters );
-/* These variables are used to check that all the tasks are still running. If a
-task gets a calculation wrong it will
-stop incrementing its check variable. */
+/* These variables are used to check that all the tasks are still running. If a
+ * task gets a calculation wrong it will
+ * stop incrementing its check variable. */
static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
/*-----------------------------------------------------------*/
void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
{
- xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
-static void vCompetingMathTask1( void *pvParameters )
+static void vCompetingMathTask1( void * pvParameters )
{
-portDOUBLE d1, d2, d3, d4;
-volatile unsigned short *pusTaskCheckVariable;
-const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222;
-const char * const pcTaskStartMsg = "Math task 1 started.\r\n";
-const char * const pcTaskFailMsg = "Math task 1 failed.\r\n";
-short sError = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for(;;)
- {
- d1 = 123.4567;
- d2 = 2345.6789;
- d3 = -918.222;
-
- d4 = ( d1 + d2 ) * d3;
-
- taskYIELD();
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( fabs( d4 - dAnswer ) > 0.001 )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
-
- taskYIELD();
- }
+ portDOUBLE d1, d2, d3, d4;
+ volatile unsigned short * pusTaskCheckVariable;
+ const portDOUBLE dAnswer = ( 123.4567 + 2345.6789 ) * -918.222;
+ const char * const pcTaskStartMsg = "Math task 1 started.\r\n";
+ const char * const pcTaskFailMsg = "Math task 1 failed.\r\n";
+ short sError = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ d1 = 123.4567;
+ d2 = 2345.6789;
+ d3 = -918.222;
+
+ d4 = ( d1 + d2 ) * d3;
+
+ taskYIELD();
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( fabs( d4 - dAnswer ) > 0.001 )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ taskYIELD();
+ }
}
/*-----------------------------------------------------------*/
-static void vCompetingMathTask2( void *pvParameters )
+static void vCompetingMathTask2( void * pvParameters )
{
-portDOUBLE d1, d2, d3, d4;
-volatile unsigned short *pusTaskCheckVariable;
-const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001;
-const char * const pcTaskStartMsg = "Math task 2 started.\r\n";
-const char * const pcTaskFailMsg = "Math task 2 failed.\r\n";
-short sError = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for( ;; )
- {
- d1 = -389.38;
- d2 = 32498.2;
- d3 = -2.0001;
-
- d4 = ( d1 / d2 ) * d3;
-
- taskYIELD();
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( fabs( d4 - dAnswer ) > 0.001 )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know
- this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
-
- taskYIELD();
- }
+ portDOUBLE d1, d2, d3, d4;
+ volatile unsigned short * pusTaskCheckVariable;
+ const portDOUBLE dAnswer = ( -389.38 / 32498.2 ) * -2.0001;
+ const char * const pcTaskStartMsg = "Math task 2 started.\r\n";
+ const char * const pcTaskFailMsg = "Math task 2 failed.\r\n";
+ short sError = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ d1 = -389.38;
+ d2 = 32498.2;
+ d3 = -2.0001;
+
+ d4 = ( d1 / d2 ) * d3;
+
+ taskYIELD();
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( fabs( d4 - dAnswer ) > 0.001 )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know
+ * this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ taskYIELD();
+ }
}
/*-----------------------------------------------------------*/
-static void vCompetingMathTask3( void *pvParameters )
+static void vCompetingMathTask3( void * pvParameters )
{
-portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
-volatile unsigned short *pusTaskCheckVariable;
-const unsigned short usArraySize = 250;
-unsigned short usPosition;
-const char * const pcTaskStartMsg = "Math task 3 started.\r\n";
-const char * const pcTaskFailMsg = "Math task 3 failed.\r\n";
-short sError = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
-
- /* Keep filling an array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- dTotal1 = 0.0;
- dTotal2 = 0.0;
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5;
- dTotal1 += ( portDOUBLE ) usPosition + 5.5;
- }
-
- taskYIELD();
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- dTotal2 += pdArray[ usPosition ];
- }
-
- dDifference = dTotal1 - dTotal2;
- if( fabs( dDifference ) > 0.001 )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- taskYIELD();
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ portDOUBLE * pdArray, dTotal1, dTotal2, dDifference;
+ volatile unsigned short * pusTaskCheckVariable;
+ const unsigned short usArraySize = 250;
+ unsigned short usPosition;
+ const char * const pcTaskStartMsg = "Math task 3 started.\r\n";
+ const char * const pcTaskFailMsg = "Math task 3 failed.\r\n";
+ short sError = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ dTotal1 = 0.0;
+ dTotal2 = 0.0;
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ pdArray[ usPosition ] = ( portDOUBLE ) usPosition + 5.5;
+ dTotal1 += ( portDOUBLE ) usPosition + 5.5;
+ }
+
+ taskYIELD();
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ dTotal2 += pdArray[ usPosition ];
+ }
+
+ dDifference = dTotal1 - dTotal2;
+
+ if( fabs( dDifference ) > 0.001 )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ taskYIELD();
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void vCompetingMathTask4( void *pvParameters )
+static void vCompetingMathTask4( void * pvParameters )
{
-portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
-volatile unsigned short *pusTaskCheckVariable;
-const unsigned short usArraySize = 250;
-unsigned short usPosition;
-const char * const pcTaskStartMsg = "Math task 4 started.\r\n";
-const char * const pcTaskFailMsg = "Math task 4 failed.\r\n";
-short sError = pdFALSE;
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
-
- /* Keep filling an array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- dTotal1 = 0.0;
- dTotal2 = 0.0;
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123;
- dTotal1 += ( portDOUBLE ) usPosition * 12.123;
- }
-
- taskYIELD();
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- dTotal2 += pdArray[ usPosition ];
- }
-
- dDifference = dTotal1 - dTotal2;
- if( fabs( dDifference ) > 0.001 )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- taskYIELD();
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ portDOUBLE * pdArray, dTotal1, dTotal2, dDifference;
+ volatile unsigned short * pusTaskCheckVariable;
+ const unsigned short usArraySize = 250;
+ unsigned short usPosition;
+ const char * const pcTaskStartMsg = "Math task 4 started.\r\n";
+ const char * const pcTaskFailMsg = "Math task 4 failed.\r\n";
+ short sError = pdFALSE;
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ pdArray = ( portDOUBLE * ) pvPortMalloc( ( size_t ) 250 * sizeof( portDOUBLE ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ dTotal1 = 0.0;
+ dTotal2 = 0.0;
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ pdArray[ usPosition ] = ( portDOUBLE ) usPosition * 12.123;
+ dTotal1 += ( portDOUBLE ) usPosition * 12.123;
+ }
+
+ taskYIELD();
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ dTotal2 += pdArray[ usPosition ];
+ }
+
+ dDifference = dTotal1 - dTotal2;
+
+ if( fabs( dDifference ) > 0.001 )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ taskYIELD();
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreMathsTaskStillRunning( void )
{
-/* Keep a history of the check variables so we know if they have been incremented
-since the last call. */
-static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
-portBASE_TYPE xReturn = pdTRUE, xTask;
-
- /* Check the maths tasks are still running by ensuring their check variables
- are still incrementing. */
- for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
- {
- if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
- {
- /* The check has not incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
- }
-
- return xReturn;
+/* Keep a history of the check variables so we know if they have been incremented
+ * since the last call. */
+ static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+ portBASE_TYPE xReturn = pdTRUE, xTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ * are still incrementing. */
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+ {
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+ }
+
+ return xReturn;
}
-
-
-
diff --git a/Demo/Common/Full/integer.c b/Demo/Common/Full/integer.c
index 49c96949e..2a70fa7d1 100644
--- a/Demo/Common/Full/integer.c
+++ b/Demo/Common/Full/integer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,21 +26,21 @@
*/
/*
-Changes from V1.2.3
-
- + The created tasks now include calls to tskYIELD(), allowing them to be used
- with the cooperative scheduler.
-*/
+ * Changes from V1.2.3
+ *
+ + The created tasks now include calls to tskYIELD(), allowing them to be used
+ + with the cooperative scheduler.
+ */
/**
- * This does the same as flop. c, but uses variables of type long instead of
- * type double.
+ * This does the same as flop. c, but uses variables of type long instead of
+ * type double.
*
- * As with flop. c, the tasks created in this file are a good test of the
- * scheduler context switch mechanism. The processor has to access 32bit
- * variables in two or four chunks (depending on the processor). The low
- * priority of these tasks means there is a high probability that a context
- * switch will occur mid calculation. See the flop. c documentation for
+ * As with flop. c, the tasks created in this file are a good test of the
+ * scheduler context switch mechanism. The processor has to access 32bit
+ * variables in two or four chunks (depending on the processor). The low
+ * priority of these tasks means there is a high probability that a context
+ * switch will occur mid calculation. See the flop. c documentation for
* more information.
*
* \page IntegerC integer.c
@@ -49,11 +49,11 @@ Changes from V1.2.3
*/
/*
-Changes from V1.2.1
-
- + The constants used in the calculations are larger to ensure the
- optimiser does not truncate them to 16 bits.
-*/
+ * Changes from V1.2.1
+ *
+ + The constants used in the calculations are larger to ensure the
+ + optimiser does not truncate them to 16 bits.
+ */
#include
@@ -65,263 +65,262 @@ Changes from V1.2.1
/* Demo program include files. */
#include "integer.h"
-#define intgSTACK_SIZE ( ( unsigned short ) 256 )
-#define intgNUMBER_OF_TASKS ( 8 )
+#define intgSTACK_SIZE ( ( unsigned short ) 256 )
+#define intgNUMBER_OF_TASKS ( 8 )
-/* Four tasks, each of which performs a different calculation on four byte
-variables. Each of the four is created twice. */
-static void vCompeteingIntMathTask1( void *pvParameters );
-static void vCompeteingIntMathTask2( void *pvParameters );
-static void vCompeteingIntMathTask3( void *pvParameters );
-static void vCompeteingIntMathTask4( void *pvParameters );
+/* Four tasks, each of which performs a different calculation on four byte
+ * variables. Each of the four is created twice. */
+static void vCompeteingIntMathTask1( void * pvParameters );
+static void vCompeteingIntMathTask2( void * pvParameters );
+static void vCompeteingIntMathTask3( void * pvParameters );
+static void vCompeteingIntMathTask4( void * pvParameters );
-/* These variables are used to check that all the tasks are still running. If a
-task gets a calculation wrong it will stop incrementing its check variable. */
+/* These variables are used to check that all the tasks are still running. If a
+* task gets a calculation wrong it will stop incrementing its check variable. */
static volatile unsigned short usTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
/*-----------------------------------------------------------*/
void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )
{
- xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
- xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask1, "IntMath1", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask2, "IntMath2", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask3, "IntMath3", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask4, "IntMath4", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask1, "IntMath5", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask2, "IntMath6", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask3, "IntMath7", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+ xTaskCreate( vCompeteingIntMathTask4, "IntMath8", intgSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
-static void vCompeteingIntMathTask1( void *pvParameters )
+static void vCompeteingIntMathTask1( void * pvParameters )
{
-long l1, l2, l3, l4;
-short sError = pdFALSE;
-volatile unsigned short *pusTaskCheckVariable;
-const long lAnswer = ( ( long ) 74565L + ( long ) 1234567L ) * ( long ) -918L;
-const char * const pcTaskStartMsg = "Integer math task 1 started.\r\n";
-const char * const pcTaskFailMsg = "Integer math task 1 failed.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for(;;)
- {
- l1 = ( long ) 74565L;
- l2 = ( long ) 1234567L;
- l3 = ( long ) -918L;
-
- l4 = ( l1 + l2 ) * l3;
-
- taskYIELD();
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( l4 != lAnswer )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ long l1, l2, l3, l4;
+ short sError = pdFALSE;
+ volatile unsigned short * pusTaskCheckVariable;
+ const long lAnswer = ( ( long ) 74565L + ( long ) 1234567L ) * ( long ) -918L;
+ const char * const pcTaskStartMsg = "Integer math task 1 started.\r\n";
+ const char * const pcTaskFailMsg = "Integer math task 1 failed.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ l1 = ( long ) 74565L;
+ l2 = ( long ) 1234567L;
+ l3 = ( long ) -918L;
+
+ l4 = ( l1 + l2 ) * l3;
+
+ taskYIELD();
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( l4 != lAnswer )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void vCompeteingIntMathTask2( void *pvParameters )
+static void vCompeteingIntMathTask2( void * pvParameters )
{
-long l1, l2, l3, l4;
-short sError = pdFALSE;
-volatile unsigned short *pusTaskCheckVariable;
-const long lAnswer = ( ( long ) -389000L / ( long ) 329999L ) * ( long ) -89L;
-const char * const pcTaskStartMsg = "Integer math task 2 started.\r\n";
-const char * const pcTaskFailMsg = "Integer math task 2 failed.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for( ;; )
- {
- l1 = -389000L;
- l2 = 329999L;
- l3 = -89L;
-
- l4 = ( l1 / l2 ) * l3;
-
- taskYIELD();
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( l4 != lAnswer )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ long l1, l2, l3, l4;
+ short sError = pdFALSE;
+ volatile unsigned short * pusTaskCheckVariable;
+ const long lAnswer = ( ( long ) -389000L / ( long ) 329999L ) * ( long ) -89L;
+ const char * const pcTaskStartMsg = "Integer math task 2 started.\r\n";
+ const char * const pcTaskFailMsg = "Integer math task 2 failed.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ l1 = -389000L;
+ l2 = 329999L;
+ l3 = -89L;
+
+ l4 = ( l1 / l2 ) * l3;
+
+ taskYIELD();
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( l4 != lAnswer )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void vCompeteingIntMathTask3( void *pvParameters )
+static void vCompeteingIntMathTask3( void * pvParameters )
{
-long *plArray, lTotal1, lTotal2;
-short sError = pdFALSE;
-volatile unsigned short *pusTaskCheckVariable;
-const unsigned short usArraySize = ( unsigned short ) 250;
-unsigned short usPosition;
-const char * const pcTaskStartMsg = "Integer math task 3 started.\r\n";
-const char * const pcTaskFailMsg = "Integer math task 3 failed.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- /* Create the array we are going to use for our check calculation. */
- plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) );
-
- /* Keep filling the array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- lTotal1 = ( long ) 0;
- lTotal2 = ( long ) 0;
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- plArray[ usPosition ] = ( long ) usPosition + ( long ) 5;
- lTotal1 += ( long ) usPosition + ( long ) 5;
- }
-
- taskYIELD();
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- lTotal2 += plArray[ usPosition ];
- }
-
- if( lTotal1 != lTotal2 )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- taskYIELD();
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ long * plArray, lTotal1, lTotal2;
+ short sError = pdFALSE;
+ volatile unsigned short * pusTaskCheckVariable;
+ const unsigned short usArraySize = ( unsigned short ) 250;
+ unsigned short usPosition;
+ const char * const pcTaskStartMsg = "Integer math task 3 started.\r\n";
+ const char * const pcTaskFailMsg = "Integer math task 3 failed.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Create the array we are going to use for our check calculation. */
+ plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) );
+
+ /* Keep filling the array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ lTotal1 = ( long ) 0;
+ lTotal2 = ( long ) 0;
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ plArray[ usPosition ] = ( long ) usPosition + ( long ) 5;
+ lTotal1 += ( long ) usPosition + ( long ) 5;
+ }
+
+ taskYIELD();
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ lTotal2 += plArray[ usPosition ];
+ }
+
+ if( lTotal1 != lTotal2 )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ taskYIELD();
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void vCompeteingIntMathTask4( void *pvParameters )
+static void vCompeteingIntMathTask4( void * pvParameters )
{
-long *plArray, lTotal1, lTotal2;
-short sError = pdFALSE;
-volatile unsigned short *pusTaskCheckVariable;
-const unsigned short usArraySize = 250;
-unsigned short usPosition;
-const char * const pcTaskStartMsg = "Integer math task 4 started.\r\n";
-const char * const pcTaskFailMsg = "Integer math task 4 failed.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( unsigned short * ) pvParameters;
-
- /* Create the array we are going to use for our check calculation. */
- plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) );
-
- /* Keep filling the array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- lTotal1 = ( long ) 0;
- lTotal2 = ( long ) 0;
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- plArray[ usPosition ] = ( long ) usPosition * ( long ) 12;
- lTotal1 += ( long ) usPosition * ( long ) 12;
- }
-
- taskYIELD();
-
- for( usPosition = 0; usPosition < usArraySize; usPosition++ )
- {
- lTotal2 += plArray[ usPosition ];
- }
-
-
- if( lTotal1 != lTotal2 )
- {
- vPrintDisplayMessage( &pcTaskFailMsg );
- sError = pdTRUE;
- }
-
- taskYIELD();
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ long * plArray, lTotal1, lTotal2;
+ short sError = pdFALSE;
+ volatile unsigned short * pusTaskCheckVariable;
+ const unsigned short usArraySize = 250;
+ unsigned short usPosition;
+ const char * const pcTaskStartMsg = "Integer math task 4 started.\r\n";
+ const char * const pcTaskFailMsg = "Integer math task 4 failed.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Create the array we are going to use for our check calculation. */
+ plArray = ( long * ) pvPortMalloc( ( size_t ) 250 * sizeof( long ) );
+
+ /* Keep filling the array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ lTotal1 = ( long ) 0;
+ lTotal2 = ( long ) 0;
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ plArray[ usPosition ] = ( long ) usPosition * ( long ) 12;
+ lTotal1 += ( long ) usPosition * ( long ) 12;
+ }
+
+ taskYIELD();
+
+ for( usPosition = 0; usPosition < usArraySize; usPosition++ )
+ {
+ lTotal2 += plArray[ usPosition ];
+ }
+
+ if( lTotal1 != lTotal2 )
+ {
+ vPrintDisplayMessage( &pcTaskFailMsg );
+ sError = pdTRUE;
+ }
+
+ taskYIELD();
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )
{
-/* Keep a history of the check variables so we know if they have been incremented
-since the last call. */
-static unsigned short usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
-portBASE_TYPE xReturn = pdTRUE, xTask;
-
- /* Check the maths tasks are still running by ensuring their check variables
- are still incrementing. */
- for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ )
- {
- if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
- {
- /* The check has not incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
- }
-
- return xReturn;
+/* Keep a history of the check variables so we know if they have been incremented
+ * since the last call. */
+ static unsigned short usLastTaskCheck[ intgNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+ portBASE_TYPE xReturn = pdTRUE, xTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ * are still incrementing. */
+ for( xTask = 0; xTask < intgNUMBER_OF_TASKS; xTask++ )
+ {
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+ }
+
+ return xReturn;
}
diff --git a/Demo/Common/Full/print.c b/Demo/Common/Full/print.c
index d4936dedf..0da9ff3e1 100644
--- a/Demo/Common/Full/print.c
+++ b/Demo/Common/Full/print.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,22 +26,22 @@
*/
/**
- * Manages a queue of strings that are waiting to be displayed. This is used to
+ * Manages a queue of strings that are waiting to be displayed. This is used to
* ensure mutual exclusion of console output.
*
- * A task wishing to display a message will call vPrintDisplayMessage (), with a
- * pointer to the string as the parameter. The pointer is posted onto the
+ * A task wishing to display a message will call vPrintDisplayMessage (), with a
+ * pointer to the string as the parameter. The pointer is posted onto the
* xPrintQueue queue.
*
- * The task spawned in main. c blocks on xPrintQueue. When a message becomes
- * available it calls pcPrintGetNextMessage () to obtain a pointer to the next
- * string, then uses the functions defined in the portable layer FileIO. c to
+ * The task spawned in main. c blocks on xPrintQueue. When a message becomes
+ * available it calls pcPrintGetNextMessage () to obtain a pointer to the next
+ * string, then uses the functions defined in the portable layer FileIO. c to
* display the message.
*
* NOTE:
- * Using console IO can disrupt real time performance - depending on the port.
- * Standard C IO routines are not designed for real time applications. While
- * standard IO is useful for demonstration and debugging an alternative method
+ * Using console IO can disrupt real time performance - depending on the port.
+ * Standard C IO routines are not designed for real time applications. While
+ * standard IO is useful for demonstration and debugging an alternative method
* should be used if you actually require console IO as part of your application.
*
* \page PrintC print.c
@@ -50,11 +50,11 @@
*/
/*
-Changes from V2.0.0
-
- + Delay periods are now specified using variables and constants of
- TickType_t rather than unsigned long.
-*/
+ * Changes from V2.0.0
+ *
+ + Delay periods are now specified using variables and constants of
+ + TickType_t rather than unsigned long.
+ */
#include
@@ -71,36 +71,34 @@ static QueueHandle_t xPrintQueue;
void vPrintInitialise( void )
{
-const unsigned portBASE_TYPE uxQueueSize = 20;
+ const unsigned portBASE_TYPE uxQueueSize = 20;
- /* Create the queue on which errors will be reported. */
- xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( char * ) );
+ /* Create the queue on which errors will be reported. */
+ xPrintQueue = xQueueCreate( uxQueueSize, ( unsigned portBASE_TYPE ) sizeof( char * ) );
}
/*-----------------------------------------------------------*/
void vPrintDisplayMessage( const char * const * ppcMessageToSend )
{
- #ifdef USE_STDIO
- xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( TickType_t ) 0 );
- #else
- /* Stop warnings. */
- ( void ) ppcMessageToSend;
- #endif
+ #ifdef USE_STDIO
+ xQueueSend( xPrintQueue, ( void * ) ppcMessageToSend, ( TickType_t ) 0 );
+ #else
+ /* Stop warnings. */
+ ( void ) ppcMessageToSend;
+ #endif
}
/*-----------------------------------------------------------*/
-const char *pcPrintGetNextMessage( TickType_t xPrintRate )
+const char * pcPrintGetNextMessage( TickType_t xPrintRate )
{
-char *pcMessage;
+ char * pcMessage;
- if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS )
- {
- return pcMessage;
- }
- else
- {
- return NULL;
- }
+ if( xQueueReceive( xPrintQueue, &pcMessage, xPrintRate ) == pdPASS )
+ {
+ return pcMessage;
+ }
+ else
+ {
+ return NULL;
+ }
}
-
-
diff --git a/Demo/Common/Full/semtest.c b/Demo/Common/Full/semtest.c
index 369881e40..f71bdf8ca 100644
--- a/Demo/Common/Full/semtest.c
+++ b/Demo/Common/Full/semtest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,24 +26,24 @@
*/
/**
- * Creates two sets of two tasks. The tasks within a set share a variable, access
+ * Creates two sets of two tasks. The tasks within a set share a variable, access
* to which is guarded by a semaphore.
- *
- * Each task starts by attempting to obtain the semaphore. On obtaining a
- * semaphore a task checks to ensure that the guarded variable has an expected
- * value. It then clears the variable to zero before counting it back up to the
- * expected value in increments of 1. After each increment the variable is checked
- * to ensure it contains the value to which it was just set. When the starting
- * value is again reached the task releases the semaphore giving the other task in
- * the set a chance to do exactly the same thing. The starting value is high
+ *
+ * Each task starts by attempting to obtain the semaphore. On obtaining a
+ * semaphore a task checks to ensure that the guarded variable has an expected
+ * value. It then clears the variable to zero before counting it back up to the
+ * expected value in increments of 1. After each increment the variable is checked
+ * to ensure it contains the value to which it was just set. When the starting
+ * value is again reached the task releases the semaphore giving the other task in
+ * the set a chance to do exactly the same thing. The starting value is high
* enough to ensure that a tick is likely to occur during the incrementing loop.
*
- * An error is flagged if at any time during the process a shared variable is
- * found to have a value other than that expected. Such an occurrence would
- * suggest an error in the mutual exclusion mechanism by which access to the
+ * An error is flagged if at any time during the process a shared variable is
+ * found to have a value other than that expected. Such an occurrence would
+ * suggest an error in the mutual exclusion mechanism by which access to the
* variable is restricted.
*
- * The first set of two tasks poll their semaphore. The second set use blocking
+ * The first set of two tasks poll their semaphore. The second set use blocking
* calls.
*
* \page SemTestC semtest.c
@@ -52,24 +52,24 @@
*/
/*
-Changes from V1.2.0:
-
- + The tasks that operate at the idle priority now use a lower expected
- count than those running at a higher priority. This prevents the low
- priority tasks from signaling an error because they have not been
- scheduled enough time for each of them to count the shared variable to
- the high value.
-
-Changes from V2.0.0
-
- + Delay periods are now specified using variables and constants of
- TickType_t rather than unsigned long.
-
-Changes from V2.1.1
-
- + The stack size now uses configMINIMAL_STACK_SIZE.
- + String constants made file scope to decrease stack depth on 8051 port.
-*/
+ * Changes from V1.2.0:
+ *
+ + The tasks that operate at the idle priority now use a lower expected
+ + count than those running at a higher priority. This prevents the low
+ + priority tasks from signaling an error because they have not been
+ + scheduled enough time for each of them to count the shared variable to
+ + the high value.
+ +
+ + Changes from V2.0.0
+ +
+ + Delay periods are now specified using variables and constants of
+ + TickType_t rather than unsigned long.
+ +
+ + Changes from V2.1.1
+ +
+ + The stack size now uses configMINIMAL_STACK_SIZE.
+ + String constants made file scope to decrease stack depth on 8051 port.
+ */
#include
@@ -83,24 +83,24 @@ Changes from V2.1.1
#include "print.h"
/* The value to which the shared variables are counted. */
-#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xfff )
-#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xff )
+#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xfff )
+#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xff )
-#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE
+#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE
-#define semtstNUM_TASKS ( 4 )
+#define semtstNUM_TASKS ( 4 )
-#define semtstDELAY_FACTOR ( ( TickType_t ) 10 )
+#define semtstDELAY_FACTOR ( ( TickType_t ) 10 )
/* The task function as described at the top of the file. */
-static void prvSemaphoreTest( void *pvParameters );
+static void prvSemaphoreTest( void * pvParameters );
/* Structure used to pass parameters to each task. */
typedef struct SEMAPHORE_PARAMETERS
{
- SemaphoreHandle_t xSemaphore;
- volatile unsigned long *pulSharedVariable;
- TickType_t xBlockTime;
+ SemaphoreHandle_t xSemaphore;
+ volatile unsigned long * pulSharedVariable;
+ TickType_t xBlockTime;
} xSemaphoreParameters;
/* Variables used to check that all the tasks are still running without errors. */
@@ -115,171 +115,172 @@ const char * const pcSemaphoreTaskStart = "Guarded shared variable task started.
void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )
{
-xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;
-const TickType_t xBlockTime = ( TickType_t ) 100;
-
- /* Create the structure used to pass parameters to the first two tasks. */
- pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
-
- if( pxFirstSemaphoreParameters != NULL )
- {
- /* Create the semaphore used by the first two tasks. */
- vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );
-
- if( pxFirstSemaphoreParameters->xSemaphore != NULL )
- {
- /* Create the variable which is to be shared by the first two tasks. */
- pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );
-
- /* Initialise the share variable to the value the tasks expect. */
- *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
-
- /* The first two tasks do not block on semaphore calls. */
- pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0;
-
- /* Spawn the first two tasks. As they poll they operate at the idle priority. */
- xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
- xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
- }
- }
-
- /* Do exactly the same to create the second set of tasks, only this time
- provide a block time for the semaphore calls. */
- pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
- if( pxSecondSemaphoreParameters != NULL )
- {
- vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );
-
- if( pxSecondSemaphoreParameters->xSemaphore != NULL )
- {
- pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );
- *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
- pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS;
-
- xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
- xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
- }
- }
+ xSemaphoreParameters * pxFirstSemaphoreParameters, * pxSecondSemaphoreParameters;
+ const TickType_t xBlockTime = ( TickType_t ) 100;
+
+ /* Create the structure used to pass parameters to the first two tasks. */
+ pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+
+ if( pxFirstSemaphoreParameters != NULL )
+ {
+ /* Create the semaphore used by the first two tasks. */
+ vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );
+
+ if( pxFirstSemaphoreParameters->xSemaphore != NULL )
+ {
+ /* Create the variable which is to be shared by the first two tasks. */
+ pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );
+
+ /* Initialise the share variable to the value the tasks expect. */
+ *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
+
+ /* The first two tasks do not block on semaphore calls. */
+ pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0;
+
+ /* Spawn the first two tasks. As they poll they operate at the idle priority. */
+ xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+ xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+ }
+ }
+
+ /* Do exactly the same to create the second set of tasks, only this time
+ * provide a block time for the semaphore calls. */
+ pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+
+ if( pxSecondSemaphoreParameters != NULL )
+ {
+ vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );
+
+ if( pxSecondSemaphoreParameters->xSemaphore != NULL )
+ {
+ pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );
+ *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
+ pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS;
+
+ xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+ xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvSemaphoreTest( void *pvParameters )
+static void prvSemaphoreTest( void * pvParameters )
{
-xSemaphoreParameters *pxParameters;
-volatile unsigned long *pulSharedVariable, ulExpectedValue;
-unsigned long ulCounter;
-short sError = pdFALSE, sCheckVariableToUse;
-
- /* See which check variable to use. sNextCheckVariable is not semaphore
- protected! */
- portENTER_CRITICAL();
- sCheckVariableToUse = sNextCheckVariable;
- sNextCheckVariable++;
- portEXIT_CRITICAL();
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcSemaphoreTaskStart );
-
- /* A structure is passed in as the parameter. This contains the shared
- variable being guarded. */
- pxParameters = ( xSemaphoreParameters * ) pvParameters;
- pulSharedVariable = pxParameters->pulSharedVariable;
-
- /* If we are blocking we use a much higher count to ensure loads of context
- switches occur during the count. */
- if( pxParameters->xBlockTime > ( TickType_t ) 0 )
- {
- ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
- }
- else
- {
- ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
- }
-
- for( ;; )
- {
- /* Try to obtain the semaphore. */
- if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
- {
- /* We have the semaphore and so expect any other tasks using the
- shared variable to have left it in the state we expect to find
- it. */
- if( *pulSharedVariable != ulExpectedValue )
- {
- vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
- sError = pdTRUE;
- }
-
- /* Clear the variable, then count it back up to the expected value
- before releasing the semaphore. Would expect a context switch or
- two during this time. */
- for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
- {
- *pulSharedVariable = ulCounter;
- if( *pulSharedVariable != ulCounter )
- {
- if( sError == pdFALSE )
- {
- vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
- }
- sError = pdTRUE;
- }
- }
-
- /* Release the semaphore, and if no errors have occurred increment the check
- variable. */
- if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
- {
- vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- if( sCheckVariableToUse < semtstNUM_TASKS )
- {
- ( sCheckVariables[ sCheckVariableToUse ] )++;
- }
- }
-
- /* If we have a block time then we are running at a priority higher
- than the idle priority. This task takes a long time to complete
- a cycle (deliberately so to test the guarding) so will be starving
- out lower priority tasks. Block for some time to allow give lower
- priority tasks some processor time. */
- vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
- }
- else
- {
- if( pxParameters->xBlockTime == ( TickType_t ) 0 )
- {
- /* We have not got the semaphore yet, so no point using the
- processor. We are not blocking when attempting to obtain the
- semaphore. */
- taskYIELD();
- }
- }
- }
+ xSemaphoreParameters * pxParameters;
+ volatile unsigned long * pulSharedVariable, ulExpectedValue;
+ unsigned long ulCounter;
+ short sError = pdFALSE, sCheckVariableToUse;
+
+ /* See which check variable to use. sNextCheckVariable is not semaphore
+ * protected! */
+ portENTER_CRITICAL();
+ sCheckVariableToUse = sNextCheckVariable;
+ sNextCheckVariable++;
+ portEXIT_CRITICAL();
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcSemaphoreTaskStart );
+
+ /* A structure is passed in as the parameter. This contains the shared
+ * variable being guarded. */
+ pxParameters = ( xSemaphoreParameters * ) pvParameters;
+ pulSharedVariable = pxParameters->pulSharedVariable;
+
+ /* If we are blocking we use a much higher count to ensure loads of context
+ * switches occur during the count. */
+ if( pxParameters->xBlockTime > ( TickType_t ) 0 )
+ {
+ ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
+ }
+ else
+ {
+ ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
+ }
+
+ for( ; ; )
+ {
+ /* Try to obtain the semaphore. */
+ if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
+ {
+ /* We have the semaphore and so expect any other tasks using the
+ * shared variable to have left it in the state we expect to find
+ * it. */
+ if( *pulSharedVariable != ulExpectedValue )
+ {
+ vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
+ sError = pdTRUE;
+ }
+
+ /* Clear the variable, then count it back up to the expected value
+ * before releasing the semaphore. Would expect a context switch or
+ * two during this time. */
+ for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
+ {
+ *pulSharedVariable = ulCounter;
+
+ if( *pulSharedVariable != ulCounter )
+ {
+ if( sError == pdFALSE )
+ {
+ vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
+ }
+
+ sError = pdTRUE;
+ }
+ }
+
+ /* Release the semaphore, and if no errors have occurred increment the check
+ * variable. */
+ if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
+ {
+ vPrintDisplayMessage( &pcPollingSemaphoreTaskError );
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ if( sCheckVariableToUse < semtstNUM_TASKS )
+ {
+ ( sCheckVariables[ sCheckVariableToUse ] )++;
+ }
+ }
+
+ /* If we have a block time then we are running at a priority higher
+ * than the idle priority. This task takes a long time to complete
+ * a cycle (deliberately so to test the guarding) so will be starving
+ * out lower priority tasks. Block for some time to allow give lower
+ * priority tasks some processor time. */
+ vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
+ }
+ else
+ {
+ if( pxParameters->xBlockTime == ( TickType_t ) 0 )
+ {
+ /* We have not got the semaphore yet, so no point using the
+ * processor. We are not blocking when attempting to obtain the
+ * semaphore. */
+ taskYIELD();
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreSemaphoreTasksStillRunning( void )
{
-static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
-portBASE_TYPE xTask, xReturn = pdTRUE;
+ static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
+ portBASE_TYPE xTask, xReturn = pdTRUE;
- for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
- {
- if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
- {
- xReturn = pdFALSE;
- }
+ for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
+ {
+ if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
+ {
+ xReturn = pdFALSE;
+ }
- sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
- }
+ sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
+ }
- return xReturn;
+ return xReturn;
}
-
-
diff --git a/Demo/Common/Minimal/AbortDelay.c b/Demo/Common/Minimal/AbortDelay.c
index 55ee4b655..ec5e46751 100644
--- a/Demo/Common/Minimal/AbortDelay.c
+++ b/Demo/Common/Minimal/AbortDelay.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -47,32 +47,32 @@
#include "AbortDelay.h"
/* This file can only be used if the functionality it tests is included in the
-build. Remove the whole file if this is not the case. */
-#if( INCLUDE_xTaskAbortDelay == 1 )
+ * build. Remove the whole file if this is not the case. */
+#if ( INCLUDE_xTaskAbortDelay == 1 )
-#if( INCLUDE_xTaskGetHandle != 1 )
- #error This test file uses the xTaskGetHandle() API function so INCLUDE_xTaskGetHandle must be set to 1 in FreeRTOSConfig.h.
-#endif
+ #if ( INCLUDE_xTaskGetHandle != 1 )
+ #error This test file uses the xTaskGetHandle() API function so INCLUDE_xTaskGetHandle must be set to 1 in FreeRTOSConfig.h.
+ #endif
/* Task priorities. Allow these to be overridden. */
-#ifndef abtCONTROLLING_PRIORITY
- #define abtCONTROLLING_PRIORITY ( configMAX_PRIORITIES - 3 )
-#endif
+ #ifndef abtCONTROLLING_PRIORITY
+ #define abtCONTROLLING_PRIORITY ( configMAX_PRIORITIES - 3 )
+ #endif
-#ifndef abtBLOCKING_PRIORITY
- #define abtBLOCKING_PRIORITY ( configMAX_PRIORITIES - 2 )
-#endif
+ #ifndef abtBLOCKING_PRIORITY
+ #define abtBLOCKING_PRIORITY ( configMAX_PRIORITIES - 2 )
+ #endif
/* The tests that are performed. */
-#define abtNOTIFY_WAIT_ABORTS 0
-#define abtNOTIFY_TAKE_ABORTS 1
-#define abtDELAY_ABORTS 2
-#define abtDELAY_UNTIL_ABORTS 3
-#define abtSEMAPHORE_TAKE_ABORTS 4
-#define abtEVENT_GROUP_ABORTS 5
-#define abtQUEUE_SEND_ABORTS 6
-#define abtSTREAM_BUFFER_RECEIVE 7
-#define abtMAX_TESTS 8
+ #define abtNOTIFY_WAIT_ABORTS 0
+ #define abtNOTIFY_TAKE_ABORTS 1
+ #define abtDELAY_ABORTS 2
+ #define abtDELAY_UNTIL_ABORTS 3
+ #define abtSEMAPHORE_TAKE_ABORTS 4
+ #define abtEVENT_GROUP_ABORTS 5
+ #define abtQUEUE_SEND_ABORTS 6
+ #define abtSTREAM_BUFFER_RECEIVE 7
+ #define abtMAX_TESTS 8
/*-----------------------------------------------------------*/
@@ -80,8 +80,8 @@ build. Remove the whole file if this is not the case. */
* The two test tasks. The controlling task specifies which test to executed.
* More information is provided in the comments within the tasks.
*/
-static void prvControllingTask( void *pvParameters );
-static void prvBlockingTask( void *pvParameters );
+ static void prvControllingTask( void * pvParameters );
+ static void prvBlockingTask( void * pvParameters );
/*
* Test functions called by the blocking task. Each function follows the same
@@ -92,666 +92,709 @@ static void prvBlockingTask( void *pvParameters );
* expected to be aborted by the controlling task half way through the block
* time.
*/
-static void prvTestAbortingTaskNotifyWait( void );
-static void prvTestAbortingTaskNotifyTake( void );
-static void prvTestAbortingTaskDelay( void );
-static void prvTestAbortingTaskDelayUntil( void );
-static void prvTestAbortingSemaphoreTake( void );
-static void prvTestAbortingEventGroupWait( void );
-static void prvTestAbortingQueueSend( void );
-static void prvTestAbortingStreamBufferReceive( void );
+ static void prvTestAbortingTaskNotifyWait( void );
+ static void prvTestAbortingTaskNotifyTake( void );
+ static void prvTestAbortingTaskDelay( void );
+ static void prvTestAbortingTaskDelayUntil( void );
+ static void prvTestAbortingSemaphoreTake( void );
+ static void prvTestAbortingEventGroupWait( void );
+ static void prvTestAbortingQueueSend( void );
+ static void prvTestAbortingStreamBufferReceive( void );
/*
* Performs a few tests to cover code paths not otherwise covered by the continuous
* tests.
*/
-static void prvPerformSingleTaskTests( void );
+ static void prvPerformSingleTaskTests( void );
/*
* Checks the amount of time a task spent in the Blocked state is within the
* expected bounds.
*/
-static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime, TickType_t xExpectedBlockTime );
+ static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime,
+ TickType_t xExpectedBlockTime );
/*-----------------------------------------------------------*/
/* Used to ensure that tasks are still executing without error. */
-static volatile BaseType_t xControllingCycles = 0, xBlockingCycles = 0;
-static volatile BaseType_t xErrorOccurred = pdFALSE;
+ static volatile BaseType_t xControllingCycles = 0, xBlockingCycles = 0;
+ static volatile BaseType_t xErrorOccurred = pdFALSE;
/* Each task needs to know the other tasks handle so they can send signals to
-each other. The handle is obtained from the task's name. */
-static const char *pcControllingTaskName = "AbtCtrl", *pcBlockingTaskName = "AbtBlk";
+ * each other. The handle is obtained from the task's name. */
+ static const char * pcControllingTaskName = "AbtCtrl", * pcBlockingTaskName = "AbtBlk";
/* The maximum amount of time a task will block for. */
-const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 100 );
-const TickType_t xHalfMaxBlockTime = pdMS_TO_TICKS( 50 );
+ const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 100 );
+ const TickType_t xHalfMaxBlockTime = pdMS_TO_TICKS( 50 );
/* The actual block time is dependent on the priority of other tasks in the
-system so the actual block time might be greater than that expected, but it
-should be within an acceptable upper bound. */
-const TickType_t xAllowableMargin = pdMS_TO_TICKS( 7 );
+ * system so the actual block time might be greater than that expected, but it
+ * should be within an acceptable upper bound. */
+ const TickType_t xAllowableMargin = pdMS_TO_TICKS( 7 );
/*-----------------------------------------------------------*/
-void vCreateAbortDelayTasks( void )
-{
- /* Create the two test tasks described above. */
- xTaskCreate( prvControllingTask, pcControllingTaskName, configMINIMAL_STACK_SIZE, NULL, abtCONTROLLING_PRIORITY, NULL );
- xTaskCreate( prvBlockingTask, pcBlockingTaskName, configMINIMAL_STACK_SIZE, NULL, abtBLOCKING_PRIORITY, NULL );
-}
+ void vCreateAbortDelayTasks( void )
+ {
+ /* Create the two test tasks described above. */
+ xTaskCreate( prvControllingTask, pcControllingTaskName, configMINIMAL_STACK_SIZE, NULL, abtCONTROLLING_PRIORITY, NULL );
+ xTaskCreate( prvBlockingTask, pcBlockingTaskName, configMINIMAL_STACK_SIZE, NULL, abtBLOCKING_PRIORITY, NULL );
+ }
/*-----------------------------------------------------------*/
-static void prvControllingTask( void *pvParameters )
-{
-TaskHandle_t xBlockingTask;
-uint32_t ulTestToPerform = abtNOTIFY_WAIT_ABORTS;
-TickType_t xTimeAtStart;
-const TickType_t xStartMargin = 2UL;
-
- /* Just to remove compiler warnings. */
- ( void ) pvParameters;
-
- xBlockingTask = xTaskGetHandle( pcBlockingTaskName );
- configASSERT( xBlockingTask );
-
- for( ;; )
- {
- /* Tell the secondary task to perform the next test. */
- xTimeAtStart = xTaskGetTickCount();
- xTaskNotify( xBlockingTask, ulTestToPerform, eSetValueWithOverwrite );
-
- /* The secondary task has a higher priority, so will now be in the
- Blocked state to wait for a maximum of xMaxBlockTime. It expects that
- period to complete with a timeout. It will then block for
- xMaxBlockTimeAgain, but this time it expects to the block time to abort
- half way through. Block until it is time to send the abort to the
- secondary task. xStartMargin is used because this task takes timing
- from the beginning of the test, whereas the blocking task takes timing
- from the entry into the Blocked state - and as the tasks run at
- different priorities, there may be some discrepancy. Also, temporarily
- raise the priority of the controlling task to that of the blocking
- task to minimise discrepancies. */
- vTaskPrioritySet( NULL, abtBLOCKING_PRIORITY );
- vTaskDelay( xMaxBlockTime + xHalfMaxBlockTime + xStartMargin );
- if( xTaskAbortDelay( xBlockingTask ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Reset the priority to the normal controlling priority. */
- vTaskPrioritySet( NULL, abtCONTROLLING_PRIORITY );
-
- /* Now wait to be notified that the secondary task has completed its
- test. */
- ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
-
- /* Did the entire test run for the expected time, which is two full
- block times plus the half block time caused by calling
- xTaskAbortDelay()? */
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, ( xMaxBlockTime + xMaxBlockTime + xHalfMaxBlockTime ) );
-
- /* Move onto the next test. */
- ulTestToPerform++;
-
- if( ulTestToPerform >= abtMAX_TESTS )
- {
- ulTestToPerform = 0;
- }
-
- /* To indicate this task is still executing. */
- xControllingCycles++;
- }
-}
+ static void prvControllingTask( void * pvParameters )
+ {
+ TaskHandle_t xBlockingTask;
+ uint32_t ulTestToPerform = abtNOTIFY_WAIT_ABORTS;
+ TickType_t xTimeAtStart;
+ const TickType_t xStartMargin = 2UL;
+
+ /* Just to remove compiler warnings. */
+ ( void ) pvParameters;
+
+ xBlockingTask = xTaskGetHandle( pcBlockingTaskName );
+ configASSERT( xBlockingTask );
+
+ for( ; ; )
+ {
+ /* Tell the secondary task to perform the next test. */
+ xTimeAtStart = xTaskGetTickCount();
+ xTaskNotify( xBlockingTask, ulTestToPerform, eSetValueWithOverwrite );
+
+ /* The secondary task has a higher priority, so will now be in the
+ * Blocked state to wait for a maximum of xMaxBlockTime. It expects that
+ * period to complete with a timeout. It will then block for
+ * xMaxBlockTimeAgain, but this time it expects to the block time to abort
+ * half way through. Block until it is time to send the abort to the
+ * secondary task. xStartMargin is used because this task takes timing
+ * from the beginning of the test, whereas the blocking task takes timing
+ * from the entry into the Blocked state - and as the tasks run at
+ * different priorities, there may be some discrepancy. Also, temporarily
+ * raise the priority of the controlling task to that of the blocking
+ * task to minimise discrepancies. */
+ vTaskPrioritySet( NULL, abtBLOCKING_PRIORITY );
+ vTaskDelay( xMaxBlockTime + xHalfMaxBlockTime + xStartMargin );
+
+ if( xTaskAbortDelay( xBlockingTask ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Reset the priority to the normal controlling priority. */
+ vTaskPrioritySet( NULL, abtCONTROLLING_PRIORITY );
+
+ /* Now wait to be notified that the secondary task has completed its
+ * test. */
+ ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+
+ /* Did the entire test run for the expected time, which is two full
+ * block times plus the half block time caused by calling
+ * xTaskAbortDelay()? */
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, ( xMaxBlockTime + xMaxBlockTime + xHalfMaxBlockTime ) );
+
+ /* Move onto the next test. */
+ ulTestToPerform++;
+
+ if( ulTestToPerform >= abtMAX_TESTS )
+ {
+ ulTestToPerform = 0;
+ }
+
+ /* To indicate this task is still executing. */
+ xControllingCycles++;
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvBlockingTask( void *pvParameters )
-{
-TaskHandle_t xControllingTask;
-uint32_t ulNotificationValue;
-const uint32_t ulMax = 0xffffffffUL;
-
- /* Just to remove compiler warnings. */
- ( void ) pvParameters;
-
- /* Start by performing a few tests to cover code not exercised in the loops
- below. */
- prvPerformSingleTaskTests();
-
- xControllingTask = xTaskGetHandle( pcControllingTaskName );
- configASSERT( xControllingTask );
-
- for( ;; )
- {
- /* Wait to be notified of the test that is to be performed next. */
- xTaskNotifyWait( 0, ulMax, &ulNotificationValue, portMAX_DELAY );
-
- switch( ulNotificationValue )
- {
- case abtNOTIFY_WAIT_ABORTS:
- prvTestAbortingTaskNotifyWait();
- break;
-
- case abtNOTIFY_TAKE_ABORTS:
- prvTestAbortingTaskNotifyTake();
- break;
-
- case abtDELAY_ABORTS:
- prvTestAbortingTaskDelay();
- break;
-
- case abtDELAY_UNTIL_ABORTS:
- prvTestAbortingTaskDelayUntil();
- break;
-
- case abtSEMAPHORE_TAKE_ABORTS:
- prvTestAbortingSemaphoreTake();
- break;
-
- case abtEVENT_GROUP_ABORTS:
- prvTestAbortingEventGroupWait();
- break;
-
- case abtQUEUE_SEND_ABORTS:
- prvTestAbortingQueueSend();
- break;
-
- case abtSTREAM_BUFFER_RECEIVE:
- prvTestAbortingStreamBufferReceive();
- break;
-
- default:
- /* Should not get here. */
- break;
- }
-
- /* Let the primary task know the test is complete. */
- xTaskNotifyGive( xControllingTask );
-
- /* To indicate this task is still executing. */
- xBlockingCycles++;
- }
-}
+ static void prvBlockingTask( void * pvParameters )
+ {
+ TaskHandle_t xControllingTask;
+ uint32_t ulNotificationValue;
+ const uint32_t ulMax = 0xffffffffUL;
+
+ /* Just to remove compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Start by performing a few tests to cover code not exercised in the loops
+ * below. */
+ prvPerformSingleTaskTests();
+
+ xControllingTask = xTaskGetHandle( pcControllingTaskName );
+ configASSERT( xControllingTask );
+
+ for( ; ; )
+ {
+ /* Wait to be notified of the test that is to be performed next. */
+ xTaskNotifyWait( 0, ulMax, &ulNotificationValue, portMAX_DELAY );
+
+ switch( ulNotificationValue )
+ {
+ case abtNOTIFY_WAIT_ABORTS:
+ prvTestAbortingTaskNotifyWait();
+ break;
+
+ case abtNOTIFY_TAKE_ABORTS:
+ prvTestAbortingTaskNotifyTake();
+ break;
+
+ case abtDELAY_ABORTS:
+ prvTestAbortingTaskDelay();
+ break;
+
+ case abtDELAY_UNTIL_ABORTS:
+ prvTestAbortingTaskDelayUntil();
+ break;
+
+ case abtSEMAPHORE_TAKE_ABORTS:
+ prvTestAbortingSemaphoreTake();
+ break;
+
+ case abtEVENT_GROUP_ABORTS:
+ prvTestAbortingEventGroupWait();
+ break;
+
+ case abtQUEUE_SEND_ABORTS:
+ prvTestAbortingQueueSend();
+ break;
+
+ case abtSTREAM_BUFFER_RECEIVE:
+ prvTestAbortingStreamBufferReceive();
+ break;
+
+ default:
+ /* Should not get here. */
+ break;
+ }
+
+ /* Let the primary task know the test is complete. */
+ xTaskNotifyGive( xControllingTask );
+
+ /* To indicate this task is still executing. */
+ xBlockingCycles++;
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvPerformSingleTaskTests( void )
-{
-TaskHandle_t xThisTask;
-BaseType_t xReturned;
-
- /* Try unblocking this task using both the task and ISR versions of the API -
- both should return false as this task is not blocked. */
- xThisTask = xTaskGetCurrentTaskHandle();
-
- xReturned = xTaskAbortDelay( xThisTask );
- if( xReturned != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
-}
+ static void prvPerformSingleTaskTests( void )
+ {
+ TaskHandle_t xThisTask;
+ BaseType_t xReturned;
+
+ /* Try unblocking this task using both the task and ISR versions of the API -
+ * both should return false as this task is not blocked. */
+ xThisTask = xTaskGetCurrentTaskHandle();
+
+ xReturned = xTaskAbortDelay( xThisTask );
+
+ if( xReturned != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingTaskDelayUntil( void )
-{
-TickType_t xTimeAtStart, xLastBlockTime;
-BaseType_t xReturned;
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* Take a copy of the time as it is updated in the call to
- xTaskDelayUntil() but its original value is needed to determine the actual
- time spend in the Blocked state. */
- xLastBlockTime = xTimeAtStart;
-
- /* This first delay should just time out. */
- xReturned = xTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
- configASSERT( xReturned == pdTRUE );
- /* Remove compiler warning about value being set but not used in the case
- configASSERT() is not defined. */
- ( void ) xReturned;
-
- /* This second delay should be aborted by the primary task half way
- through. Again take a copy of the time as it is updated in the call to
- vTaskDelayUntil() buts its original value is needed to determine the amount
- of time actually spent in the Blocked state. This uses vTaskDelayUntil()
- in place of xTaskDelayUntil() for test coverage. */
- xTimeAtStart = xTaskGetTickCount();
- xLastBlockTime = xTimeAtStart;
- vTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* As with the other tests, the third block period should not time out. */
- xTimeAtStart = xTaskGetTickCount();
- xLastBlockTime = xTimeAtStart;
- xReturned = xTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
- configASSERT( xReturned == pdTRUE );
- /* Remove compiler warning about value being set but not used in the case
- configASSERT() is not defined. */
- ( void ) xReturned;
-}
+ static void prvTestAbortingTaskDelayUntil( void )
+ {
+ TickType_t xTimeAtStart, xLastBlockTime;
+ BaseType_t xReturned;
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* Take a copy of the time as it is updated in the call to
+ * xTaskDelayUntil() but its original value is needed to determine the actual
+ * time spend in the Blocked state. */
+ xLastBlockTime = xTimeAtStart;
+
+ /* This first delay should just time out. */
+ xReturned = xTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+ configASSERT( xReturned == pdTRUE );
+
+ /* Remove compiler warning about value being set but not used in the case
+ * configASSERT() is not defined. */
+ ( void ) xReturned;
+
+ /* This second delay should be aborted by the primary task half way
+ * through. Again take a copy of the time as it is updated in the call to
+ * vTaskDelayUntil() buts its original value is needed to determine the amount
+ * of time actually spent in the Blocked state. This uses vTaskDelayUntil()
+ * in place of xTaskDelayUntil() for test coverage. */
+ xTimeAtStart = xTaskGetTickCount();
+ xLastBlockTime = xTimeAtStart;
+ vTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* As with the other tests, the third block period should not time out. */
+ xTimeAtStart = xTaskGetTickCount();
+ xLastBlockTime = xTimeAtStart;
+ xReturned = xTaskDelayUntil( &xLastBlockTime, xMaxBlockTime );
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+ configASSERT( xReturned == pdTRUE );
+
+ /* Remove compiler warning about value being set but not used in the case
+ * configASSERT() is not defined. */
+ ( void ) xReturned;
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingTaskDelay( void )
-{
-TickType_t xTimeAtStart;
+ static void prvTestAbortingTaskDelay( void )
+ {
+ TickType_t xTimeAtStart;
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
- /* This first delay should just time out. */
- vTaskDelay( xMaxBlockTime );
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+ /* This first delay should just time out. */
+ vTaskDelay( xMaxBlockTime );
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
- /* This second delay should be aborted by the primary task half way
- through. */
- vTaskDelay( xMaxBlockTime );
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+ /* This second delay should be aborted by the primary task half way
+ * through. */
+ vTaskDelay( xMaxBlockTime );
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
- /* This third delay should just time out again. */
- vTaskDelay( xMaxBlockTime );
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-}
+ /* This third delay should just time out again. */
+ vTaskDelay( xMaxBlockTime );
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingTaskNotifyTake( void )
-{
-TickType_t xTimeAtStart;
-uint32_t ulReturn;
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This first delay should just time out. */
- ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
- if( ulReturn != 0 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This second delay should be aborted by the primary task half way
- through. */
- ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
- if( ulReturn != 0 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This third delay should just time out again. */
- ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
- if( ulReturn != 0 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-}
+ static void prvTestAbortingTaskNotifyTake( void )
+ {
+ TickType_t xTimeAtStart;
+ uint32_t ulReturn;
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This first delay should just time out. */
+ ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
+
+ if( ulReturn != 0 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This second delay should be aborted by the primary task half way
+ * through. */
+ ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
+
+ if( ulReturn != 0 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This third delay should just time out again. */
+ ulReturn = ulTaskNotifyTake( pdFALSE, xMaxBlockTime );
+
+ if( ulReturn != 0 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingEventGroupWait( void )
-{
-TickType_t xTimeAtStart;
-EventGroupHandle_t xEventGroup;
-EventBits_t xBitsToWaitFor = ( EventBits_t ) 0x01, xReturn;
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- static StaticEventGroup_t xEventGroupBuffer;
-
- /* Create the event group. Statically allocated memory is used so the
- creation cannot fail. */
- xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
- }
- #else
- {
- xEventGroup = xEventGroupCreate();
- configASSERT( xEventGroup );
- }
- #endif
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This first delay should just time out. */
- xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
- if( xReturn != 0x00 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This second delay should be aborted by the primary task half way
- through. */
- xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
- if( xReturn != 0x00 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This third delay should just time out again. */
- xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
- if( xReturn != 0x00 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Not really necessary in this case, but for completeness. */
- vEventGroupDelete( xEventGroup );
-}
+ static void prvTestAbortingEventGroupWait( void )
+ {
+ TickType_t xTimeAtStart;
+ EventGroupHandle_t xEventGroup;
+ EventBits_t xBitsToWaitFor = ( EventBits_t ) 0x01, xReturn;
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ static StaticEventGroup_t xEventGroupBuffer;
+
+ /* Create the event group. Statically allocated memory is used so the
+ * creation cannot fail. */
+ xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+ }
+ #else
+ {
+ xEventGroup = xEventGroupCreate();
+ configASSERT( xEventGroup );
+ }
+ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This first delay should just time out. */
+ xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
+
+ if( xReturn != 0x00 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This second delay should be aborted by the primary task half way
+ * through. */
+ xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
+
+ if( xReturn != 0x00 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This third delay should just time out again. */
+ xReturn = xEventGroupWaitBits( xEventGroup, xBitsToWaitFor, pdTRUE, pdTRUE, xMaxBlockTime );
+
+ if( xReturn != 0x00 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Not really necessary in this case, but for completeness. */
+ vEventGroupDelete( xEventGroup );
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingStreamBufferReceive( void )
-{
-TickType_t xTimeAtStart;
-StreamBufferHandle_t xStreamBuffer;
-size_t xReturn;
-const size_t xTriggerLevelBytes = ( size_t ) 1;
-uint8_t uxRxData;
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* Defines the memory that will actually hold the streams within the
- stream buffer. */
- static uint8_t ucStorageBuffer[ sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) + 1 ];
-
- /* The variable used to hold the stream buffer structure. */
- StaticStreamBuffer_t xStreamBufferStruct;
-
-
- xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
- xTriggerLevelBytes,
- ucStorageBuffer,
- &xStreamBufferStruct );
- }
- #else
- {
- xStreamBuffer = xStreamBufferCreate( sizeof( uint8_t ), xTriggerLevelBytes );
- configASSERT( xStreamBuffer );
- }
- #endif
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This first delay should just time out. */
- xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
- if( xReturn != 0x00 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This second delay should be aborted by the primary task half way
- through xMaxBlockTime. */
- xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
- if( xReturn != 0x00 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This third delay should just time out again. */
- xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
- if( xReturn != 0x00 )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Not really necessary in this case, but for completeness. */
- vStreamBufferDelete( xStreamBuffer );
-}
+ static void prvTestAbortingStreamBufferReceive( void )
+ {
+ TickType_t xTimeAtStart;
+ StreamBufferHandle_t xStreamBuffer;
+ size_t xReturn;
+ const size_t xTriggerLevelBytes = ( size_t ) 1;
+ uint8_t uxRxData;
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ /* Defines the memory that will actually hold the streams within the
+ * stream buffer. */
+ static uint8_t ucStorageBuffer[ sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) + 1 ];
+
+ /* The variable used to hold the stream buffer structure. */
+ StaticStreamBuffer_t xStreamBufferStruct;
+
+
+ xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
+ xTriggerLevelBytes,
+ ucStorageBuffer,
+ &xStreamBufferStruct );
+ }
+ #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+ {
+ xStreamBuffer = xStreamBufferCreate( sizeof( uint8_t ), xTriggerLevelBytes );
+ configASSERT( xStreamBuffer );
+ }
+ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This first delay should just time out. */
+ xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
+
+ if( xReturn != 0x00 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This second delay should be aborted by the primary task half way
+ * through xMaxBlockTime. */
+ xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
+
+ if( xReturn != 0x00 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This third delay should just time out again. */
+ xReturn = xStreamBufferReceive( xStreamBuffer, &uxRxData, sizeof( uxRxData ), xMaxBlockTime );
+
+ if( xReturn != 0x00 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Not really necessary in this case, but for completeness. */
+ vStreamBufferDelete( xStreamBuffer );
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingQueueSend( void )
-{
-TickType_t xTimeAtStart;
-BaseType_t xReturn;
-const UBaseType_t xQueueLength = ( UBaseType_t ) 1;
-QueueHandle_t xQueue;
-uint8_t ucItemToQueue;
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- static StaticQueue_t xQueueBuffer;
- static uint8_t ucQueueStorage[ sizeof( uint8_t ) ];
-
- /* Create the queue. Statically allocated memory is used so the
- creation cannot fail. */
- xQueue = xQueueCreateStatic( xQueueLength, sizeof( uint8_t ), ucQueueStorage, &xQueueBuffer );
- }
- #else
- {
- xQueue = xQueueCreate( xQueueLength, sizeof( uint8_t ) );
- configASSERT( xQueue );
- }
- #endif
-
- /* This function tests aborting when in the blocked state waiting to send,
- so the queue must be full. There is only one space in the queue. */
- xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
- if( xReturn != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This first delay should just time out. */
- xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This second delay should be aborted by the primary task half way
- through. */
- xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This third delay should just time out again. */
- xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Not really necessary in this case, but for completeness. */
- vQueueDelete( xQueue );
-}
+ static void prvTestAbortingQueueSend( void )
+ {
+ TickType_t xTimeAtStart;
+ BaseType_t xReturn;
+ const UBaseType_t xQueueLength = ( UBaseType_t ) 1;
+ QueueHandle_t xQueue;
+ uint8_t ucItemToQueue;
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ static StaticQueue_t xQueueBuffer;
+ static uint8_t ucQueueStorage[ sizeof( uint8_t ) ];
+
+ /* Create the queue. Statically allocated memory is used so the
+ * creation cannot fail. */
+ xQueue = xQueueCreateStatic( xQueueLength, sizeof( uint8_t ), ucQueueStorage, &xQueueBuffer );
+ }
+ #else
+ {
+ xQueue = xQueueCreate( xQueueLength, sizeof( uint8_t ) );
+ configASSERT( xQueue );
+ }
+ #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+ /* This function tests aborting when in the blocked state waiting to send,
+ * so the queue must be full. There is only one space in the queue. */
+ xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+
+ if( xReturn != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This first delay should just time out. */
+ xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This second delay should be aborted by the primary task half way
+ * through. */
+ xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This third delay should just time out again. */
+ xReturn = xQueueSend( xQueue, &ucItemToQueue, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Not really necessary in this case, but for completeness. */
+ vQueueDelete( xQueue );
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingSemaphoreTake( void )
-{
-TickType_t xTimeAtStart;
-BaseType_t xReturn;
-SemaphoreHandle_t xSemaphore;
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- static StaticSemaphore_t xSemaphoreBuffer;
-
- /* Create the semaphore. Statically allocated memory is used so the
- creation cannot fail. */
- xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
- }
- #else
- {
- xSemaphore = xSemaphoreCreateBinary();
- }
- #endif
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This first delay should just time out. */
- xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This second delay should be aborted by the primary task half way
- through xMaxBlockTime. */
- xReturn = xSemaphoreTake( xSemaphore, portMAX_DELAY );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This third delay should just time out again. */
- xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Not really necessary in this case, but for completeness. */
- vSemaphoreDelete( xSemaphore );
-}
+ static void prvTestAbortingSemaphoreTake( void )
+ {
+ TickType_t xTimeAtStart;
+ BaseType_t xReturn;
+ SemaphoreHandle_t xSemaphore;
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ static StaticSemaphore_t xSemaphoreBuffer;
+
+ /* Create the semaphore. Statically allocated memory is used so the
+ * creation cannot fail. */
+ xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
+ }
+ #else
+ {
+ xSemaphore = xSemaphoreCreateBinary();
+ }
+ #endif
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This first delay should just time out. */
+ xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This second delay should be aborted by the primary task half way
+ * through xMaxBlockTime. */
+ xReturn = xSemaphoreTake( xSemaphore, portMAX_DELAY );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This third delay should just time out again. */
+ xReturn = xSemaphoreTake( xSemaphore, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Not really necessary in this case, but for completeness. */
+ vSemaphoreDelete( xSemaphore );
+ }
/*-----------------------------------------------------------*/
-static void prvTestAbortingTaskNotifyWait( void )
-{
-TickType_t xTimeAtStart;
-BaseType_t xReturn;
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This first delay should just time out. */
- xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This second delay should be aborted by the primary task half way
- through xMaxBlockTime. */
- xReturn = xTaskNotifyWait( 0, 0, NULL, portMAX_DELAY );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
-
- /* Note the time before the delay so the length of the delay is known. */
- xTimeAtStart = xTaskGetTickCount();
-
- /* This third delay should just time out again. */
- xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime );
- if( xReturn != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
- prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
-}
+ static void prvTestAbortingTaskNotifyWait( void )
+ {
+ TickType_t xTimeAtStart;
+ BaseType_t xReturn;
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This first delay should just time out. */
+ xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This second delay should be aborted by the primary task half way
+ * through xMaxBlockTime. */
+ xReturn = xTaskNotifyWait( 0, 0, NULL, portMAX_DELAY );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xHalfMaxBlockTime );
+
+ /* Note the time before the delay so the length of the delay is known. */
+ xTimeAtStart = xTaskGetTickCount();
+
+ /* This third delay should just time out again. */
+ xReturn = xTaskNotifyWait( 0, 0, NULL, xMaxBlockTime );
+
+ if( xReturn != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvCheckExpectedTimeIsWithinAnAcceptableMargin( xTimeAtStart, xMaxBlockTime );
+ }
/*-----------------------------------------------------------*/
-static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime, TickType_t xExpectedBlockTime )
-{
-TickType_t xTimeNow, xActualBlockTime;
-
- xTimeNow = xTaskGetTickCount();
- xActualBlockTime = xTimeNow - xStartTime;
-
- /* The actual block time should not be less than the expected block time. */
- if( xActualBlockTime < xExpectedBlockTime )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* The actual block time can be greater than the expected block time, as it
- depends on the priority of the other tasks, but it should be within an
- acceptable margin. */
- if( xActualBlockTime > ( xExpectedBlockTime + xAllowableMargin ) )
- {
- xErrorOccurred = pdTRUE;
- }
-}
+ static void prvCheckExpectedTimeIsWithinAnAcceptableMargin( TickType_t xStartTime,
+ TickType_t xExpectedBlockTime )
+ {
+ TickType_t xTimeNow, xActualBlockTime;
+
+ xTimeNow = xTaskGetTickCount();
+ xActualBlockTime = xTimeNow - xStartTime;
+
+ /* The actual block time should not be less than the expected block time. */
+ if( xActualBlockTime < xExpectedBlockTime )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* The actual block time can be greater than the expected block time, as it
+ * depends on the priority of the other tasks, but it should be within an
+ * acceptable margin. */
+ if( xActualBlockTime > ( xExpectedBlockTime + xAllowableMargin ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
/*-----------------------------------------------------------*/
-BaseType_t xAreAbortDelayTestTasksStillRunning( void )
-{
-static BaseType_t xLastControllingCycleCount = 0, xLastBlockingCycleCount = 0;
-BaseType_t xReturn = pdPASS;
-
- /* Have both tasks performed at least one cycle since this function was
- last called? */
- if( xControllingCycles == xLastControllingCycleCount )
- {
- xReturn = pdFAIL;
- }
-
- if( xBlockingCycles == xLastBlockingCycleCount )
- {
- xReturn = pdFAIL;
- }
-
- if( xErrorOccurred == pdTRUE )
- {
- xReturn = pdFAIL;
- }
-
- xLastBlockingCycleCount = xBlockingCycles;
- xLastControllingCycleCount = xControllingCycles;
-
- return xReturn;
-}
+ BaseType_t xAreAbortDelayTestTasksStillRunning( void )
+ {
+ static BaseType_t xLastControllingCycleCount = 0, xLastBlockingCycleCount = 0;
+ BaseType_t xReturn = pdPASS;
+
+ /* Have both tasks performed at least one cycle since this function was
+ * last called? */
+ if( xControllingCycles == xLastControllingCycleCount )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xBlockingCycles == xLastBlockingCycleCount )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xErrorOccurred == pdTRUE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ xLastBlockingCycleCount = xBlockingCycles;
+ xLastControllingCycleCount = xControllingCycles;
+
+ return xReturn;
+ }
#endif /* INCLUDE_xTaskAbortDelay == 1 */
diff --git a/Demo/Common/Minimal/BlockQ.c b/Demo/Common/Minimal/BlockQ.c
index 71de2931a..694db7f25 100644
--- a/Demo/Common/Minimal/BlockQ.c
+++ b/Demo/Common/Minimal/BlockQ.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -59,232 +59,232 @@
/* Demo program include files. */
#include "BlockQ.h"
-#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE
-#define blckqNUM_TASK_SETS ( 3 )
+#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE
+#define blckqNUM_TASK_SETS ( 3 )
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
- #error This example cannot be used if dynamic allocation is not allowed.
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+ #error This example cannot be used if dynamic allocation is not allowed.
#endif
/* Structure used to pass parameters to the blocking queue tasks. */
typedef struct BLOCKING_QUEUE_PARAMETERS
{
- QueueHandle_t xQueue; /*< The queue to be used by the task. */
- TickType_t xBlockTime; /*< The block time to use on queue reads/writes. */
- volatile short *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
+ QueueHandle_t xQueue; /*< The queue to be used by the task. */
+ TickType_t xBlockTime; /*< The block time to use on queue reads/writes. */
+ volatile short * psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */
} xBlockingQueueParameters;
/* Task function that creates an incrementing number and posts it on a queue. */
static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters );
/* Task function that removes the incrementing number from a queue and checks that
-it is the expected number. */
+ * it is the expected number. */
static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters );
/* Variables which are incremented each time an item is removed from a queue, and
-found to be the expected value.
-These are used to check that the tasks are still running. */
+ * found to be the expected value.
+ * These are used to check that the tasks are still running. */
static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
/* Variable which are incremented each time an item is posted on a queue. These
-are used to check that the tasks are still running. */
+ * are used to check that the tasks are still running. */
static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
/*-----------------------------------------------------------*/
void vStartBlockingQueueTasks( UBaseType_t uxPriority )
{
-xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;
-xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;
-xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;
-const UBaseType_t uxQueueSize1 = 1, uxQueueSize5 = 5;
-const TickType_t xBlockTime = pdMS_TO_TICKS( ( TickType_t ) 1000 );
-const TickType_t xDontBlock = ( TickType_t ) 0;
+ xBlockingQueueParameters * pxQueueParameters1, * pxQueueParameters2;
+ xBlockingQueueParameters * pxQueueParameters3, * pxQueueParameters4;
+ xBlockingQueueParameters * pxQueueParameters5, * pxQueueParameters6;
+ const UBaseType_t uxQueueSize1 = 1, uxQueueSize5 = 5;
+ const TickType_t xBlockTime = pdMS_TO_TICKS( ( TickType_t ) 1000 );
+ const TickType_t xDontBlock = ( TickType_t ) 0;
- /* Create the first two tasks as described at the top of the file. */
+ /* Create the first two tasks as described at the top of the file. */
- /* First create the structure used to pass parameters to the consumer tasks. */
- pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ /* First create the structure used to pass parameters to the consumer tasks. */
+ pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- /* Create the queue used by the first two tasks to pass the incrementing number.
- Pass a pointer to the queue in the parameter structure. */
- pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) );
+ /* Create the queue used by the first two tasks to pass the incrementing number.
+ * Pass a pointer to the queue in the parameter structure. */
+ pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) );
- /* The consumer is created first so gets a block time as described above. */
- pxQueueParameters1->xBlockTime = xBlockTime;
+ /* The consumer is created first so gets a block time as described above. */
+ pxQueueParameters1->xBlockTime = xBlockTime;
- /* Pass in the variable that this task is going to increment so we can check it
- is still running. */
- pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
+ /* Pass in the variable that this task is going to increment so we can check it
+ * is still running. */
+ pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );
- /* Create the structure used to pass parameters to the producer task. */
- pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ /* Create the structure used to pass parameters to the producer task. */
+ pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- /* Pass the queue to this task also, using the parameter structure. */
- pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
+ /* Pass the queue to this task also, using the parameter structure. */
+ pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;
- /* The producer is not going to block - as soon as it posts the consumer will
- wake and remove the item so the producer should always have room to post. */
- pxQueueParameters2->xBlockTime = xDontBlock;
+ /* The producer is not going to block - as soon as it posts the consumer will
+ * wake and remove the item so the producer should always have room to post. */
+ pxQueueParameters2->xBlockTime = xDontBlock;
- /* Pass in the variable that this task is going to increment so we can check
- it is still running. */
- pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
+ /* Pass in the variable that this task is going to increment so we can check
+ * it is still running. */
+ pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );
- /* Note the producer has a lower priority than the consumer when the tasks are
- spawned. */
- xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
- xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
+ /* Note the producer has a lower priority than the consumer when the tasks are
+ * spawned. */
+ xTaskCreate( vBlockingQueueConsumer, "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );
+ xTaskCreate( vBlockingQueueProducer, "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );
- /* Create the second two tasks as described at the top of the file. This uses
- the same mechanism but reverses the task priorities. */
+ /* Create the second two tasks as described at the top of the file. This uses
+ * the same mechanism but reverses the task priorities. */
- pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) );
- pxQueueParameters3->xBlockTime = xDontBlock;
- pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
+ pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( UBaseType_t ) sizeof( uint16_t ) );
+ pxQueueParameters3->xBlockTime = xDontBlock;
+ pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );
- pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
- pxQueueParameters4->xBlockTime = xBlockTime;
- pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
+ pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;
+ pxQueueParameters4->xBlockTime = xBlockTime;
+ pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );
- xTaskCreate( vBlockingQueueConsumer, "QConsB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vBlockingQueueProducer, "QProdB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
+ xTaskCreate( vBlockingQueueConsumer, "QConsB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vBlockingQueueProducer, "QProdB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );
- /* Create the last two tasks as described above. The mechanism is again just
- the same. This time both parameter structures are given a block time. */
- pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( UBaseType_t ) sizeof( uint16_t ) );
- pxQueueParameters5->xBlockTime = xBlockTime;
- pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
+ /* Create the last two tasks as described above. The mechanism is again just
+ * the same. This time both parameter structures are given a block time. */
+ pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( UBaseType_t ) sizeof( uint16_t ) );
+ pxQueueParameters5->xBlockTime = xBlockTime;
+ pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );
- pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
- pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
- pxQueueParameters6->xBlockTime = xBlockTime;
- pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
+ pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );
+ pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;
+ pxQueueParameters6->xBlockTime = xBlockTime;
+ pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] );
- xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vBlockingQueueProducer, "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vBlockingQueueConsumer, "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters )
{
-uint16_t usValue = 0;
-xBlockingQueueParameters *pxQueueParameters;
-short sErrorEverOccurred = pdFALSE;
-
- pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
-
- for( ;; )
- {
- if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
- {
- sErrorEverOccurred = pdTRUE;
- }
- else
- {
- /* We have successfully posted a message, so increment the variable
- used to check we are still running. */
- if( sErrorEverOccurred == pdFALSE )
- {
- ( *pxQueueParameters->psCheckVariable )++;
- }
-
- /* Increment the variable we are going to post next time round. The
- consumer will expect the numbers to follow in numerical order. */
- ++usValue;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
- }
- }
+ uint16_t usValue = 0;
+ xBlockingQueueParameters * pxQueueParameters;
+ short sErrorEverOccurred = pdFALSE;
+
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+ for( ; ; )
+ {
+ if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )
+ {
+ sErrorEverOccurred = pdTRUE;
+ }
+ else
+ {
+ /* We have successfully posted a message, so increment the variable
+ * used to check we are still running. */
+ if( sErrorEverOccurred == pdFALSE )
+ {
+ ( *pxQueueParameters->psCheckVariable )++;
+ }
+
+ /* Increment the variable we are going to post next time round. The
+ * consumer will expect the numbers to follow in numerical order. */
+ ++usValue;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters )
{
-uint16_t usData, usExpectedValue = 0;
-xBlockingQueueParameters *pxQueueParameters;
-short sErrorEverOccurred = pdFALSE;
-
- pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
-
- for( ;; )
- {
- if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
- {
- if( usData != usExpectedValue )
- {
- /* Catch-up. */
- usExpectedValue = usData;
-
- sErrorEverOccurred = pdTRUE;
- }
- else
- {
- /* We have successfully received a message, so increment the
- variable used to check we are still running. */
- if( sErrorEverOccurred == pdFALSE )
- {
- ( *pxQueueParameters->psCheckVariable )++;
- }
-
- /* Increment the value we expect to remove from the queue next time
- round. */
- ++usExpectedValue;
- }
-
- #if configUSE_PREEMPTION == 0
- {
- if( pxQueueParameters->xBlockTime == 0 )
- {
- taskYIELD();
- }
- }
- #endif
- }
- }
+ uint16_t usData, usExpectedValue = 0;
+ xBlockingQueueParameters * pxQueueParameters;
+ short sErrorEverOccurred = pdFALSE;
+
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;
+
+ for( ; ; )
+ {
+ if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )
+ {
+ if( usData != usExpectedValue )
+ {
+ /* Catch-up. */
+ usExpectedValue = usData;
+
+ sErrorEverOccurred = pdTRUE;
+ }
+ else
+ {
+ /* We have successfully received a message, so increment the
+ * variable used to check we are still running. */
+ if( sErrorEverOccurred == pdFALSE )
+ {
+ ( *pxQueueParameters->psCheckVariable )++;
+ }
+
+ /* Increment the value we expect to remove from the queue next time
+ * round. */
+ ++usExpectedValue;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ {
+ if( pxQueueParameters->xBlockTime == 0 )
+ {
+ taskYIELD();
+ }
+ }
+ #endif
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreBlockingQueuesStillRunning( void )
{
-static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
-static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
-BaseType_t xReturn = pdPASS, xTasks;
-
- /* Not too worried about mutual exclusion on these variables as they are 16
- bits and we are only reading them. We also only care to see if they have
- changed or not.
-
- Loop through each check variable to and return pdFALSE if any are found not
- to have changed since the last call. */
-
- for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
- {
- if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
- {
- xReturn = pdFALSE;
- }
- sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
-
-
- if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
- {
- xReturn = pdFALSE;
- }
- sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
- }
-
- return xReturn;
+ static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
+ static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( uint16_t ) 0, ( uint16_t ) 0, ( uint16_t ) 0 };
+ BaseType_t xReturn = pdPASS, xTasks;
+
+ /* Not too worried about mutual exclusion on these variables as they are 16
+ * bits and we are only reading them. We also only care to see if they have
+ * changed or not.
+ *
+ * Loop through each check variable to and return pdFALSE if any are found not
+ * to have changed since the last call. */
+
+ for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )
+ {
+ if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )
+ {
+ xReturn = pdFALSE;
+ }
+
+ sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];
+
+ if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )
+ {
+ xReturn = pdFALSE;
+ }
+
+ sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];
+ }
+
+ return xReturn;
}
-
diff --git a/Demo/Common/Minimal/EventGroupsDemo.c b/Demo/Common/Minimal/EventGroupsDemo.c
index 3be66c58c..256acd1e1 100644
--- a/Demo/Common/Minimal/EventGroupsDemo.c
+++ b/Demo/Common/Minimal/EventGroupsDemo.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,14 +28,14 @@
/*
-* This file contains fairly comprehensive checks on the behaviour of event
-* groups. It is not intended to be a user friendly demonstration of the
-* event groups API.
-*
-* NOTE: The tests implemented in this file are informal 'sanity' tests
-* only and are not part of the module tests that make use of the
-* mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
-*/
+ * This file contains fairly comprehensive checks on the behaviour of event
+ * groups. It is not intended to be a user friendly demonstration of the
+ * event groups API.
+ *
+ * NOTE: The tests implemented in this file are informal 'sanity' tests
+ * only and are not part of the module tests that make use of the
+ * mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
+ */
/* Scheduler include files. */
@@ -46,53 +46,53 @@
/* Demo app includes. */
#include "EventGroupsDemo.h"
-#if( INCLUDE_eTaskGetState != 1 )
- #error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file.
+#if ( INCLUDE_eTaskGetState != 1 )
+ #error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file.
#endif
/* Priorities used by the tasks. */
-#define ebSET_BIT_TASK_PRIORITY ( tskIDLE_PRIORITY )
-#define ebWAIT_BIT_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define ebSET_BIT_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define ebWAIT_BIT_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* Generic bit definitions. */
-#define ebBIT_0 ( 0x01 )
-#define ebBIT_1 ( 0x02 )
-#define ebBIT_2 ( 0x04 )
-#define ebBIT_3 ( 0x08 )
-#define ebBIT_4 ( 0x10 )
-#define ebBIT_5 ( 0x20 )
-#define ebBIT_6 ( 0x40 )
-#define ebBIT_7 ( 0x80 )
+#define ebBIT_0 ( 0x01 )
+#define ebBIT_1 ( 0x02 )
+#define ebBIT_2 ( 0x04 )
+#define ebBIT_3 ( 0x08 )
+#define ebBIT_4 ( 0x10 )
+#define ebBIT_5 ( 0x20 )
+#define ebBIT_6 ( 0x40 )
+#define ebBIT_7 ( 0x80 )
/* Combinations of bits used in the demo. */
-#define ebCOMBINED_BITS ( ebBIT_1 | ebBIT_5 | ebBIT_7 )
-#define ebALL_BITS ( ebBIT_0 | ebBIT_1 | ebBIT_2 | ebBIT_3 | ebBIT_4 | ebBIT_5 | ebBIT_6 | ebBIT_7 )
+#define ebCOMBINED_BITS ( ebBIT_1 | ebBIT_5 | ebBIT_7 )
+#define ebALL_BITS ( ebBIT_0 | ebBIT_1 | ebBIT_2 | ebBIT_3 | ebBIT_4 | ebBIT_5 | ebBIT_6 | ebBIT_7 )
/* Associate a bit to each task. These bits are used to identify all the tasks
-that synchronise with the xEventGroupSync() function. */
-#define ebSET_BIT_TASK_SYNC_BIT ebBIT_0
-#define ebWAIT_BIT_TASK_SYNC_BIT ebBIT_1
-#define ebRENDESVOUS_TASK_1_SYNC_BIT ebBIT_2
-#define ebRENDESVOUS_TASK_2_SYNC_BIT ebBIT_3
-#define ebALL_SYNC_BITS ( ebSET_BIT_TASK_SYNC_BIT | ebWAIT_BIT_TASK_SYNC_BIT | ebRENDESVOUS_TASK_1_SYNC_BIT | ebRENDESVOUS_TASK_2_SYNC_BIT )
+ * that synchronise with the xEventGroupSync() function. */
+#define ebSET_BIT_TASK_SYNC_BIT ebBIT_0
+#define ebWAIT_BIT_TASK_SYNC_BIT ebBIT_1
+#define ebRENDESVOUS_TASK_1_SYNC_BIT ebBIT_2
+#define ebRENDESVOUS_TASK_2_SYNC_BIT ebBIT_3
+#define ebALL_SYNC_BITS ( ebSET_BIT_TASK_SYNC_BIT | ebWAIT_BIT_TASK_SYNC_BIT | ebRENDESVOUS_TASK_1_SYNC_BIT | ebRENDESVOUS_TASK_2_SYNC_BIT )
/* A block time of zero simply means "don't block". */
-#define ebDONT_BLOCK ( 0 )
+#define ebDONT_BLOCK ( 0 )
/* A 5ms delay. */
-#define ebSHORT_DELAY pdMS_TO_TICKS( ( TickType_t ) 5 )
+#define ebSHORT_DELAY pdMS_TO_TICKS( ( TickType_t ) 5 )
/* Used in the selective bits test which checks no, one or both tasks blocked on
-event bits in a group are unblocked as appropriate as different bits get set. */
-#define ebSELECTIVE_BITS_1 0x03
-#define ebSELECTIVE_BITS_2 0x05
+ * event bits in a group are unblocked as appropriate as different bits get set. */
+#define ebSELECTIVE_BITS_1 0x03
+#define ebSELECTIVE_BITS_2 0x05
#ifndef ebRENDESVOUS_TEST_TASK_STACK_SIZE
- #define ebRENDESVOUS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define ebRENDESVOUS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
#ifndef ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE
- #define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
/*-----------------------------------------------------------*/
@@ -116,27 +116,29 @@ event bits in a group are unblocked as appropriate as different bits get set. */
*
* 3) Calls prvPerformTaskSyncTests() to test task synchronisation behaviour.
*/
-static void prvTestMasterTask( void *pvParameters );
+static void prvTestMasterTask( void * pvParameters );
/*
* A helper task that enables the 'test master' task to perform several
* behavioural tests. See the comments above the prvTestMasterTask() prototype
* above.
*/
-static void prvTestSlaveTask( void *pvParameters );
+static void prvTestSlaveTask( void * pvParameters );
/*
* The part of the test that is performed between the 'test master' task and the
* 'test slave' task to test the behaviour when the slave blocks on various
* event bit combinations.
*/
-static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle );
+static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError,
+ TaskHandle_t xTestSlaveTaskHandle );
/*
* The part of the test that uses all the tasks to test the task synchronisation
* behaviour.
*/
-static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle );
+static BaseType_t prvPerformTaskSyncTests( BaseType_t xError,
+ TaskHandle_t xTestSlaveTaskHandle );
/*
* Two instances of prvSyncTask() are created. They start by calling
@@ -144,7 +146,7 @@ static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, TaskHandle_t xTest
* executing the prvSelectiveBitsTestMasterFunction() function. They then loop
* to test the task synchronisation (rendezvous) behaviour.
*/
-static void prvSyncTask( void *pvParameters );
+static void prvSyncTask( void * pvParameters );
/*
* Functions used in a test that blocks two tasks on various different bits
@@ -157,7 +159,7 @@ static void prvSelectiveBitsTestSlaveFunction( void );
/*-----------------------------------------------------------*/
/* Variables that are incremented by the tasks on each cycle provided no errors
-have been found. Used to detect an error or stall in the test cycling. */
+ * have been found. Used to detect an error or stall in the test cycling. */
static volatile uint32_t ulTestMasterCycles = 0, ulTestSlaveCycles = 0, ulISRCycles = 0;
/* The event group used by all the task based tests. */
@@ -173,887 +175,885 @@ static TaskHandle_t xSyncTask1 = NULL, xSyncTask2 = NULL;
void vStartEventGroupTasks( void )
{
-TaskHandle_t xTestSlaveTaskHandle;
-
- /*
- * This file contains fairly comprehensive checks on the behaviour of event
- * groups. It is not intended to be a user friendly demonstration of the
- * event groups API.
- *
- * NOTE: The tests implemented in this file are informal 'sanity' tests
- * only and are not part of the module tests that make use of the
- * mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
- *
- * Create the test tasks as described at the top of this file.
- */
- xTaskCreate( prvTestSlaveTask, "WaitO", ebRENDESVOUS_TEST_TASK_STACK_SIZE, NULL, ebWAIT_BIT_TASK_PRIORITY, &xTestSlaveTaskHandle );
- xTaskCreate( prvTestMasterTask, "SetB", ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE, ( void * ) xTestSlaveTaskHandle, ebSET_BIT_TASK_PRIORITY, NULL );
- xTaskCreate( prvSyncTask, "Rndv", ebRENDESVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDESVOUS_TASK_1_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask1 );
- xTaskCreate( prvSyncTask, "Rndv", ebRENDESVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDESVOUS_TASK_2_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask2 );
-
- /* If the last task was created then the others will have been too. */
- configASSERT( xSyncTask2 );
-
- /* Create the event group used by the ISR tests. The event group used by
- the tasks is created by the tasks themselves. */
- xISREventGroup = xEventGroupCreate();
- configASSERT( xISREventGroup );
+ TaskHandle_t xTestSlaveTaskHandle;
+
+ /*
+ * This file contains fairly comprehensive checks on the behaviour of event
+ * groups. It is not intended to be a user friendly demonstration of the
+ * event groups API.
+ *
+ * NOTE: The tests implemented in this file are informal 'sanity' tests
+ * only and are not part of the module tests that make use of the
+ * mtCOVERAGE_TEST_MARKER macro within the event groups implementation.
+ *
+ * Create the test tasks as described at the top of this file.
+ */
+ xTaskCreate( prvTestSlaveTask, "WaitO", ebRENDESVOUS_TEST_TASK_STACK_SIZE, NULL, ebWAIT_BIT_TASK_PRIORITY, &xTestSlaveTaskHandle );
+ xTaskCreate( prvTestMasterTask, "SetB", ebEVENT_GROUP_SET_BITS_TEST_TASK_STACK_SIZE, ( void * ) xTestSlaveTaskHandle, ebSET_BIT_TASK_PRIORITY, NULL );
+ xTaskCreate( prvSyncTask, "Rndv", ebRENDESVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDESVOUS_TASK_1_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask1 );
+ xTaskCreate( prvSyncTask, "Rndv", ebRENDESVOUS_TEST_TASK_STACK_SIZE, ( void * ) ebRENDESVOUS_TASK_2_SYNC_BIT, ebWAIT_BIT_TASK_PRIORITY, &xSyncTask2 );
+
+ /* If the last task was created then the others will have been too. */
+ configASSERT( xSyncTask2 );
+
+ /* Create the event group used by the ISR tests. The event group used by
+ * the tasks is created by the tasks themselves. */
+ xISREventGroup = xEventGroupCreate();
+ configASSERT( xISREventGroup );
}
/*-----------------------------------------------------------*/
-static void prvTestMasterTask( void *pvParameters )
+static void prvTestMasterTask( void * pvParameters )
{
-BaseType_t xError;
+ BaseType_t xError;
/* The handle to the slave task is passed in as the task parameter. */
-TaskHandle_t xTestSlaveTaskHandle = ( TaskHandle_t ) pvParameters;
-
- /* Avoid compiler warnings. */
- ( void ) pvParameters;
-
- /* Create the event group used by the tasks ready for the initial tests. */
- xEventGroup = xEventGroupCreate();
- configASSERT( xEventGroup );
-
- /* Perform the tests that block two tasks on different combinations of bits,
- then set each bit in turn and check the correct tasks unblock at the correct
- times. */
- xError = prvSelectiveBitsTestMasterFunction();
-
- for( ;; )
- {
- /* Recreate the event group ready for the next cycle. */
- xEventGroup = xEventGroupCreate();
- configASSERT( xEventGroup );
-
- /* Perform the tests that check the behaviour when a single task is
- blocked on various combinations of event bits. */
- xError = prvBitCombinationTestMasterFunction( xError, xTestSlaveTaskHandle );
-
- /* Perform the task synchronisation tests. */
- xError = prvPerformTaskSyncTests( xError, xTestSlaveTaskHandle );
-
- /* Delete the event group. */
- vEventGroupDelete( xEventGroup );
-
- /* Now all the other tasks should have completed and suspended
- themselves ready for the next go around the loop. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- /* Only increment the cycle variable if no errors have been detected. */
- if( xError == pdFALSE )
- {
- ulTestMasterCycles++;
- }
-
- configASSERT( xError == pdFALSE );
- }
+ TaskHandle_t xTestSlaveTaskHandle = ( TaskHandle_t ) pvParameters;
+
+ /* Avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Create the event group used by the tasks ready for the initial tests. */
+ xEventGroup = xEventGroupCreate();
+ configASSERT( xEventGroup );
+
+ /* Perform the tests that block two tasks on different combinations of bits,
+ * then set each bit in turn and check the correct tasks unblock at the correct
+ * times. */
+ xError = prvSelectiveBitsTestMasterFunction();
+
+ for( ; ; )
+ {
+ /* Recreate the event group ready for the next cycle. */
+ xEventGroup = xEventGroupCreate();
+ configASSERT( xEventGroup );
+
+ /* Perform the tests that check the behaviour when a single task is
+ * blocked on various combinations of event bits. */
+ xError = prvBitCombinationTestMasterFunction( xError, xTestSlaveTaskHandle );
+
+ /* Perform the task synchronisation tests. */
+ xError = prvPerformTaskSyncTests( xError, xTestSlaveTaskHandle );
+
+ /* Delete the event group. */
+ vEventGroupDelete( xEventGroup );
+
+ /* Now all the other tasks should have completed and suspended
+ * themselves ready for the next go around the loop. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Only increment the cycle variable if no errors have been detected. */
+ if( xError == pdFALSE )
+ {
+ ulTestMasterCycles++;
+ }
+
+ configASSERT( xError == pdFALSE );
+ }
}
/*-----------------------------------------------------------*/
-static void prvSyncTask( void *pvParameters )
+static void prvSyncTask( void * pvParameters )
{
-EventBits_t uxSynchronisationBit, uxReturned;
-
- /* A few tests that check the behaviour when two tasks are blocked on
- various different bits within an event group are performed before this task
- enters its infinite loop to carry out its main demo function. */
- prvSelectiveBitsTestSlaveFunction();
-
- /* The bit to use to indicate this task is at the synchronisation point is
- passed in as the task parameter. */
- uxSynchronisationBit = ( EventBits_t ) pvParameters;
-
- for( ;; )
- {
- /* Now this task takes part in a task synchronisation - sometimes known
- as a 'rendezvous'. Its execution pattern is controlled by the 'test
- master' task, which is responsible for taking this task out of the
- Suspended state when it is time to test the synchronisation behaviour.
- See: http://www.freertos.org/xEventGroupSync.html. */
- vTaskSuspend( NULL );
-
- /* Set the bit that indicates this task is at the synchronisation
- point. The first time this is done the 'test master' task has a lower
- priority than this task so this task will get to the sync point before
- the set bits task - test this by calling xEventGroupSync() with a zero
- block time before calling again with a max delay - the first call should
- return before the rendezvous completes, the second only after the
- rendezvous is complete. */
- uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
- uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
- ebALL_SYNC_BITS,/* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
- ebDONT_BLOCK ); /* The maximum time to wait for the sync condition to be met before giving up. */
-
- /* No block time was specified, so as per the comments above, the
- rendezvous is not expected to have completed yet. */
- configASSERT( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS );
-
- uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
- uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
- ebALL_SYNC_BITS,/* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
- portMAX_DELAY );/* The maximum time to wait for the sync condition to be met before giving up. */
-
- /* A max delay was used, so this task should only exit the above
- function call when the sync condition is met. Check this is the
- case. */
- configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS );
-
- /* Remove compiler warning if configASSERT() is not defined. */
- ( void ) uxReturned;
-
- /* Wait until the 'test master' task unsuspends this task again. */
- vTaskSuspend( NULL );
-
- /* Set the bit that indicates this task is at the synchronisation
- point again. This time the 'test master' task has a higher priority
- than this task so will get to the sync point before this task. */
- uxReturned = xEventGroupSync( xEventGroup, uxSynchronisationBit, ebALL_SYNC_BITS, portMAX_DELAY );
-
- /* Again a max delay was used, so this task should only exit the above
- function call when the sync condition is met. Check this is the
- case. */
- configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS );
-
- /* Block on the event group again. This time the event group is going
- to be deleted while this task is blocked on it so it is expected that 0
- be returned. */
- uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY );
- configASSERT( uxReturned == 0 );
- }
+ EventBits_t uxSynchronisationBit, uxReturned;
+
+ /* A few tests that check the behaviour when two tasks are blocked on
+ * various different bits within an event group are performed before this task
+ * enters its infinite loop to carry out its main demo function. */
+ prvSelectiveBitsTestSlaveFunction();
+
+ /* The bit to use to indicate this task is at the synchronisation point is
+ * passed in as the task parameter. */
+ uxSynchronisationBit = ( EventBits_t ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Now this task takes part in a task synchronisation - sometimes known
+ * as a 'rendezvous'. Its execution pattern is controlled by the 'test
+ * master' task, which is responsible for taking this task out of the
+ * Suspended state when it is time to test the synchronisation behaviour.
+ * See: http://www.freertos.org/xEventGroupSync.html. */
+ vTaskSuspend( NULL );
+
+ /* Set the bit that indicates this task is at the synchronisation
+ * point. The first time this is done the 'test master' task has a lower
+ * priority than this task so this task will get to the sync point before
+ * the set bits task - test this by calling xEventGroupSync() with a zero
+ * block time before calling again with a max delay - the first call should
+ * return before the rendezvous completes, the second only after the
+ * rendezvous is complete. */
+ uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
+ uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
+ ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
+ ebDONT_BLOCK ); /* The maximum time to wait for the sync condition to be met before giving up. */
+
+ /* No block time was specified, so as per the comments above, the
+ * rendezvous is not expected to have completed yet. */
+ configASSERT( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS );
+
+ uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
+ uxSynchronisationBit, /* The bit to set in the event group to indicate this task is at the sync point. */
+ ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks taking part in the sync. */
+ portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met before giving up. */
+
+ /* A max delay was used, so this task should only exit the above
+ * function call when the sync condition is met. Check this is the
+ * case. */
+ configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS );
+
+ /* Remove compiler warning if configASSERT() is not defined. */
+ ( void ) uxReturned;
+
+ /* Wait until the 'test master' task unsuspends this task again. */
+ vTaskSuspend( NULL );
+
+ /* Set the bit that indicates this task is at the synchronisation
+ * point again. This time the 'test master' task has a higher priority
+ * than this task so will get to the sync point before this task. */
+ uxReturned = xEventGroupSync( xEventGroup, uxSynchronisationBit, ebALL_SYNC_BITS, portMAX_DELAY );
+
+ /* Again a max delay was used, so this task should only exit the above
+ * function call when the sync condition is met. Check this is the
+ * case. */
+ configASSERT( ( uxReturned & ebALL_SYNC_BITS ) == ebALL_SYNC_BITS );
+
+ /* Block on the event group again. This time the event group is going
+ * to be deleted while this task is blocked on it so it is expected that 0
+ * be returned. */
+ uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY );
+ configASSERT( uxReturned == 0 );
+ }
}
/*-----------------------------------------------------------*/
-static void prvTestSlaveTask( void *pvParameters )
+static void prvTestSlaveTask( void * pvParameters )
{
-EventBits_t uxReturned;
-BaseType_t xError = pdFALSE;
-
- /* Avoid compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /**********************************************************************
- * Part 1: This section is the counterpart to the
- * prvBitCombinationTestMasterFunction() function which is called by the
- * test master task.
- ***********************************************************************
-
- This task is controller by the 'test master' task (which is
- implemented by prvTestMasterTask()). Suspend until resumed by the
- 'test master' task. */
- vTaskSuspend( NULL );
-
- /* Wait indefinitely for one of the bits in ebCOMBINED_BITS to get
- set. Clear the bit on exit. */
- uxReturned = xEventGroupWaitBits( xEventGroup, /* The event group that contains the event bits being queried. */
- ebBIT_1, /* The bit to wait for. */
- pdTRUE, /* Clear the bit on exit. */
- pdTRUE, /* Wait for all the bits (only one in this case anyway). */
- portMAX_DELAY ); /* Block indefinitely to wait for the condition to be met. */
-
- /* The 'test master' task set all the bits defined by ebCOMBINED_BITS,
- only one of which was being waited for by this task. The return value
- shows the state of the event bits when the task was unblocked, however
- because the task was waiting for ebBIT_1 and 'clear on exit' was set to
- the current state of the event bits will have ebBIT_1 clear. */
- if( uxReturned != ebCOMBINED_BITS )
- {
- xError = pdTRUE;
- }
-
- /* Now call xEventGroupWaitBits() again, this time waiting for all the
- bits in ebCOMBINED_BITS to be set. This call should block until the
- 'test master' task sets ebBIT_1 - which was the bit cleared in the call
- to xEventGroupWaitBits() above. */
- uxReturned = xEventGroupWaitBits( xEventGroup,
- ebCOMBINED_BITS, /* The bits being waited on. */
- pdFALSE, /* Don't clear the bits on exit. */
- pdTRUE, /* All the bits must be set to unblock. */
- portMAX_DELAY );
-
- /* Were all the bits set? */
- if( ( uxReturned & ebCOMBINED_BITS ) != ebCOMBINED_BITS )
- {
- xError = pdTRUE;
- }
-
- /* Suspend again to wait for the 'test master' task. */
- vTaskSuspend( NULL );
-
- /* Now call xEventGroupWaitBits() again, again waiting for all the bits
- in ebCOMBINED_BITS to be set, but this time clearing the bits when the
- task is unblocked. */
- uxReturned = xEventGroupWaitBits( xEventGroup,
- ebCOMBINED_BITS, /* The bits being waited on. */
- pdTRUE, /* Clear the bits on exit. */
- pdTRUE, /* All the bits must be set to unblock. */
- portMAX_DELAY );
-
- /* The 'test master' task set all the bits in the event group, so that
- is the value that should have been returned. The bits defined by
- ebCOMBINED_BITS will have been clear again in the current value though
- as 'clear on exit' was set to pdTRUE. */
- if( uxReturned != ebALL_BITS )
- {
- xError = pdTRUE;
- }
-
-
-
-
-
- /**********************************************************************
- * Part 2: This section is the counterpart to the
- * prvPerformTaskSyncTests() function which is called by the
- * test master task.
- ***********************************************************************
-
-
- Once again wait for the 'test master' task to unsuspend this task
- when it is time for the next test. */
- vTaskSuspend( NULL );
-
- /* Now peform a synchronisation with all the other tasks. At this point
- the 'test master' task has the lowest priority so will get to the sync
- point after all the other synchronising tasks. */
- uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the sync. */
- ebWAIT_BIT_TASK_SYNC_BIT, /* The bit in the event group used to indicate this task is at the sync point. */
- ebALL_SYNC_BITS, /* The bits to wait for. These bits are set by the other tasks taking part in the sync. */
- portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met before giving up. */
-
- /* A sync with a max delay should only exit when all the synchronisation
- bits are set... */
- if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
- {
- xError = pdTRUE;
- }
-
- /* ...but now the synchronisation bits should be clear again. Read back
- the current value of the bits within the event group to check that is
- the case. Setting the bits to zero will return the bits previous value
- then leave all the bits clear. */
- if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 )
- {
- xError = pdTRUE;
- }
-
- /* Check the bits are indeed 0 now by simply reading then. */
- if( xEventGroupGetBits( xEventGroup ) != 0 )
- {
- xError = pdTRUE;
- }
-
- if( xError == pdFALSE )
- {
- /* This task is still cycling without finding an error. */
- ulTestSlaveCycles++;
- }
-
- vTaskSuspend( NULL );
-
- /* This time sync when the 'test master' task has the highest priority
- at the point where it sets its sync bit - so this time the 'test master'
- task will get to the sync point before this task. */
- uxReturned = xEventGroupSync( xEventGroup, ebWAIT_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY );
-
- /* A sync with a max delay should only exit when all the synchronisation
- bits are set... */
- if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
- {
- xError = pdTRUE;
- }
-
- /* ...but now the sync bits should be clear again. */
- if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 )
- {
- xError = pdTRUE;
- }
-
- /* Block on the event group again. This time the event group is going
- to be deleted while this task is blocked on it, so it is expected that 0
- will be returned. */
- uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY );
-
- if( uxReturned != 0 )
- {
- xError = pdTRUE;
- }
-
- if( xError == pdFALSE )
- {
- /* This task is still cycling without finding an error. */
- ulTestSlaveCycles++;
- }
-
- configASSERT( xError == pdFALSE );
- }
+ EventBits_t uxReturned;
+ BaseType_t xError = pdFALSE;
+
+ /* Avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /**********************************************************************
+ * Part 1: This section is the counterpart to the
+ * prvBitCombinationTestMasterFunction() function which is called by the
+ * test master task.
+ ***********************************************************************
+ *
+ * This task is controller by the 'test master' task (which is
+ * implemented by prvTestMasterTask()). Suspend until resumed by the
+ * 'test master' task. */
+ vTaskSuspend( NULL );
+
+ /* Wait indefinitely for one of the bits in ebCOMBINED_BITS to get
+ * set. Clear the bit on exit. */
+ uxReturned = xEventGroupWaitBits( xEventGroup, /* The event group that contains the event bits being queried. */
+ ebBIT_1, /* The bit to wait for. */
+ pdTRUE, /* Clear the bit on exit. */
+ pdTRUE, /* Wait for all the bits (only one in this case anyway). */
+ portMAX_DELAY ); /* Block indefinitely to wait for the condition to be met. */
+
+ /* The 'test master' task set all the bits defined by ebCOMBINED_BITS,
+ * only one of which was being waited for by this task. The return value
+ * shows the state of the event bits when the task was unblocked, however
+ * because the task was waiting for ebBIT_1 and 'clear on exit' was set to
+ * the current state of the event bits will have ebBIT_1 clear. */
+ if( uxReturned != ebCOMBINED_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Now call xEventGroupWaitBits() again, this time waiting for all the
+ * bits in ebCOMBINED_BITS to be set. This call should block until the
+ * 'test master' task sets ebBIT_1 - which was the bit cleared in the call
+ * to xEventGroupWaitBits() above. */
+ uxReturned = xEventGroupWaitBits( xEventGroup,
+ ebCOMBINED_BITS, /* The bits being waited on. */
+ pdFALSE, /* Don't clear the bits on exit. */
+ pdTRUE, /* All the bits must be set to unblock. */
+ portMAX_DELAY );
+
+ /* Were all the bits set? */
+ if( ( uxReturned & ebCOMBINED_BITS ) != ebCOMBINED_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Suspend again to wait for the 'test master' task. */
+ vTaskSuspend( NULL );
+
+ /* Now call xEventGroupWaitBits() again, again waiting for all the bits
+ * in ebCOMBINED_BITS to be set, but this time clearing the bits when the
+ * task is unblocked. */
+ uxReturned = xEventGroupWaitBits( xEventGroup,
+ ebCOMBINED_BITS, /* The bits being waited on. */
+ pdTRUE, /* Clear the bits on exit. */
+ pdTRUE, /* All the bits must be set to unblock. */
+ portMAX_DELAY );
+
+ /* The 'test master' task set all the bits in the event group, so that
+ * is the value that should have been returned. The bits defined by
+ * ebCOMBINED_BITS will have been clear again in the current value though
+ * as 'clear on exit' was set to pdTRUE. */
+ if( uxReturned != ebALL_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /**********************************************************************
+ * Part 2: This section is the counterpart to the
+ * prvPerformTaskSyncTests() function which is called by the
+ * test master task.
+ ***********************************************************************
+ *
+ *
+ * Once again wait for the 'test master' task to unsuspend this task
+ * when it is time for the next test. */
+ vTaskSuspend( NULL );
+
+ /* Now peform a synchronisation with all the other tasks. At this point
+ * the 'test master' task has the lowest priority so will get to the sync
+ * point after all the other synchronising tasks. */
+ uxReturned = xEventGroupSync( xEventGroup, /* The event group used for the sync. */
+ ebWAIT_BIT_TASK_SYNC_BIT, /* The bit in the event group used to indicate this task is at the sync point. */
+ ebALL_SYNC_BITS, /* The bits to wait for. These bits are set by the other tasks taking part in the sync. */
+ portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met before giving up. */
+
+ /* A sync with a max delay should only exit when all the synchronisation
+ * bits are set... */
+ if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* ...but now the synchronisation bits should be clear again. Read back
+ * the current value of the bits within the event group to check that is
+ * the case. Setting the bits to zero will return the bits previous value
+ * then leave all the bits clear. */
+ if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Check the bits are indeed 0 now by simply reading then. */
+ if( xEventGroupGetBits( xEventGroup ) != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ if( xError == pdFALSE )
+ {
+ /* This task is still cycling without finding an error. */
+ ulTestSlaveCycles++;
+ }
+
+ vTaskSuspend( NULL );
+
+ /* This time sync when the 'test master' task has the highest priority
+ * at the point where it sets its sync bit - so this time the 'test master'
+ * task will get to the sync point before this task. */
+ uxReturned = xEventGroupSync( xEventGroup, ebWAIT_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY );
+
+ /* A sync with a max delay should only exit when all the synchronisation
+ * bits are set... */
+ if( ( uxReturned & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* ...but now the sync bits should be clear again. */
+ if( xEventGroupSetBits( xEventGroup, 0x00 ) != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Block on the event group again. This time the event group is going
+ * to be deleted while this task is blocked on it, so it is expected that 0
+ * will be returned. */
+ uxReturned = xEventGroupWaitBits( xEventGroup, ebALL_SYNC_BITS, pdFALSE, pdTRUE, portMAX_DELAY );
+
+ if( uxReturned != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ if( xError == pdFALSE )
+ {
+ /* This task is still cycling without finding an error. */
+ ulTestSlaveCycles++;
+ }
+
+ configASSERT( xError == pdFALSE );
+ }
}
/*-----------------------------------------------------------*/
-static BaseType_t prvPerformTaskSyncTests( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle )
+static BaseType_t prvPerformTaskSyncTests( BaseType_t xError,
+ TaskHandle_t xTestSlaveTaskHandle )
{
-EventBits_t uxBits;
-
- /* The three tasks that take part in the synchronisation (rendezvous) are
- expected to be in the suspended state at the start of the test. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- /* Try a synch with no other tasks involved. First set all the bits other
- than this task's bit. */
- xEventGroupSetBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) );
-
- /* Then wait on just one bit - the bit that is being set. */
- uxBits = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
- ebSET_BIT_TASK_SYNC_BIT,/* The bit set by this task when it reaches the sync point. */
- ebSET_BIT_TASK_SYNC_BIT,/* The bits to wait for - in this case it is just waiting for itself. */
- portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met. */
-
- /* A sync with a max delay should only exit when all the synchronise
- bits are set...check that is the case. In this case there is only one
- sync bit anyway. */
- if( ( uxBits & ebSET_BIT_TASK_SYNC_BIT ) != ebSET_BIT_TASK_SYNC_BIT )
- {
- xError = pdTRUE;
- }
-
- /* ...but now the sync bits should be clear again, leaving all the other
- bits set (as only one bit was being waited for). */
- if( xEventGroupGetBits( xEventGroup ) != ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) )
- {
- xError = pdTRUE;
- }
-
- /* Clear all the bits to zero again. */
- xEventGroupClearBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) );
- if( xEventGroupGetBits( xEventGroup ) != 0 )
- {
- xError = pdTRUE;
- }
-
- /* Unsuspend the other tasks then check they have executed up to the
- synchronisation point. */
- vTaskResume( xTestSlaveTaskHandle );
- vTaskResume( xSyncTask1 );
- vTaskResume( xSyncTask2 );
-
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Set this task's sync bit. */
- uxBits = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
- ebSET_BIT_TASK_SYNC_BIT,/* The bit set by this task when it reaches the sync point. */
- ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks that take part in the sync. */
- portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met. */
-
- /* A sync with a max delay should only exit when all the synchronise
- bits are set...check that is the case. */
- if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
- {
- xError = pdTRUE;
- }
-
- /* ...but now the sync bits should be clear again. */
- if( xEventGroupGetBits( xEventGroup ) != 0 )
- {
- xError = pdTRUE;
- }
-
-
- /* The other tasks should now all be suspended again, ready for the next
- synchronisation. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
-
- /* Sync again - but this time set the last necessary bit as the
- highest priority task, rather than the lowest priority task. Unsuspend
- the other tasks then check they have executed up to the synchronisation
- point. */
- vTaskResume( xTestSlaveTaskHandle );
- vTaskResume( xSyncTask1 );
- vTaskResume( xSyncTask2 );
-
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Raise the priority of this task above that of the other tasks. */
- vTaskPrioritySet( NULL, ebWAIT_BIT_TASK_PRIORITY + 1 );
-
- /* Set this task's sync bit. */
- uxBits = xEventGroupSync( xEventGroup, ebSET_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY );
-
- /* A sync with a max delay should only exit when all the synchronisation
- bits are set... */
- if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
- {
- xError = pdTRUE;
- }
-
- /* ...but now the sync bits should be clear again. */
- if( xEventGroupGetBits( xEventGroup ) != 0 )
- {
- xError = pdTRUE;
- }
-
-
- /* The other tasks should now all be in the ready state again, but not
- executed yet as this task still has a higher relative priority. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eReady )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eReady )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eReady )
- {
- xError = pdTRUE;
- }
-
-
- /* Reset the priority of this task back to its original value. */
- vTaskPrioritySet( NULL, ebSET_BIT_TASK_PRIORITY );
-
- /* Now all the other tasks should have reblocked on the event bits
- to test the behaviour when the event bits are deleted. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask1 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- return xError;
+ EventBits_t uxBits;
+
+ /* The three tasks that take part in the synchronisation (rendezvous) are
+ * expected to be in the suspended state at the start of the test. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Try a synch with no other tasks involved. First set all the bits other
+ * than this task's bit. */
+ xEventGroupSetBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) );
+
+ /* Then wait on just one bit - the bit that is being set. */
+ uxBits = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
+ ebSET_BIT_TASK_SYNC_BIT, /* The bit set by this task when it reaches the sync point. */
+ ebSET_BIT_TASK_SYNC_BIT, /* The bits to wait for - in this case it is just waiting for itself. */
+ portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met. */
+
+ /* A sync with a max delay should only exit when all the synchronise
+ * bits are set...check that is the case. In this case there is only one
+ * sync bit anyway. */
+ if( ( uxBits & ebSET_BIT_TASK_SYNC_BIT ) != ebSET_BIT_TASK_SYNC_BIT )
+ {
+ xError = pdTRUE;
+ }
+
+ /* ...but now the sync bits should be clear again, leaving all the other
+ * bits set (as only one bit was being waited for). */
+ if( xEventGroupGetBits( xEventGroup ) != ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Clear all the bits to zero again. */
+ xEventGroupClearBits( xEventGroup, ( ebALL_SYNC_BITS & ~ebSET_BIT_TASK_SYNC_BIT ) );
+
+ if( xEventGroupGetBits( xEventGroup ) != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Unsuspend the other tasks then check they have executed up to the
+ * synchronisation point. */
+ vTaskResume( xTestSlaveTaskHandle );
+ vTaskResume( xSyncTask1 );
+ vTaskResume( xSyncTask2 );
+
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Set this task's sync bit. */
+ uxBits = xEventGroupSync( xEventGroup, /* The event group used for the synchronisation. */
+ ebSET_BIT_TASK_SYNC_BIT, /* The bit set by this task when it reaches the sync point. */
+ ebALL_SYNC_BITS, /* The bits to wait for - these bits are set by the other tasks that take part in the sync. */
+ portMAX_DELAY ); /* The maximum time to wait for the sync condition to be met. */
+
+ /* A sync with a max delay should only exit when all the synchronise
+ * bits are set...check that is the case. */
+ if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* ...but now the sync bits should be clear again. */
+ if( xEventGroupGetBits( xEventGroup ) != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ /* The other tasks should now all be suspended again, ready for the next
+ * synchronisation. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Sync again - but this time set the last necessary bit as the
+ * highest priority task, rather than the lowest priority task. Unsuspend
+ * the other tasks then check they have executed up to the synchronisation
+ * point. */
+ vTaskResume( xTestSlaveTaskHandle );
+ vTaskResume( xSyncTask1 );
+ vTaskResume( xSyncTask2 );
+
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Raise the priority of this task above that of the other tasks. */
+ vTaskPrioritySet( NULL, ebWAIT_BIT_TASK_PRIORITY + 1 );
+
+ /* Set this task's sync bit. */
+ uxBits = xEventGroupSync( xEventGroup, ebSET_BIT_TASK_SYNC_BIT, ebALL_SYNC_BITS, portMAX_DELAY );
+
+ /* A sync with a max delay should only exit when all the synchronisation
+ * bits are set... */
+ if( ( uxBits & ebALL_SYNC_BITS ) != ebALL_SYNC_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* ...but now the sync bits should be clear again. */
+ if( xEventGroupGetBits( xEventGroup ) != 0 )
+ {
+ xError = pdTRUE;
+ }
+
+ /* The other tasks should now all be in the ready state again, but not
+ * executed yet as this task still has a higher relative priority. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eReady )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eReady )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eReady )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Reset the priority of this task back to its original value. */
+ vTaskPrioritySet( NULL, ebSET_BIT_TASK_PRIORITY );
+
+ /* Now all the other tasks should have reblocked on the event bits
+ * to test the behaviour when the event bits are deleted. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask1 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ return xError;
}
/*-----------------------------------------------------------*/
-static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError, TaskHandle_t xTestSlaveTaskHandle )
+static BaseType_t prvBitCombinationTestMasterFunction( BaseType_t xError,
+ TaskHandle_t xTestSlaveTaskHandle )
{
-EventBits_t uxBits;
-
- /* Resume the other task. It will block, pending a single bit from
- within ebCOMBINED_BITS. */
- vTaskResume( xTestSlaveTaskHandle );
-
- /* Ensure the other task is blocked on the task. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Set all the bits in ebCOMBINED_BITS - the 'test slave' task is only
- blocked waiting for one of them. */
- xEventGroupSetBits( xEventGroup, ebCOMBINED_BITS );
-
- /* The 'test slave' task should now have executed, clearing ebBIT_1 (the
- bit it was blocked on), then re-entered the Blocked state to wait for
- all the other bits in ebCOMBINED_BITS to be set again. First check
- ebBIT_1 is clear. */
- uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
-
- if( uxBits != ( ebCOMBINED_BITS & ~ebBIT_1 ) )
- {
- xError = pdTRUE;
- }
-
- /* Ensure the other task is still in the blocked state. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Set all the bits other than ebBIT_1 - which is the bit that must be
- set before the other task unblocks. */
- xEventGroupSetBits( xEventGroup, ebALL_BITS & ~ebBIT_1 );
-
- /* Ensure all the expected bits are still set. */
- uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
-
- if( uxBits != ( ebALL_BITS & ~ebBIT_1 ) )
- {
- xError = pdTRUE;
- }
-
- /* Ensure the other task is still in the blocked state. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Now also set ebBIT_1, which should unblock the other task, which will
- then suspend itself. */
- xEventGroupSetBits( xEventGroup, ebBIT_1 );
-
- /* Ensure the other task is suspended. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- /* The other task should not have cleared the bits - so all the bits
- should still be set. */
- if( xEventGroupSetBits( xEventGroup, 0x00 ) != ebALL_BITS )
- {
- xError = pdTRUE;
- }
-
- /* Clear ebBIT_1 again. */
- if( xEventGroupClearBits( xEventGroup, ebBIT_1 ) != ebALL_BITS )
- {
- xError = pdTRUE;
- }
-
- /* Resume the other task - which will wait on all the ebCOMBINED_BITS
- again - this time clearing the bits when it is unblocked. */
- vTaskResume( xTestSlaveTaskHandle );
-
- /* Ensure the other task is blocked once again. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Set the bit the other task is waiting for. */
- xEventGroupSetBits( xEventGroup, ebBIT_1 );
-
- /* Ensure the other task is suspended once again. */
- if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- /* The other task should have cleared the bits in ebCOMBINED_BITS.
- Clear the remaining bits. */
- uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
-
- if( uxBits != ( ebALL_BITS & ~ebCOMBINED_BITS ) )
- {
- xError = pdTRUE;
- }
-
- /* Clear all bits ready for the sync with the other three tasks. The
- value returned is the value prior to the bits being cleared. */
- if( xEventGroupClearBits( xEventGroup, ebALL_BITS ) != ( ebALL_BITS & ~ebCOMBINED_BITS ) )
- {
- xError = pdTRUE;
- }
-
- /* The bits should be clear now. */
- if( xEventGroupGetBits( xEventGroup ) != 0x00 )
- {
- xError = pdTRUE;
- }
-
- return xError;
+ EventBits_t uxBits;
+
+ /* Resume the other task. It will block, pending a single bit from
+ * within ebCOMBINED_BITS. */
+ vTaskResume( xTestSlaveTaskHandle );
+
+ /* Ensure the other task is blocked on the task. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Set all the bits in ebCOMBINED_BITS - the 'test slave' task is only
+ * blocked waiting for one of them. */
+ xEventGroupSetBits( xEventGroup, ebCOMBINED_BITS );
+
+ /* The 'test slave' task should now have executed, clearing ebBIT_1 (the
+ * bit it was blocked on), then re-entered the Blocked state to wait for
+ * all the other bits in ebCOMBINED_BITS to be set again. First check
+ * ebBIT_1 is clear. */
+ uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
+
+ if( uxBits != ( ebCOMBINED_BITS & ~ebBIT_1 ) )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Ensure the other task is still in the blocked state. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Set all the bits other than ebBIT_1 - which is the bit that must be
+ * set before the other task unblocks. */
+ xEventGroupSetBits( xEventGroup, ebALL_BITS & ~ebBIT_1 );
+
+ /* Ensure all the expected bits are still set. */
+ uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
+
+ if( uxBits != ( ebALL_BITS & ~ebBIT_1 ) )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Ensure the other task is still in the blocked state. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Now also set ebBIT_1, which should unblock the other task, which will
+ * then suspend itself. */
+ xEventGroupSetBits( xEventGroup, ebBIT_1 );
+
+ /* Ensure the other task is suspended. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ /* The other task should not have cleared the bits - so all the bits
+ * should still be set. */
+ if( xEventGroupSetBits( xEventGroup, 0x00 ) != ebALL_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Clear ebBIT_1 again. */
+ if( xEventGroupClearBits( xEventGroup, ebBIT_1 ) != ebALL_BITS )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Resume the other task - which will wait on all the ebCOMBINED_BITS
+ * again - this time clearing the bits when it is unblocked. */
+ vTaskResume( xTestSlaveTaskHandle );
+
+ /* Ensure the other task is blocked once again. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Set the bit the other task is waiting for. */
+ xEventGroupSetBits( xEventGroup, ebBIT_1 );
+
+ /* Ensure the other task is suspended once again. */
+ if( eTaskGetState( xTestSlaveTaskHandle ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ /* The other task should have cleared the bits in ebCOMBINED_BITS.
+ * Clear the remaining bits. */
+ uxBits = xEventGroupWaitBits( xEventGroup, ebALL_BITS, pdFALSE, pdFALSE, ebDONT_BLOCK );
+
+ if( uxBits != ( ebALL_BITS & ~ebCOMBINED_BITS ) )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Clear all bits ready for the sync with the other three tasks. The
+ * value returned is the value prior to the bits being cleared. */
+ if( xEventGroupClearBits( xEventGroup, ebALL_BITS ) != ( ebALL_BITS & ~ebCOMBINED_BITS ) )
+ {
+ xError = pdTRUE;
+ }
+
+ /* The bits should be clear now. */
+ if( xEventGroupGetBits( xEventGroup ) != 0x00 )
+ {
+ xError = pdTRUE;
+ }
+
+ return xError;
}
/*-----------------------------------------------------------*/
static void prvSelectiveBitsTestSlaveFunction( void )
{
-EventBits_t uxPendBits, uxReturned;
-
- /* Used in a test that blocks two tasks on various different bits within an
- event group - then sets each bit in turn and checks that the correct tasks
- unblock at the correct times.
-
- This function is called by two different tasks - each of which will use a
- different bit. Check the task handle to see which task the function was
- called by. */
- if( xTaskGetCurrentTaskHandle() == xSyncTask1 )
- {
- uxPendBits = ebSELECTIVE_BITS_1;
- }
- else
- {
- uxPendBits = ebSELECTIVE_BITS_2;
- }
-
- for( ;; )
- {
- /* Wait until it is time to perform the next cycle of the test. The
- task is unsuspended by the tests implemented in the
- prvSelectiveBitsTestMasterFunction() function. */
- vTaskSuspend( NULL );
- uxReturned = xEventGroupWaitBits( xEventGroup, uxPendBits, pdTRUE, pdFALSE, portMAX_DELAY );
-
- if( uxReturned == ( EventBits_t ) 0 )
- {
- break;
- }
- }
+ EventBits_t uxPendBits, uxReturned;
+
+ /* Used in a test that blocks two tasks on various different bits within an
+ * event group - then sets each bit in turn and checks that the correct tasks
+ * unblock at the correct times.
+ *
+ * This function is called by two different tasks - each of which will use a
+ * different bit. Check the task handle to see which task the function was
+ * called by. */
+ if( xTaskGetCurrentTaskHandle() == xSyncTask1 )
+ {
+ uxPendBits = ebSELECTIVE_BITS_1;
+ }
+ else
+ {
+ uxPendBits = ebSELECTIVE_BITS_2;
+ }
+
+ for( ; ; )
+ {
+ /* Wait until it is time to perform the next cycle of the test. The
+ * task is unsuspended by the tests implemented in the
+ * prvSelectiveBitsTestMasterFunction() function. */
+ vTaskSuspend( NULL );
+ uxReturned = xEventGroupWaitBits( xEventGroup, uxPendBits, pdTRUE, pdFALSE, portMAX_DELAY );
+
+ if( uxReturned == ( EventBits_t ) 0 )
+ {
+ break;
+ }
+ }
}
/*-----------------------------------------------------------*/
static BaseType_t prvSelectiveBitsTestMasterFunction( void )
{
-BaseType_t xError = pdFALSE;
-EventBits_t uxBit;
-
- /* Used in a test that blocks two tasks on various different bits within an
- event group - then sets each bit in turn and checks that the correct tasks
- unblock at the correct times. The two other tasks (xSyncTask1 and
- xSyncTask2) call prvSelectiveBitsTestSlaveFunction() to perform their parts in
- this test.
-
- Both other tasks should start in the suspended state. */
- if( eTaskGetState( xSyncTask1 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eSuspended )
- {
- xError = pdTRUE;
- }
-
- /* Test each bit in the byte individually. */
- for( uxBit = 0x01; uxBit < 0x100; uxBit <<= 1 )
- {
- /* Resume both tasks. */
- vTaskResume( xSyncTask1 );
- vTaskResume( xSyncTask2 );
-
- /* Now both tasks should be blocked on the event group. */
- if( eTaskGetState( xSyncTask1 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- if( eTaskGetState( xSyncTask2 ) != eBlocked )
- {
- xError = pdTRUE;
- }
-
- /* Set one bit. */
- xEventGroupSetBits( xEventGroup, uxBit );
-
- /* Is the bit set in the first set of selective bits? If so the first
- sync task should have unblocked and returned to the suspended state. */
- if( ( uxBit & ebSELECTIVE_BITS_1 ) == 0 )
- {
- /* Task should not have unblocked. */
- if( eTaskGetState( xSyncTask1 ) != eBlocked )
- {
- xError = pdTRUE;
- }
- }
- else
- {
- /* Task should have unblocked and returned to the suspended state. */
- if( eTaskGetState( xSyncTask1 ) != eSuspended )
- {
- xError = pdTRUE;
- }
- }
-
- /* Same checks for the second sync task. */
- if( ( uxBit & ebSELECTIVE_BITS_2 ) == 0 )
- {
- /* Task should not have unblocked. */
- if( eTaskGetState( xSyncTask2 ) != eBlocked )
- {
- xError = pdTRUE;
- }
- }
- else
- {
- /* Task should have unblocked and returned to the suspended state. */
- if( eTaskGetState( xSyncTask2 ) != eSuspended )
- {
- xError = pdTRUE;
- }
- }
- }
-
- /* Ensure both tasks are blocked on the event group again, then delete the
- event group so the other tasks leave this portion of the test. */
- vTaskResume( xSyncTask1 );
- vTaskResume( xSyncTask2 );
-
- /* Deleting the event group is the signal that the two other tasks should
- leave the prvSelectiveBitsTestSlaveFunction() function and continue to the main
- part of their functionality. */
- vEventGroupDelete( xEventGroup );
-
- return xError;
+ BaseType_t xError = pdFALSE;
+ EventBits_t uxBit;
+
+ /* Used in a test that blocks two tasks on various different bits within an
+ * event group - then sets each bit in turn and checks that the correct tasks
+ * unblock at the correct times. The two other tasks (xSyncTask1 and
+ * xSyncTask2) call prvSelectiveBitsTestSlaveFunction() to perform their parts in
+ * this test.
+ *
+ * Both other tasks should start in the suspended state. */
+ if( eTaskGetState( xSyncTask1 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Test each bit in the byte individually. */
+ for( uxBit = 0x01; uxBit < 0x100; uxBit <<= 1 )
+ {
+ /* Resume both tasks. */
+ vTaskResume( xSyncTask1 );
+ vTaskResume( xSyncTask2 );
+
+ /* Now both tasks should be blocked on the event group. */
+ if( eTaskGetState( xSyncTask1 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ if( eTaskGetState( xSyncTask2 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+
+ /* Set one bit. */
+ xEventGroupSetBits( xEventGroup, uxBit );
+
+ /* Is the bit set in the first set of selective bits? If so the first
+ * sync task should have unblocked and returned to the suspended state. */
+ if( ( uxBit & ebSELECTIVE_BITS_1 ) == 0 )
+ {
+ /* Task should not have unblocked. */
+ if( eTaskGetState( xSyncTask1 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+ }
+ else
+ {
+ /* Task should have unblocked and returned to the suspended state. */
+ if( eTaskGetState( xSyncTask1 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+ }
+
+ /* Same checks for the second sync task. */
+ if( ( uxBit & ebSELECTIVE_BITS_2 ) == 0 )
+ {
+ /* Task should not have unblocked. */
+ if( eTaskGetState( xSyncTask2 ) != eBlocked )
+ {
+ xError = pdTRUE;
+ }
+ }
+ else
+ {
+ /* Task should have unblocked and returned to the suspended state. */
+ if( eTaskGetState( xSyncTask2 ) != eSuspended )
+ {
+ xError = pdTRUE;
+ }
+ }
+ }
+
+ /* Ensure both tasks are blocked on the event group again, then delete the
+ * event group so the other tasks leave this portion of the test. */
+ vTaskResume( xSyncTask1 );
+ vTaskResume( xSyncTask2 );
+
+ /* Deleting the event group is the signal that the two other tasks should
+ * leave the prvSelectiveBitsTestSlaveFunction() function and continue to the main
+ * part of their functionality. */
+ vEventGroupDelete( xEventGroup );
+
+ return xError;
}
/*-----------------------------------------------------------*/
void vPeriodicEventGroupsProcessing( void )
{
-static BaseType_t xCallCount = 0, xISRTestError = pdFALSE;
-const BaseType_t xSetBitCount = 100, xGetBitsCount = 200, xClearBitsCount = 300;
-const EventBits_t uxBitsToSet = 0x12U;
-EventBits_t uxReturned;
-BaseType_t xMessagePosted;
-
- /* Called periodically from the tick hook to exercise the "FromISR"
- functions. */
-
- /* Check the even group tasks were actually created. */
- configASSERT( xISREventGroup );
-
- xCallCount++;
-
- if( xCallCount == xSetBitCount )
- {
- /* All the event bits should start clear. */
- uxReturned = xEventGroupGetBitsFromISR( xISREventGroup );
- if( uxReturned != 0x00 )
- {
- xISRTestError = pdTRUE;
- }
- else
- {
- /* Set the bits. This is called from the tick hook so it is not
- necessary to use the last parameter to ensure a context switch
- occurs immediately. */
- xMessagePosted = xEventGroupSetBitsFromISR( xISREventGroup, uxBitsToSet, NULL );
- if( xMessagePosted != pdPASS )
- {
- xISRTestError = pdTRUE;
- }
- }
- }
- else if( xCallCount == xGetBitsCount )
- {
- /* Check the bits were set as expected. */
- uxReturned = xEventGroupGetBitsFromISR( xISREventGroup );
- if( uxReturned != uxBitsToSet )
- {
- xISRTestError = pdTRUE;
- }
- }
- else if( xCallCount == xClearBitsCount )
- {
- /* Clear the bits again. */
- uxReturned = ( EventBits_t ) xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );
-
- /* Check the message was posted. */
- if( uxReturned != pdPASS )
- {
- xISRTestError = pdTRUE;
- }
-
- /* Go back to the start. */
- xCallCount = 0;
-
- /* If no errors have been detected then increment the count of test
- cycles. */
- if( xISRTestError == pdFALSE )
- {
- ulISRCycles++;
- }
- }
- else
- {
- /* Nothing else to do. */
- }
+ static BaseType_t xCallCount = 0, xISRTestError = pdFALSE;
+ const BaseType_t xSetBitCount = 100, xGetBitsCount = 200, xClearBitsCount = 300;
+ const EventBits_t uxBitsToSet = 0x12U;
+ EventBits_t uxReturned;
+ BaseType_t xMessagePosted;
+
+ /* Called periodically from the tick hook to exercise the "FromISR"
+ * functions. */
+
+ /* Check the even group tasks were actually created. */
+ configASSERT( xISREventGroup );
+
+ xCallCount++;
+
+ if( xCallCount == xSetBitCount )
+ {
+ /* All the event bits should start clear. */
+ uxReturned = xEventGroupGetBitsFromISR( xISREventGroup );
+
+ if( uxReturned != 0x00 )
+ {
+ xISRTestError = pdTRUE;
+ }
+ else
+ {
+ /* Set the bits. This is called from the tick hook so it is not
+ * necessary to use the last parameter to ensure a context switch
+ * occurs immediately. */
+ xMessagePosted = xEventGroupSetBitsFromISR( xISREventGroup, uxBitsToSet, NULL );
+
+ if( xMessagePosted != pdPASS )
+ {
+ xISRTestError = pdTRUE;
+ }
+ }
+ }
+ else if( xCallCount == xGetBitsCount )
+ {
+ /* Check the bits were set as expected. */
+ uxReturned = xEventGroupGetBitsFromISR( xISREventGroup );
+
+ if( uxReturned != uxBitsToSet )
+ {
+ xISRTestError = pdTRUE;
+ }
+ }
+ else if( xCallCount == xClearBitsCount )
+ {
+ /* Clear the bits again. */
+ uxReturned = ( EventBits_t ) xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );
+
+ /* Check the message was posted. */
+ if( uxReturned != pdPASS )
+ {
+ xISRTestError = pdTRUE;
+ }
+
+ /* Go back to the start. */
+ xCallCount = 0;
+
+ /* If no errors have been detected then increment the count of test
+ * cycles. */
+ if( xISRTestError == pdFALSE )
+ {
+ ulISRCycles++;
+ }
+ }
+ else
+ {
+ /* Nothing else to do. */
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreEventGroupTasksStillRunning( void )
{
-static uint32_t ulPreviousWaitBitCycles = 0, ulPreviousSetBitCycles = 0, ulPreviousISRCycles = 0;
-BaseType_t xStatus = pdPASS;
-
- /* Check the tasks are still cycling without finding any errors. */
- if( ulPreviousSetBitCycles == ulTestMasterCycles )
- {
- xStatus = pdFAIL;
- }
- ulPreviousSetBitCycles = ulTestMasterCycles;
-
- if( ulPreviousWaitBitCycles == ulTestSlaveCycles )
- {
- xStatus = pdFAIL;
- }
- ulPreviousWaitBitCycles = ulTestSlaveCycles;
-
- if( ulPreviousISRCycles == ulISRCycles )
- {
- xStatus = pdFAIL;
- }
- ulPreviousISRCycles = ulISRCycles;
-
- return xStatus;
-}
+ static uint32_t ulPreviousWaitBitCycles = 0, ulPreviousSetBitCycles = 0, ulPreviousISRCycles = 0;
+ BaseType_t xStatus = pdPASS;
+ /* Check the tasks are still cycling without finding any errors. */
+ if( ulPreviousSetBitCycles == ulTestMasterCycles )
+ {
+ xStatus = pdFAIL;
+ }
+ ulPreviousSetBitCycles = ulTestMasterCycles;
+ if( ulPreviousWaitBitCycles == ulTestSlaveCycles )
+ {
+ xStatus = pdFAIL;
+ }
+
+ ulPreviousWaitBitCycles = ulTestSlaveCycles;
+
+ if( ulPreviousISRCycles == ulISRCycles )
+ {
+ xStatus = pdFAIL;
+ }
+
+ ulPreviousISRCycles = ulISRCycles;
+
+ return xStatus;
+}
diff --git a/Demo/Common/Minimal/GenQTest.c b/Demo/Common/Minimal/GenQTest.c
index 100e2ef88..f5169f50e 100644
--- a/Demo/Common/Minimal/GenQTest.c
+++ b/Demo/Common/Minimal/GenQTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
@@ -47,21 +46,21 @@
/* Demo program include files. */
#include "GenQTest.h"
-#define genqQUEUE_LENGTH ( 5 )
-#define intsemNO_BLOCK ( 0 )
-#define genqSHORT_BLOCK ( pdMS_TO_TICKS( 2 ) )
+#define genqQUEUE_LENGTH ( 5 )
+#define intsemNO_BLOCK ( 0 )
+#define genqSHORT_BLOCK ( pdMS_TO_TICKS( 2 ) )
-#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY )
-#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 )
+#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY )
+#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 )
#ifndef genqMUTEX_TEST_TASK_STACK_SIZE
- #define genqMUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define genqMUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
#ifndef genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE
- #define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
/*-----------------------------------------------------------*/
@@ -71,7 +70,7 @@
* check the resultant queue order is as expected. Queue data is also
* peeked.
*/
-static void prvSendFrontAndBackTest( void *pvParameters );
+static void prvSendFrontAndBackTest( void * pvParameters );
/*
* The following three tasks are used to demonstrate the mutex behaviour.
@@ -87,9 +86,9 @@ static void prvSendFrontAndBackTest( void *pvParameters );
* low priority, and is therefore immediately preempted by first the high
* priority task and then the medium priority task before it can continue.
*/
-static void prvLowPriorityMutexTask( void *pvParameters );
-static void prvMediumPriorityMutexTask( void *pvParameters );
-static void prvHighPriorityMutexTask( void *pvParameters );
+static void prvLowPriorityMutexTask( void * pvParameters );
+static void prvMediumPriorityMutexTask( void * pvParameters );
+static void prvHighPriorityMutexTask( void * pvParameters );
/*
* Tests the behaviour when a low priority task inherits the priority of a
@@ -97,29 +96,31 @@ static void prvHighPriorityMutexTask( void *pvParameters );
* first the same order as the two mutexes were obtained, and second the
* opposite order as the two mutexes were obtained.
*/
-static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex );
-static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex );
+static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex,
+ SemaphoreHandle_t xLocalMutex );
+static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex,
+ SemaphoreHandle_t xLocalMutex );
-#if( INCLUDE_xTaskAbortDelay == 1 )
+#if ( INCLUDE_xTaskAbortDelay == 1 )
- #if( configUSE_PREEMPTION == 0 )
- #error The additional tests included when INCLUDE_xTaskAbortDelay is 1 expect preemption to be used.
- #endif
+ #if ( configUSE_PREEMPTION == 0 )
+ #error The additional tests included when INCLUDE_xTaskAbortDelay is 1 expect preemption to be used.
+ #endif
- /* Tests the behaviour when a low priority task inherits the priority of a
- high priority task only for the high priority task to timeout before
- obtaining the mutex. */
- static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex );
+/* Tests the behaviour when a low priority task inherits the priority of a
+ * high priority task only for the high priority task to timeout before
+ * obtaining the mutex. */
+ static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex );
#endif
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
-detected in any of the tasks. */
+ * detected in any of the tasks. */
static volatile BaseType_t xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
-detect a stalled task - a test that is no longer running. */
+ * detect a stalled task - a test that is no longer running. */
static volatile uint32_t ulLoopCounter = 0;
static volatile uint32_t ulLoopCounter2 = 0;
@@ -127,875 +128,886 @@ static volatile uint32_t ulLoopCounter2 = 0;
static volatile uint32_t ulGuardedVariable = 0;
/* Handles used in the mutex test to suspend and resume the high and medium
-priority mutex test tasks. */
+ * priority mutex test tasks. */
static TaskHandle_t xHighPriorityMutexTask, xMediumPriorityMutexTask;
/* If INCLUDE_xTaskAbortDelay is 1 additional tests are performed, requiring an
-additional task. */
-#if( INCLUDE_xTaskAbortDelay == 1 )
- static TaskHandle_t xSecondMediumPriorityMutexTask;
+ * additional task. */
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+ static TaskHandle_t xSecondMediumPriorityMutexTask;
#endif
/* Lets the high priority semaphore task know that its wait for the semaphore
-was aborted, in which case not being able to obtain the semaphore is not to be
-considered an error. */
+ * was aborted, in which case not being able to obtain the semaphore is not to be
+ * considered an error. */
static volatile BaseType_t xBlockWasAborted = pdFALSE;
/*-----------------------------------------------------------*/
void vStartGenericQueueTasks( UBaseType_t uxPriority )
{
-QueueHandle_t xQueue;
-SemaphoreHandle_t xMutex;
-
- /* Create the queue that we are going to use for the
- prvSendFrontAndBackTest demo. */
- xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( uint32_t ) );
-
- if( xQueue != NULL )
- {
- /* vQueueAddToRegistry() adds the queue to the queue registry, if one
- is in use. The queue registry is provided as a means for kernel aware
- debuggers to locate queues and has no purpose if a kernel aware debugger
- is not being used. The call to vQueueAddToRegistry() will be removed
- by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
- defined to be less than 1. */
- vQueueAddToRegistry( xQueue, "Gen_Queue_Test" );
-
- /* Create the demo task and pass it the queue just created. We are
- passing the queue handle by value so it does not matter that it is
- declared on the stack here. */
- xTaskCreate( prvSendFrontAndBackTest, "GenQ", genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );
- }
-
- /* Create the mutex used by the prvMutexTest task. */
- xMutex = xSemaphoreCreateMutex();
-
- if( xMutex != NULL )
- {
- /* vQueueAddToRegistry() adds the mutex to the registry, if one is
- in use. The registry is provided as a means for kernel aware
- debuggers to locate mutexes and has no purpose if a kernel aware
- debugger is not being used. The call to vQueueAddToRegistry() will be
- removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
- defined or is defined to be less than 1. */
- vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Gen_Queue_Mutex" );
-
- /* Create the mutex demo tasks and pass it the mutex just created. We
- are passing the mutex handle by value so it does not matter that it is
- declared on the stack here. */
- xTaskCreate( prvLowPriorityMutexTask, "MuLow", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );
- xTaskCreate( prvMediumPriorityMutexTask, "MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );
- xTaskCreate( prvHighPriorityMutexTask, "MuHigh", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );
-
- /* If INCLUDE_xTaskAbortDelay is set then additional tests are performed,
- requiring two instances of prvHighPriorityMutexTask(). */
- #if( INCLUDE_xTaskAbortDelay == 1 )
- {
- xTaskCreate( prvHighPriorityMutexTask, "MuHigh2", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_MEDIUM_PRIORITY, &xSecondMediumPriorityMutexTask );
- }
- #endif /* INCLUDE_xTaskAbortDelay */
- }
+ QueueHandle_t xQueue;
+ SemaphoreHandle_t xMutex;
+
+ /* Create the queue that we are going to use for the
+ * prvSendFrontAndBackTest demo. */
+ xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xQueue != NULL )
+ {
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one
+ * is in use. The queue registry is provided as a means for kernel aware
+ * debuggers to locate queues and has no purpose if a kernel aware debugger
+ * is not being used. The call to vQueueAddToRegistry() will be removed
+ * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+ * defined to be less than 1. */
+ vQueueAddToRegistry( xQueue, "Gen_Queue_Test" );
+
+ /* Create the demo task and pass it the queue just created. We are
+ * passing the queue handle by value so it does not matter that it is
+ * declared on the stack here. */
+ xTaskCreate( prvSendFrontAndBackTest, "GenQ", genqGENERIC_QUEUE_TEST_TASK_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );
+ }
+
+ /* Create the mutex used by the prvMutexTest task. */
+ xMutex = xSemaphoreCreateMutex();
+
+ if( xMutex != NULL )
+ {
+ /* vQueueAddToRegistry() adds the mutex to the registry, if one is
+ * in use. The registry is provided as a means for kernel aware
+ * debuggers to locate mutexes and has no purpose if a kernel aware
+ * debugger is not being used. The call to vQueueAddToRegistry() will be
+ * removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+ * defined or is defined to be less than 1. */
+ vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Gen_Queue_Mutex" );
+
+ /* Create the mutex demo tasks and pass it the mutex just created. We
+ * are passing the mutex handle by value so it does not matter that it is
+ * declared on the stack here. */
+ xTaskCreate( prvLowPriorityMutexTask, "MuLow", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );
+ xTaskCreate( prvMediumPriorityMutexTask, "MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );
+ xTaskCreate( prvHighPriorityMutexTask, "MuHigh", genqMUTEX_TEST_TASK_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );
+
+ /* If INCLUDE_xTaskAbortDelay is set then additional tests are performed,
+ * requiring two instances of prvHighPriorityMutexTask(). */
+ #if ( INCLUDE_xTaskAbortDelay == 1 )
+ {
+ xTaskCreate( prvHighPriorityMutexTask, "MuHigh2", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_MEDIUM_PRIORITY, &xSecondMediumPriorityMutexTask );
+ }
+ #endif /* INCLUDE_xTaskAbortDelay */
+ }
}
/*-----------------------------------------------------------*/
-static void prvSendFrontAndBackTest( void *pvParameters )
+static void prvSendFrontAndBackTest( void * pvParameters )
{
-uint32_t ulData, ulData2, ulLoopCounterSnapshot;
-QueueHandle_t xQueue;
-
- #ifdef USE_STDIO
- void vPrintDisplayMessage( const char * const * ppcMessageToSend );
-
- const char * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
- #endif
-
- xQueue = ( QueueHandle_t ) pvParameters;
-
- for( ;; )
- {
- /* The queue is empty, so sending an item to the back of the queue
- should have the same effect as sending it to the front of the queue.
-
- First send to the front and check everything is as expected. */
- ulLoopCounterSnapshot = ulLoopCounter;
- xQueueSendToFront( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK );
-
- if( uxQueueMessagesWaiting( xQueue ) != 1 )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* The data we sent to the queue should equal the data we just received
- from the queue. */
- if( ulLoopCounter != ulData )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Then do the same, sending the data to the back, checking everything
- is as expected. */
- if( uxQueueMessagesWaiting( xQueue ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- ulLoopCounterSnapshot = ulLoopCounter;
- xQueueSendToBack( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK );
-
- if( uxQueueMessagesWaiting( xQueue ) != 1 )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* The data sent to the queue should equal the data just received from
- the queue. */
- if( ulLoopCounter != ulData )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
-
-
- /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */
- for( ulData = 2; ulData < 5; ulData++ )
- {
- xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
- }
-
- /* Now the order in the queue should be 2, 3, 4, with 2 being the first
- thing to be read out. Now add 1 then 0 to the front of the queue. */
- if( uxQueueMessagesWaiting( xQueue ) != 3 )
- {
- xErrorDetected = pdTRUE;
- }
- ulData = 1;
- xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
- ulData = 0;
- xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
-
- /* Now the queue should be full, and when we read the data out we
- should receive 0, 1, 2, 3, 4. */
- if( uxQueueMessagesWaiting( xQueue ) != 5 )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Check the data we read out is in the expected order. */
- for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )
- {
- /* Try peeking the data first. */
- if( xQueuePeek( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( ulData != ulData2 )
- {
- xErrorDetected = pdTRUE;
- }
-
-
- /* Now try receiving the data for real. The value should be the
- same. Clobber the value first so we know we really received it. */
- ulData2 = ~ulData2;
- if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( ulData != ulData2 )
- {
- xErrorDetected = pdTRUE;
- }
- }
-
- /* The queue should now be empty again. */
- if( uxQueueMessagesWaiting( xQueue ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
-
- /* Our queue is empty once more, add 10, 11 to the back. */
- ulData = 10;
- if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- ulData = 11;
- if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 2 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the
- front. */
- for( ulData = 9; ulData >= 7; ulData-- )
- {
- if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- }
-
- /* Now check that the queue is full, and that receiving data provides
- the expected sequence of 7, 8, 9, 10, 11. */
- if( uxQueueMessagesWaiting( xQueue ) != 5 )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Check the data we read out is in the expected order. */
- for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )
- {
- if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( ulData != ulData2 )
- {
- xErrorDetected = pdTRUE;
- }
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Increment the loop counter to indicate these tasks are still
- executing. */
- ulLoopCounter++;
- }
+ uint32_t ulData, ulData2, ulLoopCounterSnapshot;
+ QueueHandle_t xQueue;
+
+ #ifdef USE_STDIO
+ void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+ const char * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+ #endif
+
+ xQueue = ( QueueHandle_t ) pvParameters;
+
+ for( ; ; )
+ {
+ /* The queue is empty, so sending an item to the back of the queue
+ * should have the same effect as sending it to the front of the queue.
+ *
+ * First send to the front and check everything is as expected. */
+ ulLoopCounterSnapshot = ulLoopCounter;
+ xQueueSendToFront( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK );
+
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* The data we sent to the queue should equal the data we just received
+ * from the queue. */
+ if( ulLoopCounter != ulData )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Then do the same, sending the data to the back, checking everything
+ * is as expected. */
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ ulLoopCounterSnapshot = ulLoopCounter;
+ xQueueSendToBack( xQueue, ( void * ) &ulLoopCounterSnapshot, intsemNO_BLOCK );
+
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xQueueReceive( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* The data sent to the queue should equal the data just received from
+ * the queue. */
+ if( ulLoopCounter != ulData )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */
+ for( ulData = 2; ulData < 5; ulData++ )
+ {
+ xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
+ }
+
+ /* Now the order in the queue should be 2, 3, 4, with 2 being the first
+ * thing to be read out. Now add 1 then 0 to the front of the queue. */
+ if( uxQueueMessagesWaiting( xQueue ) != 3 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ ulData = 1;
+ xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
+ ulData = 0;
+ xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK );
+
+ /* Now the queue should be full, and when we read the data out we
+ * should receive 0, 1, 2, 3, 4. */
+ if( uxQueueMessagesWaiting( xQueue ) != 5 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Check the data we read out is in the expected order. */
+ for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )
+ {
+ /* Try peeking the data first. */
+ if( xQueuePeek( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulData != ulData2 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now try receiving the data for real. The value should be the
+ * same. Clobber the value first so we know we really received it. */
+ ulData2 = ~ulData2;
+
+ if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulData != ulData2 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+
+ /* The queue should now be empty again. */
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+
+ /* Our queue is empty once more, add 10, 11 to the back. */
+ ulData = 10;
+
+ if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ ulData = 11;
+
+ if( xQueueSend( xQueue, &ulData, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 2 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the
+ * front. */
+ for( ulData = 9; ulData >= 7; ulData-- )
+ {
+ if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+
+ /* Now check that the queue is full, and that receiving data provides
+ * the expected sequence of 7, 8, 9, 10, 11. */
+ if( uxQueueMessagesWaiting( xQueue ) != 5 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xQueueSendToFront( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xQueueSendToBack( xQueue, ( void * ) &ulData, intsemNO_BLOCK ) != errQUEUE_FULL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Check the data we read out is in the expected order. */
+ for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )
+ {
+ if( xQueueReceive( xQueue, &ulData2, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulData != ulData2 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Increment the loop counter to indicate these tasks are still
+ * executing. */
+ ulLoopCounter++;
+ }
}
/*-----------------------------------------------------------*/
-#if( INCLUDE_xTaskAbortDelay == 1 )
-
- static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex )
- {
- static UBaseType_t uxLoopCount = 0;
-
- /* The tests in this function are very similar, the slight variations
- are for code coverage purposes. */
-
- /* Take the mutex. It should be available now. Check before and after
- taking that the holder is reported correctly. */
- if( xSemaphoreGetMutexHolder( xMutex ) != NULL )
- {
- xErrorDetected = pdTRUE;
- }
- if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- if( xSemaphoreGetMutexHolder( xMutex ) != xTaskGetCurrentTaskHandle() )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This task's priority should be as per that assigned when the task was
- created. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now unsuspend the high priority task. This will attempt to take the
- mutex, and block when it finds it cannot obtain it. */
- vTaskResume( xHighPriorityMutexTask );
-
- /* This task should now have inherited the priority of the high priority
- task as by now the high priority task will have attempted to obtain the
- mutex. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Unblock a second medium priority task. It too will attempt to take
- the mutex and enter the Blocked state - it won't run yet though as this
- task has inherited a priority above it. */
- vTaskResume( xSecondMediumPriorityMutexTask );
-
- /* This task should still have the priority of the high priority task as
- that had already been inherited as is the highest priority of the three
- tasks using the mutex. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* On some loops, block for a short while to provide additional
- code coverage. Blocking here will allow the medium priority task to
- execute and so also block on the mutex so when the high priority task
- causes this task to disinherit the high priority it is inherited down to
- the priority of the medium priority task. When there is no delay the
- medium priority task will not run until after the disinheritance, so
- this task will disinherit back to its base priority, then only up to the
- medium priority after the medium priority has executed. */
- vTaskDelay( uxLoopCount & ( UBaseType_t ) 0x07 );
-
- /* Now force the high priority task to unblock. It will fail to obtain
- the mutex and go back to the suspended state - allowing this task to
- execute again. xBlockWasAborted is set to pdTRUE so the higher priority
- task knows that its failure to obtain the semaphore is not an error. */
- xBlockWasAborted = pdTRUE;
- if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This task has inherited the priority of xHighPriorityMutexTask so
- could still be running even though xHighPriorityMutexTask is no longer
- blocked. Delay for a short while to ensure xHighPriorityMutexTask gets
- a chance to run - indicated by this task changing priority. It should
- disinherit the high priority task, but then inherit the priority of the
- medium priority task that is waiting for the same mutex. */
- while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
- {
- /* If this task gets stuck here then the check variables will stop
- incrementing and the check task will detect the error. */
- vTaskDelay( genqSHORT_BLOCK );
- }
-
- /* Now force the medium priority task to unblock. xBlockWasAborted is
- set to pdTRUE so the medium priority task knows that its failure to
- obtain the semaphore is not an error. */
- xBlockWasAborted = pdTRUE;
- if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This time no other tasks are waiting for the mutex, so this task
- should return to its base priority. This might not happen straight
- away as it is running at the same priority as the task it just
- unblocked. */
- while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- /* If this task gets stuck here then the check variables will stop
- incrementing and the check task will detect the error. */
- vTaskDelay( genqSHORT_BLOCK );
- }
-
- /* Give the semaphore back ready for the next test. Check the mutex
- holder before and after using the "FromISR" version for code coverage. */
- if( xSemaphoreGetMutexHolderFromISR( xMutex ) != xTaskGetCurrentTaskHandle() )
- {
- xErrorDetected = pdTRUE;
- }
- xSemaphoreGive( xMutex );
- if( xSemaphoreGetMutexHolderFromISR( xMutex ) != NULL )
- {
- xErrorDetected = pdTRUE;
- }
-
- configASSERT( xErrorDetected == pdFALSE );
-
-
-
- /* Now do the same again, but this time unsuspend the tasks in the
- opposite order. This takes a different path though the code because
- when the high priority task has its block aborted there is already
- another task in the list of tasks waiting for the mutex, and the
- low priority task drops down to that priority, rather than dropping
- down to its base priority before inheriting the priority of the medium
- priority task. */
- if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This time unsuspend the medium priority task first. This will
- attempt to take the mutex, and block when it finds it cannot obtain it. */
- vTaskResume( xSecondMediumPriorityMutexTask );
-
- /* This time this task should now have inherited the priority of the
- medium task. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This time the high priority task in unsuspended second. */
- vTaskResume( xHighPriorityMutexTask );
-
- /* The high priority task should already have run, causing this task to
- inherit a priority for the second time. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This time, when the high priority task has its delay aborted and it
- fails to obtain the mutex this task will immediately have its priority
- lowered down to that of the highest priority task waiting on the mutex,
- which is the medium priority task. */
- xBlockWasAborted = pdTRUE;
- if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
- {
- /* If this task gets stuck here then the check variables will stop
- incrementing and the check task will detect the error. */
- vTaskDelay( genqSHORT_BLOCK );
- }
-
- /* And finally, when the medium priority task also have its delay
- aborted there are no other tasks waiting for the mutex so this task
- returns to its base priority. */
- xBlockWasAborted = pdTRUE;
- if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- /* If this task gets stuck here then the check variables will stop
- incrementing and the check task will detect the error. */
- vTaskDelay( genqSHORT_BLOCK );
- }
-
- /* Give the semaphore back ready for the next test. */
- xSemaphoreGive( xMutex );
-
- configASSERT( xErrorDetected == pdFALSE );
-
- /* uxLoopCount is used to add a variable delay, and in-so-doing provide
- additional code coverage. */
- uxLoopCount++;
- }
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+ static void prvHighPriorityTimeout( SemaphoreHandle_t xMutex )
+ {
+ static UBaseType_t uxLoopCount = 0;
+
+ /* The tests in this function are very similar, the slight variations
+ * are for code coverage purposes. */
+
+ /* Take the mutex. It should be available now. Check before and after
+ * taking that the holder is reported correctly. */
+ if( xSemaphoreGetMutexHolder( xMutex ) != NULL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xSemaphoreGetMutexHolder( xMutex ) != xTaskGetCurrentTaskHandle() )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This task's priority should be as per that assigned when the task was
+ * created. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now unsuspend the high priority task. This will attempt to take the
+ * mutex, and block when it finds it cannot obtain it. */
+ vTaskResume( xHighPriorityMutexTask );
+
+ /* This task should now have inherited the priority of the high priority
+ * task as by now the high priority task will have attempted to obtain the
+ * mutex. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Unblock a second medium priority task. It too will attempt to take
+ * the mutex and enter the Blocked state - it won't run yet though as this
+ * task has inherited a priority above it. */
+ vTaskResume( xSecondMediumPriorityMutexTask );
+
+ /* This task should still have the priority of the high priority task as
+ * that had already been inherited as is the highest priority of the three
+ * tasks using the mutex. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* On some loops, block for a short while to provide additional
+ * code coverage. Blocking here will allow the medium priority task to
+ * execute and so also block on the mutex so when the high priority task
+ * causes this task to disinherit the high priority it is inherited down to
+ * the priority of the medium priority task. When there is no delay the
+ * medium priority task will not run until after the disinheritance, so
+ * this task will disinherit back to its base priority, then only up to the
+ * medium priority after the medium priority has executed. */
+ vTaskDelay( uxLoopCount & ( UBaseType_t ) 0x07 );
+
+ /* Now force the high priority task to unblock. It will fail to obtain
+ * the mutex and go back to the suspended state - allowing this task to
+ * execute again. xBlockWasAborted is set to pdTRUE so the higher priority
+ * task knows that its failure to obtain the semaphore is not an error. */
+ xBlockWasAborted = pdTRUE;
+
+ if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This task has inherited the priority of xHighPriorityMutexTask so
+ * could still be running even though xHighPriorityMutexTask is no longer
+ * blocked. Delay for a short while to ensure xHighPriorityMutexTask gets
+ * a chance to run - indicated by this task changing priority. It should
+ * disinherit the high priority task, but then inherit the priority of the
+ * medium priority task that is waiting for the same mutex. */
+ while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
+ {
+ /* If this task gets stuck here then the check variables will stop
+ * incrementing and the check task will detect the error. */
+ vTaskDelay( genqSHORT_BLOCK );
+ }
+
+ /* Now force the medium priority task to unblock. xBlockWasAborted is
+ * set to pdTRUE so the medium priority task knows that its failure to
+ * obtain the semaphore is not an error. */
+ xBlockWasAborted = pdTRUE;
+
+ if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This time no other tasks are waiting for the mutex, so this task
+ * should return to its base priority. This might not happen straight
+ * away as it is running at the same priority as the task it just
+ * unblocked. */
+ while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ /* If this task gets stuck here then the check variables will stop
+ * incrementing and the check task will detect the error. */
+ vTaskDelay( genqSHORT_BLOCK );
+ }
+
+ /* Give the semaphore back ready for the next test. Check the mutex
+ * holder before and after using the "FromISR" version for code coverage. */
+ if( xSemaphoreGetMutexHolderFromISR( xMutex ) != xTaskGetCurrentTaskHandle() )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ xSemaphoreGive( xMutex );
+
+ if( xSemaphoreGetMutexHolderFromISR( xMutex ) != NULL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ configASSERT( xErrorDetected == pdFALSE );
+
+ /* Now do the same again, but this time unsuspend the tasks in the
+ * opposite order. This takes a different path though the code because
+ * when the high priority task has its block aborted there is already
+ * another task in the list of tasks waiting for the mutex, and the
+ * low priority task drops down to that priority, rather than dropping
+ * down to its base priority before inheriting the priority of the medium
+ * priority task. */
+ if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This time unsuspend the medium priority task first. This will
+ * attempt to take the mutex, and block when it finds it cannot obtain it. */
+ vTaskResume( xSecondMediumPriorityMutexTask );
+
+ /* This time this task should now have inherited the priority of the
+ * medium task. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This time the high priority task in unsuspended second. */
+ vTaskResume( xHighPriorityMutexTask );
+
+ /* The high priority task should already have run, causing this task to
+ * inherit a priority for the second time. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This time, when the high priority task has its delay aborted and it
+ * fails to obtain the mutex this task will immediately have its priority
+ * lowered down to that of the highest priority task waiting on the mutex,
+ * which is the medium priority task. */
+ xBlockWasAborted = pdTRUE;
+
+ if( xTaskAbortDelay( xHighPriorityMutexTask ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ while( uxTaskPriorityGet( NULL ) != genqMUTEX_MEDIUM_PRIORITY )
+ {
+ /* If this task gets stuck here then the check variables will stop
+ * incrementing and the check task will detect the error. */
+ vTaskDelay( genqSHORT_BLOCK );
+ }
+
+ /* And finally, when the medium priority task also have its delay
+ * aborted there are no other tasks waiting for the mutex so this task
+ * returns to its base priority. */
+ xBlockWasAborted = pdTRUE;
+
+ if( xTaskAbortDelay( xSecondMediumPriorityMutexTask ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ while( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ /* If this task gets stuck here then the check variables will stop
+ * incrementing and the check task will detect the error. */
+ vTaskDelay( genqSHORT_BLOCK );
+ }
+
+ /* Give the semaphore back ready for the next test. */
+ xSemaphoreGive( xMutex );
+
+ configASSERT( xErrorDetected == pdFALSE );
+
+ /* uxLoopCount is used to add a variable delay, and in-so-doing provide
+ * additional code coverage. */
+ uxLoopCount++;
+ }
#endif /* INCLUDE_xTaskAbortDelay == 1 */
/*-----------------------------------------------------------*/
-static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex )
+static void prvTakeTwoMutexesReturnInDifferentOrder( SemaphoreHandle_t xMutex,
+ SemaphoreHandle_t xLocalMutex )
{
- /* Take the mutex. It should be available now. */
- if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Set the guarded variable to a known start value. */
- ulGuardedVariable = 0;
-
- /* This task's priority should be as per that assigned when the task was
- created. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now unsuspend the high priority task. This will attempt to take the
- mutex, and block when it finds it cannot obtain it. */
- vTaskResume( xHighPriorityMutexTask );
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Ensure the task is reporting its priority as blocked and not
- suspended (as it would have done in versions up to V7.5.3). */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* This task should now have inherited the priority of the high priority
- task as by now the high priority task will have attempted to obtain the
- mutex. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Attempt to set the priority of this task to the test priority -
- between the idle priority and the medium/high test priorities, but the
- actual priority should remain at the high priority. */
- vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now unsuspend the medium priority task. This should not run as the
- inherited priority of this task is above that of the medium priority
- task. */
- vTaskResume( xMediumPriorityMutexTask );
-
- /* If the medium priority task did run then it will have incremented the
- guarded variable. */
- if( ulGuardedVariable != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Take the local mutex too, so two mutexes are now held. */
- if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* When the semaphore is given back the priority of this task should not
- yet be disinherited because the local mutex is still held. This is a
- simplification to allow FreeRTOS to be integrated with middleware that
- attempts to hold multiple mutexes without bloating the code with complex
- algorithms. It is possible that the high priority mutex task will
- execute as it shares a priority with this task. */
- if( xSemaphoreGive( xMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* The guarded variable is only incremented by the medium priority task,
- which still should not have executed as this task should remain at the
- higher priority, ensure this is the case. */
- if( ulGuardedVariable != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now also give back the local mutex, taking the held count back to 0.
- This time the priority of this task should be disinherited back to the
- priority to which it was set while the mutex was held. This means
- the medium priority task should execute and increment the guarded
- variable. When this task next runs both the high and medium priority
- tasks will have been suspended again. */
- if( xSemaphoreGive( xLocalMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Check the guarded variable did indeed increment... */
- if( ulGuardedVariable != 1 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* ... and that the priority of this task has been disinherited to
- genqMUTEX_TEST_PRIORITY. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Set the priority of this task back to its original value, ready for
- the next loop around this test. */
- vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );
+ /* Take the mutex. It should be available now. */
+ if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Set the guarded variable to a known start value. */
+ ulGuardedVariable = 0;
+
+ /* This task's priority should be as per that assigned when the task was
+ * created. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now unsuspend the high priority task. This will attempt to take the
+ * mutex, and block when it finds it cannot obtain it. */
+ vTaskResume( xHighPriorityMutexTask );
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Ensure the task is reporting its priority as blocked and not
+ * suspended (as it would have done in versions up to V7.5.3). */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* This task should now have inherited the priority of the high priority
+ * task as by now the high priority task will have attempted to obtain the
+ * mutex. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Attempt to set the priority of this task to the test priority -
+ * between the idle priority and the medium/high test priorities, but the
+ * actual priority should remain at the high priority. */
+ vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );
+
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now unsuspend the medium priority task. This should not run as the
+ * inherited priority of this task is above that of the medium priority
+ * task. */
+ vTaskResume( xMediumPriorityMutexTask );
+
+ /* If the medium priority task did run then it will have incremented the
+ * guarded variable. */
+ if( ulGuardedVariable != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Take the local mutex too, so two mutexes are now held. */
+ if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* When the semaphore is given back the priority of this task should not
+ * yet be disinherited because the local mutex is still held. This is a
+ * simplification to allow FreeRTOS to be integrated with middleware that
+ * attempts to hold multiple mutexes without bloating the code with complex
+ * algorithms. It is possible that the high priority mutex task will
+ * execute as it shares a priority with this task. */
+ if( xSemaphoreGive( xMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* The guarded variable is only incremented by the medium priority task,
+ * which still should not have executed as this task should remain at the
+ * higher priority, ensure this is the case. */
+ if( ulGuardedVariable != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now also give back the local mutex, taking the held count back to 0.
+ * This time the priority of this task should be disinherited back to the
+ * priority to which it was set while the mutex was held. This means
+ * the medium priority task should execute and increment the guarded
+ * variable. When this task next runs both the high and medium priority
+ * tasks will have been suspended again. */
+ if( xSemaphoreGive( xLocalMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Check the guarded variable did indeed increment... */
+ if( ulGuardedVariable != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* ... and that the priority of this task has been disinherited to
+ * genqMUTEX_TEST_PRIORITY. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Set the priority of this task back to its original value, ready for
+ * the next loop around this test. */
+ vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );
}
/*-----------------------------------------------------------*/
-static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex, SemaphoreHandle_t xLocalMutex )
+static void prvTakeTwoMutexesReturnInSameOrder( SemaphoreHandle_t xMutex,
+ SemaphoreHandle_t xLocalMutex )
{
- /* Take the mutex. It should be available now. */
- if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Set the guarded variable to a known start value. */
- ulGuardedVariable = 0;
-
- /* This task's priority should be as per that assigned when the task was
- created. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now unsuspend the high priority task. This will attempt to take the
- mutex, and block when it finds it cannot obtain it. */
- vTaskResume( xHighPriorityMutexTask );
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Ensure the task is reporting its priority as blocked and not
- suspended (as it would have done in versions up to V7.5.3). */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* This task should now have inherited the priority of the high priority
- task as by now the high priority task will have attempted to obtain the
- mutex. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now unsuspend the medium priority task. This should not run as the
- inherited priority of this task is above that of the medium priority
- task. */
- vTaskResume( xMediumPriorityMutexTask );
-
- /* If the medium priority task did run then it will have incremented the
- guarded variable. */
- if( ulGuardedVariable != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Take the local mutex too, so two mutexes are now held. */
- if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* When the local semaphore is given back the priority of this task should
- not yet be disinherited because the shared mutex is still held. This is a
- simplification to allow FreeRTOS to be integrated with middleware that
- attempts to hold multiple mutexes without bloating the code with complex
- algorithms. It is possible that the high priority mutex task will
- execute as it shares a priority with this task. */
- if( xSemaphoreGive( xLocalMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* The guarded variable is only incremented by the medium priority task,
- which still should not have executed as this task should remain at the
- higher priority, ensure this is the case. */
- if( ulGuardedVariable != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now also give back the shared mutex, taking the held count back to 0.
- This time the priority of this task should be disinherited back to the
- priority at which it was created. This means the medium priority task
- should execute and increment the guarded variable. When this task next runs
- both the high and medium priority tasks will have been suspended again. */
- if( xSemaphoreGive( xMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* Check the guarded variable did indeed increment... */
- if( ulGuardedVariable != 1 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* ... and that the priority of this task has been disinherited to
- genqMUTEX_LOW_PRIORITY. */
- if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
+ /* Take the mutex. It should be available now. */
+ if( xSemaphoreTake( xMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Set the guarded variable to a known start value. */
+ ulGuardedVariable = 0;
+
+ /* This task's priority should be as per that assigned when the task was
+ * created. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now unsuspend the high priority task. This will attempt to take the
+ * mutex, and block when it finds it cannot obtain it. */
+ vTaskResume( xHighPriorityMutexTask );
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Ensure the task is reporting its priority as blocked and not
+ * suspended (as it would have done in versions up to V7.5.3). */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xHighPriorityMutexTask ) == eBlocked );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* This task should now have inherited the priority of the high priority
+ * task as by now the high priority task will have attempted to obtain the
+ * mutex. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now unsuspend the medium priority task. This should not run as the
+ * inherited priority of this task is above that of the medium priority
+ * task. */
+ vTaskResume( xMediumPriorityMutexTask );
+
+ /* If the medium priority task did run then it will have incremented the
+ * guarded variable. */
+ if( ulGuardedVariable != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Take the local mutex too, so two mutexes are now held. */
+ if( xSemaphoreTake( xLocalMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* When the local semaphore is given back the priority of this task should
+ * not yet be disinherited because the shared mutex is still held. This is a
+ * simplification to allow FreeRTOS to be integrated with middleware that
+ * attempts to hold multiple mutexes without bloating the code with complex
+ * algorithms. It is possible that the high priority mutex task will
+ * execute as it shares a priority with this task. */
+ if( xSemaphoreGive( xLocalMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* The guarded variable is only incremented by the medium priority task,
+ * which still should not have executed as this task should remain at the
+ * higher priority, ensure this is the case. */
+ if( ulGuardedVariable != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now also give back the shared mutex, taking the held count back to 0.
+ * This time the priority of this task should be disinherited back to the
+ * priority at which it was created. This means the medium priority task
+ * should execute and increment the guarded variable. When this task next runs
+ * both the high and medium priority tasks will have been suspended again. */
+ if( xSemaphoreGive( xMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* Check the guarded variable did indeed increment... */
+ if( ulGuardedVariable != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* ... and that the priority of this task has been disinherited to
+ * genqMUTEX_LOW_PRIORITY. */
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
}
/*-----------------------------------------------------------*/
-static void prvLowPriorityMutexTask( void *pvParameters )
+static void prvLowPriorityMutexTask( void * pvParameters )
{
-SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters, xLocalMutex;
-
- #ifdef USE_STDIO
- void vPrintDisplayMessage( const char * const * ppcMessageToSend );
-
- const char * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
- #endif
-
- /* The local mutex is used to check the 'mutexs held' count. */
- xLocalMutex = xSemaphoreCreateMutex();
- configASSERT( xLocalMutex );
-
- for( ;; )
- {
- /* The first tests exercise the priority inheritance when two mutexes
- are taken then returned in a different order to which they were
- taken. */
- prvTakeTwoMutexesReturnInDifferentOrder( xMutex, xLocalMutex );
-
- /* Just to show this task is still running. */
- ulLoopCounter2++;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* The second tests exercise the priority inheritance when two mutexes
- are taken then returned in the same order in which they were taken. */
- prvTakeTwoMutexesReturnInSameOrder( xMutex, xLocalMutex );
-
- /* Just to show this task is still running. */
- ulLoopCounter2++;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- #if( INCLUDE_xTaskAbortDelay == 1 )
- {
- /* Tests the behaviour when a low priority task inherits the
- priority of a high priority task only for the high priority task to
- timeout before obtaining the mutex. */
- prvHighPriorityTimeout( xMutex );
- }
- #endif
- }
+ SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters, xLocalMutex;
+
+ #ifdef USE_STDIO
+ void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+ const char * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+ #endif
+
+ /* The local mutex is used to check the 'mutex held' count. */
+ xLocalMutex = xSemaphoreCreateMutex();
+ configASSERT( xLocalMutex );
+
+ for( ; ; )
+ {
+ /* The first tests exercise the priority inheritance when two mutexes
+ * are taken then returned in a different order to which they were
+ * taken. */
+ prvTakeTwoMutexesReturnInDifferentOrder( xMutex, xLocalMutex );
+
+ /* Just to show this task is still running. */
+ ulLoopCounter2++;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* The second tests exercise the priority inheritance when two mutexes
+ * are taken then returned in the same order in which they were taken. */
+ prvTakeTwoMutexesReturnInSameOrder( xMutex, xLocalMutex );
+
+ /* Just to show this task is still running. */
+ ulLoopCounter2++;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ #if ( INCLUDE_xTaskAbortDelay == 1 )
+ {
+ /* Tests the behaviour when a low priority task inherits the
+ * priority of a high priority task only for the high priority task to
+ * timeout before obtaining the mutex. */
+ prvHighPriorityTimeout( xMutex );
+ }
+ #endif
+ }
}
/*-----------------------------------------------------------*/
-static void prvMediumPriorityMutexTask( void *pvParameters )
+static void prvMediumPriorityMutexTask( void * pvParameters )
{
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* The medium priority task starts by suspending itself. The low
- priority task will unsuspend this task when required. */
- vTaskSuspend( NULL );
-
- /* When this task unsuspends all it does is increment the guarded
- variable, this is so the low priority task knows that it has
- executed. */
- ulGuardedVariable++;
- }
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* The medium priority task starts by suspending itself. The low
+ * priority task will unsuspend this task when required. */
+ vTaskSuspend( NULL );
+
+ /* When this task unsuspends all it does is increment the guarded
+ * variable, this is so the low priority task knows that it has
+ * executed. */
+ ulGuardedVariable++;
+ }
}
/*-----------------------------------------------------------*/
-static void prvHighPriorityMutexTask( void *pvParameters )
+static void prvHighPriorityMutexTask( void * pvParameters )
{
-SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters;
-
- for( ;; )
- {
- /* The high priority task starts by suspending itself. The low
- priority task will unsuspend this task when required. */
- vTaskSuspend( NULL );
-
- /* When this task unsuspends all it does is attempt to obtain the
- mutex. It should find the mutex is not available so a block time is
- specified. */
- if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS )
- {
- /* This task would expect to obtain the mutex unless its wait for
- the mutex was aborted. */
- if( xBlockWasAborted == pdFALSE )
- {
- xErrorDetected = pdTRUE;
- }
- else
- {
- xBlockWasAborted = pdFALSE;
- }
- }
- else
- {
- /* When the mutex is eventually obtained it is just given back before
- returning to suspend ready for the next cycle. */
- if( xSemaphoreGive( xMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- }
- }
+ SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters;
+
+ for( ; ; )
+ {
+ /* The high priority task starts by suspending itself. The low
+ * priority task will unsuspend this task when required. */
+ vTaskSuspend( NULL );
+
+ /* When this task unsuspends all it does is attempt to obtain the
+ * mutex. It should find the mutex is not available so a block time is
+ * specified. */
+ if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS )
+ {
+ /* This task would expect to obtain the mutex unless its wait for
+ * the mutex was aborted. */
+ if( xBlockWasAborted == pdFALSE )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ else
+ {
+ xBlockWasAborted = pdFALSE;
+ }
+ }
+ else
+ {
+ /* When the mutex is eventually obtained it is just given back before
+ * returning to suspend ready for the next cycle. */
+ if( xSemaphoreGive( xMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -1003,27 +1015,25 @@ SemaphoreHandle_t xMutex = ( SemaphoreHandle_t ) pvParameters;
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreGenericQueueTasksStillRunning( void )
{
-static uint32_t ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;
+ static uint32_t ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;
- /* If the demo task is still running then we expect the loop counters to
- have incremented since this function was last called. */
- if( ulLastLoopCounter == ulLoopCounter )
- {
- xErrorDetected = pdTRUE;
- }
+ /* If the demo task is still running then we expect the loop counters to
+ * have incremented since this function was last called. */
+ if( ulLastLoopCounter == ulLoopCounter )
+ {
+ xErrorDetected = pdTRUE;
+ }
- if( ulLastLoopCounter2 == ulLoopCounter2 )
- {
- xErrorDetected = pdTRUE;
- }
+ if( ulLastLoopCounter2 == ulLoopCounter2 )
+ {
+ xErrorDetected = pdTRUE;
+ }
- ulLastLoopCounter = ulLoopCounter;
- ulLastLoopCounter2 = ulLoopCounter2;
+ ulLastLoopCounter = ulLoopCounter;
+ ulLastLoopCounter2 = ulLoopCounter2;
- /* Errors detected in the task itself will have latched xErrorDetected
- to true. */
+ /* Errors detected in the task itself will have latched xErrorDetected
+ * to true. */
- return ( BaseType_t ) !xErrorDetected;
+ return ( BaseType_t ) !xErrorDetected;
}
-
-
diff --git a/Demo/Common/Minimal/IntQueue.c b/Demo/Common/Minimal/IntQueue.c
index 0cea77ad2..4894d7821 100644
--- a/Demo/Common/Minimal/IntQueue.c
+++ b/Demo/Common/Minimal/IntQueue.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -52,99 +52,101 @@
#include "IntQueue.h"
#include "IntQueueTimer.h"
-#if( INCLUDE_eTaskGetState != 1 )
- #error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file.
+#if ( INCLUDE_eTaskGetState != 1 )
+ #error INCLUDE_eTaskGetState must be set to 1 in FreeRTOSConfig.h to use this demo file.
#endif
/* Priorities used by test tasks. */
#ifndef intqHIGHER_PRIORITY
- #define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 2 )
+ #define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 2 )
#endif
-#define intqLOWER_PRIORITY ( tskIDLE_PRIORITY )
+#define intqLOWER_PRIORITY ( tskIDLE_PRIORITY )
/* The number of values to send/receive before checking that all values were
-processed as expected. */
-#define intqNUM_VALUES_TO_LOG ( 200 )
-#define intqSHORT_DELAY ( 140 )
+ * processed as expected. */
+#define intqNUM_VALUES_TO_LOG ( 200 )
+#define intqSHORT_DELAY ( 140 )
/* The value by which the value being sent to or received from a queue should
-increment past intqNUM_VALUES_TO_LOG before we check that all values have been
-sent/received correctly. This is done to ensure that all tasks and interrupts
-accessing the queue have completed their accesses with the
-intqNUM_VALUES_TO_LOG range. */
-#define intqVALUE_OVERRUN ( 50 )
+ * increment past intqNUM_VALUES_TO_LOG before we check that all values have been
+ * sent/received correctly. This is done to ensure that all tasks and interrupts
+ * accessing the queue have completed their accesses with the
+ * intqNUM_VALUES_TO_LOG range. */
+#define intqVALUE_OVERRUN ( 50 )
/* The delay used by the polling task. A short delay is used for code
-coverage. */
-#define intqONE_TICK_DELAY ( 1 )
+ * coverage. */
+#define intqONE_TICK_DELAY ( 1 )
/* Each task and interrupt is given a unique identifier. This value is used to
-identify which task sent or received each value. The identifier is also used
-to distinguish between two tasks that are running the same task function. */
-#define intqHIGH_PRIORITY_TASK1 ( ( UBaseType_t ) 1 )
-#define intqHIGH_PRIORITY_TASK2 ( ( UBaseType_t ) 2 )
-#define intqLOW_PRIORITY_TASK ( ( UBaseType_t ) 3 )
-#define intqFIRST_INTERRUPT ( ( UBaseType_t ) 4 )
-#define intqSECOND_INTERRUPT ( ( UBaseType_t ) 5 )
-#define intqQUEUE_LENGTH ( ( UBaseType_t ) 10 )
+ * identify which task sent or received each value. The identifier is also used
+ * to distinguish between two tasks that are running the same task function. */
+#define intqHIGH_PRIORITY_TASK1 ( ( UBaseType_t ) 1 )
+#define intqHIGH_PRIORITY_TASK2 ( ( UBaseType_t ) 2 )
+#define intqLOW_PRIORITY_TASK ( ( UBaseType_t ) 3 )
+#define intqFIRST_INTERRUPT ( ( UBaseType_t ) 4 )
+#define intqSECOND_INTERRUPT ( ( UBaseType_t ) 5 )
+#define intqQUEUE_LENGTH ( ( UBaseType_t ) 10 )
/* At least intqMIN_ACCEPTABLE_TASK_COUNT values should be sent to/received
-from each queue by each task, otherwise an error is detected. */
-#define intqMIN_ACCEPTABLE_TASK_COUNT ( 5 )
+ * from each queue by each task, otherwise an error is detected. */
+#define intqMIN_ACCEPTABLE_TASK_COUNT ( 5 )
/* Send the next value to the queue that is normally empty. This is called
-from within the interrupts. */
-#define timerNORMALLY_EMPTY_TX() \
- if( xQueueIsQueueFullFromISR( xNormallyEmptyQueue ) != pdTRUE ) \
- { \
- UBaseType_t uxSavedInterruptStatus; \
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
- { \
- uxValueForNormallyEmptyQueue++; \
- if( xQueueSendFromISR( xNormallyEmptyQueue, ( void * ) &uxValueForNormallyEmptyQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \
- { \
- uxValueForNormallyEmptyQueue--; \
- } \
- } \
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
- } \
+ * from within the interrupts. */
+#define timerNORMALLY_EMPTY_TX() \
+ if( xQueueIsQueueFullFromISR( xNormallyEmptyQueue ) != pdTRUE ) \
+ { \
+ UBaseType_t uxSavedInterruptStatus; \
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
+ { \
+ uxValueForNormallyEmptyQueue++; \
+ if( xQueueSendFromISR( xNormallyEmptyQueue, ( void * ) &uxValueForNormallyEmptyQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \
+ { \
+ uxValueForNormallyEmptyQueue--; \
+ } \
+ } \
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
+ } \
+
/* Send the next value to the queue that is normally full. This is called
-from within the interrupts. */
-#define timerNORMALLY_FULL_TX() \
- if( xQueueIsQueueFullFromISR( xNormallyFullQueue ) != pdTRUE ) \
- { \
- UBaseType_t uxSavedInterruptStatus; \
- uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
- { \
- uxValueForNormallyFullQueue++; \
- if( xQueueSendFromISR( xNormallyFullQueue, ( void * ) &uxValueForNormallyFullQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \
- { \
- uxValueForNormallyFullQueue--; \
- } \
- } \
- portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
- } \
+ * from within the interrupts. */
+#define timerNORMALLY_FULL_TX() \
+ if( xQueueIsQueueFullFromISR( xNormallyFullQueue ) != pdTRUE ) \
+ { \
+ UBaseType_t uxSavedInterruptStatus; \
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); \
+ { \
+ uxValueForNormallyFullQueue++; \
+ if( xQueueSendFromISR( xNormallyFullQueue, ( void * ) &uxValueForNormallyFullQueue, &xHigherPriorityTaskWoken ) != pdPASS ) \
+ { \
+ uxValueForNormallyFullQueue--; \
+ } \
+ } \
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
+ } \
+
/* Receive a value from the normally empty queue. This is called from within
-an interrupt. */
-#define timerNORMALLY_EMPTY_RX() \
- if( xQueueReceiveFromISR( xNormallyEmptyQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) != pdPASS ) \
- { \
- prvQueueAccessLogError( __LINE__ ); \
- } \
- else \
- { \
- prvRecordValue_NormallyEmpty( uxRxedValue, intqSECOND_INTERRUPT ); \
- }
+ * an interrupt. */
+#define timerNORMALLY_EMPTY_RX() \
+ if( xQueueReceiveFromISR( xNormallyEmptyQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) != pdPASS ) \
+ { \
+ prvQueueAccessLogError( __LINE__ ); \
+ } \
+ else \
+ { \
+ prvRecordValue_NormallyEmpty( uxRxedValue, intqSECOND_INTERRUPT ); \
+ }
/* Receive a value from the normally full queue. This is called from within
-an interrupt. */
-#define timerNORMALLY_FULL_RX() \
- if( xQueueReceiveFromISR( xNormallyFullQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) == pdPASS ) \
- { \
- prvRecordValue_NormallyFull( uxRxedValue, intqSECOND_INTERRUPT ); \
- } \
+ * an interrupt. */
+#define timerNORMALLY_FULL_RX() \
+ if( xQueueReceiveFromISR( xNormallyFullQueue, &uxRxedValue, &xHigherPriorityTaskWoken ) == pdPASS ) \
+ { \
+ prvRecordValue_NormallyFull( uxRxedValue, intqSECOND_INTERRUPT ); \
+ } \
/*-----------------------------------------------------------*/
@@ -156,7 +158,7 @@ static QueueHandle_t xNormallyEmptyQueue, xNormallyFullQueue;
static volatile UBaseType_t uxHighPriorityLoops1 = 0, uxHighPriorityLoops2 = 0, uxLowPriorityLoops1 = 0, uxLowPriorityLoops2 = 0;
/* Any unexpected behaviour sets xErrorStatus to fail and log the line that
-caused the error in xErrorLine. */
+ * caused the error in xErrorLine. */
static BaseType_t xErrorStatus = pdPASS;
static volatile UBaseType_t xErrorLine = ( UBaseType_t ) 0;
@@ -164,30 +166,32 @@ static volatile UBaseType_t xErrorLine = ( UBaseType_t ) 0;
static BaseType_t xWasSuspended = pdFALSE;
/* The values that are sent to the queues. An incremented value is sent each
-time to each queue. */
+ * time to each queue. */
static volatile UBaseType_t uxValueForNormallyEmptyQueue = 0, uxValueForNormallyFullQueue = 0;
/* A handle to some of the tasks is required so they can be suspended/resumed. */
TaskHandle_t xHighPriorityNormallyEmptyTask1, xHighPriorityNormallyEmptyTask2, xHighPriorityNormallyFullTask1, xHighPriorityNormallyFullTask2;
/* When a value is received in a queue the value is ticked off in the array
-the array position of the value is set to a the identifier of the task or
-interrupt that accessed the queue. This way missing or duplicate values can be
-detected. */
+ * the array position of the value is set to a the identifier of the task or
+ * interrupt that accessed the queue. This way missing or duplicate values can be
+ * detected. */
static uint8_t ucNormallyEmptyReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 };
static uint8_t ucNormallyFullReceivedValues[ intqNUM_VALUES_TO_LOG ] = { 0 };
/* The test tasks themselves. */
-static void prvLowerPriorityNormallyEmptyTask( void *pvParameters );
-static void prvLowerPriorityNormallyFullTask( void *pvParameters );
-static void prvHigherPriorityNormallyEmptyTask( void *pvParameters );
-static void prv1stHigherPriorityNormallyFullTask( void *pvParameters );
-static void prv2ndHigherPriorityNormallyFullTask( void *pvParameters );
+static void prvLowerPriorityNormallyEmptyTask( void * pvParameters );
+static void prvLowerPriorityNormallyFullTask( void * pvParameters );
+static void prvHigherPriorityNormallyEmptyTask( void * pvParameters );
+static void prv1stHigherPriorityNormallyFullTask( void * pvParameters );
+static void prv2ndHigherPriorityNormallyFullTask( void * pvParameters );
/* Used to mark the positions within the ucNormallyEmptyReceivedValues and
-ucNormallyFullReceivedValues arrays, while checking for duplicates. */
-static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue, UBaseType_t uxSource );
-static void prvRecordValue_NormallyFull( UBaseType_t uxValue, UBaseType_t uxSource );
+ * ucNormallyFullReceivedValues arrays, while checking for duplicates. */
+static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue,
+ UBaseType_t uxSource );
+static void prvRecordValue_NormallyFull( UBaseType_t uxValue,
+ UBaseType_t uxSource );
/* Logs the line on which an error occurred. */
static void prvQueueAccessLogError( UBaseType_t uxLine );
@@ -196,532 +200,535 @@ static void prvQueueAccessLogError( UBaseType_t uxLine );
void vStartInterruptQueueTasks( void )
{
- /* Start the test tasks. */
- xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H1QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask1 );
- xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H2QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask2 );
- xTaskCreate( prvLowerPriorityNormallyEmptyTask, "L1QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL );
- xTaskCreate( prv1stHigherPriorityNormallyFullTask, "H1QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask1 );
- xTaskCreate( prv2ndHigherPriorityNormallyFullTask, "H2QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask2 );
- xTaskCreate( prvLowerPriorityNormallyFullTask, "L2QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL );
-
- /* Create the queues that are accessed by multiple tasks and multiple
- interrupts. */
- xNormallyFullQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) );
- xNormallyEmptyQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) );
-
- /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
- in use. The queue registry is provided as a means for kernel aware
- debuggers to locate queues and has no purpose if a kernel aware debugger
- is not being used. The call to vQueueAddToRegistry() will be removed
- by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
- defined to be less than 1. */
- vQueueAddToRegistry( xNormallyFullQueue, "NormallyFull" );
- vQueueAddToRegistry( xNormallyEmptyQueue, "NormallyEmpty" );
+ /* Start the test tasks. */
+ xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H1QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask1 );
+ xTaskCreate( prvHigherPriorityNormallyEmptyTask, "H2QRx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyEmptyTask2 );
+ xTaskCreate( prvLowerPriorityNormallyEmptyTask, "L1QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL );
+ xTaskCreate( prv1stHigherPriorityNormallyFullTask, "H1QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK1, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask1 );
+ xTaskCreate( prv2ndHigherPriorityNormallyFullTask, "H2QTx", configMINIMAL_STACK_SIZE, ( void * ) intqHIGH_PRIORITY_TASK2, intqHIGHER_PRIORITY, &xHighPriorityNormallyFullTask2 );
+ xTaskCreate( prvLowerPriorityNormallyFullTask, "L2QRx", configMINIMAL_STACK_SIZE, NULL, intqLOWER_PRIORITY, NULL );
+
+ /* Create the queues that are accessed by multiple tasks and multiple
+ * interrupts. */
+ xNormallyFullQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) );
+ xNormallyEmptyQueue = xQueueCreate( intqQUEUE_LENGTH, ( UBaseType_t ) sizeof( UBaseType_t ) );
+
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+ * in use. The queue registry is provided as a means for kernel aware
+ * debuggers to locate queues and has no purpose if a kernel aware debugger
+ * is not being used. The call to vQueueAddToRegistry() will be removed
+ * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+ * defined to be less than 1. */
+ vQueueAddToRegistry( xNormallyFullQueue, "NormallyFull" );
+ vQueueAddToRegistry( xNormallyEmptyQueue, "NormallyEmpty" );
}
/*-----------------------------------------------------------*/
-static void prvRecordValue_NormallyFull( UBaseType_t uxValue, UBaseType_t uxSource )
+static void prvRecordValue_NormallyFull( UBaseType_t uxValue,
+ UBaseType_t uxSource )
{
- if( uxValue < intqNUM_VALUES_TO_LOG )
- {
- /* We don't expect to receive the same value twice, so if the value
- has already been marked as received an error has occurred. */
- if( ucNormallyFullReceivedValues[ uxValue ] != 0x00 )
- {
- prvQueueAccessLogError( __LINE__ );
- }
-
- /* Log that this value has been received. */
- ucNormallyFullReceivedValues[ uxValue ] = ( uint8_t ) uxSource;
- }
+ if( uxValue < intqNUM_VALUES_TO_LOG )
+ {
+ /* We don't expect to receive the same value twice, so if the value
+ * has already been marked as received an error has occurred. */
+ if( ucNormallyFullReceivedValues[ uxValue ] != 0x00 )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ /* Log that this value has been received. */
+ ucNormallyFullReceivedValues[ uxValue ] = ( uint8_t ) uxSource;
+ }
}
/*-----------------------------------------------------------*/
-static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue, UBaseType_t uxSource )
+static void prvRecordValue_NormallyEmpty( UBaseType_t uxValue,
+ UBaseType_t uxSource )
{
- if( uxValue < intqNUM_VALUES_TO_LOG )
- {
- /* We don't expect to receive the same value twice, so if the value
- has already been marked as received an error has occurred. */
- if( ucNormallyEmptyReceivedValues[ uxValue ] != 0x00 )
- {
- prvQueueAccessLogError( __LINE__ );
- }
-
- /* Log that this value has been received. */
- ucNormallyEmptyReceivedValues[ uxValue ] = ( uint8_t ) uxSource;
- }
+ if( uxValue < intqNUM_VALUES_TO_LOG )
+ {
+ /* We don't expect to receive the same value twice, so if the value
+ * has already been marked as received an error has occurred. */
+ if( ucNormallyEmptyReceivedValues[ uxValue ] != 0x00 )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ /* Log that this value has been received. */
+ ucNormallyEmptyReceivedValues[ uxValue ] = ( uint8_t ) uxSource;
+ }
}
/*-----------------------------------------------------------*/
static void prvQueueAccessLogError( UBaseType_t uxLine )
{
- /* Latch the line number that caused the error. */
- xErrorLine = uxLine;
- xErrorStatus = pdFAIL;
+ /* Latch the line number that caused the error. */
+ xErrorLine = uxLine;
+ xErrorStatus = pdFAIL;
}
/*-----------------------------------------------------------*/
-static void prvHigherPriorityNormallyEmptyTask( void *pvParameters )
+static void prvHigherPriorityNormallyEmptyTask( void * pvParameters )
{
-UBaseType_t uxRxed, ux, uxTask1, uxTask2, uxInterrupts, uxErrorCount1 = 0, uxErrorCount2 = 0;
-
- /* The timer should not be started until after the scheduler has started.
- More than one task is running this code so we check the parameter value
- to determine which task should start the timer. */
- if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 )
- {
- vInitialiseTimerForIntQueueTest();
- }
-
- for( ;; )
- {
- /* Block waiting to receive a value from the normally empty queue.
- Interrupts will write to the queue so we should receive a value. */
- if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqSHORT_DELAY ) != pdPASS )
- {
- prvQueueAccessLogError( __LINE__ );
- }
- else
- {
- /* Note which value was received so we can check all expected
- values are received and no values are duplicated. */
- prvRecordValue_NormallyEmpty( uxRxed, ( UBaseType_t ) pvParameters );
- }
-
- /* Ensure the other task running this code gets a chance to execute. */
- taskYIELD();
-
- if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 )
- {
- /* Have we received all the expected values? */
- if( uxValueForNormallyEmptyQueue > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) )
- {
- vTaskSuspend( xHighPriorityNormallyEmptyTask2 );
-
- uxTask1 = 0;
- uxTask2 = 0;
- uxInterrupts = 0;
-
- /* Loop through the array, checking that both tasks have
- placed values into the array, and that no values are missing.
- Start at 1 as we expect position 0 to be unused. */
- for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ )
- {
- if( ucNormallyEmptyReceivedValues[ ux ] == 0 )
- {
- /* A value is missing. */
- prvQueueAccessLogError( __LINE__ );
- }
- else
- {
- if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK1 )
- {
- /* Value was placed into the array by task 1. */
- uxTask1++;
- }
- else if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK2 )
- {
- /* Value was placed into the array by task 2. */
- uxTask2++;
- }
- else if( ucNormallyEmptyReceivedValues[ ux ] == intqSECOND_INTERRUPT )
- {
- uxInterrupts++;
- }
- }
- }
-
- if( uxTask1 < intqMIN_ACCEPTABLE_TASK_COUNT )
- {
- /* Only task 2 seemed to log any values. */
- uxErrorCount1++;
- if( uxErrorCount1 > 2 )
- {
- prvQueueAccessLogError( __LINE__ );
- }
- }
- else
- {
- uxErrorCount1 = 0;
- }
-
- if( uxTask2 < intqMIN_ACCEPTABLE_TASK_COUNT )
- {
- /* Only task 1 seemed to log any values. */
- uxErrorCount2++;
- if( uxErrorCount2 > 2 )
- {
- prvQueueAccessLogError( __LINE__ );
- }
- }
- else
- {
- uxErrorCount2 = 0;
- }
-
- if( uxInterrupts == 0 )
- {
- prvQueueAccessLogError( __LINE__ );
- }
-
- /* Clear the array again, ready to start a new cycle. */
- memset( ucNormallyEmptyReceivedValues, 0x00, sizeof( ucNormallyEmptyReceivedValues ) );
-
- uxHighPriorityLoops1++;
- uxValueForNormallyEmptyQueue = 0;
-
- /* Suspend ourselves, allowing the lower priority task to
- actually receive something from the queue. Until now it
- will have been prevented from doing so by the higher
- priority tasks. The lower priority task will resume us
- if it receives something. We will then resume the other
- higher priority task. */
- vTaskSuspend( NULL );
- vTaskResume( xHighPriorityNormallyEmptyTask2 );
- }
- }
- }
+ UBaseType_t uxRxed, ux, uxTask1, uxTask2, uxInterrupts, uxErrorCount1 = 0, uxErrorCount2 = 0;
+
+ /* The timer should not be started until after the scheduler has started.
+ * More than one task is running this code so we check the parameter value
+ * to determine which task should start the timer. */
+ if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 )
+ {
+ vInitialiseTimerForIntQueueTest();
+ }
+
+ for( ; ; )
+ {
+ /* Block waiting to receive a value from the normally empty queue.
+ * Interrupts will write to the queue so we should receive a value. */
+ if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqSHORT_DELAY ) != pdPASS )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+ else
+ {
+ /* Note which value was received so we can check all expected
+ * values are received and no values are duplicated. */
+ prvRecordValue_NormallyEmpty( uxRxed, ( UBaseType_t ) pvParameters );
+ }
+
+ /* Ensure the other task running this code gets a chance to execute. */
+ taskYIELD();
+
+ if( ( UBaseType_t ) pvParameters == intqHIGH_PRIORITY_TASK1 )
+ {
+ /* Have we received all the expected values? */
+ if( uxValueForNormallyEmptyQueue > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) )
+ {
+ vTaskSuspend( xHighPriorityNormallyEmptyTask2 );
+
+ uxTask1 = 0;
+ uxTask2 = 0;
+ uxInterrupts = 0;
+
+ /* Loop through the array, checking that both tasks have
+ * placed values into the array, and that no values are missing.
+ * Start at 1 as we expect position 0 to be unused. */
+ for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ )
+ {
+ if( ucNormallyEmptyReceivedValues[ ux ] == 0 )
+ {
+ /* A value is missing. */
+ prvQueueAccessLogError( __LINE__ );
+ }
+ else
+ {
+ if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK1 )
+ {
+ /* Value was placed into the array by task 1. */
+ uxTask1++;
+ }
+ else if( ucNormallyEmptyReceivedValues[ ux ] == intqHIGH_PRIORITY_TASK2 )
+ {
+ /* Value was placed into the array by task 2. */
+ uxTask2++;
+ }
+ else if( ucNormallyEmptyReceivedValues[ ux ] == intqSECOND_INTERRUPT )
+ {
+ uxInterrupts++;
+ }
+ }
+ }
+
+ if( uxTask1 < intqMIN_ACCEPTABLE_TASK_COUNT )
+ {
+ /* Only task 2 seemed to log any values. */
+ uxErrorCount1++;
+
+ if( uxErrorCount1 > 2 )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+ }
+ else
+ {
+ uxErrorCount1 = 0;
+ }
+
+ if( uxTask2 < intqMIN_ACCEPTABLE_TASK_COUNT )
+ {
+ /* Only task 1 seemed to log any values. */
+ uxErrorCount2++;
+
+ if( uxErrorCount2 > 2 )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+ }
+ else
+ {
+ uxErrorCount2 = 0;
+ }
+
+ if( uxInterrupts == 0 )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ /* Clear the array again, ready to start a new cycle. */
+ memset( ucNormallyEmptyReceivedValues, 0x00, sizeof( ucNormallyEmptyReceivedValues ) );
+
+ uxHighPriorityLoops1++;
+ uxValueForNormallyEmptyQueue = 0;
+
+ /* Suspend ourselves, allowing the lower priority task to
+ * actually receive something from the queue. Until now it
+ * will have been prevented from doing so by the higher
+ * priority tasks. The lower priority task will resume us
+ * if it receives something. We will then resume the other
+ * higher priority task. */
+ vTaskSuspend( NULL );
+ vTaskResume( xHighPriorityNormallyEmptyTask2 );
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvLowerPriorityNormallyEmptyTask( void *pvParameters )
+static void prvLowerPriorityNormallyEmptyTask( void * pvParameters )
{
-UBaseType_t uxValue, uxRxed;
-
- /* The parameters are not being used so avoid compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqONE_TICK_DELAY ) != errQUEUE_EMPTY )
- {
- /* A value should only be obtained when the high priority task is
- suspended. */
- if( eTaskGetState( xHighPriorityNormallyEmptyTask1 ) != eSuspended )
- {
- prvQueueAccessLogError( __LINE__ );
- }
-
- prvRecordValue_NormallyEmpty( uxRxed, intqLOW_PRIORITY_TASK );
-
- /* Wake the higher priority task again. */
- vTaskResume( xHighPriorityNormallyEmptyTask1 );
- uxLowPriorityLoops1++;
- }
- else
- {
- /* Raise our priority while we send so we can preempt the higher
- priority task, and ensure we get the Tx value into the queue. */
- vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 );
-
- portENTER_CRITICAL();
- {
- uxValueForNormallyEmptyQueue++;
- uxValue = uxValueForNormallyEmptyQueue;
- }
- portEXIT_CRITICAL();
-
- if( xQueueSend( xNormallyEmptyQueue, &uxValue, portMAX_DELAY ) != pdPASS )
- {
- prvQueueAccessLogError( __LINE__ );
- }
-
- vTaskPrioritySet( NULL, intqLOWER_PRIORITY );
- }
- }
+ UBaseType_t uxValue, uxRxed;
+
+ /* The parameters are not being used so avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ if( xQueueReceive( xNormallyEmptyQueue, &uxRxed, intqONE_TICK_DELAY ) != errQUEUE_EMPTY )
+ {
+ /* A value should only be obtained when the high priority task is
+ * suspended. */
+ if( eTaskGetState( xHighPriorityNormallyEmptyTask1 ) != eSuspended )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ prvRecordValue_NormallyEmpty( uxRxed, intqLOW_PRIORITY_TASK );
+
+ /* Wake the higher priority task again. */
+ vTaskResume( xHighPriorityNormallyEmptyTask1 );
+ uxLowPriorityLoops1++;
+ }
+ else
+ {
+ /* Raise our priority while we send so we can preempt the higher
+ * priority task, and ensure we get the Tx value into the queue. */
+ vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 );
+
+ portENTER_CRITICAL();
+ {
+ uxValueForNormallyEmptyQueue++;
+ uxValue = uxValueForNormallyEmptyQueue;
+ }
+ portEXIT_CRITICAL();
+
+ if( xQueueSend( xNormallyEmptyQueue, &uxValue, portMAX_DELAY ) != pdPASS )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ vTaskPrioritySet( NULL, intqLOWER_PRIORITY );
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prv1stHigherPriorityNormallyFullTask( void *pvParameters )
+static void prv1stHigherPriorityNormallyFullTask( void * pvParameters )
{
-UBaseType_t uxValueToTx, ux, uxInterrupts;
-
- /* The parameters are not being used so avoid compiler warnings. */
- ( void ) pvParameters;
-
- /* Make sure the queue starts full or near full. >> 1 as there are two
- high priority tasks. */
- for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ )
- {
- portENTER_CRITICAL();
- {
- uxValueForNormallyFullQueue++;
- uxValueToTx = uxValueForNormallyFullQueue;
- }
- portEXIT_CRITICAL();
-
- xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY );
- }
-
- for( ;; )
- {
- portENTER_CRITICAL();
- {
- uxValueForNormallyFullQueue++;
- uxValueToTx = uxValueForNormallyFullQueue;
- }
- portEXIT_CRITICAL();
-
- if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS )
- {
- /* intqHIGH_PRIORITY_TASK2 is never suspended so we would not
- expect it to ever time out. */
- prvQueueAccessLogError( __LINE__ );
- }
-
- /* Allow the other task running this code to run. */
- taskYIELD();
-
- /* Have all the expected values been sent to the queue? */
- if( uxValueToTx > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) )
- {
- /* Make sure the other high priority task completes its send of
- any values below intqNUM_VALUE_TO_LOG. */
- vTaskDelay( intqSHORT_DELAY );
-
- vTaskSuspend( xHighPriorityNormallyFullTask2 );
-
- if( xWasSuspended == pdTRUE )
- {
- /* We would have expected the other high priority task to have
- set this back to false by now. */
- prvQueueAccessLogError( __LINE__ );
- }
-
- /* Set the suspended flag so an error is not logged if the other
- task recognises a time out when it is unsuspended. */
- xWasSuspended = pdTRUE;
-
- /* Check interrupts are also sending. */
- uxInterrupts = 0U;
-
- /* Start at 1 as we expect position 0 to be unused. */
- for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ )
- {
- if( ucNormallyFullReceivedValues[ ux ] == 0 )
- {
- /* A value was missing. */
- prvQueueAccessLogError( __LINE__ );
- }
- else if( ucNormallyFullReceivedValues[ ux ] == intqSECOND_INTERRUPT )
- {
- uxInterrupts++;
- }
- }
-
- if( uxInterrupts == 0 )
- {
- /* No writes from interrupts were found. Are interrupts
- actually running? */
- prvQueueAccessLogError( __LINE__ );
- }
-
- /* Reset the array ready for the next cycle. */
- memset( ucNormallyFullReceivedValues, 0x00, sizeof( ucNormallyFullReceivedValues ) );
-
- uxHighPriorityLoops2++;
- uxValueForNormallyFullQueue = 0;
-
- /* Suspend ourselves, allowing the lower priority task to
- actually receive something from the queue. Until now it
- will have been prevented from doing so by the higher
- priority tasks. The lower priority task will resume us
- if it receives something. We will then resume the other
- higher priority task. */
- vTaskSuspend( NULL );
- vTaskResume( xHighPriorityNormallyFullTask2 );
- }
- }
+ UBaseType_t uxValueToTx, ux, uxInterrupts;
+
+ /* The parameters are not being used so avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Make sure the queue starts full or near full. >> 1 as there are two
+ * high priority tasks. */
+ for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ )
+ {
+ portENTER_CRITICAL();
+ {
+ uxValueForNormallyFullQueue++;
+ uxValueToTx = uxValueForNormallyFullQueue;
+ }
+ portEXIT_CRITICAL();
+
+ xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY );
+ }
+
+ for( ; ; )
+ {
+ portENTER_CRITICAL();
+ {
+ uxValueForNormallyFullQueue++;
+ uxValueToTx = uxValueForNormallyFullQueue;
+ }
+ portEXIT_CRITICAL();
+
+ if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS )
+ {
+ /* intqHIGH_PRIORITY_TASK2 is never suspended so we would not
+ * expect it to ever time out. */
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ /* Allow the other task running this code to run. */
+ taskYIELD();
+
+ /* Have all the expected values been sent to the queue? */
+ if( uxValueToTx > ( intqNUM_VALUES_TO_LOG + intqVALUE_OVERRUN ) )
+ {
+ /* Make sure the other high priority task completes its send of
+ * any values below intqNUM_VALUE_TO_LOG. */
+ vTaskDelay( intqSHORT_DELAY );
+
+ vTaskSuspend( xHighPriorityNormallyFullTask2 );
+
+ if( xWasSuspended == pdTRUE )
+ {
+ /* We would have expected the other high priority task to have
+ * set this back to false by now. */
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ /* Set the suspended flag so an error is not logged if the other
+ * task recognises a time out when it is unsuspended. */
+ xWasSuspended = pdTRUE;
+
+ /* Check interrupts are also sending. */
+ uxInterrupts = 0U;
+
+ /* Start at 1 as we expect position 0 to be unused. */
+ for( ux = 1; ux < intqNUM_VALUES_TO_LOG; ux++ )
+ {
+ if( ucNormallyFullReceivedValues[ ux ] == 0 )
+ {
+ /* A value was missing. */
+ prvQueueAccessLogError( __LINE__ );
+ }
+ else if( ucNormallyFullReceivedValues[ ux ] == intqSECOND_INTERRUPT )
+ {
+ uxInterrupts++;
+ }
+ }
+
+ if( uxInterrupts == 0 )
+ {
+ /* No writes from interrupts were found. Are interrupts
+ * actually running? */
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ /* Reset the array ready for the next cycle. */
+ memset( ucNormallyFullReceivedValues, 0x00, sizeof( ucNormallyFullReceivedValues ) );
+
+ uxHighPriorityLoops2++;
+ uxValueForNormallyFullQueue = 0;
+
+ /* Suspend ourselves, allowing the lower priority task to
+ * actually receive something from the queue. Until now it
+ * will have been prevented from doing so by the higher
+ * priority tasks. The lower priority task will resume us
+ * if it receives something. We will then resume the other
+ * higher priority task. */
+ vTaskSuspend( NULL );
+ vTaskResume( xHighPriorityNormallyFullTask2 );
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prv2ndHigherPriorityNormallyFullTask( void *pvParameters )
+static void prv2ndHigherPriorityNormallyFullTask( void * pvParameters )
{
-UBaseType_t uxValueToTx, ux;
-
- /* The parameters are not being used so avoid compiler warnings. */
- ( void ) pvParameters;
-
- /* Make sure the queue starts full or near full. >> 1 as there are two
- high priority tasks. */
- for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ )
- {
- portENTER_CRITICAL();
- {
- uxValueForNormallyFullQueue++;
- uxValueToTx = uxValueForNormallyFullQueue;
- }
- portEXIT_CRITICAL();
-
- xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY );
- }
-
- for( ;; )
- {
- portENTER_CRITICAL();
- {
- uxValueForNormallyFullQueue++;
- uxValueToTx = uxValueForNormallyFullQueue;
- }
- portEXIT_CRITICAL();
-
- if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS )
- {
- if( xWasSuspended != pdTRUE )
- {
- /* It is ok to time out if the task has been suspended. */
- prvQueueAccessLogError( __LINE__ );
- }
- }
-
- xWasSuspended = pdFALSE;
-
- taskYIELD();
- }
+ UBaseType_t uxValueToTx, ux;
+
+ /* The parameters are not being used so avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Make sure the queue starts full or near full. >> 1 as there are two
+ * high priority tasks. */
+ for( ux = 0; ux < ( intqQUEUE_LENGTH >> 1 ); ux++ )
+ {
+ portENTER_CRITICAL();
+ {
+ uxValueForNormallyFullQueue++;
+ uxValueToTx = uxValueForNormallyFullQueue;
+ }
+ portEXIT_CRITICAL();
+
+ xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY );
+ }
+
+ for( ; ; )
+ {
+ portENTER_CRITICAL();
+ {
+ uxValueForNormallyFullQueue++;
+ uxValueToTx = uxValueForNormallyFullQueue;
+ }
+ portEXIT_CRITICAL();
+
+ if( xQueueSend( xNormallyFullQueue, &uxValueToTx, intqSHORT_DELAY ) != pdPASS )
+ {
+ if( xWasSuspended != pdTRUE )
+ {
+ /* It is ok to time out if the task has been suspended. */
+ prvQueueAccessLogError( __LINE__ );
+ }
+ }
+
+ xWasSuspended = pdFALSE;
+
+ taskYIELD();
+ }
}
/*-----------------------------------------------------------*/
-static void prvLowerPriorityNormallyFullTask( void *pvParameters )
+static void prvLowerPriorityNormallyFullTask( void * pvParameters )
{
-UBaseType_t uxValue, uxTxed = 9999;
-
- /* The parameters are not being used so avoid compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- if( xQueueSend( xNormallyFullQueue, &uxTxed, intqONE_TICK_DELAY ) != errQUEUE_FULL )
- {
- /* Should only succeed when the higher priority task is suspended */
- if( eTaskGetState( xHighPriorityNormallyFullTask1 ) != eSuspended )
- {
- prvQueueAccessLogError( __LINE__ );
- }
-
- vTaskResume( xHighPriorityNormallyFullTask1 );
- uxLowPriorityLoops2++;
- }
- else
- {
- /* Raise our priority while we receive so we can preempt the higher
- priority task, and ensure we get the value from the queue. */
- vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 );
-
- if( xQueueReceive( xNormallyFullQueue, &uxValue, portMAX_DELAY ) != pdPASS )
- {
- prvQueueAccessLogError( __LINE__ );
- }
- else
- {
- prvRecordValue_NormallyFull( uxValue, intqLOW_PRIORITY_TASK );
- }
-
- vTaskPrioritySet( NULL, intqLOWER_PRIORITY );
- }
- }
+ UBaseType_t uxValue, uxTxed = 9999;
+
+ /* The parameters are not being used so avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ if( xQueueSend( xNormallyFullQueue, &uxTxed, intqONE_TICK_DELAY ) != errQUEUE_FULL )
+ {
+ /* Should only succeed when the higher priority task is suspended */
+ if( eTaskGetState( xHighPriorityNormallyFullTask1 ) != eSuspended )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+
+ vTaskResume( xHighPriorityNormallyFullTask1 );
+ uxLowPriorityLoops2++;
+ }
+ else
+ {
+ /* Raise our priority while we receive so we can preempt the higher
+ * priority task, and ensure we get the value from the queue. */
+ vTaskPrioritySet( NULL, intqHIGHER_PRIORITY + 1 );
+
+ if( xQueueReceive( xNormallyFullQueue, &uxValue, portMAX_DELAY ) != pdPASS )
+ {
+ prvQueueAccessLogError( __LINE__ );
+ }
+ else
+ {
+ prvRecordValue_NormallyFull( uxValue, intqLOW_PRIORITY_TASK );
+ }
+
+ vTaskPrioritySet( NULL, intqLOWER_PRIORITY );
+ }
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xFirstTimerHandler( void )
{
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-UBaseType_t uxRxedValue;
-static UBaseType_t uxNextOperation = 0;
-
- /* Called from a timer interrupt. Perform various read and write
- accesses on the queues. */
-
- uxNextOperation++;
-
- if( uxNextOperation & ( UBaseType_t ) 0x01 )
- {
- timerNORMALLY_EMPTY_TX();
- timerNORMALLY_EMPTY_TX();
- timerNORMALLY_EMPTY_TX();
- }
- else
- {
- timerNORMALLY_FULL_RX();
- timerNORMALLY_FULL_RX();
- timerNORMALLY_FULL_RX();
- }
-
- return xHigherPriorityTaskWoken;
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ UBaseType_t uxRxedValue;
+ static UBaseType_t uxNextOperation = 0;
+
+ /* Called from a timer interrupt. Perform various read and write
+ * accesses on the queues. */
+
+ uxNextOperation++;
+
+ if( uxNextOperation & ( UBaseType_t ) 0x01 )
+ {
+ timerNORMALLY_EMPTY_TX();
+ timerNORMALLY_EMPTY_TX();
+ timerNORMALLY_EMPTY_TX();
+ }
+ else
+ {
+ timerNORMALLY_FULL_RX();
+ timerNORMALLY_FULL_RX();
+ timerNORMALLY_FULL_RX();
+ }
+
+ return xHigherPriorityTaskWoken;
}
/*-----------------------------------------------------------*/
BaseType_t xSecondTimerHandler( void )
{
-UBaseType_t uxRxedValue;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-static UBaseType_t uxNextOperation = 0;
-
- /* Called from a timer interrupt. Perform various read and write
- accesses on the queues. */
-
- uxNextOperation++;
-
- if( uxNextOperation & ( UBaseType_t ) 0x01 )
- {
- timerNORMALLY_EMPTY_TX();
- timerNORMALLY_EMPTY_TX();
-
- timerNORMALLY_EMPTY_RX();
- timerNORMALLY_EMPTY_RX();
- }
- else
- {
- timerNORMALLY_FULL_RX();
- timerNORMALLY_FULL_TX();
- timerNORMALLY_FULL_TX();
- timerNORMALLY_FULL_TX();
- }
-
- return xHigherPriorityTaskWoken;
+ UBaseType_t uxRxedValue;
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ static UBaseType_t uxNextOperation = 0;
+
+ /* Called from a timer interrupt. Perform various read and write
+ * accesses on the queues. */
+
+ uxNextOperation++;
+
+ if( uxNextOperation & ( UBaseType_t ) 0x01 )
+ {
+ timerNORMALLY_EMPTY_TX();
+ timerNORMALLY_EMPTY_TX();
+
+ timerNORMALLY_EMPTY_RX();
+ timerNORMALLY_EMPTY_RX();
+ }
+ else
+ {
+ timerNORMALLY_FULL_RX();
+ timerNORMALLY_FULL_TX();
+ timerNORMALLY_FULL_TX();
+ timerNORMALLY_FULL_TX();
+ }
+
+ return xHigherPriorityTaskWoken;
}
/*-----------------------------------------------------------*/
BaseType_t xAreIntQueueTasksStillRunning( void )
{
-static UBaseType_t uxLastHighPriorityLoops1 = 0, uxLastHighPriorityLoops2 = 0, uxLastLowPriorityLoops1 = 0, uxLastLowPriorityLoops2 = 0;
+ static UBaseType_t uxLastHighPriorityLoops1 = 0, uxLastHighPriorityLoops2 = 0, uxLastLowPriorityLoops1 = 0, uxLastLowPriorityLoops2 = 0;
- /* xErrorStatus can be set outside of this function. This function just
- checks that all the tasks are still cycling. */
+ /* xErrorStatus can be set outside of this function. This function just
+ * checks that all the tasks are still cycling. */
- if( uxHighPriorityLoops1 == uxLastHighPriorityLoops1 )
- {
- /* The high priority 1 task has stalled. */
- prvQueueAccessLogError( __LINE__ );
- }
+ if( uxHighPriorityLoops1 == uxLastHighPriorityLoops1 )
+ {
+ /* The high priority 1 task has stalled. */
+ prvQueueAccessLogError( __LINE__ );
+ }
- uxLastHighPriorityLoops1 = uxHighPriorityLoops1;
+ uxLastHighPriorityLoops1 = uxHighPriorityLoops1;
- if( uxHighPriorityLoops2 == uxLastHighPriorityLoops2 )
- {
- /* The high priority 2 task has stalled. */
- prvQueueAccessLogError( __LINE__ );
- }
+ if( uxHighPriorityLoops2 == uxLastHighPriorityLoops2 )
+ {
+ /* The high priority 2 task has stalled. */
+ prvQueueAccessLogError( __LINE__ );
+ }
- uxLastHighPriorityLoops2 = uxHighPriorityLoops2;
+ uxLastHighPriorityLoops2 = uxHighPriorityLoops2;
- if( uxLowPriorityLoops1 == uxLastLowPriorityLoops1 )
- {
- /* The low priority 1 task has stalled. */
- prvQueueAccessLogError( __LINE__ );
- }
+ if( uxLowPriorityLoops1 == uxLastLowPriorityLoops1 )
+ {
+ /* The low priority 1 task has stalled. */
+ prvQueueAccessLogError( __LINE__ );
+ }
- uxLastLowPriorityLoops1 = uxLowPriorityLoops1;
+ uxLastLowPriorityLoops1 = uxLowPriorityLoops1;
- if( uxLowPriorityLoops2 == uxLastLowPriorityLoops2 )
- {
- /* The low priority 2 task has stalled. */
- prvQueueAccessLogError( __LINE__ );
- }
+ if( uxLowPriorityLoops2 == uxLastLowPriorityLoops2 )
+ {
+ /* The low priority 2 task has stalled. */
+ prvQueueAccessLogError( __LINE__ );
+ }
- uxLastLowPriorityLoops2 = uxLowPriorityLoops2;
+ uxLastLowPriorityLoops2 = uxLowPriorityLoops2;
- return xErrorStatus;
+ return xErrorStatus;
}
-
diff --git a/Demo/Common/Minimal/IntSemTest.c b/Demo/Common/Minimal/IntSemTest.c
index 70358a2bf..747b937aa 100644
--- a/Demo/Common/Minimal/IntSemTest.c
+++ b/Demo/Common/Minimal/IntSemTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -44,18 +44,18 @@
/*-----------------------------------------------------------*/
/* The priorities of the test tasks. */
-#define intsemMASTER_PRIORITY ( tskIDLE_PRIORITY )
-#define intsemSLAVE_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define intsemMASTER_PRIORITY ( tskIDLE_PRIORITY )
+#define intsemSLAVE_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which the tick hook will give the mutex. */
-#define intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ( 100 )
+#define intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ( 100 )
/* A block time of 0 means 'don't block'. */
-#define intsemNO_BLOCK 0
+#define intsemNO_BLOCK 0
/* The maximum count value for the counting semaphore given from an
-interrupt. */
-#define intsemMAX_COUNT 3
+ * interrupt. */
+#define intsemMAX_COUNT 3
/*-----------------------------------------------------------*/
@@ -69,8 +69,8 @@ interrupt. */
* on a mutex that is shared between the master and the slave - which is a
* separate mutex to that given by the interrupt.
*/
-static void vInterruptMutexSlaveTask( void *pvParameters );
-static void vInterruptMutexMasterTask( void *pvParameters );
+static void vInterruptMutexSlaveTask( void * pvParameters );
+static void vInterruptMutexMasterTask( void * pvParameters );
/*
* A test whereby the master takes the shared and interrupt mutexes in that
@@ -90,37 +90,37 @@ static void prvTakeAndGiveInTheOppositeOrder( void );
* A simple task that interacts with an interrupt using a counting semaphore,
* primarily for code coverage purposes.
*/
-static void vInterruptCountingSemaphoreTask( void *pvParameters );
+static void vInterruptCountingSemaphoreTask( void * pvParameters );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
-detected in any of the tasks. */
+ * detected in any of the tasks. */
static volatile BaseType_t xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
-detect a stalled task - a test that is no longer running. */
+ * detect a stalled task - a test that is no longer running. */
static volatile uint32_t ulMasterLoops = 0, ulCountingSemaphoreLoops = 0;
/* Handles of the test tasks that must be accessed from other test tasks. */
static TaskHandle_t xSlaveHandle;
/* A mutex which is given from an interrupt - although generally mutexes should
-not be used given in interrupts (and definitely never taken in an interrupt)
-there are some circumstances when it may be desirable. */
+ * not be used given in interrupts (and definitely never taken in an interrupt)
+ * there are some circumstances when it may be desirable. */
static SemaphoreHandle_t xISRMutex = NULL;
/* A counting semaphore which is given from an interrupt. */
static SemaphoreHandle_t xISRCountingSemaphore = NULL;
/* A mutex which is shared between the master and slave tasks - the master
-does both sharing of this mutex with the slave and receiving a mutex from the
-interrupt. */
+ * does both sharing of this mutex with the slave and receiving a mutex from the
+ * interrupt. */
static SemaphoreHandle_t xMasterSlaveMutex = NULL;
/* Flag that allows the master task to control when the interrupt gives or does
-not give the mutex. There is no mutual exclusion on this variable, but this is
-only test code and it should be fine in the 32=bit test environment. */
+ * not give the mutex. There is no mutual exclusion on this variable, but this is
+ * only test code and it should be fine in the 32=bit test environment. */
static BaseType_t xOkToGiveMutex = pdFALSE, xOkToGiveCountingSemaphore = pdFALSE;
/* Used to coordinate timing between tasks and the interrupt. */
@@ -130,396 +130,402 @@ const TickType_t xInterruptGivePeriod = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIV
void vStartInterruptSemaphoreTasks( void )
{
- /* Create the semaphores that are given from an interrupt. */
- xISRMutex = xSemaphoreCreateMutex();
- configASSERT( xISRMutex );
- xISRCountingSemaphore = xSemaphoreCreateCounting( intsemMAX_COUNT, 0 );
- configASSERT( xISRCountingSemaphore );
-
- /* Create the mutex that is shared between the master and slave tasks (the
- master receives a mutex from an interrupt and shares a mutex with the
- slave. */
- xMasterSlaveMutex = xSemaphoreCreateMutex();
- configASSERT( xMasterSlaveMutex );
-
- /* Create the tasks that share mutexes between then and with interrupts. */
- xTaskCreate( vInterruptMutexSlaveTask, "IntMuS", configMINIMAL_STACK_SIZE, NULL, intsemSLAVE_PRIORITY, &xSlaveHandle );
- xTaskCreate( vInterruptMutexMasterTask, "IntMuM", configMINIMAL_STACK_SIZE, NULL, intsemMASTER_PRIORITY, NULL );
-
- /* Create the task that blocks on the counting semaphore. */
- xTaskCreate( vInterruptCountingSemaphoreTask, "IntCnt", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ /* Create the semaphores that are given from an interrupt. */
+ xISRMutex = xSemaphoreCreateMutex();
+ configASSERT( xISRMutex );
+ xISRCountingSemaphore = xSemaphoreCreateCounting( intsemMAX_COUNT, 0 );
+ configASSERT( xISRCountingSemaphore );
+
+ /* Create the mutex that is shared between the master and slave tasks (the
+ * master receives a mutex from an interrupt and shares a mutex with the
+ * slave. */
+ xMasterSlaveMutex = xSemaphoreCreateMutex();
+ configASSERT( xMasterSlaveMutex );
+
+ /* Create the tasks that share mutexes between then and with interrupts. */
+ xTaskCreate( vInterruptMutexSlaveTask, "IntMuS", configMINIMAL_STACK_SIZE, NULL, intsemSLAVE_PRIORITY, &xSlaveHandle );
+ xTaskCreate( vInterruptMutexMasterTask, "IntMuM", configMINIMAL_STACK_SIZE, NULL, intsemMASTER_PRIORITY, NULL );
+
+ /* Create the task that blocks on the counting semaphore. */
+ xTaskCreate( vInterruptCountingSemaphoreTask, "IntCnt", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
}
/*-----------------------------------------------------------*/
-static void vInterruptMutexMasterTask( void *pvParameters )
+static void vInterruptMutexMasterTask( void * pvParameters )
{
- /* Just to avoid compiler warnings. */
- ( void ) pvParameters;
+ /* Just to avoid compiler warnings. */
+ ( void ) pvParameters;
- for( ;; )
- {
- prvTakeAndGiveInTheSameOrder();
+ for( ; ; )
+ {
+ prvTakeAndGiveInTheSameOrder();
- /* Ensure not to starve out other tests. */
- ulMasterLoops++;
- vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
+ /* Ensure not to starve out other tests. */
+ ulMasterLoops++;
+ vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
- prvTakeAndGiveInTheOppositeOrder();
+ prvTakeAndGiveInTheOppositeOrder();
- /* Ensure not to starve out other tests. */
- ulMasterLoops++;
- vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
- }
+ /* Ensure not to starve out other tests. */
+ ulMasterLoops++;
+ vTaskDelay( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS );
+ }
}
/*-----------------------------------------------------------*/
static void prvTakeAndGiveInTheSameOrder( void )
{
- /* Ensure the slave is suspended, and that this task is running at the
- lower priority as expected as the start conditions. */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Take the semaphore that is shared with the slave. */
- if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This task now has the mutex. Unsuspend the slave so it too
- attempts to take the mutex. */
- vTaskResume( xSlaveHandle );
-
- /* The slave has the higher priority so should now have executed and
- blocked on the semaphore. */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* This task should now have inherited the priority of the slave
- task. */
- if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now wait a little longer than the time between ISR gives to also
- obtain the ISR mutex. */
- xOkToGiveMutex = pdTRUE;
- if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- xOkToGiveMutex = pdFALSE;
-
- /* Attempting to take again immediately should fail as the mutex is
- already held. */
- if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Should still be at the priority of the slave task. */
- if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Give back the ISR semaphore to ensure the priority is not
- disinherited as the shared mutex (which the higher priority task is
- attempting to obtain) is still held. */
- if( xSemaphoreGive( xISRMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Finally give back the shared mutex. This time the higher priority
- task should run before this task runs again - so this task should have
- disinherited the priority and the higher priority task should be in the
- suspended state again. */
- if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* Reset the mutex ready for the next round. */
- xQueueReset( xISRMutex );
+ /* Ensure the slave is suspended, and that this task is running at the
+ * lower priority as expected as the start conditions. */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Take the semaphore that is shared with the slave. */
+ if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This task now has the mutex. Unsuspend the slave so it too
+ * attempts to take the mutex. */
+ vTaskResume( xSlaveHandle );
+
+ /* The slave has the higher priority so should now have executed and
+ * blocked on the semaphore. */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* This task should now have inherited the priority of the slave
+ * task. */
+ if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now wait a little longer than the time between ISR gives to also
+ * obtain the ISR mutex. */
+ xOkToGiveMutex = pdTRUE;
+
+ if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ xOkToGiveMutex = pdFALSE;
+
+ /* Attempting to take again immediately should fail as the mutex is
+ * already held. */
+ if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Should still be at the priority of the slave task. */
+ if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Give back the ISR semaphore to ensure the priority is not
+ * disinherited as the shared mutex (which the higher priority task is
+ * attempting to obtain) is still held. */
+ if( xSemaphoreGive( xISRMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Finally give back the shared mutex. This time the higher priority
+ * task should run before this task runs again - so this task should have
+ * disinherited the priority and the higher priority task should be in the
+ * suspended state again. */
+ if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* Reset the mutex ready for the next round. */
+ xQueueReset( xISRMutex );
}
/*-----------------------------------------------------------*/
static void prvTakeAndGiveInTheOppositeOrder( void )
{
- /* Ensure the slave is suspended, and that this task is running at the
- lower priority as expected as the start conditions. */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Take the semaphore that is shared with the slave. */
- if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* This task now has the mutex. Unsuspend the slave so it too
- attempts to take the mutex. */
- vTaskResume( xSlaveHandle );
-
- /* The slave has the higher priority so should now have executed and
- blocked on the semaphore. */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* This task should now have inherited the priority of the slave
- task. */
- if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now wait a little longer than the time between ISR gives to also
- obtain the ISR mutex. */
- xOkToGiveMutex = pdTRUE;
- if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- xOkToGiveMutex = pdFALSE;
-
- /* Attempting to take again immediately should fail as the mutex is
- already held. */
- if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Should still be at the priority of the slave task. */
- if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Give back the shared semaphore to ensure the priority is not disinherited
- as the ISR mutex is still held. The higher priority slave task should run
- before this task runs again. */
- if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Should still be at the priority of the slave task as this task still
- holds one semaphore (this is a simplification in the priority inheritance
- mechanism. */
- if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Give back the ISR semaphore, which should result in the priority being
- disinherited as it was the last mutex held. */
- if( xSemaphoreGive( xISRMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Reset the mutex ready for the next round. */
- xQueueReset( xISRMutex );
+ /* Ensure the slave is suspended, and that this task is running at the
+ * lower priority as expected as the start conditions. */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xSlaveHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Take the semaphore that is shared with the slave. */
+ if( xSemaphoreTake( xMasterSlaveMutex, intsemNO_BLOCK ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* This task now has the mutex. Unsuspend the slave so it too
+ * attempts to take the mutex. */
+ vTaskResume( xSlaveHandle );
+
+ /* The slave has the higher priority so should now have executed and
+ * blocked on the semaphore. */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xSlaveHandle ) == eBlocked );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* This task should now have inherited the priority of the slave
+ * task. */
+ if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now wait a little longer than the time between ISR gives to also
+ * obtain the ISR mutex. */
+ xOkToGiveMutex = pdTRUE;
+
+ if( xSemaphoreTake( xISRMutex, ( xInterruptGivePeriod * 2 ) ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ xOkToGiveMutex = pdFALSE;
+
+ /* Attempting to take again immediately should fail as the mutex is
+ * already held. */
+ if( xSemaphoreTake( xISRMutex, intsemNO_BLOCK ) != pdFAIL )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Should still be at the priority of the slave task. */
+ if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Give back the shared semaphore to ensure the priority is not disinherited
+ * as the ISR mutex is still held. The higher priority slave task should run
+ * before this task runs again. */
+ if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Should still be at the priority of the slave task as this task still
+ * holds one semaphore (this is a simplification in the priority inheritance
+ * mechanism. */
+ if( uxTaskPriorityGet( NULL ) != intsemSLAVE_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Give back the ISR semaphore, which should result in the priority being
+ * disinherited as it was the last mutex held. */
+ if( xSemaphoreGive( xISRMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxTaskPriorityGet( NULL ) != intsemMASTER_PRIORITY )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Reset the mutex ready for the next round. */
+ xQueueReset( xISRMutex );
}
/*-----------------------------------------------------------*/
-static void vInterruptMutexSlaveTask( void *pvParameters )
+static void vInterruptMutexSlaveTask( void * pvParameters )
{
- /* Just to avoid compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* This task starts by suspending itself so when it executes can be
- controlled by the master task. */
- vTaskSuspend( NULL );
-
- /* This task will execute when the master task already holds the mutex.
- Attempting to take the mutex will place this task in the Blocked
- state. */
- if( xSemaphoreTake( xMasterSlaveMutex, portMAX_DELAY ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
- }
+ /* Just to avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* This task starts by suspending itself so when it executes can be
+ * controlled by the master task. */
+ vTaskSuspend( NULL );
+
+ /* This task will execute when the master task already holds the mutex.
+ * Attempting to take the mutex will place this task in the Blocked
+ * state. */
+ if( xSemaphoreTake( xMasterSlaveMutex, portMAX_DELAY ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xSemaphoreGive( xMasterSlaveMutex ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void vInterruptCountingSemaphoreTask( void *pvParameters )
+static void vInterruptCountingSemaphoreTask( void * pvParameters )
{
-BaseType_t xCount;
-const TickType_t xDelay = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) * ( intsemMAX_COUNT + 1 );
-
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Expect to start with the counting semaphore empty. */
- if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Wait until it is expected that the interrupt will have filled the
- counting semaphore. */
- xOkToGiveCountingSemaphore = pdTRUE;
- vTaskDelay( xDelay );
- xOkToGiveCountingSemaphore = pdFALSE;
-
- /* Now it is expected that the counting semaphore is full. */
- if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != intsemMAX_COUNT )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueSpacesAvailable( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- ulCountingSemaphoreLoops++;
-
- /* Expect to be able to take the counting semaphore intsemMAX_COUNT
- times. A block time of 0 is used as the semaphore should already be
- there. */
- xCount = 0;
- while( xSemaphoreTake( xISRCountingSemaphore, 0 ) == pdPASS )
- {
- xCount++;
- }
-
- if( xCount != intsemMAX_COUNT )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Now raise the priority of this task so it runs immediately that the
- semaphore is given from the interrupt. */
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
-
- /* Block to wait for the semaphore to be given from the interrupt. */
- xOkToGiveCountingSemaphore = pdTRUE;
- xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY );
- xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY );
- xOkToGiveCountingSemaphore = pdFALSE;
-
- /* Reset the priority so as not to disturbe other tests too much. */
- vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
-
- ulCountingSemaphoreLoops++;
- }
+ BaseType_t xCount;
+ const TickType_t xDelay = pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) * ( intsemMAX_COUNT + 1 );
+
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Expect to start with the counting semaphore empty. */
+ if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Wait until it is expected that the interrupt will have filled the
+ * counting semaphore. */
+ xOkToGiveCountingSemaphore = pdTRUE;
+ vTaskDelay( xDelay );
+ xOkToGiveCountingSemaphore = pdFALSE;
+
+ /* Now it is expected that the counting semaphore is full. */
+ if( uxQueueMessagesWaiting( ( QueueHandle_t ) xISRCountingSemaphore ) != intsemMAX_COUNT )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueSpacesAvailable( ( QueueHandle_t ) xISRCountingSemaphore ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ ulCountingSemaphoreLoops++;
+
+ /* Expect to be able to take the counting semaphore intsemMAX_COUNT
+ * times. A block time of 0 is used as the semaphore should already be
+ * there. */
+ xCount = 0;
+
+ while( xSemaphoreTake( xISRCountingSemaphore, 0 ) == pdPASS )
+ {
+ xCount++;
+ }
+
+ if( xCount != intsemMAX_COUNT )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now raise the priority of this task so it runs immediately that the
+ * semaphore is given from the interrupt. */
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+
+ /* Block to wait for the semaphore to be given from the interrupt. */
+ xOkToGiveCountingSemaphore = pdTRUE;
+ xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY );
+ xSemaphoreTake( xISRCountingSemaphore, portMAX_DELAY );
+ xOkToGiveCountingSemaphore = pdFALSE;
+
+ /* Reset the priority so as not to disturbe other tests too much. */
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+
+ ulCountingSemaphoreLoops++;
+ }
}
/*-----------------------------------------------------------*/
void vInterruptSemaphorePeriodicTest( void )
{
-static TickType_t xLastGiveTime = 0;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-TickType_t xTimeNow;
-
- /* No mutual exclusion on xOkToGiveMutex, but this is only test code (and
- only executed on a 32-bit architecture) so ignore that in this case. */
- xTimeNow = xTaskGetTickCountFromISR();
- if( ( ( TickType_t ) ( xTimeNow - xLastGiveTime ) ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) )
- {
- configASSERT( xISRMutex );
- if( xOkToGiveMutex != pdFALSE )
- {
- /* Null is used as the second parameter in this give, and non-NULL
- in the other gives for code coverage reasons. */
- xSemaphoreGiveFromISR( xISRMutex, NULL );
-
- /* Second give attempt should fail. */
- configASSERT( xSemaphoreGiveFromISR( xISRMutex, &xHigherPriorityTaskWoken ) == pdFAIL );
- }
-
- if( xOkToGiveCountingSemaphore != pdFALSE )
- {
- xSemaphoreGiveFromISR( xISRCountingSemaphore, &xHigherPriorityTaskWoken );
- }
- xLastGiveTime = xTimeNow;
- }
-
- /* Remove compiler warnings about the value being set but not used. */
- ( void ) xHigherPriorityTaskWoken;
+ static TickType_t xLastGiveTime = 0;
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ TickType_t xTimeNow;
+
+ /* No mutual exclusion on xOkToGiveMutex, but this is only test code (and
+ * only executed on a 32-bit architecture) so ignore that in this case. */
+ xTimeNow = xTaskGetTickCountFromISR();
+
+ if( ( ( TickType_t ) ( xTimeNow - xLastGiveTime ) ) >= pdMS_TO_TICKS( intsemINTERRUPT_MUTEX_GIVE_PERIOD_MS ) )
+ {
+ configASSERT( xISRMutex );
+
+ if( xOkToGiveMutex != pdFALSE )
+ {
+ /* Null is used as the second parameter in this give, and non-NULL
+ * in the other gives for code coverage reasons. */
+ xSemaphoreGiveFromISR( xISRMutex, NULL );
+
+ /* Second give attempt should fail. */
+ configASSERT( xSemaphoreGiveFromISR( xISRMutex, &xHigherPriorityTaskWoken ) == pdFAIL );
+ }
+
+ if( xOkToGiveCountingSemaphore != pdFALSE )
+ {
+ xSemaphoreGiveFromISR( xISRCountingSemaphore, &xHigherPriorityTaskWoken );
+ }
+
+ xLastGiveTime = xTimeNow;
+ }
+
+ /* Remove compiler warnings about the value being set but not used. */
+ ( void ) xHigherPriorityTaskWoken;
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreInterruptSemaphoreTasksStillRunning( void )
{
-static uint32_t ulLastMasterLoopCounter = 0, ulLastCountingSemaphoreLoops = 0;
+ static uint32_t ulLastMasterLoopCounter = 0, ulLastCountingSemaphoreLoops = 0;
- /* If the demo tasks are running then it is expected that the loop counters
- will have changed since this function was last called. */
- if( ulLastMasterLoopCounter == ulMasterLoops )
- {
- xErrorDetected = pdTRUE;
- }
+ /* If the demo tasks are running then it is expected that the loop counters
+ * will have changed since this function was last called. */
+ if( ulLastMasterLoopCounter == ulMasterLoops )
+ {
+ xErrorDetected = pdTRUE;
+ }
- ulLastMasterLoopCounter = ulMasterLoops;
+ ulLastMasterLoopCounter = ulMasterLoops;
- if( ulLastCountingSemaphoreLoops == ulCountingSemaphoreLoops )
- {
- xErrorDetected = pdTRUE;
- }
+ if( ulLastCountingSemaphoreLoops == ulCountingSemaphoreLoops )
+ {
+ xErrorDetected = pdTRUE;
+ }
- ulLastCountingSemaphoreLoops = ulCountingSemaphoreLoops++;
+ ulLastCountingSemaphoreLoops = ulCountingSemaphoreLoops++;
- /* Errors detected in the task itself will have latched xErrorDetected
- to true. */
+ /* Errors detected in the task itself will have latched xErrorDetected
+ * to true. */
- return ( BaseType_t ) !xErrorDetected;
+ return ( BaseType_t ) !xErrorDetected;
}
-
-
diff --git a/Demo/Common/Minimal/MessageBufferAMP.c b/Demo/Common/Minimal/MessageBufferAMP.c
index 15ed82e12..9e6d0567e 100644
--- a/Demo/Common/Minimal/MessageBufferAMP.c
+++ b/Demo/Common/Minimal/MessageBufferAMP.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/*
@@ -69,22 +68,22 @@
#include "MessageBufferAMP.h"
/* Enough for 3 4 byte pointers, including the additional 4 bytes per message
-overhead of message buffers. */
-#define mbaCONTROL_MESSAGE_BUFFER_SIZE ( 24 )
+ * overhead of message buffers. */
+#define mbaCONTROL_MESSAGE_BUFFER_SIZE ( 24 )
/* Enough four 4 8 byte strings, plus the additional 4 bytes per message
-overhead of message buffers. */
-#define mbaTASK_MESSAGE_BUFFER_SIZE ( 60 )
+ * overhead of message buffers. */
+#define mbaTASK_MESSAGE_BUFFER_SIZE ( 60 )
/* The number of instances of prvCoreBTasks that are created. */
-#define mbaNUMBER_OF_CORE_B_TASKS 2
+#define mbaNUMBER_OF_CORE_B_TASKS 2
/* A block time of 0 simply means, don't block. */
-#define mbaDONT_BLOCK 0
+#define mbaDONT_BLOCK 0
/* Macro that mimics an interrupt service routine executing by simply calling
-the routine inline. */
-#define mbaGENERATE_CORE_B_INTERRUPT() prvCoreBInterruptHandler()
+ * the routine inline. */
+#define mbaGENERATE_CORE_B_INTERRUPT() prvCoreBInterruptHandler()
/*-----------------------------------------------------------*/
@@ -92,14 +91,14 @@ the routine inline. */
* Implementation of the task that, on a real dual core device, would run on
* core A and send message to tasks running on core B.
*/
-static void prvCoreATask( void *pvParameters );
+static void prvCoreATask( void * pvParameters );
/*
* Implementation of the task that, on a real dual core device, would run on
* core B and receive message from core A. The demo creates two instances of
* this task.
*/
-static void prvCoreBTasks( void *pvParameters );
+static void prvCoreBTasks( void * pvParameters );
/*
* The function that, on a real dual core device, would handle inter-core
@@ -113,218 +112,217 @@ static void prvCoreBInterruptHandler( void );
static MessageBufferHandle_t xCoreBMessageBuffers[ mbaNUMBER_OF_CORE_B_TASKS ];
/* The control message buffer. This is used to pass the handle of the message
-message buffer that holds application data into the core to core interrupt
-service routine. */
+ * message buffer that holds application data into the core to core interrupt
+ * service routine. */
static MessageBufferHandle_t xControlMessageBuffer;
/* Counters used to indicate to the check that the tasks are still executing. */
static uint32_t ulCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ];
/* Set to pdFALSE if any errors are detected. Used to inform the check task
-that something might be wrong. */
+ * that something might be wrong. */
BaseType_t xDemoStatus = pdPASS;
/*-----------------------------------------------------------*/
void vStartMessageBufferAMPTasks( configSTACK_DEPTH_TYPE xStackSize )
{
-BaseType_t x;
-
- xControlMessageBuffer = xMessageBufferCreate( mbaCONTROL_MESSAGE_BUFFER_SIZE );
-
- xTaskCreate( prvCoreATask, /* The function that implements the task. */
- "AMPCoreA", /* Human readable name for the task. */
- xStackSize, /* Stack size (in words!). */
- NULL, /* Task parameter is not used. */
- tskIDLE_PRIORITY, /* The priority at which the task is created. */
- NULL ); /* No use for the task handle. */
-
- for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
- {
- xCoreBMessageBuffers[ x ] = xMessageBufferCreate( mbaTASK_MESSAGE_BUFFER_SIZE );
- configASSERT( xCoreBMessageBuffers[ x ] );
-
- /* Pass the loop counter into the created task using the task's
- parameter. The task then uses the value as an index into the
- ulCycleCounters and xCoreBMessageBuffers arrays. */
- xTaskCreate( prvCoreBTasks,
- "AMPCoreB1",
- xStackSize,
- ( void * ) x,
- tskIDLE_PRIORITY + 1,
- NULL );
- }
+ BaseType_t x;
+
+ xControlMessageBuffer = xMessageBufferCreate( mbaCONTROL_MESSAGE_BUFFER_SIZE );
+
+ xTaskCreate( prvCoreATask, /* The function that implements the task. */
+ "AMPCoreA", /* Human readable name for the task. */
+ xStackSize, /* Stack size (in words!). */
+ NULL, /* Task parameter is not used. */
+ tskIDLE_PRIORITY, /* The priority at which the task is created. */
+ NULL ); /* No use for the task handle. */
+
+ for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
+ {
+ xCoreBMessageBuffers[ x ] = xMessageBufferCreate( mbaTASK_MESSAGE_BUFFER_SIZE );
+ configASSERT( xCoreBMessageBuffers[ x ] );
+
+ /* Pass the loop counter into the created task using the task's
+ * parameter. The task then uses the value as an index into the
+ * ulCycleCounters and xCoreBMessageBuffers arrays. */
+ xTaskCreate( prvCoreBTasks,
+ "AMPCoreB1",
+ xStackSize,
+ ( void * ) x,
+ tskIDLE_PRIORITY + 1,
+ NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvCoreATask( void *pvParameters )
+static void prvCoreATask( void * pvParameters )
{
-BaseType_t x;
-uint32_t ulNextValue = 0;
-const TickType_t xDelay = pdMS_TO_TICKS( 250 );
-char cString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */
-
- /* Remove warning about unused parameters. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Create the next string to send. The value is incremented on each
- loop iteration, and the length of the string changes as the number of
- digits in the value increases. */
- sprintf( cString, "%lu", ( unsigned long ) ulNextValue );
-
- /* Send the value from this (pseudo) Core A to the tasks on the (pseudo)
- Core B via the message buffers. This will result in sbSEND_COMPLETED()
- being executed, which in turn will write the handle of the message
- buffer written to into xControlMessageBuffer then generate an interrupt
- in core B. */
- for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
- {
- xMessageBufferSend( /* The message buffer to write to. */
- xCoreBMessageBuffers[ x ],
- /* The source of the data to send. */
- ( void * ) cString,
- /* The length of the data to send. */
- strlen( cString ),
- /* The block time, should the buffer be full. */
- mbaDONT_BLOCK );
- }
-
- /* Delay before repeating with a different and potentially different
- length string. */
- vTaskDelay( xDelay );
- ulNextValue++;
- }
+ BaseType_t x;
+ uint32_t ulNextValue = 0;
+ const TickType_t xDelay = pdMS_TO_TICKS( 250 );
+ char cString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */
+
+ /* Remove warning about unused parameters. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Create the next string to send. The value is incremented on each
+ * loop iteration, and the length of the string changes as the number of
+ * digits in the value increases. */
+ sprintf( cString, "%lu", ( unsigned long ) ulNextValue );
+
+ /* Send the value from this (pseudo) Core A to the tasks on the (pseudo)
+ * Core B via the message buffers. This will result in sbSEND_COMPLETED()
+ * being executed, which in turn will write the handle of the message
+ * buffer written to into xControlMessageBuffer then generate an interrupt
+ * in core B. */
+ for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
+ {
+ xMessageBufferSend( /* The message buffer to write to. */
+ xCoreBMessageBuffers[ x ],
+ /* The source of the data to send. */
+ ( void * ) cString,
+ /* The length of the data to send. */
+ strlen( cString ),
+ /* The block time, should the buffer be full. */
+ mbaDONT_BLOCK );
+ }
+
+ /* Delay before repeating with a different and potentially different
+ * length string. */
+ vTaskDelay( xDelay );
+ ulNextValue++;
+ }
}
/*-----------------------------------------------------------*/
-static void prvCoreBTasks( void *pvParameters )
+static void prvCoreBTasks( void * pvParameters )
{
-BaseType_t x;
-size_t xReceivedBytes;
-uint32_t ulNextValue = 0;
-char cExpectedString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */
-char cReceivedString[ 15 ];
-
- /* The index into the xCoreBMessageBuffers and ulLoopCounter arrays is
- passed into this task using the task's parameter. */
- x = ( BaseType_t ) pvParameters;
- configASSERT( x < mbaNUMBER_OF_CORE_B_TASKS );
-
- for( ;; )
- {
- /* Create the string that is expected to be received this time round. */
- sprintf( cExpectedString, "%lu", ( unsigned long ) ulNextValue );
-
- /* Wait to receive the next message from core A. */
- memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
- xReceivedBytes = xMessageBufferReceive( /* The message buffer to receive from. */
- xCoreBMessageBuffers[ x ],
- /* Location to store received data. */
- cReceivedString,
- /* Maximum number of bytes to receive. */
- sizeof( cReceivedString ),
- /* Ticks to wait if buffer is empty. */
- portMAX_DELAY );
-
- /* Check the number of bytes received was as expected. */
- configASSERT( xReceivedBytes == strlen( cExpectedString ) );
- ( void ) xReceivedBytes; /* Incase configASSERT() is not defined. */
-
- /* If the received string matches that expected then increment the loop
- counter so the check task knows this task is still running. */
- if( strcmp( cReceivedString, cExpectedString ) == 0 )
- {
- ( ulCycleCounters[ x ] )++;
- }
- else
- {
- xDemoStatus = pdFAIL;
- }
-
- /* Expect the next string in sequence the next time around. */
- ulNextValue++;
- }
+ BaseType_t x;
+ size_t xReceivedBytes;
+ uint32_t ulNextValue = 0;
+ char cExpectedString[ 15 ]; /* At least large enough to hold "4294967295\0" (0xffffffff). */
+ char cReceivedString[ 15 ];
+
+ /* The index into the xCoreBMessageBuffers and ulLoopCounter arrays is
+ * passed into this task using the task's parameter. */
+ x = ( BaseType_t ) pvParameters;
+ configASSERT( x < mbaNUMBER_OF_CORE_B_TASKS );
+
+ for( ; ; )
+ {
+ /* Create the string that is expected to be received this time round. */
+ sprintf( cExpectedString, "%lu", ( unsigned long ) ulNextValue );
+
+ /* Wait to receive the next message from core A. */
+ memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
+ xReceivedBytes = xMessageBufferReceive( /* The message buffer to receive from. */
+ xCoreBMessageBuffers[ x ],
+ /* Location to store received data. */
+ cReceivedString,
+ /* Maximum number of bytes to receive. */
+ sizeof( cReceivedString ),
+ /* Ticks to wait if buffer is empty. */
+ portMAX_DELAY );
+
+ /* Check the number of bytes received was as expected. */
+ configASSERT( xReceivedBytes == strlen( cExpectedString ) );
+ ( void ) xReceivedBytes; /* Incase configASSERT() is not defined. */
+
+ /* If the received string matches that expected then increment the loop
+ * counter so the check task knows this task is still running. */
+ if( strcmp( cReceivedString, cExpectedString ) == 0 )
+ {
+ ( ulCycleCounters[ x ] )++;
+ }
+ else
+ {
+ xDemoStatus = pdFAIL;
+ }
+
+ /* Expect the next string in sequence the next time around. */
+ ulNextValue++;
+ }
}
/*-----------------------------------------------------------*/
/* Called by the reimplementation of sbSEND_COMPLETED(), which can be defined
-as follows in FreeRTOSConfig.h:
-#define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer )
-*/
+ * as follows in FreeRTOSConfig.h:
+ #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer )
+ */
void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer )
{
-MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
-
- /* If sbSEND_COMPLETED() has been implemented as above, then this function
- is called from within xMessageBufferSend(). As this function also calls
- xMessageBufferSend() itself it is necessary to guard against a recursive
- call. If the message buffer just updated is the message buffer written to
- by this function, then this is a recursive call, and the function can just
- exit without taking further action. */
- if( xUpdatedBuffer != xControlMessageBuffer )
- {
- /* Use xControlMessageBuffer to pass the handle of the message buffer
- written to by core A to the interrupt handler about to be generated in
- core B. */
- xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK );
-
- /* This is where the interrupt would be generated. In this case it is
- not a genuine interrupt handler that executes, just a standard function
- call. */
- mbaGENERATE_CORE_B_INTERRUPT();
- }
+ MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
+
+ /* If sbSEND_COMPLETED() has been implemented as above, then this function
+ * is called from within xMessageBufferSend(). As this function also calls
+ * xMessageBufferSend() itself it is necessary to guard against a recursive
+ * call. If the message buffer just updated is the message buffer written to
+ * by this function, then this is a recursive call, and the function can just
+ * exit without taking further action. */
+ if( xUpdatedBuffer != xControlMessageBuffer )
+ {
+ /* Use xControlMessageBuffer to pass the handle of the message buffer
+ * written to by core A to the interrupt handler about to be generated in
+ * core B. */
+ xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK );
+
+ /* This is where the interrupt would be generated. In this case it is
+ * not a genuine interrupt handler that executes, just a standard function
+ * call. */
+ mbaGENERATE_CORE_B_INTERRUPT();
+ }
}
/*-----------------------------------------------------------*/
/* Handler for the interrupts that are triggered on core A but execute on core
-B. */
+ * B. */
static void prvCoreBInterruptHandler( void )
{
-MessageBufferHandle_t xUpdatedMessageBuffer;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-
- /* xControlMessageBuffer contains the handle of the message buffer that
- contains data. */
- if( xMessageBufferReceive( xControlMessageBuffer,
- &xUpdatedMessageBuffer,
- sizeof( xUpdatedMessageBuffer ),
- mbaDONT_BLOCK ) == sizeof( xUpdatedMessageBuffer ) )
- {
- /* Call the API function that sends a notification to any task that is
- blocked on the xUpdatedMessageBuffer message buffer waiting for data to
- arrive. */
- xMessageBufferSendCompletedFromISR( xUpdatedMessageBuffer, &xHigherPriorityTaskWoken );
- }
-
- /* Normal FreeRTOS yield from interrupt semantics, where
- xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to
- pdTRUE if the interrupt safe API unblocks a task that has a priority above
- that of the currently executing task. */
- portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ MessageBufferHandle_t xUpdatedMessageBuffer;
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+ /* xControlMessageBuffer contains the handle of the message buffer that
+ * contains data. */
+ if( xMessageBufferReceive( xControlMessageBuffer,
+ &xUpdatedMessageBuffer,
+ sizeof( xUpdatedMessageBuffer ),
+ mbaDONT_BLOCK ) == sizeof( xUpdatedMessageBuffer ) )
+ {
+ /* Call the API function that sends a notification to any task that is
+ * blocked on the xUpdatedMessageBuffer message buffer waiting for data to
+ * arrive. */
+ xMessageBufferSendCompletedFromISR( xUpdatedMessageBuffer, &xHigherPriorityTaskWoken );
+ }
+
+ /* Normal FreeRTOS yield from interrupt semantics, where
+ * xHigherPriorityTaskWoken is initialized to pdFALSE and will then get set to
+ * pdTRUE if the interrupt safe API unblocks a task that has a priority above
+ * that of the currently executing task. */
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
BaseType_t xAreMessageBufferAMPTasksStillRunning( void )
{
-static uint32_t ulLastCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ] = { 0 };
-BaseType_t x;
-
- /* Called by the check task to determine the health status of the tasks
- implemented in this demo. */
- for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
- {
- if( ulLastCycleCounters[ x ] == ulCycleCounters[ x ] )
- {
- xDemoStatus = pdFAIL;
- }
- else
- {
- ulLastCycleCounters[ x ] = ulCycleCounters[ x ];
- }
- }
-
- return xDemoStatus;
+ static uint32_t ulLastCycleCounters[ mbaNUMBER_OF_CORE_B_TASKS ] = { 0 };
+ BaseType_t x;
+
+ /* Called by the check task to determine the health status of the tasks
+ * implemented in this demo. */
+ for( x = 0; x < mbaNUMBER_OF_CORE_B_TASKS; x++ )
+ {
+ if( ulLastCycleCounters[ x ] == ulCycleCounters[ x ] )
+ {
+ xDemoStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastCycleCounters[ x ] = ulCycleCounters[ x ];
+ }
+ }
+
+ return xDemoStatus;
}
-
diff --git a/Demo/Common/Minimal/MessageBufferDemo.c b/Demo/Common/Minimal/MessageBufferDemo.c
index 8a977eae4..4bd679c8e 100644
--- a/Demo/Common/Minimal/MessageBufferDemo.c
+++ b/Demo/Common/Minimal/MessageBufferDemo.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -38,29 +38,29 @@
#include "MessageBufferDemo.h"
/* The number of bytes of storage in the message buffers used in this test. */
-#define mbMESSAGE_BUFFER_LENGTH_BYTES ( ( size_t ) 50 )
+#define mbMESSAGE_BUFFER_LENGTH_BYTES ( ( size_t ) 50 )
/* The number of additional bytes used to store the length of each message. */
-#define mbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+#define mbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
/* Start and end ASCII characters used in messages sent to the buffers. */
-#define mbASCII_SPACE 32
-#define mbASCII_TILDA 126
+#define mbASCII_SPACE 32
+#define mbASCII_TILDA 126
/* Defines the number of tasks to create in this test and demo. */
-#define mbNUMBER_OF_ECHO_CLIENTS ( 2 )
-#define mbNUMBER_OF_SENDER_TASKS ( 2 )
+#define mbNUMBER_OF_ECHO_CLIENTS ( 2 )
+#define mbNUMBER_OF_SENDER_TASKS ( 2 )
/* Priority of the test tasks. The send and receive go from low to high
-priority tasks, and from high to low priority tasks. */
-#define mbLOWER_PRIORITY ( tskIDLE_PRIORITY )
-#define mbHIGHER_PRIORITY ( tskIDLE_PRIORITY + 1 )
+ * priority tasks, and from high to low priority tasks. */
+#define mbLOWER_PRIORITY ( tskIDLE_PRIORITY )
+#define mbHIGHER_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* Block times used when sending and receiving from the message buffers. */
-#define mbRX_TX_BLOCK_TIME pdMS_TO_TICKS( 175UL )
+#define mbRX_TX_BLOCK_TIME pdMS_TO_TICKS( 175UL )
/* A block time of 0 means "don't block". */
-#define mbDONT_BLOCK ( 0 )
+#define mbDONT_BLOCK ( 0 )
/*-----------------------------------------------------------*/
@@ -75,797 +75,898 @@ static void prvSingleTaskTests( MessageBufferHandle_t xMessageBuffer );
* message back to the echo client which, checks it receives exactly what it
* sent.
*/
-static void prvEchoClient( void *pvParameters );
-static void prvEchoServer( void *pvParameters );
+static void prvEchoClient( void * pvParameters );
+static void prvEchoServer( void * pvParameters );
/*
* Tasks that send and receive to a message buffer at a low priority and without
* blocking, so the send and receive functions interleave in time as the tasks
* are switched in and out.
*/
-static void prvNonBlockingReceiverTask( void *pvParameters );
-static void prvNonBlockingSenderTask( void *pvParameters );
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- /* This file tests both statically and dynamically allocated message buffers.
- Allocate the structures and buffers to be used by the statically allocated
- objects, which get used in the echo tests. */
- static void prvReceiverTask( void *pvParameters );
- static void prvSenderTask( void *pvParameters );
-
- static StaticMessageBuffer_t xStaticMessageBuffers[ mbNUMBER_OF_ECHO_CLIENTS ];
- static uint8_t ucBufferStorage[ mbNUMBER_OF_SENDER_TASKS ][ mbMESSAGE_BUFFER_LENGTH_BYTES + 1 ];
- static uint32_t ulSenderLoopCounters[ mbNUMBER_OF_SENDER_TASKS ] = { 0 };
+static void prvNonBlockingReceiverTask( void * pvParameters );
+static void prvNonBlockingSenderTask( void * pvParameters );
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+/* This file tests both statically and dynamically allocated message buffers.
+ * Allocate the structures and buffers to be used by the statically allocated
+ * objects, which get used in the echo tests. */
+ static void prvReceiverTask( void * pvParameters );
+ static void prvSenderTask( void * pvParameters );
+
+ static StaticMessageBuffer_t xStaticMessageBuffers[ mbNUMBER_OF_ECHO_CLIENTS ];
+ static uint8_t ucBufferStorage[ mbNUMBER_OF_SENDER_TASKS ][ mbMESSAGE_BUFFER_LENGTH_BYTES + 1 ];
+ static uint32_t ulSenderLoopCounters[ mbNUMBER_OF_SENDER_TASKS ] = { 0 };
#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+#if ( configRUN_ADDITIONAL_TESTS == 1 )
+ #define mbCOHERENCE_TEST_BUFFER_SIZE 20
+ #define mbCOHERENCE_TEST_BYTES_WRITTEN 5
+ #define mbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+ #define mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING ( mbCOHERENCE_TEST_BUFFER_SIZE - ( mbCOHERENCE_TEST_BYTES_WRITTEN + mbBYTES_TO_STORE_MESSAGE_LENGTH ) )
+
+ static void prvSpaceAvailableCoherenceActor( void * pvParameters );
+ static void prvSpaceAvailableCoherenceTester( void * pvParameters );
+ static MessageBufferHandle_t xCoherenceTestMessageBuffer = NULL;
+
+ static uint32_t ulSizeCoherencyTestCycles = 0UL;
+#endif /* if ( configRUN_ADDITIONAL_TESTS == 1 ) */
+
/*-----------------------------------------------------------*/
/* The buffers used by the echo client and server tasks. */
typedef struct ECHO_MESSAGE_BUFFERS
{
- /* Handles to the data structures that describe the message buffers. */
- MessageBufferHandle_t xEchoClientBuffer;
- MessageBufferHandle_t xEchoServerBuffer;
+ /* Handles to the data structures that describe the message buffers. */
+ MessageBufferHandle_t xEchoClientBuffer;
+ MessageBufferHandle_t xEchoServerBuffer;
} EchoMessageBuffers_t;
static uint32_t ulEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
/* The non-blocking tasks monitor their operation, and if no errors have been
-found, increment ulNonBlockingRxCounter. xAreMessageBufferTasksStillRunning()
-then checks ulNonBlockingRxCounter and only returns pdPASS if
-ulNonBlockingRxCounter is still incrementing. */
+ * found, increment ulNonBlockingRxCounter. xAreMessageBufferTasksStillRunning()
+ * then checks ulNonBlockingRxCounter and only returns pdPASS if
+ * ulNonBlockingRxCounter is still incrementing. */
static uint32_t ulNonBlockingRxCounter = 0;
/* A message that is longer than the buffer, parts of which are written to the
-message buffer to test writing different lengths at different offsets. */
-static const char *pc55ByteString = "One two three four five six seven eight nine ten eleve";
+ * message buffer to test writing different lengths at different offsets. */
+static const char * pc55ByteString = "One two three four five six seven eight nine ten eleve";
/* Remember the required stack size so tasks can be created at run time (after
-initialisation time. */
+ * initialisation time. */
static configSTACK_DEPTH_TYPE xBlockingStackSize = 0;
/*-----------------------------------------------------------*/
-void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize )
+void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize )
{
-MessageBufferHandle_t xMessageBuffer;
-
-#ifndef configMESSAGE_BUFFER_BLOCK_TASK_STACK_SIZE
- xBlockingStackSize = ( xStackSize + ( xStackSize >> 1U ) );
-#else
- xBlockingStackSize = configMESSAGE_BUFFER_BLOCK_TASK_STACK_SIZE;
-#endif
-
- /* The echo servers sets up the message buffers before creating the echo
- client tasks. One set of tasks has the server as the higher priority, and
- the other has the client as the higher priority. */
- xTaskCreate( prvEchoServer, "1EchoServer", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL );
- xTaskCreate( prvEchoServer, "2EchoServer", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL );
-
- /* The non blocking tasks run continuously and will interleave with each
- other, so must be created at the lowest priority. The message buffer they
- use is created and passed in using the task's parameter. */
- xMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
- xTaskCreate( prvNonBlockingReceiverTask, "NonBlkRx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL );
- xTaskCreate( prvNonBlockingSenderTask, "NonBlkTx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL );
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* The sender tasks set up the message buffers before creating the
- receiver tasks. Priorities must be 0 and 1 as the priority is used to
- index into the xStaticMessageBuffers and ucBufferStorage arrays. */
- xTaskCreate( prvSenderTask, "1Sender", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL );
- xTaskCreate( prvSenderTask, "2Sender", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL );
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ MessageBufferHandle_t xMessageBuffer;
+
+ #ifndef configMESSAGE_BUFFER_BLOCK_TASK_STACK_SIZE
+ xBlockingStackSize = ( xStackSize + ( xStackSize >> 1U ) );
+ #else
+ xBlockingStackSize = configMESSAGE_BUFFER_BLOCK_TASK_STACK_SIZE;
+ #endif
+
+ /* The echo servers sets up the message buffers before creating the echo
+ * client tasks. One set of tasks has the server as the higher priority, and
+ * the other has the client as the higher priority. */
+ xTaskCreate( prvEchoServer, "1EchoServer", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL );
+ xTaskCreate( prvEchoServer, "2EchoServer", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL );
+
+ /* The non blocking tasks run continuously and will interleave with each
+ * other, so must be created at the lowest priority. The message buffer they
+ * use is created and passed in using the task's parameter. */
+ xMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ xTaskCreate( prvNonBlockingReceiverTask, "NonBlkRx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvNonBlockingSenderTask, "NonBlkTx", xStackSize, ( void * ) xMessageBuffer, tskIDLE_PRIORITY, NULL );
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ /* The sender tasks set up the message buffers before creating the
+ * receiver tasks. Priorities must be 0 and 1 as the priority is used to
+ * index into the xStaticMessageBuffers and ucBufferStorage arrays. */
+ xTaskCreate( prvSenderTask, "1Sender", xBlockingStackSize, NULL, mbHIGHER_PRIORITY, NULL );
+ xTaskCreate( prvSenderTask, "2Sender", xBlockingStackSize, NULL, mbLOWER_PRIORITY, NULL );
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ #if ( configRUN_ADDITIONAL_TESTS == 1 )
+ {
+ xCoherenceTestMessageBuffer = xMessageBufferCreate( mbCOHERENCE_TEST_BUFFER_SIZE );
+ configASSERT( xCoherenceTestMessageBuffer );
+
+ xTaskCreate( prvSpaceAvailableCoherenceActor, "mbsanity1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvSpaceAvailableCoherenceTester, "mbsanity2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ }
+ #endif
}
/*-----------------------------------------------------------*/
static void prvSingleTaskTests( MessageBufferHandle_t xMessageBuffer )
{
-size_t xReturned, xItem, xExpectedSpace, xNextLength;
-const size_t xMax6ByteMessages = mbMESSAGE_BUFFER_LENGTH_BYTES / ( 6 + mbBYTES_TO_STORE_MESSAGE_LENGTH );
-const size_t x6ByteLength = 6, x17ByteLength = 17;
-uint8_t *pucFullBuffer, *pucData, *pucReadData;
-TickType_t xTimeBeforeCall, xTimeAfterCall;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 25 ), xAllowableMargin = pdMS_TO_TICKS( 3 );
-UBaseType_t uxOriginalPriority;
-
- /* Remove warning in case configASSERT() is not defined. */
- ( void ) xAllowableMargin;
-
- /* To minimise stack and heap usage a full size buffer is allocated from
- the heap, then buffers which hold smaller amounts of data are overlayed
- with the larger buffer - just make sure not to use both at once!. */
- pucFullBuffer = pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
- configASSERT( pucFullBuffer );
-
- pucData = pucFullBuffer;
- pucReadData = pucData + x17ByteLength;
-
- /* Nothing has been added or removed yet, so expect the free space to be
- exactly as created and the length of the next message to be 0. */
- xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
- configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
- configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == 0 );
- /* In case configASSERT() is not define. */
- ( void ) xExpectedSpace;
- ( void ) xNextLength;
-
- /* Try sending more bytes than possible, first using the FromISR version, then
- with an infinite block time to ensure this task does not lock up. */
- xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, mbMESSAGE_BUFFER_LENGTH_BYTES + sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ), NULL );
- configASSERT( xReturned == ( size_t ) 0 );
- /* In case configASSERT() is not defined. */
- ( void ) xReturned;
- xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, mbMESSAGE_BUFFER_LENGTH_BYTES + sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ), portMAX_DELAY );
- configASSERT( xReturned == ( size_t ) 0 );
- /* In case configASSERT() is not defined. */
- ( void ) xReturned;
-
- /* The buffer is 50 bytes long. When an item is added to the buffer an
- additional 4 bytes are added to hold the item's size. That means adding
- 6 bytes to the buffer will actually add 10 bytes to the buffer. Therefore,
- with a 50 byte buffer, a maximum of 5 6 bytes items can be added before the
- buffer is completely full. NOTE: The numbers in this paragraph assume
- sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) == 4. */
- for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
- {
- configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdFALSE );
-
- /* Generate recognisable data to write to the buffer. This is just
- ascii characters that shows which loop iteration the data was written
- in. The 'FromISR' version is used to give it some exercise as a block
- time is not used. That requires the call to be in a critical section
- so this code can also run on FreeRTOS ports that do not support
- interrupt nesting (and so don't have interrupt safe critical
- sections).*/
- memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
- taskENTER_CRITICAL();
- {
- xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, x6ByteLength, NULL );
- }
- taskEXIT_CRITICAL();
- configASSERT( xReturned == x6ByteLength );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* The space in the buffer will have reduced by the amount of user data
- written into the buffer and the amount of space used to store the length
- of the data written into the buffer. */
- xExpectedSpace -= ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
- xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
- configASSERT( xReturned == xExpectedSpace );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Only 6 byte messages are written. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == x6ByteLength );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
- }
-
- /* Now the buffer should be full, and attempting to add anything will should
- fail. */
- configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdTRUE );
- xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), mbDONT_BLOCK );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Adding with a timeout should also fail after the appropriate time. The
- priority is temporarily boosted in this part of the test to keep the
- allowable margin to a minimum. */
- uxOriginalPriority = uxTaskPriorityGet( NULL );
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
- xTimeBeforeCall = xTaskGetTickCount();
- xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime );
- xTimeAfterCall = xTaskGetTickCount();
- vTaskPrioritySet( NULL, uxOriginalPriority );
- configASSERT( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime );
- configASSERT( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) xTimeBeforeCall;
- ( void ) xTimeAfterCall;
-
-
- /* The buffer is now full of data in the form "000000", "111111", etc. Make
- sure the data is read out as expected. */
- for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
- {
- /* Generate the data that is expected to be read out for this loop
- iteration. */
- memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
-
- /* Try reading the message into a buffer that is too small. The message
- should remain in the buffer. */
- xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength - 1, mbDONT_BLOCK );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Should still be at least one 6 byte message still available. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == x6ByteLength );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
-
- /* Read the next 6 bytes out. The 'FromISR' version is used to give it
- some exercise as a block time is not used. THa requires the code to be
- in a critical section so this test can be run with FreeRTOS ports that
- do not support interrupt nesting (and therefore don't have interrupt
- safe critical sections). */
- taskENTER_CRITICAL();
- {
- xReturned = xMessageBufferReceiveFromISR( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, NULL );
- }
- taskEXIT_CRITICAL();
- configASSERT( xReturned == x6ByteLength );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Does the data read out match that expected? */
- configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 );
-
- /* The space in the buffer will have increased by the amount of user
- data read from into the buffer and the amount of space used to store the
- length of the data read into the buffer. */
- xExpectedSpace += ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
- xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
- configASSERT( xReturned == xExpectedSpace );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- }
-
- /* The buffer should be empty again. */
- configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
- xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
- configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
- ( void ) xExpectedSpace; /* In case configASSERT() is not defined. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == 0 );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
-
-
- /* Reading with a timeout should also fail after the appropriate time. The
- priority is temporarily boosted in this part of the test to keep the
- allowable margin to a minimum. */
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
- xTimeBeforeCall = xTaskGetTickCount();
- xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime );
- xTimeAfterCall = xTaskGetTickCount();
- vTaskPrioritySet( NULL, uxOriginalPriority );
- configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime );
- configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) xTimeBeforeCall;
- ( void ) xTimeAfterCall;
-
-
- /* In the next loop 17 bytes are written to then read out on each iteration.
- The expected length variable is always used after 17 bytes have been written
- into the buffer - the length of the message is also written, making a total
- of 21 bytes consumed for each 17 byte message. */
- xExpectedSpace = mbMESSAGE_BUFFER_LENGTH_BYTES - ( x17ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
-
- /* Reading and writing 17 bytes at a time will result in 21 bytes being
- written into the buffer, and as 50 is not divisible by 21, writing multiple
- times will cause the data to wrap in the buffer.*/
- for( xItem = 0; xItem < 100; xItem++ )
- {
- /* Generate recognisable data to write to the queue. This is just
- ascii characters that shows which loop iteration the data was written
- in. */
- memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength );
- xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, x17ByteLength, mbDONT_BLOCK );
- configASSERT( xReturned == x17ByteLength );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Only 17 byte messages are written. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == x17ByteLength );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
-
- /* The space in the buffer will have reduced by the amount of user data
- written into the buffer and the amount of space used to store the length
- of the data written into the buffer. */
- xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
- configASSERT( xReturned == xExpectedSpace );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Read the 17 bytes out again. */
- xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x17ByteLength, mbDONT_BLOCK );
- configASSERT( xReturned == x17ByteLength );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Does the data read out match that expected? */
- configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 );
-
- /* Don't expect any messages to be available as the data was read out
- again. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == 0 );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
- }
-
- /* The buffer should be empty again. */
- configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
- xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
- configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
-
- /* Cannot write within sizeof( size_t ) (assumed to be 4 bytes in this test)
- bytes of the full 50 bytes, as that would not leave space for the four bytes
- taken by the data length. */
- xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES, mbDONT_BLOCK );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- #ifndef configMESSAGE_BUFFER_LENGTH_TYPE
- {
- /* The following will fail if configMESSAGE_BUFFER_LENGTH_TYPE is set
- to a non 32-bit type. */
- xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 1, mbDONT_BLOCK );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 2, mbDONT_BLOCK );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 3, mbDONT_BLOCK );
- configASSERT( xReturned == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- }
- #endif
-
- /* Don't expect any messages to be available as the above were too large to
- get written. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == 0 );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
-
- /* Can write mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) bytes though. */
- xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK );
- configASSERT( xReturned == mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
- configASSERT( xNextLength == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) );
- ( void ) xNextLength; /* In case configASSERT() is not defined. */
- xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucFullBuffer, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK );
- configASSERT( xReturned == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- configASSERT( memcmp( ( const void * ) pucFullBuffer, pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) == 0 );
-
- /* Clean up. */
- vPortFree( pucFullBuffer );
- xMessageBufferReset( xMessageBuffer );
+ size_t xReturned, xItem, xExpectedSpace, xNextLength;
+ const size_t xMax6ByteMessages = mbMESSAGE_BUFFER_LENGTH_BYTES / ( 6 + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+ const size_t x6ByteLength = 6, x17ByteLength = 17;
+ uint8_t * pucFullBuffer, * pucData, * pucReadData;
+ TickType_t xTimeBeforeCall, xTimeAfterCall;
+ const TickType_t xBlockTime = pdMS_TO_TICKS( 25 ), xAllowableMargin = pdMS_TO_TICKS( 3 );
+ UBaseType_t uxOriginalPriority;
+
+ /* Remove warning in case configASSERT() is not defined. */
+ ( void ) xAllowableMargin;
+
+ /* To minimise stack and heap usage a full size buffer is allocated from
+ * the heap, then buffers which hold smaller amounts of data are overlayed
+ * with the larger buffer - just make sure not to use both at once!. */
+ pucFullBuffer = pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ configASSERT( pucFullBuffer );
+
+ pucData = pucFullBuffer;
+ pucReadData = pucData + x17ByteLength;
+
+ /* Nothing has been added or removed yet, so expect the free space to be
+ * exactly as created and the length of the next message to be 0. */
+ xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
+ configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
+ configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == 0 );
+ /* In case configASSERT() is not define. */
+ ( void ) xExpectedSpace;
+ ( void ) xNextLength;
+
+ /* Try sending more bytes than possible, first using the FromISR version, then
+ * with an infinite block time to ensure this task does not lock up. */
+ xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, mbMESSAGE_BUFFER_LENGTH_BYTES + sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ), NULL );
+ configASSERT( xReturned == ( size_t ) 0 );
+ /* In case configASSERT() is not defined. */
+ ( void ) xReturned;
+ xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, mbMESSAGE_BUFFER_LENGTH_BYTES + sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ), portMAX_DELAY );
+ configASSERT( xReturned == ( size_t ) 0 );
+ /* In case configASSERT() is not defined. */
+ ( void ) xReturned;
+
+ /* The buffer is 50 bytes long. When an item is added to the buffer an
+ * additional 4 bytes are added to hold the item's size. That means adding
+ * 6 bytes to the buffer will actually add 10 bytes to the buffer. Therefore,
+ * with a 50 byte buffer, a maximum of 5 6 bytes items can be added before the
+ * buffer is completely full. NOTE: The numbers in this paragraph assume
+ * sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) == 4. */
+ for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+ {
+ configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdFALSE );
+
+ /* Generate recognisable data to write to the buffer. This is just
+ * ascii characters that shows which loop iteration the data was written
+ * in. The 'FromISR' version is used to give it some exercise as a block
+ * time is not used. That requires the call to be in a critical section
+ * so this code can also run on FreeRTOS ports that do not support
+ * interrupt nesting (and so don't have interrupt safe critical
+ * sections).*/
+ memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+ taskENTER_CRITICAL();
+ {
+ xReturned = xMessageBufferSendFromISR( xMessageBuffer, ( void * ) pucData, x6ByteLength, NULL );
+ }
+ taskEXIT_CRITICAL();
+ configASSERT( xReturned == x6ByteLength );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* The space in the buffer will have reduced by the amount of user data
+ * written into the buffer and the amount of space used to store the length
+ * of the data written into the buffer. */
+ xExpectedSpace -= ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+ xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
+ configASSERT( xReturned == xExpectedSpace );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Only 6 byte messages are written. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == x6ByteLength );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+ }
+
+ /* Now the buffer should be full, and attempting to add anything will should
+ * fail. */
+ configASSERT( xMessageBufferIsFull( xMessageBuffer ) == pdTRUE );
+ xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), mbDONT_BLOCK );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Adding with a timeout should also fail after the appropriate time. The
+ * priority is temporarily boosted in this part of the test to keep the
+ * allowable margin to a minimum. */
+ uxOriginalPriority = uxTaskPriorityGet( NULL );
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+ xTimeBeforeCall = xTaskGetTickCount();
+ xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime );
+ xTimeAfterCall = xTaskGetTickCount();
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+ configASSERT( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime );
+ configASSERT( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) xTimeBeforeCall;
+ ( void ) xTimeAfterCall;
+
+ /* The buffer is now full of data in the form "000000", "111111", etc. Make
+ * sure the data is read out as expected. */
+ for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+ {
+ /* Generate the data that is expected to be read out for this loop
+ * iteration. */
+ memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+
+ /* Try reading the message into a buffer that is too small. The message
+ * should remain in the buffer. */
+ xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength - 1, mbDONT_BLOCK );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Should still be at least one 6 byte message still available. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == x6ByteLength );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+ /* Read the next 6 bytes out. The 'FromISR' version is used to give it
+ * some exercise as a block time is not used. THa requires the code to be
+ * in a critical section so this test can be run with FreeRTOS ports that
+ * do not support interrupt nesting (and therefore don't have interrupt
+ * safe critical sections). */
+ taskENTER_CRITICAL();
+ {
+ xReturned = xMessageBufferReceiveFromISR( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, NULL );
+ }
+ taskEXIT_CRITICAL();
+ configASSERT( xReturned == x6ByteLength );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Does the data read out match that expected? */
+ configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 );
+
+ /* The space in the buffer will have increased by the amount of user
+ * data read from into the buffer and the amount of space used to store the
+ * length of the data read into the buffer. */
+ xExpectedSpace += ( x6ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+ xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
+ configASSERT( xReturned == xExpectedSpace );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ }
+
+ /* The buffer should be empty again. */
+ configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
+ xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
+ configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
+ ( void ) xExpectedSpace; /* In case configASSERT() is not defined. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == 0 );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+
+ /* Reading with a timeout should also fail after the appropriate time. The
+ * priority is temporarily boosted in this part of the test to keep the
+ * allowable margin to a minimum. */
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+ xTimeBeforeCall = xTaskGetTickCount();
+ xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime );
+ xTimeAfterCall = xTaskGetTickCount();
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+ configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) >= xBlockTime );
+ configASSERT( ( xTimeAfterCall - xTimeBeforeCall ) < ( xBlockTime + xAllowableMargin ) );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) xTimeBeforeCall;
+ ( void ) xTimeAfterCall;
+
+
+ /* In the next loop 17 bytes are written to then read out on each iteration.
+ * The expected length variable is always used after 17 bytes have been written
+ * into the buffer - the length of the message is also written, making a total
+ * of 21 bytes consumed for each 17 byte message. */
+ xExpectedSpace = mbMESSAGE_BUFFER_LENGTH_BYTES - ( x17ByteLength + mbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+ /* Reading and writing 17 bytes at a time will result in 21 bytes being
+ * written into the buffer, and as 50 is not divisible by 21, writing multiple
+ * times will cause the data to wrap in the buffer.*/
+ for( xItem = 0; xItem < 100; xItem++ )
+ {
+ /* Generate recognisable data to write to the queue. This is just
+ * ascii characters that shows which loop iteration the data was written
+ * in. */
+ memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength );
+ xReturned = xMessageBufferSend( xMessageBuffer, ( void * ) pucData, x17ByteLength, mbDONT_BLOCK );
+ configASSERT( xReturned == x17ByteLength );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Only 17 byte messages are written. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == x17ByteLength );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+ /* The space in the buffer will have reduced by the amount of user data
+ * written into the buffer and the amount of space used to store the length
+ * of the data written into the buffer. */
+ xReturned = xMessageBufferSpaceAvailable( xMessageBuffer );
+ configASSERT( xReturned == xExpectedSpace );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Read the 17 bytes out again. */
+ xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucReadData, x17ByteLength, mbDONT_BLOCK );
+ configASSERT( xReturned == x17ByteLength );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Does the data read out match that expected? */
+ configASSERT( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 );
+
+ /* Don't expect any messages to be available as the data was read out
+ * again. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == 0 );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+ }
+
+ /* The buffer should be empty again. */
+ configASSERT( xMessageBufferIsEmpty( xMessageBuffer ) == pdTRUE );
+ xExpectedSpace = xMessageBufferSpaceAvailable( xMessageBuffer );
+ configASSERT( xExpectedSpace == mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+ /* Cannot write within sizeof( size_t ) (assumed to be 4 bytes in this test)
+ * bytes of the full 50 bytes, as that would not leave space for the four bytes
+ * taken by the data length. */
+ xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES, mbDONT_BLOCK );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ #ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+ {
+ /* The following will fail if configMESSAGE_BUFFER_LENGTH_TYPE is set
+ * to a non 32-bit type. */
+ xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 1, mbDONT_BLOCK );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 2, mbDONT_BLOCK );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - 3, mbDONT_BLOCK );
+ configASSERT( xReturned == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ }
+ #endif /* ifndef configMESSAGE_BUFFER_LENGTH_TYPE */
+
+ /* Don't expect any messages to be available as the above were too large to
+ * get written. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == 0 );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+
+ /* Can write mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) bytes though. */
+ xReturned = xMessageBufferSend( xMessageBuffer, ( const void * ) pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK );
+ configASSERT( xReturned == mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ xNextLength = xMessageBufferNextLengthBytes( xMessageBuffer );
+ configASSERT( xNextLength == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) );
+ ( void ) xNextLength; /* In case configASSERT() is not defined. */
+ xReturned = xMessageBufferReceive( xMessageBuffer, ( void * ) pucFullBuffer, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ), mbDONT_BLOCK );
+ configASSERT( xReturned == ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ configASSERT( memcmp( ( const void * ) pucFullBuffer, pc55ByteString, mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) == 0 );
+
+ /* Clean up. */
+ vPortFree( pucFullBuffer );
+ xMessageBufferReset( xMessageBuffer );
}
/*-----------------------------------------------------------*/
-static void prvNonBlockingSenderTask( void *pvParameters )
+static void prvNonBlockingSenderTask( void * pvParameters )
{
-MessageBufferHandle_t xMessageBuffer;
-int32_t iDataToSend = 0;
-size_t xStringLength;
-const int32_t iMaxValue = 1500;
-char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
-
- /* In this case the message buffer has already been created and is passed
- into the task using the task's parameter. */
- xMessageBuffer = ( MessageBufferHandle_t ) pvParameters;
-
- /* Create a string from an incrementing number. The length of the
- string will increase and decrease as the value of the number increases
- then overflows. */
- memset( cTxString, 0x00, sizeof( cTxString ) );
- sprintf( cTxString, "%d", ( int ) iDataToSend );
- xStringLength = strlen( cTxString );
-
- for( ;; )
- {
- /* Doesn't block so calls can interleave with the non-blocking
- receives performed by prvNonBlockingReceiverTask(). */
- if( xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), mbDONT_BLOCK ) == xStringLength )
- {
- iDataToSend++;
-
- if( iDataToSend > iMaxValue )
- {
- /* The value sent is reset back to 0 to ensure the string being sent
- does not remain at the same length for too long. */
- iDataToSend = 0;
- }
-
- /* Create the next string. */
- memset( cTxString, 0x00, sizeof( cTxString ) );
- sprintf( cTxString, "%d", ( int ) iDataToSend );
- xStringLength = strlen( cTxString );
- }
- }
+ MessageBufferHandle_t xMessageBuffer;
+ int32_t iDataToSend = 0;
+ size_t xStringLength;
+ const int32_t iMaxValue = 1500;
+ char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
+
+ /* In this case the message buffer has already been created and is passed
+ * into the task using the task's parameter. */
+
+ xMessageBuffer = ( MessageBufferHandle_t ) pvParameters;
+
+ /* Create a string from an incrementing number. The length of the
+ * string will increase and decrease as the value of the number increases
+ * then overflows. */
+ memset( cTxString, 0x00, sizeof( cTxString ) );
+ sprintf( cTxString, "%d", ( int ) iDataToSend );
+ xStringLength = strlen( cTxString );
+
+ for( ; ; )
+ {
+ /* Doesn't block so calls can interleave with the non-blocking
+ * receives performed by prvNonBlockingReceiverTask(). */
+ if( xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), mbDONT_BLOCK ) == xStringLength )
+ {
+ iDataToSend++;
+
+ if( iDataToSend > iMaxValue )
+ {
+ /* The value sent is reset back to 0 to ensure the string being sent
+ * does not remain at the same length for too long. */
+ iDataToSend = 0;
+ }
+
+ /* Create the next string. */
+ memset( cTxString, 0x00, sizeof( cTxString ) );
+ sprintf( cTxString, "%d", ( int ) iDataToSend );
+ xStringLength = strlen( cTxString );
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvNonBlockingReceiverTask( void *pvParameters )
+static void prvNonBlockingReceiverTask( void * pvParameters )
{
-MessageBufferHandle_t xMessageBuffer;
-BaseType_t xNonBlockingReceiveError = pdFALSE;
-int32_t iDataToSend = 0;
-size_t xStringLength, xReceiveLength;
-const int32_t iMaxValue = 1500;
-char cExpectedString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
-char cRxString[ 12 ];
-
- /* In this case the message buffer has already been created and is passed
- into the task using the task's parameter. */
- xMessageBuffer = ( MessageBufferHandle_t ) pvParameters;
-
- /* Create a string from an incrementing number. The length of the
- string will increase and decrease as the value of the number increases
- then overflows. This should always match the string sent to the buffer by
- the non blocking sender task. */
- memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
- memset( cRxString, 0x00, sizeof( cRxString ) );
- sprintf( cExpectedString, "%d", ( int ) iDataToSend );
- xStringLength = strlen( cExpectedString );
-
- for( ;; )
- {
- /* Doesn't block so calls can interleave with the non-blocking
- receives performed by prvNonBlockingReceiverTask(). */
- xReceiveLength = xMessageBufferReceive( xMessageBuffer, ( void * ) cRxString, sizeof( cRxString ), mbDONT_BLOCK );
-
- /* Should only ever receive no data is available, or the expected
- length of data is available. */
- if( ( xReceiveLength != 0 ) && ( xReceiveLength != xStringLength ) )
- {
- xNonBlockingReceiveError = pdTRUE;
- }
-
- if( xReceiveLength == xStringLength )
- {
- /* Ensure the received data was that expected, then generate the
- next expected string. */
- if( strcmp( cRxString, cExpectedString ) != 0 )
- {
- xNonBlockingReceiveError = pdTRUE;
- }
-
- iDataToSend++;
-
- if( iDataToSend > iMaxValue )
- {
- /* The value sent is reset back to 0 to ensure the string being sent
- does not remain at the same length for too long. */
- iDataToSend = 0;
- }
-
- memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
- memset( cRxString, 0x00, sizeof( cRxString ) );
- sprintf( cExpectedString, "%d", ( int ) iDataToSend );
- xStringLength = strlen( cExpectedString );
-
- if( xNonBlockingReceiveError == pdFALSE )
- {
- /* No errors detected so increment the counter that lets the
- check task know this test is still functioning correctly. */
- ulNonBlockingRxCounter++;
- }
- }
- }
+ MessageBufferHandle_t xMessageBuffer;
+ BaseType_t xNonBlockingReceiveError = pdFALSE;
+ int32_t iDataToSend = 0;
+ size_t xStringLength, xReceiveLength;
+ const int32_t iMaxValue = 1500;
+ char cExpectedString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
+ char cRxString[ 12 ];
+
+ /* In this case the message buffer has already been created and is passed
+ * into the task using the task's parameter. */
+ xMessageBuffer = ( MessageBufferHandle_t ) pvParameters;
+
+ /* Create a string from an incrementing number. The length of the
+ * string will increase and decrease as the value of the number increases
+ * then overflows. This should always match the string sent to the buffer by
+ * the non blocking sender task. */
+ memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
+ memset( cRxString, 0x00, sizeof( cRxString ) );
+ sprintf( cExpectedString, "%d", ( int ) iDataToSend );
+ xStringLength = strlen( cExpectedString );
+
+ for( ; ; )
+ {
+ /* Doesn't block so calls can interleave with the non-blocking
+ * receives performed by prvNonBlockingReceiverTask(). */
+ xReceiveLength = xMessageBufferReceive( xMessageBuffer, ( void * ) cRxString, sizeof( cRxString ), mbDONT_BLOCK );
+
+ /* Should only ever receive no data is available, or the expected
+ * length of data is available. */
+ if( ( xReceiveLength != 0 ) && ( xReceiveLength != xStringLength ) )
+ {
+ xNonBlockingReceiveError = pdTRUE;
+ }
+
+ if( xReceiveLength == xStringLength )
+ {
+ /* Ensure the received data was that expected, then generate the
+ * next expected string. */
+ if( strcmp( cRxString, cExpectedString ) != 0 )
+ {
+ xNonBlockingReceiveError = pdTRUE;
+ }
+
+ iDataToSend++;
+
+ if( iDataToSend > iMaxValue )
+ {
+ /* The value sent is reset back to 0 to ensure the string being sent
+ * does not remain at the same length for too long. */
+ iDataToSend = 0;
+ }
+
+ memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
+ memset( cRxString, 0x00, sizeof( cRxString ) );
+ sprintf( cExpectedString, "%d", ( int ) iDataToSend );
+ xStringLength = strlen( cExpectedString );
+
+ if( xNonBlockingReceiveError == pdFALSE )
+ {
+ /* No errors detected so increment the counter that lets the
+ * check task know this test is still functioning correctly. */
+ ulNonBlockingRxCounter++;
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
- static void prvSenderTask( void *pvParameters )
- {
- MessageBufferHandle_t xMessageBuffer, xTempMessageBuffer;
- int32_t iDataToSend = 0;
- const int32_t iSendsBetweenIncrements = 100;
- char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
- const TickType_t xTicksToWait = mbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 );
- StaticMessageBuffer_t xStaticMessageBuffer;
- size_t xBytesSent;
-
-
- /* The task's priority is used as an index into the loop counters used to
- indicate this task is still running. */
- UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
-
- /* Make sure a change in priority does not inadvertently result in an
- invalid array index. */
- configASSERT( uxIndex < mbNUMBER_OF_ECHO_CLIENTS );
-
- /* Avoid compiler warnings about unused parameters. */
- ( void ) pvParameters;
-
- xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ) / mbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */
- &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */
- &( xStaticMessageBuffers[ uxIndex ] ) ); /* The static message buffer structure to use within the array. */
-
- /* Now the message buffer has been created the receiver task can be created.
- If this sender task has the higher priority then the receiver task is
- created at the lower priority - if this sender task has the lower priority
- then the receiver task is created at the higher priority. */
- if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY )
- {
- /* Here prvSingleTaskTests() performs various tests on a message buffer
- that was created statically. */
- prvSingleTaskTests( xMessageBuffer );
- xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize, ( void * ) xMessageBuffer, mbHIGHER_PRIORITY, NULL );
- }
- else
- {
- xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize, ( void * ) xMessageBuffer, mbLOWER_PRIORITY, NULL );
- }
-
- for( ;; )
- {
- /* Create a string from an incrementing number. The length of the
- string will increase and decrease as the value of the number increases
- then overflows. */
- memset( cTxString, 0x00, sizeof( cTxString ) );
- sprintf( cTxString, "%d", ( int ) iDataToSend );
-
- do
- {
- xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), xTicksToWait );
- } while ( xBytesSent == 0 ); /* Buffer may become full when receiver is running at the idle priority. */
-
- iDataToSend++;
-
- if( ( iDataToSend % iSendsBetweenIncrements ) == 0 )
- {
- /* Increment a loop counter so a check task can tell this task is
- still running as expected. */
- ulSenderLoopCounters[ uxIndex ]++;
-
- if( uxTaskPriorityGet( NULL ) == mbHIGHER_PRIORITY )
- {
- /* Allow other tasks to run. */
- vTaskDelay( xShortDelay );
- }
-
- /* This message buffer is just created and deleted to ensure no
- issues when attempting to delete a message buffer that was
- created using statically allocated memory. To save stack space
- the buffer is set to point to the cTxString array - this is
- ok because nothing is actually written to the memory. */
- xTempMessageBuffer = xMessageBufferCreateStatic( sizeof( cTxString ), ( uint8_t * ) cTxString, &xStaticMessageBuffer );
- vMessageBufferDelete( xTempMessageBuffer );
- }
- }
- }
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ static void prvSenderTask( void * pvParameters )
+ {
+ MessageBufferHandle_t xMessageBuffer, xTempMessageBuffer;
+ int32_t iDataToSend = 0;
+ const int32_t iSendsBetweenIncrements = 100;
+ char cTxString[ 12 ]; /* Large enough to hold a 32 number in ASCII. */
+ const TickType_t xTicksToWait = mbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 );
+ StaticMessageBuffer_t xStaticMessageBuffer;
+ size_t xBytesSent;
+
+
+ /* The task's priority is used as an index into the loop counters used to
+ * indicate this task is still running. */
+ UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+
+ /* Make sure a change in priority does not inadvertently result in an
+ * invalid array index. */
+ configASSERT( uxIndex < mbNUMBER_OF_ECHO_CLIENTS );
+
+ /* Avoid compiler warnings about unused parameters. */
+ ( void ) pvParameters;
+
+ xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ) / mbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */
+ &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */
+ &( xStaticMessageBuffers[ uxIndex ] ) ); /* The static message buffer structure to use within the array. */
+
+ /* Now the message buffer has been created the receiver task can be created.
+ * If this sender task has the higher priority then the receiver task is
+ * created at the lower priority - if this sender task has the lower priority
+ * then the receiver task is created at the higher priority. */
+ if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY )
+ {
+ /* Here prvSingleTaskTests() performs various tests on a message buffer
+ * that was created statically. */
+ prvSingleTaskTests( xMessageBuffer );
+ xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize, ( void * ) xMessageBuffer, mbHIGHER_PRIORITY, NULL );
+ }
+ else
+ {
+ xTaskCreate( prvReceiverTask, "MsgReceiver", xBlockingStackSize, ( void * ) xMessageBuffer, mbLOWER_PRIORITY, NULL );
+ }
+
+ for( ; ; )
+ {
+ /* Create a string from an incrementing number. The length of the
+ * string will increase and decrease as the value of the number increases
+ * then overflows. */
+ memset( cTxString, 0x00, sizeof( cTxString ) );
+ sprintf( cTxString, "%d", ( int ) iDataToSend );
+
+ do
+ {
+ xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) cTxString, strlen( cTxString ), xTicksToWait );
+ } while( xBytesSent == 0 ); /* Buffer may become full when receiver is running at the idle priority. */
+
+ iDataToSend++;
+
+ if( ( iDataToSend % iSendsBetweenIncrements ) == 0 )
+ {
+ /* Increment a loop counter so a check task can tell this task is
+ * still running as expected. */
+ ulSenderLoopCounters[ uxIndex ]++;
+
+ if( uxTaskPriorityGet( NULL ) == mbHIGHER_PRIORITY )
+ {
+ /* Allow other tasks to run. */
+ vTaskDelay( xShortDelay );
+ }
+
+ /* This message buffer is just created and deleted to ensure no
+ * issues when attempting to delete a message buffer that was
+ * created using statically allocated memory. To save stack space
+ * the buffer is set to point to the cTxString array - this is
+ * ok because nothing is actually written to the memory. */
+ xTempMessageBuffer = xMessageBufferCreateStatic( sizeof( cTxString ), ( uint8_t * ) cTxString, &xStaticMessageBuffer );
+ vMessageBufferDelete( xTempMessageBuffer );
+ }
+ }
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
- static void prvReceiverTask( void *pvParameters )
- {
- MessageBufferHandle_t * const pxMessageBuffer = ( MessageBufferHandle_t * ) pvParameters;
- char cExpectedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
- char cReceivedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
- int32_t iExpectedData = 0;
- const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL );
- size_t xReceivedBytes;
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- for( ;; )
- {
- /* Generate the next expected string in the cExpectedString buffer. */
- memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
- sprintf( cExpectedString, "%d", ( int ) iExpectedData );
+ static void prvReceiverTask( void * pvParameters )
+ {
+ MessageBufferHandle_t * const pxMessageBuffer = ( MessageBufferHandle_t * ) pvParameters;
+ char cExpectedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
+ char cReceivedString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
+ int32_t iExpectedData = 0;
+ const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL );
+ size_t xReceivedBytes;
- /* Receive the next string from the message buffer. */
- memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
+ for( ; ; )
+ {
+ /* Generate the next expected string in the cExpectedString buffer. */
+ memset( cExpectedString, 0x00, sizeof( cExpectedString ) );
+ sprintf( cExpectedString, "%d", ( int ) iExpectedData );
- do
- {
- xReceivedBytes = xMessageBufferReceive( pxMessageBuffer, ( void * ) cReceivedString, sizeof( cExpectedString ), xTicksToWait );
+ /* Receive the next string from the message buffer. */
+ memset( cReceivedString, 0x00, sizeof( cReceivedString ) );
- } while( xReceivedBytes == 0 );
+ do
+ {
+ xReceivedBytes = xMessageBufferReceive( pxMessageBuffer, ( void * ) cReceivedString, sizeof( cExpectedString ), xTicksToWait );
+ } while( xReceivedBytes == 0 );
- /* Ensure the received string matches the expected string. */
- configASSERT( strcmp( cExpectedString, cReceivedString ) == 0 );
+ /* Ensure the received string matches the expected string. */
+ configASSERT( strcmp( cExpectedString, cReceivedString ) == 0 );
- iExpectedData++;
- }
- }
+ iExpectedData++;
+ }
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
-static void prvEchoClient( void *pvParameters )
+static void prvEchoClient( void * pvParameters )
{
-size_t xSendLength = 0, ux;
-char *pcStringToSend, *pcStringReceived, cNextChar = mbASCII_SPACE;
-const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 );
+ size_t xSendLength = 0, ux;
+ char * pcStringToSend, * pcStringReceived, cNextChar = mbASCII_SPACE;
+ const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 );
/* The task's priority is used as an index into the loop counters used to
-indicate this task is still running. */
-UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+ * indicate this task is still running. */
+ UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
/* Pointers to the client and server message buffers are passed into this task
-using the task's parameter. */
-EchoMessageBuffers_t *pxMessageBuffers = ( EchoMessageBuffers_t * ) pvParameters;
-
- /* Prevent compiler warnings. */
- ( void ) pvParameters;
-
- /* Create the buffer into which strings to send to the server will be
- created, and the buffer into which strings echoed back from the server will
- be copied. */
- pcStringToSend = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
- pcStringReceived = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
-
- configASSERT( pcStringToSend );
- configASSERT( pcStringReceived );
-
- for( ;; )
- {
- /* Generate the length of the next string to send. */
- xSendLength++;
-
- /* The message buffer is being used to hold variable length data, so
- each data item requires sizeof( size_t ) bytes to hold the data's
- length, hence the sizeof() in the if() condition below. */
- if( xSendLength > ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) )
- {
- /* Back to a string length of 1. */
- xSendLength = sizeof( char );
-
- /* Maintain a count of the number of times this code executes so a
- check task can determine if this task is still functioning as
- expected or not. As there are two client tasks, and the priorities
- used are 0 and 1, the task's priority is used as an index into the
- loop count array. */
- ulEchoLoopCounters[ uxIndex ]++;
- }
-
- memset( pcStringToSend, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
-
- for( ux = 0; ux < xSendLength; ux++ )
- {
- pcStringToSend[ ux ] = cNextChar;
-
- cNextChar++;
-
- if( cNextChar > mbASCII_TILDA )
- {
- cNextChar = mbASCII_SPACE;
- }
- }
-
- /* Send the generated string to the buffer. */
- do
- {
- ux = xMessageBufferSend( pxMessageBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait );
-
- if( ux == 0 )
- {
- mtCOVERAGE_TEST_MARKER();
- }
-
- } while( ux == 0 );
-
- /* Wait for the string to be echoed back. */
- memset( pcStringReceived, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
- xMessageBufferReceive( pxMessageBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY );
-
- configASSERT( strcmp( pcStringToSend, pcStringReceived ) == 0 );
- }
+ * using the task's parameter. */
+ EchoMessageBuffers_t * pxMessageBuffers = ( EchoMessageBuffers_t * ) pvParameters;
+
+ /* Prevent compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Create the buffer into which strings to send to the server will be
+ * created, and the buffer into which strings echoed back from the server will
+ * be copied. */
+ pcStringToSend = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ pcStringReceived = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+ configASSERT( pcStringToSend );
+ configASSERT( pcStringReceived );
+
+ for( ; ; )
+ {
+ /* Generate the length of the next string to send. */
+ xSendLength++;
+
+ /* The message buffer is being used to hold variable length data, so
+ * each data item requires sizeof( size_t ) bytes to hold the data's
+ * length, hence the sizeof() in the if() condition below. */
+ if( xSendLength > ( mbMESSAGE_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) )
+ {
+ /* Back to a string length of 1. */
+ xSendLength = sizeof( char );
+
+ /* Maintain a count of the number of times this code executes so a
+ * check task can determine if this task is still functioning as
+ * expected or not. As there are two client tasks, and the priorities
+ * used are 0 and 1, the task's priority is used as an index into the
+ * loop count array. */
+ ulEchoLoopCounters[ uxIndex ]++;
+ }
+
+ memset( pcStringToSend, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+ for( ux = 0; ux < xSendLength; ux++ )
+ {
+ pcStringToSend[ ux ] = cNextChar;
+
+ cNextChar++;
+
+ if( cNextChar > mbASCII_TILDA )
+ {
+ cNextChar = mbASCII_SPACE;
+ }
+ }
+
+ /* Send the generated string to the buffer. */
+ do
+ {
+ ux = xMessageBufferSend( pxMessageBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait );
+
+ if( ux == 0 )
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ } while( ux == 0 );
+
+ /* Wait for the string to be echoed back. */
+ memset( pcStringReceived, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
+ xMessageBufferReceive( pxMessageBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY );
+
+ configASSERT( strcmp( pcStringToSend, pcStringReceived ) == 0 );
+ }
}
/*-----------------------------------------------------------*/
-static void prvEchoServer( void *pvParameters )
+static void prvEchoServer( void * pvParameters )
{
-MessageBufferHandle_t xTempMessageBuffer;
-size_t xReceivedLength;
-char *pcReceivedString;
-EchoMessageBuffers_t xMessageBuffers;
-TickType_t xTimeOnEntering;
-const TickType_t xTicksToBlock = pdMS_TO_TICKS( 250UL );
-
- /* Prevent compiler warnings about unused parameters. */
- ( void ) pvParameters;
-
- /* Create the message buffer used to send data from the client to the server,
- and the message buffer used to echo the data from the server back to the
- client. */
- xMessageBuffers.xEchoClientBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
- xMessageBuffers.xEchoServerBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
- configASSERT( xMessageBuffers.xEchoClientBuffer );
- configASSERT( xMessageBuffers.xEchoServerBuffer );
-
- /* Create the buffer into which received strings will be copied. */
- pcReceivedString = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
- configASSERT( pcReceivedString );
-
- /* Don't expect to receive anything yet! */
- xTimeOnEntering = xTaskGetTickCount();
- xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, xTicksToBlock );
- configASSERT( ( ( TickType_t ) ( xTaskGetTickCount() - xTimeOnEntering ) ) >= xTicksToBlock );
- configASSERT( xReceivedLength == 0 );
- ( void ) xTimeOnEntering; /* In case configASSERT() is not defined. */
-
- /* Now the message buffers have been created the echo client task can be
- created. If this server task has the higher priority then the client task
- is created at the lower priority - if this server task has the lower
- priority then the client task is created at the higher priority. */
- if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY )
- {
- xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbHIGHER_PRIORITY, NULL );
- }
- else
- {
- /* Here prvSingleTaskTests() performs various tests on a message buffer
- that was created dynamically. */
- prvSingleTaskTests( xMessageBuffers.xEchoClientBuffer );
- xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbLOWER_PRIORITY, NULL );
- }
-
- for( ;; )
- {
- memset( pcReceivedString, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
-
- /* Has any data been sent by the client? */
- xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, portMAX_DELAY );
-
- /* Should always receive data as max delay was used. */
- configASSERT( xReceivedLength > 0 );
-
- /* Echo the received data back to the client. */
- xMessageBufferSend( xMessageBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY );
-
- /* This message buffer is just created and deleted to ensure no memory
- leaks. */
- xTempMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
- vMessageBufferDelete( xTempMessageBuffer );
- }
+ MessageBufferHandle_t xTempMessageBuffer;
+ size_t xReceivedLength;
+ char * pcReceivedString;
+ EchoMessageBuffers_t xMessageBuffers;
+ TickType_t xTimeOnEntering;
+ const TickType_t xTicksToBlock = pdMS_TO_TICKS( 250UL );
+
+ /* Prevent compiler warnings about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Create the message buffer used to send data from the client to the server,
+ * and the message buffer used to echo the data from the server back to the
+ * client. */
+ xMessageBuffers.xEchoClientBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ xMessageBuffers.xEchoServerBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ configASSERT( xMessageBuffers.xEchoClientBuffer );
+ configASSERT( xMessageBuffers.xEchoServerBuffer );
+
+ /* Create the buffer into which received strings will be copied. */
+ pcReceivedString = ( char * ) pvPortMalloc( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ configASSERT( pcReceivedString );
+
+ /* Don't expect to receive anything yet! */
+ xTimeOnEntering = xTaskGetTickCount();
+ xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, xTicksToBlock );
+ configASSERT( ( ( TickType_t ) ( xTaskGetTickCount() - xTimeOnEntering ) ) >= xTicksToBlock );
+ configASSERT( xReceivedLength == 0 );
+ ( void ) xTimeOnEntering; /* In case configASSERT() is not defined. */
+
+ /* Now the message buffers have been created the echo client task can be
+ * created. If this server task has the higher priority then the client task
+ * is created at the lower priority - if this server task has the lower
+ * priority then the client task is created at the higher priority. */
+ if( uxTaskPriorityGet( NULL ) == mbLOWER_PRIORITY )
+ {
+ xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbHIGHER_PRIORITY, NULL );
+ }
+ else
+ {
+ /* Here prvSingleTaskTests() performs various tests on a message buffer
+ * that was created dynamically. */
+ prvSingleTaskTests( xMessageBuffers.xEchoClientBuffer );
+ xTaskCreate( prvEchoClient, "EchoClient", configMINIMAL_STACK_SIZE, ( void * ) &xMessageBuffers, mbLOWER_PRIORITY, NULL );
+ }
+
+ for( ; ; )
+ {
+ memset( pcReceivedString, 0x00, mbMESSAGE_BUFFER_LENGTH_BYTES );
+
+ /* Has any data been sent by the client? */
+ xReceivedLength = xMessageBufferReceive( xMessageBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, mbMESSAGE_BUFFER_LENGTH_BYTES, portMAX_DELAY );
+
+ /* Should always receive data as max delay was used. */
+ configASSERT( xReceivedLength > 0 );
+
+ /* Echo the received data back to the client. */
+ xMessageBufferSend( xMessageBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY );
+
+ /* This message buffer is just created and deleted to ensure no memory
+ * leaks. */
+ xTempMessageBuffer = xMessageBufferCreate( mbMESSAGE_BUFFER_LENGTH_BYTES );
+ vMessageBufferDelete( xTempMessageBuffer );
+ }
}
/*-----------------------------------------------------------*/
+/* Tests within configRUN_ADDITIONAL_TESTS blocks only execute on larger
+ * platforms or have been added to pre-existing files that are already in use
+ * by other test projects without ensuring they don't cause those pre-existing
+ * projects to run out of program or data memory. */
+#if ( configRUN_ADDITIONAL_TESTS == 1 )
+
+ static void prvSpaceAvailableCoherenceActor( void * pvParameters )
+ {
+ static char * cTxString = "12345";
+ char cRxString[ mbCOHERENCE_TEST_BYTES_WRITTEN + 1 ]; /* +1 for NULL terminator. */
+
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Add bytes to the buffer so the other task should see
+ * mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING bytes free. */
+ xMessageBufferSend( xCoherenceTestMessageBuffer, ( void * ) cTxString, strlen( cTxString ), 0 );
+ configASSERT( xMessageBufferSpacesAvailable( xCoherenceTestMessageBuffer ) == mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING );
+
+ /* Read out message again so the other task should read the full
+ * mbCOHERENCE_TEST_BUFFER_SIZE bytes free again. */
+ memset( ( void * ) cRxString, 0x00, sizeof( cRxString ) );
+ xMessageBufferReceive( xCoherenceTestMessageBuffer, ( void * ) cRxString, mbCOHERENCE_TEST_BYTES_WRITTEN, 0 );
+ configASSERT( strcmp( cTxString, cRxString ) == 0 );
+ }
+ }
+ /*-----------------------------------------------------------*/
+
+ static void prvSpaceAvailableCoherenceTester( void * pvParameters )
+ {
+ size_t xSpaceAvailable;
+ BaseType_t xErrorFound = pdFALSE;
+
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* This message buffer is only ever empty or contains 5 bytes. So all
+ * queries of its free space should result in one of the two values tested
+ * below. */
+ xSpaceAvailable = xMessageBufferSpacesAvailable( xCoherenceTestMessageBuffer );
+
+ if( ( xSpaceAvailable == mbCOHERENCE_TEST_BUFFER_SIZE ) ||
+ ( xSpaceAvailable == mbEXPECTED_FREE_BYTES_AFTER_WRITING_STRING ) )
+ {
+ /* Only continue to increment the variable that shows this task
+ * is still executing if no errors have been found. */
+ if( xErrorFound == pdFALSE )
+ {
+ ulSizeCoherencyTestCycles++;
+ }
+ }
+ else
+ {
+ xErrorFound = pdTRUE;
+ }
+
+ configASSERT( xErrorFound == pdFALSE );
+ }
+ }
+
+#endif /* configRUN_ADDITIONAL_TESTS == 1 */
+/*-----------------------------------------------------------*/
+
BaseType_t xAreMessageBufferTasksStillRunning( void )
{
-static uint32_t ulLastEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
-static uint32_t ulLastNonBlockingRxCounter = 0;
-BaseType_t xReturn = pdPASS, x;
-
- for( x = 0; x < mbNUMBER_OF_ECHO_CLIENTS; x++ )
- {
- if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] )
- {
- xReturn = pdFAIL;
- }
- else
- {
- ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ];
- }
- }
-
- if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter )
- {
- xReturn = pdFAIL;
- }
- else
- {
- ulLastNonBlockingRxCounter = ulNonBlockingRxCounter;
- }
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- static uint32_t ulLastSenderLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
-
- for( x = 0; x < mbNUMBER_OF_SENDER_TASKS; x++ )
- {
- if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] )
- {
- xReturn = pdFAIL;
- }
- else
- {
- ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ];
- }
- }
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
-
- return xReturn;
+ static uint32_t ulLastEchoLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+ static uint32_t ulLastNonBlockingRxCounter = 0;
+ BaseType_t xReturn = pdPASS, x;
+
+ for( x = 0; x < mbNUMBER_OF_ECHO_CLIENTS; x++ )
+ {
+ if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ];
+ }
+ }
+
+ if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ulLastNonBlockingRxCounter = ulNonBlockingRxCounter;
+ }
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ static uint32_t ulLastSenderLoopCounters[ mbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+
+ for( x = 0; x < mbNUMBER_OF_SENDER_TASKS; x++ )
+ {
+ if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ];
+ }
+ }
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ #if ( configRUN_ADDITIONAL_TESTS == 1 )
+ {
+ static uint32_t ullastSizeCoherencyTestCycles = 0UL;
+
+ if( ullastSizeCoherencyTestCycles == ulSizeCoherencyTestCycles )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ullastSizeCoherencyTestCycles = ulSizeCoherencyTestCycles;
+ }
+ }
+ #endif /* if ( configRUN_ADDITIONAL_TESTS == 1 ) */
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
-
-
diff --git a/Demo/Common/Minimal/PollQ.c b/Demo/Common/Minimal/PollQ.c
index ebbf906ed..b462946d0 100644
--- a/Demo/Common/Minimal/PollQ.c
+++ b/Demo/Common/Minimal/PollQ.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -49,11 +49,11 @@
*/
/*
-Changes from V2.0.0
-
- + Delay periods are now specified using variables and constants of
- TickType_t rather than uint32_t.
-*/
+ * Changes from V2.0.0
+ *
+ + Delay periods are now specified using variables and constants of
+ + TickType_t rather than uint32_t.
+ */
#include
@@ -65,13 +65,13 @@ Changes from V2.0.0
/* Demo program include files. */
#include "PollQ.h"
-#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE
-#define pollqQUEUE_SIZE ( 10 )
-#define pollqPRODUCER_DELAY ( pdMS_TO_TICKS( ( TickType_t ) 200 ) )
-#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( TickType_t ) ( 20 / portTICK_PERIOD_MS ) )
-#define pollqNO_DELAY ( ( TickType_t ) 0 )
-#define pollqVALUES_TO_PRODUCE ( ( BaseType_t ) 3 )
-#define pollqINITIAL_VALUE ( ( BaseType_t ) 0 )
+#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE
+#define pollqQUEUE_SIZE ( 10 )
+#define pollqPRODUCER_DELAY ( pdMS_TO_TICKS( ( TickType_t ) 200 ) )
+#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( TickType_t ) ( 20 / portTICK_PERIOD_MS ) )
+#define pollqNO_DELAY ( ( TickType_t ) 0 )
+#define pollqVALUES_TO_PRODUCE ( ( BaseType_t ) 3 )
+#define pollqINITIAL_VALUE ( ( BaseType_t ) 0 )
/* The task that posts the incrementing number onto the queue. */
static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );
@@ -80,144 +80,144 @@ static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );
static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters );
/* Variables that are used to check that the tasks are still running with no
-errors. */
+ * errors. */
static volatile BaseType_t xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE;
/*-----------------------------------------------------------*/
void vStartPolledQueueTasks( UBaseType_t uxPriority )
{
-static QueueHandle_t xPolledQueue;
-
- /* Create the queue used by the producer and consumer. */
- xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( UBaseType_t ) sizeof( uint16_t ) );
-
- if( xPolledQueue != NULL )
- {
- /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
- in use. The queue registry is provided as a means for kernel aware
- debuggers to locate queues and has no purpose if a kernel aware debugger
- is not being used. The call to vQueueAddToRegistry() will be removed
- by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
- defined to be less than 1. */
- vQueueAddToRegistry( xPolledQueue, "Poll_Test_Queue" );
-
- /* Spawn the producer and consumer. */
- xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL );
- xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL );
- }
+ static QueueHandle_t xPolledQueue;
+
+ /* Create the queue used by the producer and consumer. */
+ xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( UBaseType_t ) sizeof( uint16_t ) );
+
+ if( xPolledQueue != NULL )
+ {
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+ * in use. The queue registry is provided as a means for kernel aware
+ * debuggers to locate queues and has no purpose if a kernel aware debugger
+ * is not being used. The call to vQueueAddToRegistry() will be removed
+ * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+ * defined to be less than 1. */
+ vQueueAddToRegistry( xPolledQueue, "Poll_Test_Queue" );
+
+ /* Spawn the producer and consumer. */
+ xTaskCreate( vPolledQueueConsumer, "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL );
+ xTaskCreate( vPolledQueueProducer, "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( TaskHandle_t * ) NULL );
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vPolledQueueProducer, pvParameters )
{
-uint16_t usValue = ( uint16_t ) 0;
-BaseType_t xError = pdFALSE, xLoop;
-
- for( ;; )
- {
- for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )
- {
- /* Send an incrementing number on the queue without blocking. */
- if( xQueueSend( *( ( QueueHandle_t * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )
- {
- /* We should never find the queue full so if we get here there
- has been an error. */
- xError = pdTRUE;
- }
- else
- {
- if( xError == pdFALSE )
- {
- /* If an error has ever been recorded we stop incrementing the
- check variable. */
- portENTER_CRITICAL();
- xPollingProducerCount++;
- portEXIT_CRITICAL();
- }
-
- /* Update the value we are going to post next time around. */
- usValue++;
- }
- }
-
- /* Wait before we start posting again to ensure the consumer runs and
- empties the queue. */
- vTaskDelay( pollqPRODUCER_DELAY );
- }
-} /*lint !e818 Function prototype must conform to API. */
+ uint16_t usValue = ( uint16_t ) 0;
+ BaseType_t xError = pdFALSE, xLoop;
+
+ for( ; ; )
+ {
+ for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )
+ {
+ /* Send an incrementing number on the queue without blocking. */
+ if( xQueueSend( *( ( QueueHandle_t * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )
+ {
+ /* We should never find the queue full so if we get here there
+ * has been an error. */
+ xError = pdTRUE;
+ }
+ else
+ {
+ if( xError == pdFALSE )
+ {
+ /* If an error has ever been recorded we stop incrementing the
+ * check variable. */
+ portENTER_CRITICAL();
+ xPollingProducerCount++;
+ portEXIT_CRITICAL();
+ }
+
+ /* Update the value we are going to post next time around. */
+ usValue++;
+ }
+ }
+
+ /* Wait before we start posting again to ensure the consumer runs and
+ * empties the queue. */
+ vTaskDelay( pollqPRODUCER_DELAY );
+ }
+} /*lint !e818 Function prototype must conform to API. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters )
{
-uint16_t usData, usExpectedValue = ( uint16_t ) 0;
-BaseType_t xError = pdFALSE;
-
- for( ;; )
- {
- /* Loop until the queue is empty. */
- while( uxQueueMessagesWaiting( *( ( QueueHandle_t * ) pvParameters ) ) )
- {
- if( xQueueReceive( *( ( QueueHandle_t * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )
- {
- if( usData != usExpectedValue )
- {
- /* This is not what we expected to receive so an error has
- occurred. */
- xError = pdTRUE;
-
- /* Catch-up to the value we received so our next expected
- value should again be correct. */
- usExpectedValue = usData;
- }
- else
- {
- if( xError == pdFALSE )
- {
- /* Only increment the check variable if no errors have
- occurred. */
- portENTER_CRITICAL();
- xPollingConsumerCount++;
- portEXIT_CRITICAL();
- }
- }
-
- /* Next time round we would expect the number to be one higher. */
- usExpectedValue++;
- }
- }
-
- /* Now the queue is empty we block, allowing the producer to place more
- items in the queue. */
- vTaskDelay( pollqCONSUMER_DELAY );
- }
+ uint16_t usData, usExpectedValue = ( uint16_t ) 0;
+ BaseType_t xError = pdFALSE;
+
+ for( ; ; )
+ {
+ /* Loop until the queue is empty. */
+ while( uxQueueMessagesWaiting( *( ( QueueHandle_t * ) pvParameters ) ) )
+ {
+ if( xQueueReceive( *( ( QueueHandle_t * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )
+ {
+ if( usData != usExpectedValue )
+ {
+ /* This is not what we expected to receive so an error has
+ * occurred. */
+ xError = pdTRUE;
+
+ /* Catch-up to the value we received so our next expected
+ * value should again be correct. */
+ usExpectedValue = usData;
+ }
+ else
+ {
+ if( xError == pdFALSE )
+ {
+ /* Only increment the check variable if no errors have
+ * occurred. */
+ portENTER_CRITICAL();
+ xPollingConsumerCount++;
+ portEXIT_CRITICAL();
+ }
+ }
+
+ /* Next time round we would expect the number to be one higher. */
+ usExpectedValue++;
+ }
+ }
+
+ /* Now the queue is empty we block, allowing the producer to place more
+ * items in the queue. */
+ vTaskDelay( pollqCONSUMER_DELAY );
+ }
} /*lint !e818 Function prototype must conform to API. */
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running with no errors. */
BaseType_t xArePollingQueuesStillRunning( void )
{
-BaseType_t xReturn;
-
- /* Check both the consumer and producer poll count to check they have both
- been changed since out last trip round. We do not need a critical section
- around the check variables as this is called from a higher priority than
- the other tasks that access the same variables. */
- if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||
- ( xPollingProducerCount == pollqINITIAL_VALUE )
- )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- /* Set the check variables back down so we know if they have been
- incremented the next time around. */
- xPollingConsumerCount = pollqINITIAL_VALUE;
- xPollingProducerCount = pollqINITIAL_VALUE;
-
- return xReturn;
+ BaseType_t xReturn;
+
+ /* Check both the consumer and producer poll count to check they have both
+ * been changed since out last trip round. We do not need a critical section
+ * around the check variables as this is called from a higher priority than
+ * the other tasks that access the same variables. */
+ if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||
+ ( xPollingProducerCount == pollqINITIAL_VALUE )
+ )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ /* Set the check variables back down so we know if they have been
+ * incremented the next time around. */
+ xPollingConsumerCount = pollqINITIAL_VALUE;
+ xPollingProducerCount = pollqINITIAL_VALUE;
+
+ return xReturn;
}
diff --git a/Demo/Common/Minimal/QPeek.c b/Demo/Common/Minimal/QPeek.c
index f3b552341..ea822457d 100644
--- a/Demo/Common/Minimal/QPeek.c
+++ b/Demo/Common/Minimal/QPeek.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -43,14 +43,14 @@
/* Demo program include files. */
#include "QPeek.h"
-#define qpeekQUEUE_LENGTH ( 5 )
-#define qpeekNO_BLOCK ( 0 )
-#define qpeekSHORT_DELAY ( 10 )
+#define qpeekQUEUE_LENGTH ( 5 )
+#define qpeekNO_BLOCK ( 0 )
+#define qpeekSHORT_DELAY ( 10 )
-#define qpeekLOW_PRIORITY ( tskIDLE_PRIORITY + 0 )
-#define qpeekMEDIUM_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define qpeekHIGH_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define qpeekHIGHEST_PRIORITY ( tskIDLE_PRIORITY + 3 )
+#define qpeekLOW_PRIORITY ( tskIDLE_PRIORITY + 0 )
+#define qpeekMEDIUM_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define qpeekHIGH_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define qpeekHIGHEST_PRIORITY ( tskIDLE_PRIORITY + 3 )
/*-----------------------------------------------------------*/
@@ -59,19 +59,19 @@
* Each task is given a different priority to demonstrate the order in which
* tasks are woken as data is peeked from a queue.
*/
-static void prvLowPriorityPeekTask( void *pvParameters );
-static void prvMediumPriorityPeekTask( void *pvParameters );
-static void prvHighPriorityPeekTask( void *pvParameters );
-static void prvHighestPriorityPeekTask( void *pvParameters );
+static void prvLowPriorityPeekTask( void * pvParameters );
+static void prvMediumPriorityPeekTask( void * pvParameters );
+static void prvHighPriorityPeekTask( void * pvParameters );
+static void prvHighestPriorityPeekTask( void * pvParameters );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
-detected in any of the tasks. */
+ * detected in any of the tasks. */
static volatile BaseType_t xErrorDetected = pdFALSE;
/* Counter that is incremented on each cycle of a test. This is used to
-detect a stalled task - a test that is no longer running. */
+ * detect a stalled task - a test that is no longer running. */
static volatile uint32_t ulLoopCounter = 0;
/* Handles to the test tasks. */
@@ -80,361 +80,362 @@ TaskHandle_t xMediumPriorityTask, xHighPriorityTask, xHighestPriorityTask;
void vStartQueuePeekTasks( void )
{
-QueueHandle_t xQueue;
-
- /* Create the queue that we are going to use for the test/demo. */
- xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( uint32_t ) );
-
- if( xQueue != NULL )
- {
- /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
- in use. The queue registry is provided as a means for kernel aware
- debuggers to locate queues and has no purpose if a kernel aware debugger
- is not being used. The call to vQueueAddToRegistry() will be removed
- by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
- defined to be less than 1. */
- vQueueAddToRegistry( xQueue, "QPeek_Test_Queue" );
-
- /* Create the demo tasks and pass it the queue just created. We are
- passing the queue handle by value so it does not matter that it is declared
- on the stack here. */
- xTaskCreate( prvLowPriorityPeekTask, "PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL );
- xTaskCreate( prvMediumPriorityPeekTask, "PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask );
- xTaskCreate( prvHighPriorityPeekTask, "PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask );
- xTaskCreate( prvHighestPriorityPeekTask, "PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask );
- }
+ QueueHandle_t xQueue;
+
+ /* Create the queue that we are going to use for the test/demo. */
+ xQueue = xQueueCreate( qpeekQUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xQueue != NULL )
+ {
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+ * in use. The queue registry is provided as a means for kernel aware
+ * debuggers to locate queues and has no purpose if a kernel aware debugger
+ * is not being used. The call to vQueueAddToRegistry() will be removed
+ * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+ * defined to be less than 1. */
+ vQueueAddToRegistry( xQueue, "QPeek_Test_Queue" );
+
+ /* Create the demo tasks and pass it the queue just created. We are
+ * passing the queue handle by value so it does not matter that it is declared
+ * on the stack here. */
+ xTaskCreate( prvLowPriorityPeekTask, "PeekL", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekLOW_PRIORITY, NULL );
+ xTaskCreate( prvMediumPriorityPeekTask, "PeekM", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekMEDIUM_PRIORITY, &xMediumPriorityTask );
+ xTaskCreate( prvHighPriorityPeekTask, "PeekH1", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGH_PRIORITY, &xHighPriorityTask );
+ xTaskCreate( prvHighestPriorityPeekTask, "PeekH2", configMINIMAL_STACK_SIZE, ( void * ) xQueue, qpeekHIGHEST_PRIORITY, &xHighestPriorityTask );
+ }
}
/*-----------------------------------------------------------*/
-static void prvHighestPriorityPeekTask( void *pvParameters )
+static void prvHighestPriorityPeekTask( void * pvParameters )
{
-QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
-uint32_t ulValue;
-
- #ifdef USE_STDIO
- {
- void vPrintDisplayMessage( const char * const * ppcMessageToSend );
-
- const char * const pcTaskStartMsg = "Queue peek test started.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
- }
- #endif
-
- for( ;; )
- {
- /* Try peeking from the queue. The queue should be empty so we will
- block, allowing the high priority task to execute. */
- if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
- {
- /* We expected to have received something by the time we unblock. */
- xErrorDetected = pdTRUE;
- }
-
- /* When we reach here the high and medium priority tasks should still
- be blocked on the queue. We unblocked because the low priority task
- wrote a value to the queue, which we should have peeked. Peeking the
- data (rather than receiving it) will leave the data on the queue, so
- the high priority task should then have also been unblocked, but not
- yet executed. */
- if( ulValue != 0x11223344 )
- {
- /* We did not receive the expected value. */
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 1 )
- {
- /* The message should have been left on the queue. */
- xErrorDetected = pdTRUE;
- }
-
- /* Now we are going to actually receive the data, so when the high
- priority task runs it will find the queue empty and return to the
- blocked state. */
- ulValue = 0;
- if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
- {
- /* We expected to receive the value. */
- xErrorDetected = pdTRUE;
- }
-
- if( ulValue != 0x11223344 )
- {
- /* We did not receive the expected value - which should have been
- the same value as was peeked. */
- xErrorDetected = pdTRUE;
- }
-
- /* Now we will block again as the queue is once more empty. The low
- priority task can then execute again. */
- if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
- {
- /* We expected to have received something by the time we unblock. */
- xErrorDetected = pdTRUE;
- }
-
- /* When we get here the low priority task should have again written to the
- queue. */
- if( ulValue != 0x01234567 )
- {
- /* We did not receive the expected value. */
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 1 )
- {
- /* The message should have been left on the queue. */
- xErrorDetected = pdTRUE;
- }
-
- /* We only peeked the data, so suspending ourselves now should enable
- the high priority task to also peek the data. The high priority task
- will have been unblocked when we peeked the data as we left the data
- in the queue. */
- vTaskSuspend( NULL );
-
-
-
- /* This time we are going to do the same as the above test, but the
- high priority task is going to receive the data, rather than peek it.
- This means that the medium priority task should never peek the value. */
- if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( ulValue != 0xaabbaabb )
- {
- xErrorDetected = pdTRUE;
- }
-
- vTaskSuspend( NULL );
- }
+ QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+ uint32_t ulValue;
+
+ #ifdef USE_STDIO
+ {
+ void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+ const char * const pcTaskStartMsg = "Queue peek test started.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+ }
+ #endif
+
+ for( ; ; )
+ {
+ /* Try peeking from the queue. The queue should be empty so we will
+ * block, allowing the high priority task to execute. */
+ if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+ {
+ /* We expected to have received something by the time we unblock. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* When we reach here the high and medium priority tasks should still
+ * be blocked on the queue. We unblocked because the low priority task
+ * wrote a value to the queue, which we should have peeked. Peeking the
+ * data (rather than receiving it) will leave the data on the queue, so
+ * the high priority task should then have also been unblocked, but not
+ * yet executed. */
+ if( ulValue != 0x11223344 )
+ {
+ /* We did not receive the expected value. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )
+ {
+ /* The message should have been left on the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now we are going to actually receive the data, so when the high
+ * priority task runs it will find the queue empty and return to the
+ * blocked state. */
+ ulValue = 0;
+
+ if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+ {
+ /* We expected to receive the value. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulValue != 0x11223344 )
+ {
+ /* We did not receive the expected value - which should have been
+ * the same value as was peeked. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Now we will block again as the queue is once more empty. The low
+ * priority task can then execute again. */
+ if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+ {
+ /* We expected to have received something by the time we unblock. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* When we get here the low priority task should have again written to the
+ * queue. */
+ if( ulValue != 0x01234567 )
+ {
+ /* We did not receive the expected value. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )
+ {
+ /* The message should have been left on the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* We only peeked the data, so suspending ourselves now should enable
+ * the high priority task to also peek the data. The high priority task
+ * will have been unblocked when we peeked the data as we left the data
+ * in the queue. */
+ vTaskSuspend( NULL );
+
+ /* This time we are going to do the same as the above test, but the
+ * high priority task is going to receive the data, rather than peek it.
+ * This means that the medium priority task should never peek the value. */
+ if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulValue != 0xaabbaabb )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ vTaskSuspend( NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvHighPriorityPeekTask( void *pvParameters )
+static void prvHighPriorityPeekTask( void * pvParameters )
{
-QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
-uint32_t ulValue;
-
- for( ;; )
- {
- /* Try peeking from the queue. The queue should be empty so we will
- block, allowing the medium priority task to execute. Both the high
- and highest priority tasks will then be blocked on the queue. */
- if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
- {
- /* We expected to have received something by the time we unblock. */
- xErrorDetected = pdTRUE;
- }
-
- /* When we get here the highest priority task should have peeked the data
- (unblocking this task) then suspended (allowing this task to also peek
- the data). */
- if( ulValue != 0x01234567 )
- {
- /* We did not receive the expected value. */
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 1 )
- {
- /* The message should have been left on the queue. */
- xErrorDetected = pdTRUE;
- }
-
- /* We only peeked the data, so suspending ourselves now should enable
- the medium priority task to also peek the data. The medium priority task
- will have been unblocked when we peeked the data as we left the data
- in the queue. */
- vTaskSuspend( NULL );
-
-
- /* This time we are going actually receive the value, so the medium
- priority task will never peek the data - we removed it from the queue. */
- if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- if( ulValue != 0xaabbaabb )
- {
- xErrorDetected = pdTRUE;
- }
-
- vTaskSuspend( NULL );
- }
+ QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+ uint32_t ulValue;
+
+ for( ; ; )
+ {
+ /* Try peeking from the queue. The queue should be empty so we will
+ * block, allowing the medium priority task to execute. Both the high
+ * and highest priority tasks will then be blocked on the queue. */
+ if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+ {
+ /* We expected to have received something by the time we unblock. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* When we get here the highest priority task should have peeked the data
+ * (unblocking this task) then suspended (allowing this task to also peek
+ * the data). */
+ if( ulValue != 0x01234567 )
+ {
+ /* We did not receive the expected value. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )
+ {
+ /* The message should have been left on the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* We only peeked the data, so suspending ourselves now should enable
+ * the medium priority task to also peek the data. The medium priority task
+ * will have been unblocked when we peeked the data as we left the data
+ * in the queue. */
+ vTaskSuspend( NULL );
+
+ /* This time we are going actually receive the value, so the medium
+ * priority task will never peek the data - we removed it from the queue. */
+ if( xQueueReceive( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulValue != 0xaabbaabb )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ vTaskSuspend( NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvMediumPriorityPeekTask( void *pvParameters )
+static void prvMediumPriorityPeekTask( void * pvParameters )
{
-QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
-uint32_t ulValue;
-
- for( ;; )
- {
- /* Try peeking from the queue. The queue should be empty so we will
- block, allowing the low priority task to execute. The highest, high
- and medium priority tasks will then all be blocked on the queue. */
- if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
- {
- /* We expected to have received something by the time we unblock. */
- xErrorDetected = pdTRUE;
- }
-
- /* When we get here the high priority task should have peeked the data
- (unblocking this task) then suspended (allowing this task to also peek
- the data). */
- if( ulValue != 0x01234567 )
- {
- /* We did not receive the expected value. */
- xErrorDetected = pdTRUE;
- }
-
- if( uxQueueMessagesWaiting( xQueue ) != 1 )
- {
- /* The message should have been left on the queue. */
- xErrorDetected = pdTRUE;
- }
-
- /* Just so we know the test is still running. */
- ulLoopCounter++;
-
- /* Now we can suspend ourselves so the low priority task can execute
- again. */
- vTaskSuspend( NULL );
- }
+ QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+ uint32_t ulValue;
+
+ for( ; ; )
+ {
+ /* Try peeking from the queue. The queue should be empty so we will
+ * block, allowing the low priority task to execute. The highest, high
+ * and medium priority tasks will then all be blocked on the queue. */
+ if( xQueuePeek( xQueue, &ulValue, portMAX_DELAY ) != pdPASS )
+ {
+ /* We expected to have received something by the time we unblock. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* When we get here the high priority task should have peeked the data
+ * (unblocking this task) then suspended (allowing this task to also peek
+ * the data). */
+ if( ulValue != 0x01234567 )
+ {
+ /* We did not receive the expected value. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )
+ {
+ /* The message should have been left on the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Just so we know the test is still running. */
+ ulLoopCounter++;
+
+ /* Now we can suspend ourselves so the low priority task can execute
+ * again. */
+ vTaskSuspend( NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvLowPriorityPeekTask( void *pvParameters )
+static void prvLowPriorityPeekTask( void * pvParameters )
{
-QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
-uint32_t ulValue;
-
- for( ;; )
- {
- /* Write some data to the queue. This should unblock the highest
- priority task that is waiting to peek data from the queue. */
- ulValue = 0x11223344;
- if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
- {
- /* We were expecting the queue to be empty so we should not of
- had a problem writing to the queue. */
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* By the time we get here the data should have been removed from
- the queue. */
- if( uxQueueMessagesWaiting( xQueue ) != 0 )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* Write another value to the queue, again waking the highest priority
- task that is blocked on the queue. */
- ulValue = 0x01234567;
- if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
- {
- /* We were expecting the queue to be empty so we should not of
- had a problem writing to the queue. */
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* All the other tasks should now have successfully peeked the data.
- The data is still in the queue so we should be able to receive it. */
- ulValue = 0;
- if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
- {
- /* We expected to receive the data. */
- xErrorDetected = pdTRUE;
- }
-
- if( ulValue != 0x01234567 )
- {
- /* We did not receive the expected value. */
- xErrorDetected = pdTRUE;
- }
-
- /* Lets just delay a while as this is an intensive test as we don't
- want to starve other tests of processing time. */
- vTaskDelay( qpeekSHORT_DELAY );
-
- /* Unsuspend the other tasks so we can repeat the test - this time
- however not all the other tasks will peek the data as the high
- priority task is actually going to remove it from the queue. Send
- to front is used just to be different. As the queue is empty it
- makes no difference to the result. */
- vTaskResume( xMediumPriorityTask );
- vTaskResume( xHighPriorityTask );
- vTaskResume( xHighestPriorityTask );
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- ulValue = 0xaabbaabb;
- if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
- {
- /* We were expecting the queue to be empty so we should not of
- had a problem writing to the queue. */
- xErrorDetected = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* This time we should find that the queue is empty. The high priority
- task actually removed the data rather than just peeking it. */
- if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY )
- {
- /* We expected to receive the data. */
- xErrorDetected = pdTRUE;
- }
-
- /* Unsuspend the highest and high priority tasks so we can go back
- and repeat the whole thing. The medium priority task should not be
- suspended as it was not able to peek the data in this last case. */
- vTaskResume( xHighPriorityTask );
- vTaskResume( xHighestPriorityTask );
-
- /* Lets just delay a while as this is an intensive test as we don't
- want to starve other tests of processing time. */
- vTaskDelay( qpeekSHORT_DELAY );
- }
+ QueueHandle_t xQueue = ( QueueHandle_t ) pvParameters;
+ uint32_t ulValue;
+
+ for( ; ; )
+ {
+ /* Write some data to the queue. This should unblock the highest
+ * priority task that is waiting to peek data from the queue. */
+ ulValue = 0x11223344;
+
+ if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+ {
+ /* We were expecting the queue to be empty so we should not of
+ * had a problem writing to the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* By the time we get here the data should have been removed from
+ * the queue. */
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Write another value to the queue, again waking the highest priority
+ * task that is blocked on the queue. */
+ ulValue = 0x01234567;
+
+ if( xQueueSendToBack( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+ {
+ /* We were expecting the queue to be empty so we should not of
+ * had a problem writing to the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* All the other tasks should now have successfully peeked the data.
+ * The data is still in the queue so we should be able to receive it. */
+ ulValue = 0;
+
+ if( xQueueReceive( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+ {
+ /* We expected to receive the data. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( ulValue != 0x01234567 )
+ {
+ /* We did not receive the expected value. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Lets just delay a while as this is an intensive test as we don't
+ * want to starve other tests of processing time. */
+ vTaskDelay( qpeekSHORT_DELAY );
+
+ /* Unsuspend the other tasks so we can repeat the test - this time
+ * however not all the other tasks will peek the data as the high
+ * priority task is actually going to remove it from the queue. Send
+ * to front is used just to be different. As the queue is empty it
+ * makes no difference to the result. */
+ vTaskResume( xMediumPriorityTask );
+ vTaskResume( xHighPriorityTask );
+ vTaskResume( xHighestPriorityTask );
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ ulValue = 0xaabbaabb;
+
+ if( xQueueSendToFront( xQueue, &ulValue, qpeekNO_BLOCK ) != pdPASS )
+ {
+ /* We were expecting the queue to be empty so we should not of
+ * had a problem writing to the queue. */
+ xErrorDetected = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* This time we should find that the queue is empty. The high priority
+ * task actually removed the data rather than just peeking it. */
+ if( xQueuePeek( xQueue, &ulValue, qpeekNO_BLOCK ) != errQUEUE_EMPTY )
+ {
+ /* We expected to receive the data. */
+ xErrorDetected = pdTRUE;
+ }
+
+ /* Unsuspend the highest and high priority tasks so we can go back
+ * and repeat the whole thing. The medium priority task should not be
+ * suspended as it was not able to peek the data in this last case. */
+ vTaskResume( xHighPriorityTask );
+ vTaskResume( xHighestPriorityTask );
+
+ /* Lets just delay a while as this is an intensive test as we don't
+ * want to starve other tests of processing time. */
+ vTaskDelay( qpeekSHORT_DELAY );
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreQueuePeekTasksStillRunning( void )
{
-static uint32_t ulLastLoopCounter = 0;
+ static uint32_t ulLastLoopCounter = 0;
- /* If the demo task is still running then we expect the loopcounter to
- have incremented since this function was last called. */
- if( ulLastLoopCounter == ulLoopCounter )
- {
- xErrorDetected = pdTRUE;
- }
+ /* If the demo task is still running then we expect the loopcounter to
+ * have incremented since this function was last called. */
+ if( ulLastLoopCounter == ulLoopCounter )
+ {
+ xErrorDetected = pdTRUE;
+ }
- ulLastLoopCounter = ulLoopCounter;
+ ulLastLoopCounter = ulLoopCounter;
- /* Errors detected in the task itself will have latched xErrorDetected
- to true. */
+ /* Errors detected in the task itself will have latched xErrorDetected
+ * to true. */
- return ( BaseType_t ) !xErrorDetected;
+ return ( BaseType_t ) !xErrorDetected;
}
-
diff --git a/Demo/Common/Minimal/QueueOverwrite.c b/Demo/Common/Minimal/QueueOverwrite.c
index 2323b4de6..82fa8c557 100644
--- a/Demo/Common/Minimal/QueueOverwrite.c
+++ b/Demo/Common/Minimal/QueueOverwrite.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -39,192 +39,198 @@
#include "QueueOverwrite.h"
/* A block time of 0 just means "don't block". */
-#define qoDONT_BLOCK 0
+#define qoDONT_BLOCK 0
/* Number of times to overwrite the value in the queue. */
-#define qoLOOPS 5
+#define qoLOOPS 5
/* The task that uses the queue. */
-static void prvQueueOverwriteTask( void *pvParameters );
+static void prvQueueOverwriteTask( void * pvParameters );
/* Variable that is incremented on each loop of prvQueueOverwriteTask() provided
-prvQueueOverwriteTask() has not found any errors. */
+ * prvQueueOverwriteTask() has not found any errors. */
static uint32_t ulLoopCounter = 0;
/* Set to pdFALSE if an error is discovered by the
-vQueueOverwritePeriodicISRDemo() function. */
+ * vQueueOverwritePeriodicISRDemo() function. */
static BaseType_t xISRTestStatus = pdPASS;
/* The queue that is accessed from the ISR. The queue accessed by the task is
-created inside the task itself. */
+ * created inside the task itself. */
static QueueHandle_t xISRQueue = NULL;
/*-----------------------------------------------------------*/
void vStartQueueOverwriteTask( UBaseType_t uxPriority )
{
-const UBaseType_t uxQueueLength = 1;
+ const UBaseType_t uxQueueLength = 1;
- /* Create the queue used by the ISR. xQueueOverwriteFromISR() should only
- be used on queues that have a length of 1. */
- xISRQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) );
+ /* Create the queue used by the ISR. xQueueOverwriteFromISR() should only
+ * be used on queues that have a length of 1. */
+ xISRQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) );
- /* Create the test task. The queue used by the test task is created inside
- the task itself. */
- xTaskCreate( prvQueueOverwriteTask, "QOver", configMINIMAL_STACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+ /* Create the test task. The queue used by the test task is created inside
+ * the task itself. */
+ xTaskCreate( prvQueueOverwriteTask, "QOver", configMINIMAL_STACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
}
/*-----------------------------------------------------------*/
-static void prvQueueOverwriteTask( void *pvParameters )
+static void prvQueueOverwriteTask( void * pvParameters )
{
-QueueHandle_t xTaskQueue;
-const UBaseType_t uxQueueLength = 1;
-uint32_t ulValue, ulStatus = pdPASS, x;
-
- /* The parameter is not used. */
- ( void ) pvParameters;
-
- /* Create the queue. xQueueOverwrite() should only be used on queues that
- have a length of 1. */
- xTaskQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) );
- configASSERT( xTaskQueue );
-
- for( ;; )
- {
- /* The queue is empty. Writing to the queue then reading from the queue
- should return the item written. */
- ulValue = 10;
- xQueueOverwrite( xTaskQueue, &ulValue );
-
- ulValue = 0;
- xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK );
-
- if( ulValue != 10 )
- {
- ulStatus = pdFAIL;
- }
-
- /* Now try writing to the queue several times. Each time the value
- in the queue should get overwritten. */
- for( x = 0; x < qoLOOPS; x++ )
- {
- /* Write to the queue. */
- xQueueOverwrite( xTaskQueue, &x );
-
- /* Check the value in the queue is that written, even though the
- queue was not necessarily empty. */
- xQueuePeek( xTaskQueue, &ulValue, qoDONT_BLOCK );
- if( ulValue != x )
- {
- ulStatus = pdFAIL;
- }
-
- /* There should always be one item in the queue. */
- if( uxQueueMessagesWaiting( xTaskQueue ) != uxQueueLength )
- {
- ulStatus = pdFAIL;
- }
- }
-
- /* Empty the queue again. */
- xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK );
-
- if( uxQueueMessagesWaiting( xTaskQueue ) != 0 )
- {
- ulStatus = pdFAIL;
- }
-
- if( ulStatus != pdFAIL )
- {
- /* Increment a counter to show this task is still running without
- error. */
- ulLoopCounter++;
- }
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
- }
+ QueueHandle_t xTaskQueue;
+ const UBaseType_t uxQueueLength = 1;
+ uint32_t ulValue, ulStatus = pdPASS, x;
+
+ /* The parameter is not used. */
+ ( void ) pvParameters;
+
+ /* Create the queue. xQueueOverwrite() should only be used on queues that
+ * have a length of 1. */
+ xTaskQueue = xQueueCreate( uxQueueLength, ( UBaseType_t ) sizeof( uint32_t ) );
+ configASSERT( xTaskQueue );
+
+ for( ; ; )
+ {
+ /* The queue is empty. Writing to the queue then reading from the queue
+ * should return the item written. */
+ ulValue = 10;
+ xQueueOverwrite( xTaskQueue, &ulValue );
+
+ ulValue = 0;
+ xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK );
+
+ if( ulValue != 10 )
+ {
+ ulStatus = pdFAIL;
+ }
+
+ /* Now try writing to the queue several times. Each time the value
+ * in the queue should get overwritten. */
+ for( x = 0; x < qoLOOPS; x++ )
+ {
+ /* Write to the queue. */
+ xQueueOverwrite( xTaskQueue, &x );
+
+ /* Check the value in the queue is that written, even though the
+ * queue was not necessarily empty. */
+ xQueuePeek( xTaskQueue, &ulValue, qoDONT_BLOCK );
+
+ if( ulValue != x )
+ {
+ ulStatus = pdFAIL;
+ }
+
+ /* There should always be one item in the queue. */
+ if( uxQueueMessagesWaiting( xTaskQueue ) != uxQueueLength )
+ {
+ ulStatus = pdFAIL;
+ }
+ }
+
+ /* Empty the queue again. */
+ xQueueReceive( xTaskQueue, &ulValue, qoDONT_BLOCK );
+
+ if( uxQueueMessagesWaiting( xTaskQueue ) != 0 )
+ {
+ ulStatus = pdFAIL;
+ }
+
+ if( ulStatus != pdFAIL )
+ {
+ /* Increment a counter to show this task is still running without
+ * error. */
+ ulLoopCounter++;
+ }
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xIsQueueOverwriteTaskStillRunning( void )
{
-BaseType_t xReturn;
-
- if( xISRTestStatus != pdPASS )
- {
- xReturn = pdFAIL;
- }
- else if( ulLoopCounter > 0 )
- {
- xReturn = pdPASS;
- }
- else
- {
- /* The task has either stalled of discovered an error. */
- xReturn = pdFAIL;
- }
-
- ulLoopCounter = 0;
-
- return xReturn;
+ BaseType_t xReturn;
+
+ if( xISRTestStatus != pdPASS )
+ {
+ xReturn = pdFAIL;
+ }
+ else if( ulLoopCounter > 0 )
+ {
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* The task has either stalled of discovered an error. */
+ xReturn = pdFAIL;
+ }
+
+ ulLoopCounter = 0;
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
void vQueueOverwritePeriodicISRDemo( void )
{
-static uint32_t ulCallCount = 0;
-const uint32_t ulTx1 = 10UL, ulTx2 = 20UL, ulNumberOfSwitchCases = 3UL;
-uint32_t ulRx;
-
- /* This function should be called from an interrupt, such as the tick hook
- function vApplicationTickHook(). */
-
- configASSERT( xISRQueue );
-
- switch( ulCallCount )
- {
- case 0:
- /* The queue is empty. Write ulTx1 to the queue. In this demo the
- last parameter is not used because there are no tasks blocked on
- this queue. */
- xQueueOverwriteFromISR( xISRQueue, &ulTx1, NULL );
-
- /* Peek the queue to check it holds the expected value. */
- xQueuePeekFromISR( xISRQueue, &ulRx );
- if( ulRx != ulTx1 )
- {
- xISRTestStatus = pdFAIL;
- }
- break;
-
- case 1:
- /* The queue already holds ulTx1. Overwrite the value in the queue
- with ulTx2. */
- xQueueOverwriteFromISR( xISRQueue, &ulTx2, NULL );
- break;
-
- case 2:
- /* Read from the queue to empty the queue again. The value read
- should be ulTx2. */
- xQueueReceiveFromISR( xISRQueue, &ulRx, NULL );
-
- if( ulRx != ulTx2 )
- {
- xISRTestStatus = pdFAIL;
- }
- break;
- }
-
- /* Run the next case in the switch statement above next time this function
- is called. */
- ulCallCount++;
-
- if( ulCallCount >= ulNumberOfSwitchCases )
- {
- /* Go back to the start. */
- ulCallCount = 0;
- }
-}
+ static uint32_t ulCallCount = 0;
+ const uint32_t ulTx1 = 10UL, ulTx2 = 20UL, ulNumberOfSwitchCases = 3UL;
+ uint32_t ulRx;
+
+ /* This function should be called from an interrupt, such as the tick hook
+ * function vApplicationTickHook(). */
+
+ configASSERT( xISRQueue );
+
+ switch( ulCallCount )
+ {
+ case 0:
+
+ /* The queue is empty. Write ulTx1 to the queue. In this demo the
+ * last parameter is not used because there are no tasks blocked on
+ * this queue. */
+ xQueueOverwriteFromISR( xISRQueue, &ulTx1, NULL );
+
+ /* Peek the queue to check it holds the expected value. */
+ xQueuePeekFromISR( xISRQueue, &ulRx );
+
+ if( ulRx != ulTx1 )
+ {
+ xISRTestStatus = pdFAIL;
+ }
+
+ break;
+ case 1:
+
+ /* The queue already holds ulTx1. Overwrite the value in the queue
+ * with ulTx2. */
+ xQueueOverwriteFromISR( xISRQueue, &ulTx2, NULL );
+ break;
+
+ case 2:
+
+ /* Read from the queue to empty the queue again. The value read
+ * should be ulTx2. */
+ xQueueReceiveFromISR( xISRQueue, &ulRx, NULL );
+
+ if( ulRx != ulTx2 )
+ {
+ xISRTestStatus = pdFAIL;
+ }
+
+ break;
+ }
+
+ /* Run the next case in the switch statement above next time this function
+ * is called. */
+ ulCallCount++;
+
+ if( ulCallCount >= ulNumberOfSwitchCases )
+ {
+ /* Go back to the start. */
+ ulCallCount = 0;
+ }
+}
diff --git a/Demo/Common/Minimal/QueueSet.c b/Demo/Common/Minimal/QueueSet.c
index 0c0e6de26..4e21e93c9 100644
--- a/Demo/Common/Minimal/QueueSet.c
+++ b/Demo/Common/Minimal/QueueSet.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -52,66 +52,66 @@
#include "QueueSet.h"
-#if( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */
+#if ( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */
/* The number of queues that are created and added to the queue set. */
-#define queuesetNUM_QUEUES_IN_SET 3
+ #define queuesetNUM_QUEUES_IN_SET 3
/* The length of each created queue. */
-#define queuesetQUEUE_LENGTH 3
+ #define queuesetQUEUE_LENGTH 3
/* Block times used in this demo. A block time or 0 means "don't block". */
-#define queuesetSHORT_DELAY 200
-#define queuesetDONT_BLOCK 0
+ #define queuesetSHORT_DELAY 200
+ #define queuesetDONT_BLOCK 0
/* Messages are sent in incrementing order from both a task and an interrupt.
-The task sends values in the range 0 to 0xfffe, and the interrupt sends values
-in the range of 0xffff to ULONG_MAX. */
-#define queuesetINITIAL_ISR_TX_VALUE 0xffffUL
+ * The task sends values in the range 0 to 0xfffe, and the interrupt sends values
+ * in the range of 0xffff to ULONG_MAX. */
+ #define queuesetINITIAL_ISR_TX_VALUE 0xffffUL
/* The priorities used in this demo. */
-#define queuesetLOW_PRIORITY ( tskIDLE_PRIORITY )
-#define queuesetMEDIUM_PRIORITY ( queuesetLOW_PRIORITY + 1 )
+ #define queuesetLOW_PRIORITY ( tskIDLE_PRIORITY )
+ #define queuesetMEDIUM_PRIORITY ( queuesetLOW_PRIORITY + 1 )
/* For test purposes the priority of the sending task is changed after every
-queuesetPRIORITY_CHANGE_LOOPS number of values are sent to a queue. */
-#define queuesetPRIORITY_CHANGE_LOOPS ( ( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH ) * 2 )
+ * queuesetPRIORITY_CHANGE_LOOPS number of values are sent to a queue. */
+ #define queuesetPRIORITY_CHANGE_LOOPS ( ( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH ) * 2 )
/* The ISR sends to the queue every queuesetISR_TX_PERIOD ticks. */
-#define queuesetISR_TX_PERIOD ( 100UL )
+ #define queuesetISR_TX_PERIOD ( 100UL )
/* A delay inserted when the Tx task changes its priority to be above the idle
-task priority to ensure the idle priority tasks get some CPU time before the
-next iteration of the queue set Tx task. */
-#define queuesetTX_LOOP_DELAY pdMS_TO_TICKS( ( TickType_t ) 200 )
+ * task priority to ensure the idle priority tasks get some CPU time before the
+ * next iteration of the queue set Tx task. */
+ #define queuesetTX_LOOP_DELAY pdMS_TO_TICKS( ( TickType_t ) 200 )
/* The allowable maximum deviation between a received value and the expected
-received value. A deviation will occur when data is received from a queue
-inside an ISR in between a task receiving from a queue and the task checking
-the received value. */
-#define queuesetALLOWABLE_RX_DEVIATION 3
+ * received value. A deviation will occur when data is received from a queue
+ * inside an ISR in between a task receiving from a queue and the task checking
+ * the received value. */
+ #define queuesetALLOWABLE_RX_DEVIATION 3
/* Ignore values that are at the boundaries of allowable values to make the
-testing of limits easier (don't have to deal with wrapping values). */
-#define queuesetIGNORED_BOUNDARY ( queuesetALLOWABLE_RX_DEVIATION * 2 )
+ * testing of limits easier (don't have to deal with wrapping values). */
+ #define queuesetIGNORED_BOUNDARY ( queuesetALLOWABLE_RX_DEVIATION * 2 )
-typedef enum
-{
- eEqualPriority = 0, /* Tx and Rx tasks have the same priority. */
- eTxHigherPriority, /* The priority of the Tx task is above that of the Rx task. */
- eTxLowerPriority /* The priority of the Tx task is below that of the Rx task. */
-} eRelativePriorities;
+ typedef enum
+ {
+ eEqualPriority = 0, /* Tx and Rx tasks have the same priority. */
+ eTxHigherPriority, /* The priority of the Tx task is above that of the Rx task. */
+ eTxLowerPriority /* The priority of the Tx task is below that of the Rx task. */
+ } eRelativePriorities;
/*
* The task that periodically sends to the queue set.
*/
-static void prvQueueSetSendingTask( void *pvParameters );
+ static void prvQueueSetSendingTask( void * pvParameters );
/*
* The task that reads from the queue set.
*/
-static void prvQueueSetReceivingTask( void *pvParameters );
+ static void prvQueueSetReceivingTask( void * pvParameters );
/*
* Check the value received from a queue is the expected value. Some values
@@ -119,999 +119,1043 @@ static void prvQueueSetReceivingTask( void *pvParameters );
* range of the value being used to distinguish between the two message
* sources.
*/
-static void prvCheckReceivedValue( uint32_t ulReceived );
+ static void prvCheckReceivedValue( uint32_t ulReceived );
/*
* For purposes of test coverage, functions that read from and write to a
* queue set from an ISR respectively.
*/
-static void prvReceiveFromQueueInSetFromISR( void );
-static void prvSendToQueueInSetFromISR( void );
+ static void prvReceiveFromQueueInSetFromISR( void );
+ static void prvSendToQueueInSetFromISR( void );
/*
* Create the queues and add them to a queue set before resuming the Tx
* task.
*/
-static void prvSetupTest( void );
+ static void prvSetupTest( void );
/*
* Checks a value received from a queue falls within the range of expected
* values.
*/
-static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived, uint32_t ulExpectedReceived );
+ static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived,
+ uint32_t ulExpectedReceived );
/*
* Increase test coverage by occasionally change the priorities of the two tasks
* relative to each other.
*/
-static void prvChangeRelativePriorities( void );
+ static void prvChangeRelativePriorities( void );
/*
* Queue overwrites can only be performed on queues of length of one, requiring
* a special test function so a queue of length 1 can temporarily be added to a
* set.
*/
-static void prvTestQueueOverwriteWithQueueSet( void );
+ static void prvTestQueueOverwriteWithQueueSet( void );
/*
* Test the case where two queues within a set are written to with
* xQueueOverwrite().
*/
-static void prvTestQueueOverwriteOnTwoQueusInQueueSet( void );
-static void prvTestQueueOverwriteFromISROnTwoQueusInQueueSet( void );
+ static void prvTestQueueOverwriteOnTwoQueusInQueueSet( void );
+ static void prvTestQueueOverwriteFromISROnTwoQueusInQueueSet( void );
/*
* Local pseudo random number seed and return functions. Used to avoid calls
* to the standard library.
*/
-static size_t prvRand( void );
-static void prvSRand( size_t uxSeed );
+ static size_t prvRand( void );
+ static void prvSRand( size_t uxSeed );
/*-----------------------------------------------------------*/
/* The queues that are added to the set. */
-static QueueHandle_t xQueues[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
+ static QueueHandle_t xQueues[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
/* Counts how many times each queue in the set is used to ensure all the
-queues are used. */
-static uint32_t ulQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
+ * queues are used. */
+ static uint32_t ulQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
/* The handle of the queue set to which the queues are added. */
-static QueueSetHandle_t xQueueSet;
+ static QueueSetHandle_t xQueueSet;
/* If the prvQueueSetReceivingTask() task has not detected any errors then
-it increments ulCycleCounter on each iteration.
-xAreQueueSetTasksStillRunning() returns pdPASS if the value of
-ulCycleCounter has changed between consecutive calls, and pdFALSE if
-ulCycleCounter has stopped incrementing (indicating an error condition). */
-static volatile uint32_t ulCycleCounter = 0UL;
+ * it increments ulCycleCounter on each iteration.
+ * xAreQueueSetTasksStillRunning() returns pdPASS if the value of
+ * ulCycleCounter has changed between consecutive calls, and pdFALSE if
+ * ulCycleCounter has stopped incrementing (indicating an error condition). */
+ static volatile uint32_t ulCycleCounter = 0UL;
/* Set to pdFAIL if an error is detected by any queue set task.
-ulCycleCounter will only be incremented if xQueueSetTasksSatus equals pdPASS. */
-static volatile BaseType_t xQueueSetTasksStatus = pdPASS;
+ * ulCycleCounter will only be incremented if xQueueSetTasksSatus equals pdPASS. */
+ static volatile BaseType_t xQueueSetTasksStatus = pdPASS;
/* Just a flag to let the function that writes to a queue from an ISR know that
-the queues are setup and can be used. */
-static volatile BaseType_t xSetupComplete = pdFALSE;
+ * the queues are setup and can be used. */
+ static volatile BaseType_t xSetupComplete = pdFALSE;
/* The value sent to the queue from the ISR is file scope so the
-xAreQueeuSetTasksStillRunning() function can check it is incrementing as
-expected. */
-static volatile uint32_t ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
+ * xAreQueeuSetTasksStillRunning() function can check it is incrementing as
+ * expected. */
+ static volatile uint32_t ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
/* Used by the pseudo random number generator. */
-static size_t uxNextRand = 0;
+ static size_t uxNextRand = 0;
/* The task handles are stored so their priorities can be changed. */
-TaskHandle_t xQueueSetSendingTask, xQueueSetReceivingTask;
+ TaskHandle_t xQueueSetSendingTask, xQueueSetReceivingTask;
/*-----------------------------------------------------------*/
-void vStartQueueSetTasks( void )
-{
- /* Create the tasks. */
- xTaskCreate( prvQueueSetSendingTask, "SetTx", configMINIMAL_STACK_SIZE, NULL, queuesetMEDIUM_PRIORITY, &xQueueSetSendingTask );
-
- if( xQueueSetSendingTask != NULL )
- {
- xTaskCreate( prvQueueSetReceivingTask, "SetRx", configMINIMAL_STACK_SIZE, ( void * ) xQueueSetSendingTask, queuesetMEDIUM_PRIORITY, &xQueueSetReceivingTask );
-
- /* It is important that the sending task does not attempt to write to a
- queue before the queue has been created. It is therefore placed into
- the suspended state before the scheduler has started. It is resumed by
- the receiving task after the receiving task has created the queues and
- added the queues to the queue set. */
- vTaskSuspend( xQueueSetSendingTask );
- }
-}
+ void vStartQueueSetTasks( void )
+ {
+ /* Create the tasks. */
+ xTaskCreate( prvQueueSetSendingTask, "SetTx", configMINIMAL_STACK_SIZE, NULL, queuesetMEDIUM_PRIORITY, &xQueueSetSendingTask );
+
+ if( xQueueSetSendingTask != NULL )
+ {
+ xTaskCreate( prvQueueSetReceivingTask, "SetRx", configMINIMAL_STACK_SIZE, ( void * ) xQueueSetSendingTask, queuesetMEDIUM_PRIORITY, &xQueueSetReceivingTask );
+
+ /* It is important that the sending task does not attempt to write to a
+ * queue before the queue has been created. It is therefore placed into
+ * the suspended state before the scheduler has started. It is resumed by
+ * the receiving task after the receiving task has created the queues and
+ * added the queues to the queue set. */
+ vTaskSuspend( xQueueSetSendingTask );
+ }
+ }
/*-----------------------------------------------------------*/
-BaseType_t xAreQueueSetTasksStillRunning( void )
-{
-static uint32_t ulLastCycleCounter, ulLastISRTxValue = 0;
-static uint32_t ulLastQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
-BaseType_t xReturn = pdPASS, x;
-
- if( ulLastCycleCounter == ulCycleCounter )
- {
- /* The cycle counter is no longer being incremented. Either one of the
- tasks is stalled or an error has been detected. */
- xReturn = pdFAIL;
- }
-
- ulLastCycleCounter = ulCycleCounter;
-
- /* Ensure that all the queues in the set have been used. This ensures the
- test is working as intended and guards against the rand() in the Tx task
- missing some values. */
- for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ )
- {
- if( ulLastQueueUsedCounter[ x ] == ulQueueUsedCounter[ x ] )
- {
- xReturn = pdFAIL;
- }
-
- ulLastQueueUsedCounter[ x ] = ulQueueUsedCounter[ x ];
- }
-
- /* Check the global status flag. */
- if( xQueueSetTasksStatus != pdPASS )
- {
- xReturn = pdFAIL;
- }
-
- /* Check that the ISR is still sending values to the queues too. */
- if( ulISRTxValue == ulLastISRTxValue )
- {
- xReturn = pdFAIL;
- }
- else
- {
- ulLastISRTxValue = ulISRTxValue;
- }
-
- return xReturn;
-}
+ BaseType_t xAreQueueSetTasksStillRunning( void )
+ {
+ static uint32_t ulLastCycleCounter, ulLastISRTxValue = 0;
+ static uint32_t ulLastQueueUsedCounter[ queuesetNUM_QUEUES_IN_SET ] = { 0 };
+ BaseType_t xReturn = pdPASS, x;
+
+ if( ulLastCycleCounter == ulCycleCounter )
+ {
+ /* The cycle counter is no longer being incremented. Either one of the
+ * tasks is stalled or an error has been detected. */
+ xReturn = pdFAIL;
+ }
+
+ ulLastCycleCounter = ulCycleCounter;
+
+ /* Ensure that all the queues in the set have been used. This ensures the
+ * test is working as intended and guards against the rand() in the Tx task
+ * missing some values. */
+ for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ )
+ {
+ if( ulLastQueueUsedCounter[ x ] == ulQueueUsedCounter[ x ] )
+ {
+ xReturn = pdFAIL;
+ }
+
+ ulLastQueueUsedCounter[ x ] = ulQueueUsedCounter[ x ];
+ }
+
+ /* Check the global status flag. */
+ if( xQueueSetTasksStatus != pdPASS )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Check that the ISR is still sending values to the queues too. */
+ if( ulISRTxValue == ulLastISRTxValue )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ulLastISRTxValue = ulISRTxValue;
+ }
+
+ return xReturn;
+ }
/*-----------------------------------------------------------*/
-static void prvQueueSetSendingTask( void *pvParameters )
-{
-uint32_t ulTaskTxValue = 0;
-size_t uxQueueToWriteTo;
-QueueHandle_t xQueueInUse;
-
- /* Remove compiler warning about the unused parameter. */
- ( void ) pvParameters;
-
- /* Seed mini pseudo random number generator. */
- prvSRand( ( size_t ) &ulTaskTxValue );
-
- for( ;; )
- {
- /* Generate the index for the queue to which a value is to be sent. */
- uxQueueToWriteTo = prvRand() % queuesetNUM_QUEUES_IN_SET;
- xQueueInUse = xQueues[ uxQueueToWriteTo ];
-
- /* Note which index is being written to to ensure all the queues are
- used. */
- ( ulQueueUsedCounter[ uxQueueToWriteTo ] )++;
-
- /* Send to the queue to unblock the task that is waiting for data to
- arrive on a queue within the queue set to which this queue belongs. */
- if( xQueueSendToBack( xQueueInUse, &ulTaskTxValue, portMAX_DELAY ) != pdPASS )
- {
- /* The send should always pass as an infinite block time was
- used. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- ulTaskTxValue++;
-
- /* If the Tx value has reached the range used by the ISR then set it
- back to 0. */
- if( ulTaskTxValue == queuesetINITIAL_ISR_TX_VALUE )
- {
- ulTaskTxValue = 0;
- }
-
- /* Increase test coverage by occasionally change the priorities of the
- two tasks relative to each other. */
- prvChangeRelativePriorities();
- }
-}
+ static void prvQueueSetSendingTask( void * pvParameters )
+ {
+ uint32_t ulTaskTxValue = 0;
+ size_t uxQueueToWriteTo;
+ QueueHandle_t xQueueInUse;
+
+ /* Remove compiler warning about the unused parameter. */
+ ( void ) pvParameters;
+
+ /* Seed mini pseudo random number generator. */
+ prvSRand( ( size_t ) &ulTaskTxValue );
+
+ for( ; ; )
+ {
+ /* Generate the index for the queue to which a value is to be sent. */
+ uxQueueToWriteTo = prvRand() % queuesetNUM_QUEUES_IN_SET;
+ xQueueInUse = xQueues[ uxQueueToWriteTo ];
+
+ /* Note which index is being written to to ensure all the queues are
+ * used. */
+ ( ulQueueUsedCounter[ uxQueueToWriteTo ] )++;
+
+ /* Send to the queue to unblock the task that is waiting for data to
+ * arrive on a queue within the queue set to which this queue belongs. */
+ if( xQueueSendToBack( xQueueInUse, &ulTaskTxValue, portMAX_DELAY ) != pdPASS )
+ {
+ /* The send should always pass as an infinite block time was
+ * used. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ ulTaskTxValue++;
+
+ /* If the Tx value has reached the range used by the ISR then set it
+ * back to 0. */
+ if( ulTaskTxValue == queuesetINITIAL_ISR_TX_VALUE )
+ {
+ ulTaskTxValue = 0;
+ }
+
+ /* Increase test coverage by occasionally change the priorities of the
+ * two tasks relative to each other. */
+ prvChangeRelativePriorities();
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvChangeRelativePriorities( void )
-{
-static UBaseType_t ulLoops = 0;
-static eRelativePriorities ePriorities = eEqualPriority;
-
- /* Occasionally change the task priority relative to the priority of
- the receiving task. */
- ulLoops++;
- if( ulLoops >= queuesetPRIORITY_CHANGE_LOOPS )
- {
- ulLoops = 0;
-
- switch( ePriorities )
- {
- case eEqualPriority:
- /* Both tasks are running with medium priority. Now lower the
- priority of the receiving task so the Tx task has the higher
- relative priority. */
- vTaskPrioritySet( xQueueSetReceivingTask, queuesetLOW_PRIORITY );
- ePriorities = eTxHigherPriority;
- break;
-
- case eTxHigherPriority:
- /* The Tx task is running with a higher priority than the Rx
- task. Switch the priorities around so the Rx task has the
- higher relative priority. */
- vTaskPrioritySet( xQueueSetReceivingTask, queuesetMEDIUM_PRIORITY );
- vTaskPrioritySet( xQueueSetSendingTask, queuesetLOW_PRIORITY );
- ePriorities = eTxLowerPriority;
- break;
-
- case eTxLowerPriority:
- /* The Tx task is running with a lower priority than the Rx
- task. Make the priorities equal again. */
- vTaskPrioritySet( xQueueSetSendingTask, queuesetMEDIUM_PRIORITY );
- ePriorities = eEqualPriority;
-
- /* When both tasks are using a non-idle priority the queue set
- tasks will starve idle priority tasks of execution time - so
- relax a bit before the next iteration to minimise the impact. */
- vTaskDelay( queuesetTX_LOOP_DELAY );
-
- break;
- }
- }
-}
+ static void prvChangeRelativePriorities( void )
+ {
+ static UBaseType_t ulLoops = 0;
+ static eRelativePriorities ePriorities = eEqualPriority;
+
+ /* Occasionally change the task priority relative to the priority of
+ * the receiving task. */
+ ulLoops++;
+
+ if( ulLoops >= queuesetPRIORITY_CHANGE_LOOPS )
+ {
+ ulLoops = 0;
+
+ switch( ePriorities )
+ {
+ case eEqualPriority:
+
+ /* Both tasks are running with medium priority. Now lower the
+ * priority of the receiving task so the Tx task has the higher
+ * relative priority. */
+ vTaskPrioritySet( xQueueSetReceivingTask, queuesetLOW_PRIORITY );
+ ePriorities = eTxHigherPriority;
+ break;
+
+ case eTxHigherPriority:
+
+ /* The Tx task is running with a higher priority than the Rx
+ * task. Switch the priorities around so the Rx task has the
+ * higher relative priority. */
+ vTaskPrioritySet( xQueueSetReceivingTask, queuesetMEDIUM_PRIORITY );
+ vTaskPrioritySet( xQueueSetSendingTask, queuesetLOW_PRIORITY );
+ ePriorities = eTxLowerPriority;
+ break;
+
+ case eTxLowerPriority:
+
+ /* The Tx task is running with a lower priority than the Rx
+ * task. Make the priorities equal again. */
+ vTaskPrioritySet( xQueueSetSendingTask, queuesetMEDIUM_PRIORITY );
+ ePriorities = eEqualPriority;
+
+ /* When both tasks are using a non-idle priority the queue set
+ * tasks will starve idle priority tasks of execution time - so
+ * relax a bit before the next iteration to minimise the impact. */
+ vTaskDelay( queuesetTX_LOOP_DELAY );
+
+ break;
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvQueueSetReceivingTask( void *pvParameters )
-{
-uint32_t ulReceived;
-QueueHandle_t xActivatedQueue;
-TickType_t xBlockTime;
-
- /* Remove compiler warnings. */
- ( void ) pvParameters;
-
- /* Create the queues and add them to the queue set before resuming the Tx
- task. */
- prvSetupTest();
-
- for( ;; )
- {
- /* For test coverage reasons, the block time is dependent on the
- priority of this task - which changes during the test. When the task
- is at the idle priority it polls the queue set. */
- if( uxTaskPriorityGet( NULL ) == tskIDLE_PRIORITY )
- {
- xBlockTime = 0;
- }
- else
- {
- xBlockTime = portMAX_DELAY;
- }
-
- /* Wait for a message to arrive on one of the queues in the set. */
- xActivatedQueue = xQueueSelectFromSet( xQueueSet, portMAX_DELAY );
-
- if( xActivatedQueue == NULL )
- {
- if( xBlockTime != 0 )
- {
- /* This should not happen as an infinite delay was used. */
- xQueueSetTasksStatus = pdFAIL;
- }
- }
- else
- {
- /* Reading from the queue should pass with a zero block time as
- this task will only run when something has been posted to a task
- in the queue set. */
- if( xQueueReceive( xActivatedQueue, &ulReceived, queuesetDONT_BLOCK ) != pdPASS )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Ensure the value received was the value expected. This function
- manipulates file scope data and is also called from an ISR, hence
- the critical section. */
- taskENTER_CRITICAL();
- {
- prvCheckReceivedValue( ulReceived );
- }
- taskEXIT_CRITICAL();
-
- if( xQueueSetTasksStatus == pdPASS )
- {
- ulCycleCounter++;
- }
- }
- }
-}
+ static void prvQueueSetReceivingTask( void * pvParameters )
+ {
+ uint32_t ulReceived;
+ QueueHandle_t xActivatedQueue;
+ TickType_t xBlockTime;
+
+ /* Remove compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Create the queues and add them to the queue set before resuming the Tx
+ * task. */
+ prvSetupTest();
+
+ for( ; ; )
+ {
+ /* For test coverage reasons, the block time is dependent on the
+ * priority of this task - which changes during the test. When the task
+ * is at the idle priority it polls the queue set. */
+ if( uxTaskPriorityGet( NULL ) == tskIDLE_PRIORITY )
+ {
+ xBlockTime = 0;
+ }
+ else
+ {
+ xBlockTime = portMAX_DELAY;
+ }
+
+ /* Wait for a message to arrive on one of the queues in the set. */
+ xActivatedQueue = xQueueSelectFromSet( xQueueSet, portMAX_DELAY );
+
+ if( xActivatedQueue == NULL )
+ {
+ if( xBlockTime != 0 )
+ {
+ /* This should not happen as an infinite delay was used. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+ }
+ else
+ {
+ /* Reading from the queue should pass with a zero block time as
+ * this task will only run when something has been posted to a task
+ * in the queue set. */
+ if( xQueueReceive( xActivatedQueue, &ulReceived, queuesetDONT_BLOCK ) != pdPASS )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Ensure the value received was the value expected. This function
+ * manipulates file scope data and is also called from an ISR, hence
+ * the critical section. */
+ taskENTER_CRITICAL();
+ {
+ prvCheckReceivedValue( ulReceived );
+ }
+ taskEXIT_CRITICAL();
+
+ if( xQueueSetTasksStatus == pdPASS )
+ {
+ ulCycleCounter++;
+ }
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-void vQueueSetAccessQueueSetFromISR( void )
-{
-static uint32_t ulCallCount = 0;
-
- /* xSetupComplete is set to pdTRUE when the queues have been created and
- are available for use. */
- if( xSetupComplete == pdTRUE )
- {
- /* It is intended that this function is called from the tick hook
- function, so each call is one tick period apart. */
- ulCallCount++;
- if( ulCallCount > queuesetISR_TX_PERIOD )
- {
- ulCallCount = 0;
-
- /* First attempt to read from the queue set. */
- prvReceiveFromQueueInSetFromISR();
-
- /* Then write to the queue set. */
- prvSendToQueueInSetFromISR();
- }
- }
-}
+ void vQueueSetAccessQueueSetFromISR( void )
+ {
+ static uint32_t ulCallCount = 0;
+
+ /* xSetupComplete is set to pdTRUE when the queues have been created and
+ * are available for use. */
+ if( xSetupComplete == pdTRUE )
+ {
+ /* It is intended that this function is called from the tick hook
+ * function, so each call is one tick period apart. */
+ ulCallCount++;
+
+ if( ulCallCount > queuesetISR_TX_PERIOD )
+ {
+ ulCallCount = 0;
+
+ /* First attempt to read from the queue set. */
+ prvReceiveFromQueueInSetFromISR();
+
+ /* Then write to the queue set. */
+ prvSendToQueueInSetFromISR();
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvCheckReceivedValue( uint32_t ulReceived )
-{
-static uint32_t ulExpectedReceivedFromTask = 0, ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE;
-
- /* Values are received in tasks and interrupts. It is likely that the
- receiving task will sometimes get preempted by the receiving interrupt
- between reading a value from the queue and calling this function. When
- that happens, if the receiving interrupt calls this function the values
- will get passed into this function slightly out of order. For that
- reason the value passed in is tested against a small range of expected
- values, rather than a single absolute value. To make the range testing
- easier values in the range limits are ignored. */
-
- /* If the received value is equal to or greater than
- queuesetINITIAL_ISR_TX_VALUE then it was sent by an ISR. */
- if( ulReceived >= queuesetINITIAL_ISR_TX_VALUE )
- {
- /* The value was sent from the ISR. */
- if( ( ulReceived - queuesetINITIAL_ISR_TX_VALUE ) < queuesetIGNORED_BOUNDARY )
- {
- /* The value received is at the lower limit of the expected range.
- Don't test it and expect to receive one higher next time. */
- }
- else if( ( ULONG_MAX - ulReceived ) <= queuesetIGNORED_BOUNDARY )
- {
- /* The value received is at the higher limit of the expected range.
- Don't test it and expect to wrap soon. */
- }
- else
- {
- /* Check the value against its expected value range. */
- if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromISR ) != pdPASS )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
- }
-
- configASSERT( xQueueSetTasksStatus );
-
- /* It is expected to receive an incrementing number. */
- ulExpectedReceivedFromISR++;
- if( ulExpectedReceivedFromISR == 0 )
- {
- ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE;
- }
- }
- else
- {
- /* The value was sent from the Tx task. */
- if( ulReceived < queuesetIGNORED_BOUNDARY )
- {
- /* The value received is at the lower limit of the expected range.
- Don't test it, and expect to receive one higher next time. */
- }
- else if( ( ( queuesetINITIAL_ISR_TX_VALUE - 1 ) - ulReceived ) <= queuesetIGNORED_BOUNDARY )
- {
- /* The value received is at the higher limit of the expected range.
- Don't test it and expect to wrap soon. */
- }
- else
- {
- /* Check the value against its expected value range. */
- if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromTask ) != pdPASS )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
- }
-
- configASSERT( xQueueSetTasksStatus );
-
- /* It is expected to receive an incrementing number. */
- ulExpectedReceivedFromTask++;
- if( ulExpectedReceivedFromTask >= queuesetINITIAL_ISR_TX_VALUE )
- {
- ulExpectedReceivedFromTask = 0;
- }
- }
-}
+ static void prvCheckReceivedValue( uint32_t ulReceived )
+ {
+ static uint32_t ulExpectedReceivedFromTask = 0, ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE;
+
+ /* Values are received in tasks and interrupts. It is likely that the
+ * receiving task will sometimes get preempted by the receiving interrupt
+ * between reading a value from the queue and calling this function. When
+ * that happens, if the receiving interrupt calls this function the values
+ * will get passed into this function slightly out of order. For that
+ * reason the value passed in is tested against a small range of expected
+ * values, rather than a single absolute value. To make the range testing
+ * easier values in the range limits are ignored. */
+
+ /* If the received value is equal to or greater than
+ * queuesetINITIAL_ISR_TX_VALUE then it was sent by an ISR. */
+ if( ulReceived >= queuesetINITIAL_ISR_TX_VALUE )
+ {
+ /* The value was sent from the ISR. */
+ if( ( ulReceived - queuesetINITIAL_ISR_TX_VALUE ) < queuesetIGNORED_BOUNDARY )
+ {
+ /* The value received is at the lower limit of the expected range.
+ * Don't test it and expect to receive one higher next time. */
+ }
+ else if( ( ULONG_MAX - ulReceived ) <= queuesetIGNORED_BOUNDARY )
+ {
+ /* The value received is at the higher limit of the expected range.
+ * Don't test it and expect to wrap soon. */
+ }
+ else
+ {
+ /* Check the value against its expected value range. */
+ if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromISR ) != pdPASS )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+ }
+
+ configASSERT( xQueueSetTasksStatus );
+
+ /* It is expected to receive an incrementing number. */
+ ulExpectedReceivedFromISR++;
+
+ if( ulExpectedReceivedFromISR == 0 )
+ {
+ ulExpectedReceivedFromISR = queuesetINITIAL_ISR_TX_VALUE;
+ }
+ }
+ else
+ {
+ /* The value was sent from the Tx task. */
+ if( ulReceived < queuesetIGNORED_BOUNDARY )
+ {
+ /* The value received is at the lower limit of the expected range.
+ * Don't test it, and expect to receive one higher next time. */
+ }
+ else if( ( ( queuesetINITIAL_ISR_TX_VALUE - 1 ) - ulReceived ) <= queuesetIGNORED_BOUNDARY )
+ {
+ /* The value received is at the higher limit of the expected range.
+ * Don't test it and expect to wrap soon. */
+ }
+ else
+ {
+ /* Check the value against its expected value range. */
+ if( prvCheckReceivedValueWithinExpectedRange( ulReceived, ulExpectedReceivedFromTask ) != pdPASS )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+ }
+
+ configASSERT( xQueueSetTasksStatus );
+
+ /* It is expected to receive an incrementing number. */
+ ulExpectedReceivedFromTask++;
+
+ if( ulExpectedReceivedFromTask >= queuesetINITIAL_ISR_TX_VALUE )
+ {
+ ulExpectedReceivedFromTask = 0;
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived, uint32_t ulExpectedReceived )
-{
-BaseType_t xReturn = pdPASS;
-
- if( ulReceived > ulExpectedReceived )
- {
- configASSERT( ( ulReceived - ulExpectedReceived ) <= queuesetALLOWABLE_RX_DEVIATION );
- if( ( ulReceived - ulExpectedReceived ) > queuesetALLOWABLE_RX_DEVIATION )
- {
- xReturn = pdFALSE;
- }
- }
- else
- {
- configASSERT( ( ulExpectedReceived - ulReceived ) <= queuesetALLOWABLE_RX_DEVIATION );
- if( ( ulExpectedReceived - ulReceived ) > queuesetALLOWABLE_RX_DEVIATION )
- {
- xReturn = pdFALSE;
- }
- }
-
- return xReturn;
-}
+ static BaseType_t prvCheckReceivedValueWithinExpectedRange( uint32_t ulReceived,
+ uint32_t ulExpectedReceived )
+ {
+ BaseType_t xReturn = pdPASS;
+
+ if( ulReceived > ulExpectedReceived )
+ {
+ configASSERT( ( ulReceived - ulExpectedReceived ) <= queuesetALLOWABLE_RX_DEVIATION );
+
+ if( ( ulReceived - ulExpectedReceived ) > queuesetALLOWABLE_RX_DEVIATION )
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ else
+ {
+ configASSERT( ( ulExpectedReceived - ulReceived ) <= queuesetALLOWABLE_RX_DEVIATION );
+
+ if( ( ulExpectedReceived - ulReceived ) > queuesetALLOWABLE_RX_DEVIATION )
+ {
+ xReturn = pdFALSE;
+ }
+ }
+
+ return xReturn;
+ }
/*-----------------------------------------------------------*/
-static void prvReceiveFromQueueInSetFromISR( void )
-{
-QueueSetMemberHandle_t xActivatedQueue;
-uint32_t ulReceived;
-
- /* See if any of the queues in the set contain data. */
- xActivatedQueue = xQueueSelectFromSetFromISR( xQueueSet );
-
- if( xActivatedQueue != NULL )
- {
- /* Reading from the queue for test purposes only. */
- if( xQueueReceiveFromISR( xActivatedQueue, &ulReceived, NULL ) != pdPASS )
- {
- /* Data should have been available as the handle was returned from
- xQueueSelectFromSetFromISR(). */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Ensure the value received was the value expected. */
- prvCheckReceivedValue( ulReceived );
- }
-}
+ static void prvReceiveFromQueueInSetFromISR( void )
+ {
+ QueueSetMemberHandle_t xActivatedQueue;
+ uint32_t ulReceived;
+
+ /* See if any of the queues in the set contain data. */
+ xActivatedQueue = xQueueSelectFromSetFromISR( xQueueSet );
+
+ if( xActivatedQueue != NULL )
+ {
+ /* Reading from the queue for test purposes only. */
+ if( xQueueReceiveFromISR( xActivatedQueue, &ulReceived, NULL ) != pdPASS )
+ {
+ /* Data should have been available as the handle was returned from
+ * xQueueSelectFromSetFromISR(). */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Ensure the value received was the value expected. */
+ prvCheckReceivedValue( ulReceived );
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvSendToQueueInSetFromISR( void )
-{
-static BaseType_t xQueueToWriteTo = 0;
-uint32_t ulTxValueSnapshot = ulISRTxValue;
-
- if( xQueueSendFromISR( xQueues[ xQueueToWriteTo ], ( void * ) &ulTxValueSnapshot, NULL ) == pdPASS )
- {
- ulISRTxValue++;
-
- /* If the Tx value has wrapped then set it back to its initial value. */
- if( ulISRTxValue == 0UL )
- {
- ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
- }
-
- /* Use a different queue next time. */
- xQueueToWriteTo++;
- if( xQueueToWriteTo >= queuesetNUM_QUEUES_IN_SET )
- {
- xQueueToWriteTo = 0;
- }
- }
-}
+ static void prvSendToQueueInSetFromISR( void )
+ {
+ static BaseType_t xQueueToWriteTo = 0;
+ uint32_t ulTxValueSnapshot = ulISRTxValue;
+
+ if( xQueueSendFromISR( xQueues[ xQueueToWriteTo ], ( void * ) &ulTxValueSnapshot, NULL ) == pdPASS )
+ {
+ ulISRTxValue++;
+
+ /* If the Tx value has wrapped then set it back to its initial value. */
+ if( ulISRTxValue == 0UL )
+ {
+ ulISRTxValue = queuesetINITIAL_ISR_TX_VALUE;
+ }
+
+ /* Use a different queue next time. */
+ xQueueToWriteTo++;
+
+ if( xQueueToWriteTo >= queuesetNUM_QUEUES_IN_SET )
+ {
+ xQueueToWriteTo = 0;
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvTestQueueOverwriteWithQueueSet( void )
-{
-uint32_t ulValueToSend = 0, ulValueReceived = 0;
-QueueHandle_t xQueueHandle = NULL, xReceivedHandle = NULL;
-const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
-
- /* Create a queue that has a length of one - a requirement in order to call
- xQueueOverwrite. This will get deleted again when this test completes. */
- xQueueHandle = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
- configASSERT( xQueueHandle );
-
- if( xQueueHandle != NULL )
- {
- xQueueAddToSet( xQueueHandle, xQueueSet );
-
- /* Add an item to the queue then ensure the queue set correctly
- indicates that one item is available, and that item is indeed the
- queue written to. */
- xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
- {
- /* Expected one item in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle )
- {
- /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
- held in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Now overwrite the value in the queue and ensure the queue set state
- doesn't change as the number of items in the queues within the set have
- not changed. */
- ulValueToSend++;
- xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
- {
- /* Still expected one item in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle )
- {
- /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
- held in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Also ensure the value received from the queue is the overwritten
- value, not the value originally written. */
- xQueueReceive( xQueueHandle, &ulValueReceived, queuesetDONT_BLOCK );
- if( ulValueReceived != ulValueToSend )
- {
- /* Unexpected value received from the queue. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Should be anything in the queue set now. */
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != NULL )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Clean up. */
- xQueueRemoveFromSet( xQueueHandle, xQueueSet );
- vQueueDelete( xQueueHandle );
- }
-}
+ static void prvTestQueueOverwriteWithQueueSet( void )
+ {
+ uint32_t ulValueToSend = 0, ulValueReceived = 0;
+ QueueHandle_t xQueueHandle = NULL, xReceivedHandle = NULL;
+ const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
+
+ /* Create a queue that has a length of one - a requirement in order to call
+ * xQueueOverwrite. This will get deleted again when this test completes. */
+ xQueueHandle = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
+ configASSERT( xQueueHandle );
+
+ if( xQueueHandle != NULL )
+ {
+ xQueueAddToSet( xQueueHandle, xQueueSet );
+
+ /* Add an item to the queue then ensure the queue set correctly
+ * indicates that one item is available, and that item is indeed the
+ * queue written to. */
+ xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+ {
+ /* Expected one item in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle )
+ {
+ /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+ * held in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Now overwrite the value in the queue and ensure the queue set state
+ * doesn't change as the number of items in the queues within the set have
+ * not changed. */
+ ulValueToSend++;
+ xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+ {
+ /* Still expected one item in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle )
+ {
+ /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+ * held in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Also ensure the value received from the queue is the overwritten
+ * value, not the value originally written. */
+ xQueueReceive( xQueueHandle, &ulValueReceived, queuesetDONT_BLOCK );
+
+ if( ulValueReceived != ulValueToSend )
+ {
+ /* Unexpected value received from the queue. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Should be anything in the queue set now. */
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != NULL )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Clean up. */
+ xQueueRemoveFromSet( xQueueHandle, xQueueSet );
+ vQueueDelete( xQueueHandle );
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvTestQueueOverwriteOnTwoQueusInQueueSet( void )
-{
-uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0;
-QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL;
-const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
-
- /* Create two queues that have a length of one - a requirement in order to call
- xQueueOverwrite. These will get deleted again when this test completes. */
- xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
- configASSERT( xQueueHandle1 );
- xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
- configASSERT( xQueueHandle2 );
-
- if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) )
- {
- /* Add both queues to the queue set. */
- xQueueAddToSet( xQueueHandle1, xQueueSet );
- xQueueAddToSet( xQueueHandle2, xQueueSet );
-
- /* Add an item using the first queue. */
- xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend1 );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
- {
- /* Expected one item in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle1 )
- {
- /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
- held in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
- /* Next add an item to the second queue. */
- xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend2 );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* The head of the queue set should not have changed though. */
- xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle1 )
- {
- /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
- held in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
-
-
- /* Now overwrite the value in the queue and ensure the queue set state
- doesn't change as the number of items in the queues within the set have
- not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue
- 2 should hold the value ulValueToSend1. */
- xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
- /* Repeat the above to ensure the queue set state doesn't change. */
- xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
- /* Now when reading from the queue set we expect the handle to the first
- queue to be received first, and for that queue to hold ulValueToSend2 as the
- originally written value was overwritten. Likewise the second handle received
- from the set should be that of the second queue, and that queue should hold
- ulValueToSend1 as the originally written value was overwritten. */
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle1 )
- {
- /* Wrote to xQueueHandle1 first so expected that handle to be read from
- the set first. */
- xQueueSetTasksStatus = pdFAIL;
- }
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
- {
- /* One value was read from the set, so now only expect a single value
- in the set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
- if( ulValueReceived != ulValueToSend2 )
- {
- /* Unexpected value received from the queue. ulValueToSend1 was written
- first, but then overwritten with ulValueToSend2; */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle2 )
- {
- /* xQueueHandle1 has already been removed from the set so expect only
- xQueueHandle2 to be left. */
- xQueueSetTasksStatus = pdFAIL;
- }
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 )
- {
- /* The last value was read from the set so don't expect any more. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
- if( ulValueReceived != ulValueToSend1 )
- {
- /* Unexpected value received from the queue. ulValueToSend2 was written
- first, but then overwritten with ulValueToSend1. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
-
-
- /* Should be anything in the queue set now. */
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != NULL )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Clean up. */
- xQueueRemoveFromSet( xQueueHandle1, xQueueSet );
- xQueueRemoveFromSet( xQueueHandle2, xQueueSet );
- vQueueDelete( xQueueHandle1 );
- vQueueDelete( xQueueHandle2 );
- }
-}
+ static void prvTestQueueOverwriteOnTwoQueusInQueueSet( void )
+ {
+ uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0;
+ QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL;
+ const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
+
+ /* Create two queues that have a length of one - a requirement in order to call
+ * xQueueOverwrite. These will get deleted again when this test completes. */
+ xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
+ configASSERT( xQueueHandle1 );
+ xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
+ configASSERT( xQueueHandle2 );
+
+ if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) )
+ {
+ /* Add both queues to the queue set. */
+ xQueueAddToSet( xQueueHandle1, xQueueSet );
+ xQueueAddToSet( xQueueHandle2, xQueueSet );
+
+ /* Add an item using the first queue. */
+ xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend1 );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+ {
+ /* Expected one item in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle1 )
+ {
+ /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+ * held in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Next add an item to the second queue. */
+ xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend2 );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* The head of the queue set should not have changed though. */
+ xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle1 )
+ {
+ /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+ * held in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Now overwrite the value in the queue and ensure the queue set state
+ * doesn't change as the number of items in the queues within the set have
+ * not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue
+ * 2 should hold the value ulValueToSend1. */
+ xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Repeat the above to ensure the queue set state doesn't change. */
+ xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Now when reading from the queue set we expect the handle to the first
+ * queue to be received first, and for that queue to hold ulValueToSend2 as the
+ * originally written value was overwritten. Likewise the second handle received
+ * from the set should be that of the second queue, and that queue should hold
+ * ulValueToSend1 as the originally written value was overwritten. */
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle1 )
+ {
+ /* Wrote to xQueueHandle1 first so expected that handle to be read from
+ * the set first. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+ {
+ /* One value was read from the set, so now only expect a single value
+ * in the set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
+
+ if( ulValueReceived != ulValueToSend2 )
+ {
+ /* Unexpected value received from the queue. ulValueToSend1 was written
+ * first, but then overwritten with ulValueToSend2; */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle2 )
+ {
+ /* xQueueHandle1 has already been removed from the set so expect only
+ * xQueueHandle2 to be left. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 )
+ {
+ /* The last value was read from the set so don't expect any more. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
+
+ if( ulValueReceived != ulValueToSend1 )
+ {
+ /* Unexpected value received from the queue. ulValueToSend2 was written
+ * first, but then overwritten with ulValueToSend1. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Should be anything in the queue set now. */
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != NULL )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Clean up. */
+ xQueueRemoveFromSet( xQueueHandle1, xQueueSet );
+ xQueueRemoveFromSet( xQueueHandle2, xQueueSet );
+ vQueueDelete( xQueueHandle1 );
+ vQueueDelete( xQueueHandle2 );
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvTestQueueOverwriteFromISROnTwoQueusInQueueSet( void )
-{
-uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0;
-QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL;
-const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
-
- /* Create two queues that have a length of one - a requirement in order to call
- xQueueOverwrite. These will get deleted again when this test completes. */
- xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
- configASSERT( xQueueHandle1 );
- xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
- configASSERT( xQueueHandle2 );
-
- if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) )
- {
- /* Add both queues to the queue set. */
- xQueueAddToSet( xQueueHandle1, xQueueSet );
- xQueueAddToSet( xQueueHandle2, xQueueSet );
-
- /* Add an item using the first queue using the 'FromISR' version of the
- overwrite function. */
- xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend1, NULL );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
- {
- /* Expected one item in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle1 )
- {
- /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
- held in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
- /* Next add an item to the second queue using the 'FromISR' version of the
- overwrite function. */
- xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend2, NULL );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* The head of the queue set should not have changed though. */
- xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle1 )
- {
- /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
- held in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
-
-
- /* Now overwrite the value in the queue and ensure the queue set state
- doesn't change as the number of items in the queues within the set have
- not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue
- 2 should hold the value ulValueToSend1. */
- xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
- /* Repeat the above to ensure the queue set state doesn't change. */
- xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL );
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
- {
- /* Still expected two items in the queue set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
- /* Now when reading from the queue set we expect the handle to the first
- queue to be received first, and for that queue to hold ulValueToSend2 as the
- originally written value was overwritten. Likewise the second handle received
- from the set should be that of the second queue, and that queue should hold
- ulValueToSend1 as the originally written value was overwritten. */
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle1 )
- {
- /* Wrote to xQueueHandle1 first so expected that handle to be read from
- the set first. */
- xQueueSetTasksStatus = pdFAIL;
- }
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
- {
- /* One value was read from the set, so now only expect a single value
- in the set. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
- if( ulValueReceived != ulValueToSend2 )
- {
- /* Unexpected value received from the queue. ulValueToSend1 was written
- first, but then overwritten with ulValueToSend2; */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != xQueueHandle2 )
- {
- /* xQueueHandle1 has already been removed from the set so expect only
- xQueueHandle2 to be left. */
- xQueueSetTasksStatus = pdFAIL;
- }
- if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 )
- {
- /* The last value was read from the set so don't expect any more. */
- xQueueSetTasksStatus = pdFAIL;
- }
- xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
- if( ulValueReceived != ulValueToSend1 )
- {
- /* Unexpected value received from the queue. ulValueToSend2 was written
- first, but then overwritten with ulValueToSend1. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
-
-
-
- /* Should be anything in the queue set now. */
- xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
- if( xReceivedHandle != NULL )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Clean up. */
- xQueueRemoveFromSet( xQueueHandle1, xQueueSet );
- xQueueRemoveFromSet( xQueueHandle2, xQueueSet );
- vQueueDelete( xQueueHandle1 );
- vQueueDelete( xQueueHandle2 );
- }
-}
+ static void prvTestQueueOverwriteFromISROnTwoQueusInQueueSet( void )
+ {
+ uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0;
+ QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL;
+ const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1;
+
+ /* Create two queues that have a length of one - a requirement in order to call
+ * xQueueOverwrite. These will get deleted again when this test completes. */
+ xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
+ configASSERT( xQueueHandle1 );
+ xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) );
+ configASSERT( xQueueHandle2 );
+
+ if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) )
+ {
+ /* Add both queues to the queue set. */
+ xQueueAddToSet( xQueueHandle1, xQueueSet );
+ xQueueAddToSet( xQueueHandle2, xQueueSet );
+
+ /* Add an item using the first queue using the 'FromISR' version of the
+ * overwrite function. */
+ xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend1, NULL );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+ {
+ /* Expected one item in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle1 )
+ {
+ /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+ * held in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Next add an item to the second queue using the 'FromISR' version of the
+ * overwrite function. */
+ xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend2, NULL );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* The head of the queue set should not have changed though. */
+ xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle1 )
+ {
+ /* Wrote to xQueueHandle so expected xQueueHandle to be the handle
+ * held in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Now overwrite the value in the queue and ensure the queue set state
+ * doesn't change as the number of items in the queues within the set have
+ * not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue
+ * 2 should hold the value ulValueToSend1. */
+ xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Repeat the above to ensure the queue set state doesn't change. */
+ xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL );
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 )
+ {
+ /* Still expected two items in the queue set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Now when reading from the queue set we expect the handle to the first
+ * queue to be received first, and for that queue to hold ulValueToSend2 as the
+ * originally written value was overwritten. Likewise the second handle received
+ * from the set should be that of the second queue, and that queue should hold
+ * ulValueToSend1 as the originally written value was overwritten. */
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle1 )
+ {
+ /* Wrote to xQueueHandle1 first so expected that handle to be read from
+ * the set first. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 )
+ {
+ /* One value was read from the set, so now only expect a single value
+ * in the set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
+
+ if( ulValueReceived != ulValueToSend2 )
+ {
+ /* Unexpected value received from the queue. ulValueToSend1 was written
+ * first, but then overwritten with ulValueToSend2; */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != xQueueHandle2 )
+ {
+ /* xQueueHandle1 has already been removed from the set so expect only
+ * xQueueHandle2 to be left. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 )
+ {
+ /* The last value was read from the set so don't expect any more. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK );
+
+ if( ulValueReceived != ulValueToSend1 )
+ {
+ /* Unexpected value received from the queue. ulValueToSend2 was written
+ * first, but then overwritten with ulValueToSend1. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Should be anything in the queue set now. */
+ xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK );
+
+ if( xReceivedHandle != NULL )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Clean up. */
+ xQueueRemoveFromSet( xQueueHandle1, xQueueSet );
+ xQueueRemoveFromSet( xQueueHandle2, xQueueSet );
+ vQueueDelete( xQueueHandle1 );
+ vQueueDelete( xQueueHandle2 );
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvSetupTest( void )
-{
-BaseType_t x;
-uint32_t ulValueToSend = 0;
-
- /* Ensure the queues are created and the queue set configured before the
- sending task is unsuspended.
-
- First Create the queue set such that it will be able to hold a message for
- every space in every queue in the set. */
- xQueueSet = xQueueCreateSet( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH );
-
- for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ )
- {
- /* Create the queue and add it to the set. The queue is just holding
- uint32_t value. */
- xQueues[ x ] = xQueueCreate( queuesetQUEUE_LENGTH, sizeof( uint32_t ) );
- configASSERT( xQueues[ x ] );
- if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdPASS )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
- else
- {
- /* The queue has now been added to the queue set and cannot be added to
- another. */
- if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdFAIL )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
- }
- }
-
- /* Attempt to remove a queue from a queue set it does not belong
- to (NULL being passed as the queue set in this case). */
- if( xQueueRemoveFromSet( xQueues[ 0 ], NULL ) != pdFAIL )
- {
- /* It is not possible to successfully remove a queue from a queue
- set it does not belong to. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Attempt to remove a queue from the queue set it does belong to. */
- if( xQueueRemoveFromSet( xQueues[ 0 ], xQueueSet ) != pdPASS )
- {
- /* It should be possible to remove the queue from the queue set it
- does belong to. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Add an item to the queue before attempting to add it back into the
- set. */
- xQueueSend( xQueues[ 0 ], ( void * ) &ulValueToSend, 0 );
- if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdFAIL )
- {
- /* Should not be able to add a non-empty queue to a set. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Remove the item from the queue before adding the queue back into the
- set so the dynamic tests can begin. */
- xQueueReceive( xQueues[ 0 ], &ulValueToSend, 0 );
- if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdPASS )
- {
- /* If the queue was successfully removed from the queue set then it
- should be possible to add it back in again. */
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* The task that sends to the queues is not running yet, so attempting to
- read from the queue set should fail. */
- if( xQueueSelectFromSet( xQueueSet, queuesetSHORT_DELAY ) != NULL )
- {
- xQueueSetTasksStatus = pdFAIL;
- }
-
- /* Testing the behaviour of queue sets when a queue overwrite operation is
- performed on a set member requires a special test as overwrites can only
- be performed on queues that have a length of 1. */
- prvTestQueueOverwriteWithQueueSet();
-
- /* Test the case where two queues within a set are written to with
- xQueueOverwrite(). */
- prvTestQueueOverwriteOnTwoQueusInQueueSet();
- prvTestQueueOverwriteFromISROnTwoQueusInQueueSet();
-
- /* In case any of the above have already indicated a failure. */
- configASSERT( xQueueSetTasksStatus != pdFAIL );
-
- /* Resume the task that writes to the queues. */
- vTaskResume( xQueueSetSendingTask );
-
- /* Let the ISR access the queues also. */
- xSetupComplete = pdTRUE;
-}
+ static void prvSetupTest( void )
+ {
+ BaseType_t x;
+ uint32_t ulValueToSend = 0;
+
+ /* Ensure the queues are created and the queue set configured before the
+ * sending task is unsuspended.
+ *
+ * First Create the queue set such that it will be able to hold a message for
+ * every space in every queue in the set. */
+ xQueueSet = xQueueCreateSet( queuesetNUM_QUEUES_IN_SET * queuesetQUEUE_LENGTH );
+
+ for( x = 0; x < queuesetNUM_QUEUES_IN_SET; x++ )
+ {
+ /* Create the queue and add it to the set. The queue is just holding
+ * uint32_t value. */
+ xQueues[ x ] = xQueueCreate( queuesetQUEUE_LENGTH, sizeof( uint32_t ) );
+ configASSERT( xQueues[ x ] );
+
+ if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdPASS )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+ else
+ {
+ /* The queue has now been added to the queue set and cannot be added to
+ * another. */
+ if( xQueueAddToSet( xQueues[ x ], xQueueSet ) != pdFAIL )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+ }
+ }
+
+ /* Attempt to remove a queue from a queue set it does not belong
+ * to (NULL being passed as the queue set in this case). */
+ if( xQueueRemoveFromSet( xQueues[ 0 ], NULL ) != pdFAIL )
+ {
+ /* It is not possible to successfully remove a queue from a queue
+ * set it does not belong to. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Attempt to remove a queue from the queue set it does belong to. */
+ if( xQueueRemoveFromSet( xQueues[ 0 ], xQueueSet ) != pdPASS )
+ {
+ /* It should be possible to remove the queue from the queue set it
+ * does belong to. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Add an item to the queue before attempting to add it back into the
+ * set. */
+ xQueueSend( xQueues[ 0 ], ( void * ) &ulValueToSend, 0 );
+
+ if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdFAIL )
+ {
+ /* Should not be able to add a non-empty queue to a set. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Remove the item from the queue before adding the queue back into the
+ * set so the dynamic tests can begin. */
+ xQueueReceive( xQueues[ 0 ], &ulValueToSend, 0 );
+
+ if( xQueueAddToSet( xQueues[ 0 ], xQueueSet ) != pdPASS )
+ {
+ /* If the queue was successfully removed from the queue set then it
+ * should be possible to add it back in again. */
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* The task that sends to the queues is not running yet, so attempting to
+ * read from the queue set should fail. */
+ if( xQueueSelectFromSet( xQueueSet, queuesetSHORT_DELAY ) != NULL )
+ {
+ xQueueSetTasksStatus = pdFAIL;
+ }
+
+ /* Testing the behaviour of queue sets when a queue overwrite operation is
+ * performed on a set member requires a special test as overwrites can only
+ * be performed on queues that have a length of 1. */
+ prvTestQueueOverwriteWithQueueSet();
+
+ /* Test the case where two queues within a set are written to with
+ * xQueueOverwrite(). */
+ prvTestQueueOverwriteOnTwoQueusInQueueSet();
+ prvTestQueueOverwriteFromISROnTwoQueusInQueueSet();
+
+ /* In case any of the above have already indicated a failure. */
+ configASSERT( xQueueSetTasksStatus != pdFAIL );
+
+ /* Resume the task that writes to the queues. */
+ vTaskResume( xQueueSetSendingTask );
+
+ /* Let the ISR access the queues also. */
+ xSetupComplete = pdTRUE;
+ }
/*-----------------------------------------------------------*/
-static size_t prvRand( void )
-{
- uxNextRand = ( uxNextRand * ( size_t ) 1103515245 ) + ( size_t ) 12345;
- return ( uxNextRand / ( size_t ) 65536 ) % ( size_t ) 32768;
-}
+ static size_t prvRand( void )
+ {
+ uxNextRand = ( uxNextRand * ( size_t ) 1103515245 ) + ( size_t ) 12345;
+ return ( uxNextRand / ( size_t ) 65536 ) % ( size_t ) 32768;
+ }
/*-----------------------------------------------------------*/
-static void prvSRand( size_t uxSeed )
-{
- uxNextRand = uxSeed;
-}
+ static void prvSRand( size_t uxSeed )
+ {
+ uxNextRand = uxSeed;
+ }
#endif /* ( configUSE_QUEUE_SETS == 1 ) */
diff --git a/Demo/Common/Minimal/QueueSetPolling.c b/Demo/Common/Minimal/QueueSetPolling.c
index 1f74ef319..ae55ea20e 100644
--- a/Demo/Common/Minimal/QueueSetPolling.c
+++ b/Demo/Common/Minimal/QueueSetPolling.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -51,131 +51,132 @@
/* Demo includes. */
#include "QueueSetPolling.h"
-#if( configUSE_QUEUE_SETS == 1 ) /* Remove tests if queue sets are not defined. */
+#if ( configUSE_QUEUE_SETS == 1 ) /* Remove tests if queue sets are not defined. */
/* The length of each created queue. */
-#define setpollQUEUE_LENGTH 10
+ #define setpollQUEUE_LENGTH 10
/* Block times used in this demo. A block time or 0 means "don't block". */
-#define setpollDONT_BLOCK 0
+ #define setpollDONT_BLOCK 0
/* The ISR sends to the queue every setpollISR_TX_PERIOD ticks. */
-#define queuesetISR_TX_PERIOD ( 50UL )
+ #define queuesetISR_TX_PERIOD ( 50UL )
/*
* The task that reads from the queue set.
*/
-static void prvQueueSetReceivingTask( void *pvParameters );
+ static void prvQueueSetReceivingTask( void * pvParameters );
/*-----------------------------------------------------------*/
/* The queue that is added to the set. */
-static QueueHandle_t xQueue = NULL;
+ static QueueHandle_t xQueue = NULL;
/* The handle of the queue set to which the queue is added. */
-static QueueSetHandle_t xQueueSet = NULL;
+ static QueueSetHandle_t xQueueSet = NULL;
/* Set to pdFAIL if an error is detected by any queue set task.
-ulCycleCounter will only be incremented if xQueueSetTasksSatus equals pdPASS. */
-static volatile BaseType_t xQueueSetPollStatus = pdPASS;
+ * ulCycleCounter will only be incremented if xQueueSetTasksSatus equals pdPASS. */
+ static volatile BaseType_t xQueueSetPollStatus = pdPASS;
/* Counter used to ensure the task is still running. */
-static uint32_t ulCycleCounter = 0;
+ static uint32_t ulCycleCounter = 0;
/*-----------------------------------------------------------*/
-void vStartQueueSetPollingTask( void )
-{
- /* Create the queue that is added to the set, the set, and add the queue to
- the set. */
- xQueue = xQueueCreate( setpollQUEUE_LENGTH, sizeof( uint32_t ) );
- xQueueSet = xQueueCreateSet( setpollQUEUE_LENGTH );
-
- if( ( xQueue != NULL ) && ( xQueueSet != NULL ) )
- {
- xQueueAddToSet( xQueue, xQueueSet );
-
- /* Create the task. */
- xTaskCreate( prvQueueSetReceivingTask, "SetPoll", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- }
-}
+ void vStartQueueSetPollingTask( void )
+ {
+ /* Create the queue that is added to the set, the set, and add the queue to
+ * the set. */
+ xQueue = xQueueCreate( setpollQUEUE_LENGTH, sizeof( uint32_t ) );
+ xQueueSet = xQueueCreateSet( setpollQUEUE_LENGTH );
+
+ if( ( xQueue != NULL ) && ( xQueueSet != NULL ) )
+ {
+ xQueueAddToSet( xQueue, xQueueSet );
+
+ /* Create the task. */
+ xTaskCreate( prvQueueSetReceivingTask, "SetPoll", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvQueueSetReceivingTask( void *pvParameters )
-{
-uint32_t ulReceived, ulExpected = 0;
-QueueHandle_t xActivatedQueue;
-
- /* Remove compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Is a message waiting? A block time is not used to ensure the queue
- set is polled while it is being written to from an interrupt. */
- xActivatedQueue = xQueueSelectFromSet( xQueueSet, setpollDONT_BLOCK );
-
- if( xActivatedQueue != NULL )
- {
- /* Reading from the queue should pass with a zero block time as
- this task will only run when something has been posted to a task
- in the queue set. */
- if( xQueueReceive( xActivatedQueue, &ulReceived, setpollDONT_BLOCK ) != pdPASS )
- {
- xQueueSetPollStatus = pdFAIL;
- }
-
- if( ulReceived == ulExpected )
- {
- ulExpected++;
- }
- else
- {
- xQueueSetPollStatus = pdFAIL;
- }
-
- if( xQueueSetPollStatus == pdPASS )
- {
- ulCycleCounter++;
- }
- }
- }
-}
+ static void prvQueueSetReceivingTask( void * pvParameters )
+ {
+ uint32_t ulReceived, ulExpected = 0;
+ QueueHandle_t xActivatedQueue;
+
+ /* Remove compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Is a message waiting? A block time is not used to ensure the queue
+ * set is polled while it is being written to from an interrupt. */
+ xActivatedQueue = xQueueSelectFromSet( xQueueSet, setpollDONT_BLOCK );
+
+ if( xActivatedQueue != NULL )
+ {
+ /* Reading from the queue should pass with a zero block time as
+ * this task will only run when something has been posted to a task
+ * in the queue set. */
+ if( xQueueReceive( xActivatedQueue, &ulReceived, setpollDONT_BLOCK ) != pdPASS )
+ {
+ xQueueSetPollStatus = pdFAIL;
+ }
+
+ if( ulReceived == ulExpected )
+ {
+ ulExpected++;
+ }
+ else
+ {
+ xQueueSetPollStatus = pdFAIL;
+ }
+
+ if( xQueueSetPollStatus == pdPASS )
+ {
+ ulCycleCounter++;
+ }
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-void vQueueSetPollingInterruptAccess( void )
-{
-static uint32_t ulCallCount = 0, ulValueToSend = 0;
-
- /* It is intended that this function is called from the tick hook
- function, so each call is one tick period apart. */
- ulCallCount++;
- if( ulCallCount > queuesetISR_TX_PERIOD )
- {
- ulCallCount = 0;
-
- if( xQueueSendFromISR( xQueue, ( void * ) &ulValueToSend, NULL ) == pdPASS )
- {
- /* Send the next value next time. */
- ulValueToSend++;
- }
- }
-}
+ void vQueueSetPollingInterruptAccess( void )
+ {
+ static uint32_t ulCallCount = 0, ulValueToSend = 0;
+
+ /* It is intended that this function is called from the tick hook
+ * function, so each call is one tick period apart. */
+ ulCallCount++;
+
+ if( ulCallCount > queuesetISR_TX_PERIOD )
+ {
+ ulCallCount = 0;
+
+ if( xQueueSendFromISR( xQueue, ( void * ) &ulValueToSend, NULL ) == pdPASS )
+ {
+ /* Send the next value next time. */
+ ulValueToSend++;
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-BaseType_t xAreQueueSetPollTasksStillRunning( void )
-{
-static uint32_t ulLastCycleCounter = 0;
+ BaseType_t xAreQueueSetPollTasksStillRunning( void )
+ {
+ static uint32_t ulLastCycleCounter = 0;
- if( ulLastCycleCounter == ulCycleCounter )
- {
- xQueueSetPollStatus = pdFAIL;
- }
+ if( ulLastCycleCounter == ulCycleCounter )
+ {
+ xQueueSetPollStatus = pdFAIL;
+ }
- ulLastCycleCounter = ulCycleCounter;
+ ulLastCycleCounter = ulCycleCounter;
- return xQueueSetPollStatus;
-}
+ return xQueueSetPollStatus;
+ }
/*-----------------------------------------------------------*/
diff --git a/Demo/Common/Minimal/StaticAllocation.c b/Demo/Common/Minimal/StaticAllocation.c
index 477f514ad..45bc99f38 100644
--- a/Demo/Common/Minimal/StaticAllocation.c
+++ b/Demo/Common/Minimal/StaticAllocation.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -47,26 +47,26 @@
#include "StaticAllocation.h"
/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
/* The priority at which the task that performs the tests is created. */
-#define staticTASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+ #define staticTASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The length of the queue, in items, not bytes, used in the queue static
-allocation tests. */
-#define staticQUEUE_LENGTH_IN_ITEMS ( 5 )
+ * allocation tests. */
+ #define staticQUEUE_LENGTH_IN_ITEMS ( 5 )
/* A block time of 0 simply means "don't block". */
-#define staticDONT_BLOCK ( ( TickType_t ) 0 )
+ #define staticDONT_BLOCK ( ( TickType_t ) 0 )
/* Binary semaphores have a maximum count of 1. */
-#define staticBINARY_SEMAPHORE_MAX_COUNT ( 1 )
+ #define staticBINARY_SEMAPHORE_MAX_COUNT ( 1 )
/* The size of the stack used by the task that runs the tests. */
-#define staticCREATOR_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )
+ #define staticCREATOR_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 )
/* The number of times the software timer will execute before stopping itself. */
-#define staticMAX_TIMER_CALLBACK_EXECUTIONS ( 5 )
+ #define staticMAX_TIMER_CALLBACK_EXECUTIONS ( 5 )
/*-----------------------------------------------------------*/
@@ -75,73 +75,73 @@ allocation tests. */
* The task that repeatedly creates and deletes statically allocated tasks, and
* other RTOS objects.
*/
-static void prvStaticallyAllocatedCreator( void *pvParameters );
+ static void prvStaticallyAllocatedCreator( void * pvParameters );
/*
* The callback function used by the software timer that is repeatedly created
* and deleted using both static and dynamically allocated memory.
*/
-static void prvTimerCallback( TimerHandle_t xExpiredTimer );
+ static void prvTimerCallback( TimerHandle_t xExpiredTimer );
/*
* A task that is created and deleted multiple times, using both statically and
* dynamically allocated stack and TCB.
*/
-static void prvStaticallyAllocatedTask( void *pvParameters );
+ static void prvStaticallyAllocatedTask( void * pvParameters );
/*
* A function that demonstrates and tests the API functions that create and
* delete tasks using both statically and dynamically allocated TCBs and stacks.
*/
-static void prvCreateAndDeleteStaticallyAllocatedTasks( void );
+ static void prvCreateAndDeleteStaticallyAllocatedTasks( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete event groups using both statically and dynamically allocated RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void );
+ static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete queues using both statically and dynamically allocated RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedQueues( void );
+ static void prvCreateAndDeleteStaticallyAllocatedQueues( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete binary semaphores using both statically and dynamically allocated RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void );
+ static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete software timers using both statically and dynamically allocated RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedTimers( void );
+ static void prvCreateAndDeleteStaticallyAllocatedTimers( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete mutexes using both statically and dynamically allocated RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedMutexes( void );
+ static void prvCreateAndDeleteStaticallyAllocatedMutexes( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete counting semaphores using both statically and dynamically allocated
* RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void );
+ static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void );
/*
* A function that demonstrates and tests the API functions that create and
* delete recursive mutexes using both statically and dynamically allocated RAM.
*/
-static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void );
+ static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void );
/*
* Utility function to create pseudo random numbers.
*/
-static UBaseType_t prvRand( void );
+ static UBaseType_t prvRand( void );
/*
* The task that creates and deletes other tasks has to delay occasionally to
@@ -149,958 +149,965 @@ static UBaseType_t prvRand( void );
* random delay time is used just to add a little bit of randomisation into the
* execution pattern. prvGetNextDelayTime() generates the pseudo random delay.
*/
-static TickType_t prvGetNextDelayTime( void );
+ static TickType_t prvGetNextDelayTime( void );
/*
* Checks the basic operation of a queue after it has been created.
*/
-static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue );
+ static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue );
/*
* Checks the basic operation of a recursive mutex after it has been created.
*/
-static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore );
+ static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore );
/*
* Checks the basic operation of a binary semaphore after it has been created.
*/
-static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore, UBaseType_t uxMaxCount );
+ static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore,
+ UBaseType_t uxMaxCount );
/*
* Checks the basic operation of an event group after it has been created.
*/
-static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup );
+ static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup );
/*-----------------------------------------------------------*/
/* StaticTask_t is a publicly accessible structure that has the same size and
-alignment requirements as the real TCB structure. It is provided as a mechanism
-for applications to know the size of the TCB (which is dependent on the
-architecture and configuration file settings) without breaking the strict data
-hiding policy by exposing the real TCB. This StaticTask_t variable is passed
-into the xTaskCreateStatic() function that creates the
-prvStaticallyAllocatedCreator() task, and will hold the TCB of the created
-tasks. */
-static StaticTask_t xCreatorTaskTCBBuffer;
+ * alignment requirements as the real TCB structure. It is provided as a mechanism
+ * for applications to know the size of the TCB (which is dependent on the
+ * architecture and configuration file settings) without breaking the strict data
+ * hiding policy by exposing the real TCB. This StaticTask_t variable is passed
+ * into the xTaskCreateStatic() function that creates the
+ * prvStaticallyAllocatedCreator() task, and will hold the TCB of the created
+ * tasks. */
+ static StaticTask_t xCreatorTaskTCBBuffer;
/* This is the stack that will be used by the prvStaticallyAllocatedCreator()
-task, which is itself created using statically allocated buffers (so without any
-dynamic memory allocation). */
-static StackType_t uxCreatorTaskStackBuffer[ staticCREATOR_TASK_STACK_SIZE ];
+ * task, which is itself created using statically allocated buffers (so without any
+ * dynamic memory allocation). */
+ static StackType_t uxCreatorTaskStackBuffer[ staticCREATOR_TASK_STACK_SIZE ];
/* Used by the pseudo random number generating function. */
-static uint32_t ulNextRand = 0;
+ static uint32_t ulNextRand = 0;
/* Used so a check task can ensure this test is still executing, and not
-stalled. */
-static volatile UBaseType_t uxCycleCounter = 0;
+ * stalled. */
+ static volatile UBaseType_t uxCycleCounter = 0;
/* A variable that gets set to pdTRUE if an error is detected. */
-static volatile BaseType_t xErrorOccurred = pdFALSE;
+ static volatile BaseType_t xErrorOccurred = pdFALSE;
/*-----------------------------------------------------------*/
-void vStartStaticallyAllocatedTasks( void )
-{
- /* Create a single task, which then repeatedly creates and deletes the other
- RTOS objects using both statically and dynamically allocated RAM. */
- xTaskCreateStatic( prvStaticallyAllocatedCreator, /* The function that implements the task being created. */
- "StatCreate", /* Text name for the task - not used by the RTOS, its just to assist debugging. */
- staticCREATOR_TASK_STACK_SIZE, /* Size of the buffer passed in as the stack - in words, not bytes! */
- NULL, /* Parameter passed into the task - not used in this case. */
- staticTASK_PRIORITY, /* Priority of the task. */
- &( uxCreatorTaskStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */
- &xCreatorTaskTCBBuffer ); /* The variable that will hold the task's TCB. */
-}
+ void vStartStaticallyAllocatedTasks( void )
+ {
+ /* Create a single task, which then repeatedly creates and deletes the other
+ * RTOS objects using both statically and dynamically allocated RAM. */
+ xTaskCreateStatic( prvStaticallyAllocatedCreator, /* The function that implements the task being created. */
+ "StatCreate", /* Text name for the task - not used by the RTOS, its just to assist debugging. */
+ staticCREATOR_TASK_STACK_SIZE, /* Size of the buffer passed in as the stack - in words, not bytes! */
+ NULL, /* Parameter passed into the task - not used in this case. */
+ staticTASK_PRIORITY, /* Priority of the task. */
+ &( uxCreatorTaskStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */
+ &xCreatorTaskTCBBuffer ); /* The variable that will hold the task's TCB. */
+ }
/*-----------------------------------------------------------*/
-static void prvStaticallyAllocatedCreator( void *pvParameters )
-{
- /* Avoid compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Loop, running functions that create and delete the various RTOS
- objects that can be optionally created using either static or dynamic
- memory allocation. */
- prvCreateAndDeleteStaticallyAllocatedTasks();
- prvCreateAndDeleteStaticallyAllocatedQueues();
-
- /* Delay to ensure lower priority tasks get CPU time, and increment the
- cycle counter so a 'check' task can determine that this task is still
- executing. */
- vTaskDelay( prvGetNextDelayTime() );
- uxCycleCounter++;
-
- prvCreateAndDeleteStaticallyAllocatedBinarySemaphores();
- prvCreateAndDeleteStaticallyAllocatedCountingSemaphores();
-
- vTaskDelay( prvGetNextDelayTime() );
- uxCycleCounter++;
-
- prvCreateAndDeleteStaticallyAllocatedMutexes();
- prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes();
-
- vTaskDelay( prvGetNextDelayTime() );
- uxCycleCounter++;
-
- prvCreateAndDeleteStaticallyAllocatedEventGroups();
- prvCreateAndDeleteStaticallyAllocatedTimers();
- }
-}
+ static void prvStaticallyAllocatedCreator( void * pvParameters )
+ {
+ /* Avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Loop, running functions that create and delete the various RTOS
+ * objects that can be optionally created using either static or dynamic
+ * memory allocation. */
+ prvCreateAndDeleteStaticallyAllocatedTasks();
+ prvCreateAndDeleteStaticallyAllocatedQueues();
+
+ /* Delay to ensure lower priority tasks get CPU time, and increment the
+ * cycle counter so a 'check' task can determine that this task is still
+ * executing. */
+ vTaskDelay( prvGetNextDelayTime() );
+ uxCycleCounter++;
+
+ prvCreateAndDeleteStaticallyAllocatedBinarySemaphores();
+ prvCreateAndDeleteStaticallyAllocatedCountingSemaphores();
+
+ vTaskDelay( prvGetNextDelayTime() );
+ uxCycleCounter++;
+
+ prvCreateAndDeleteStaticallyAllocatedMutexes();
+ prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes();
+
+ vTaskDelay( prvGetNextDelayTime() );
+ uxCycleCounter++;
+
+ prvCreateAndDeleteStaticallyAllocatedEventGroups();
+ prvCreateAndDeleteStaticallyAllocatedTimers();
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void )
-{
-SemaphoreHandle_t xSemaphore;
-const UBaseType_t uxMaxCount = ( UBaseType_t ) 10;
+ static void prvCreateAndDeleteStaticallyAllocatedCountingSemaphores( void )
+ {
+ SemaphoreHandle_t xSemaphore;
+ const UBaseType_t uxMaxCount = ( UBaseType_t ) 10;
/* StaticSemaphore_t is a publicly accessible structure that has the same size
-and alignment requirements as the real semaphore structure. It is provided as a
-mechanism for applications to know the size of the semaphore (which is dependent
-on the architecture and configuration file settings) without breaking the strict
-data hiding policy by exposing the real semaphore internals. This
-StaticSemaphore_t variable is passed into the xSemaphoreCreateCountingStatic()
-function calls within this function. NOTE: In most usage scenarios now it is
-faster and more memory efficient to use a direct to task notification instead of
-a counting semaphore. http://www.freertos.org/RTOS-task-notifications.html */
-StaticSemaphore_t xSemaphoreBuffer;
-
- /* Create the semaphore. xSemaphoreCreateCountingStatic() has one more
- parameter than the usual xSemaphoreCreateCounting() function. The parameter
- is a pointer to the pre-allocated StaticSemaphore_t structure, which will
- hold information on the semaphore in an anonymous way. If the pointer is
- passed as NULL then the structure will be allocated dynamically, just as
- when xSemaphoreCreateCounting() is called. */
- xSemaphore = xSemaphoreCreateCountingStatic( uxMaxCount, 0, &xSemaphoreBuffer );
-
- /* The semaphore handle should equal the static semaphore structure passed
- into the xSemaphoreCreateBinaryStatic() function. */
- configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
-
- /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
- prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount );
-
- /* Delete the semaphore again so the buffers can be reused. */
- vSemaphoreDelete( xSemaphore );
-
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- /* Now do the same but using dynamically allocated buffers to ensure the
- delete functions are working correctly in both the static and dynamic
- allocation cases. */
- xSemaphore = xSemaphoreCreateCounting( uxMaxCount, 0 );
- configASSERT( xSemaphore != NULL );
- prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount );
- vSemaphoreDelete( xSemaphore );
- }
- #endif
-}
+ * and alignment requirements as the real semaphore structure. It is provided as a
+ * mechanism for applications to know the size of the semaphore (which is dependent
+ * on the architecture and configuration file settings) without breaking the strict
+ * data hiding policy by exposing the real semaphore internals. This
+ * StaticSemaphore_t variable is passed into the xSemaphoreCreateCountingStatic()
+ * function calls within this function. NOTE: In most usage scenarios now it is
+ * faster and more memory efficient to use a direct to task notification instead of
+ * a counting semaphore. http://www.freertos.org/RTOS-task-notifications.html */
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ /* Create the semaphore. xSemaphoreCreateCountingStatic() has one more
+ * parameter than the usual xSemaphoreCreateCounting() function. The parameter
+ * is a pointer to the pre-allocated StaticSemaphore_t structure, which will
+ * hold information on the semaphore in an anonymous way. If the pointer is
+ * passed as NULL then the structure will be allocated dynamically, just as
+ * when xSemaphoreCreateCounting() is called. */
+ xSemaphore = xSemaphoreCreateCountingStatic( uxMaxCount, 0, &xSemaphoreBuffer );
+
+ /* The semaphore handle should equal the static semaphore structure passed
+ * into the xSemaphoreCreateBinaryStatic() function. */
+ configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+ /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+ prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount );
+
+ /* Delete the semaphore again so the buffers can be reused. */
+ vSemaphoreDelete( xSemaphore );
+
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* Now do the same but using dynamically allocated buffers to ensure the
+ * delete functions are working correctly in both the static and dynamic
+ * allocation cases. */
+ xSemaphore = xSemaphoreCreateCounting( uxMaxCount, 0 );
+ configASSERT( xSemaphore != NULL );
+ prvSanityCheckCreatedSemaphore( xSemaphore, uxMaxCount );
+ vSemaphoreDelete( xSemaphore );
+ }
+ #endif
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void )
-{
-SemaphoreHandle_t xSemaphore;
+ static void prvCreateAndDeleteStaticallyAllocatedRecursiveMutexes( void )
+ {
+ SemaphoreHandle_t xSemaphore;
/* StaticSemaphore_t is a publicly accessible structure that has the same size
-and alignment requirements as the real semaphore structure. It is provided as a
-mechanism for applications to know the size of the semaphore (which is dependent
-on the architecture and configuration file settings) without breaking the strict
-data hiding policy by exposing the real semaphore internals. This
-StaticSemaphore_t variable is passed into the
-xSemaphoreCreateRecursiveMutexStatic() function calls within this function. */
-StaticSemaphore_t xSemaphoreBuffer;
-
- /* Create the semaphore. xSemaphoreCreateRecursiveMutexStatic() has one
- more parameter than the usual xSemaphoreCreateRecursiveMutex() function.
- The parameter is a pointer to the pre-allocated StaticSemaphore_t structure,
- which will hold information on the semaphore in an anonymous way. If the
- pointer is passed as NULL then the structure will be allocated dynamically,
- just as when xSemaphoreCreateRecursiveMutex() is called. */
- xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xSemaphoreBuffer );
-
- /* The semaphore handle should equal the static semaphore structure passed
- into the xSemaphoreCreateBinaryStatic() function. */
- configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
-
- /* Ensure the semaphore passes a few sanity checks as a valid
- recursive semaphore. */
- prvSanityCheckCreatedRecursiveMutex( xSemaphore );
-
- /* Delete the semaphore again so the buffers can be reused. */
- vSemaphoreDelete( xSemaphore );
-
- /* Now do the same using dynamically allocated buffers to ensure the delete
- functions are working correctly in both the static and dynamic memory
- allocation cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- xSemaphore = xSemaphoreCreateRecursiveMutex();
- configASSERT( xSemaphore != NULL );
- prvSanityCheckCreatedRecursiveMutex( xSemaphore );
- vSemaphoreDelete( xSemaphore );
- }
- #endif
-}
+ * and alignment requirements as the real semaphore structure. It is provided as a
+ * mechanism for applications to know the size of the semaphore (which is dependent
+ * on the architecture and configuration file settings) without breaking the strict
+ * data hiding policy by exposing the real semaphore internals. This
+ * StaticSemaphore_t variable is passed into the
+ * xSemaphoreCreateRecursiveMutexStatic() function calls within this function. */
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ /* Create the semaphore. xSemaphoreCreateRecursiveMutexStatic() has one
+ * more parameter than the usual xSemaphoreCreateRecursiveMutex() function.
+ * The parameter is a pointer to the pre-allocated StaticSemaphore_t structure,
+ * which will hold information on the semaphore in an anonymous way. If the
+ * pointer is passed as NULL then the structure will be allocated dynamically,
+ * just as when xSemaphoreCreateRecursiveMutex() is called. */
+ xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xSemaphoreBuffer );
+
+ /* The semaphore handle should equal the static semaphore structure passed
+ * into the xSemaphoreCreateBinaryStatic() function. */
+ configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+ /* Ensure the semaphore passes a few sanity checks as a valid
+ * recursive semaphore. */
+ prvSanityCheckCreatedRecursiveMutex( xSemaphore );
+
+ /* Delete the semaphore again so the buffers can be reused. */
+ vSemaphoreDelete( xSemaphore );
+
+ /* Now do the same using dynamically allocated buffers to ensure the delete
+ * functions are working correctly in both the static and dynamic memory
+ * allocation cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ xSemaphore = xSemaphoreCreateRecursiveMutex();
+ configASSERT( xSemaphore != NULL );
+ prvSanityCheckCreatedRecursiveMutex( xSemaphore );
+ vSemaphoreDelete( xSemaphore );
+ }
+ #endif
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedQueues( void )
-{
-QueueHandle_t xQueue;
+ static void prvCreateAndDeleteStaticallyAllocatedQueues( void )
+ {
+ QueueHandle_t xQueue;
/* StaticQueue_t is a publicly accessible structure that has the same size and
-alignment requirements as the real queue structure. It is provided as a
-mechanism for applications to know the size of the queue (which is dependent on
-the architecture and configuration file settings) without breaking the strict
-data hiding policy by exposing the real queue internals. This StaticQueue_t
-variable is passed into the xQueueCreateStatic() function calls within this
-function. */
-static StaticQueue_t xStaticQueue;
+ * alignment requirements as the real queue structure. It is provided as a
+ * mechanism for applications to know the size of the queue (which is dependent on
+ * the architecture and configuration file settings) without breaking the strict
+ * data hiding policy by exposing the real queue internals. This StaticQueue_t
+ * variable is passed into the xQueueCreateStatic() function calls within this
+ * function. */
+ static StaticQueue_t xStaticQueue;
/* The queue storage area must be large enough to hold the maximum number of
-items it is possible for the queue to hold at any one time, which equals the
-queue length (in items, not bytes) multiplied by the size of each item. In this
-case the queue will hold staticQUEUE_LENGTH_IN_ITEMS 64-bit items. See
-http://www.freertos.org/Embedded-RTOS-Queues.html */
-static uint8_t ucQueueStorageArea[ staticQUEUE_LENGTH_IN_ITEMS * sizeof( uint64_t ) ];
-
- /* Create the queue. xQueueCreateStatic() has two more parameters than the
- usual xQueueCreate() function. The first new parameter is a pointer to the
- pre-allocated queue storage area. The second new parameter is a pointer to
- the StaticQueue_t structure that will hold the queue state information in
- an anonymous way. If the two pointers are passed as NULL then the data
- will be allocated dynamically as if xQueueCreate() had been called. */
- xQueue = xQueueCreateStatic( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */
- sizeof( uint64_t ), /* The size of each item. */
- ucQueueStorageArea, /* The buffer used to hold items within the queue. */
- &xStaticQueue ); /* The static queue structure that will hold the state of the queue. */
-
- /* The queue handle should equal the static queue structure passed into the
- xQueueCreateStatic() function. */
- configASSERT( xQueue == ( QueueHandle_t ) &xStaticQueue );
-
- /* Ensure the queue passes a few sanity checks as a valid queue. */
- prvSanityCheckCreatedQueue( xQueue );
-
- /* Delete the queue again so the buffers can be reused. */
- vQueueDelete( xQueue );
-
- /* Now do the same using a dynamically allocated queue to ensure the delete
- function is working correctly in both the static and dynamic memory
- allocation cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- xQueue = xQueueCreate( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */
- sizeof( uint64_t ) ); /* The size of each item. */
-
- /* The queue handle should equal the static queue structure passed into the
- xQueueCreateStatic() function. */
- configASSERT( xQueue != NULL );
-
- /* Ensure the queue passes a few sanity checks as a valid queue. */
- prvSanityCheckCreatedQueue( xQueue );
-
- /* Delete the queue again so the buffers can be reused. */
- vQueueDelete( xQueue );
- }
- #endif
-}
+ * items it is possible for the queue to hold at any one time, which equals the
+ * queue length (in items, not bytes) multiplied by the size of each item. In this
+ * case the queue will hold staticQUEUE_LENGTH_IN_ITEMS 64-bit items. See
+ * http://www.freertos.org/Embedded-RTOS-Queues.html */
+ static uint8_t ucQueueStorageArea[ staticQUEUE_LENGTH_IN_ITEMS * sizeof( uint64_t ) ];
+
+ /* Create the queue. xQueueCreateStatic() has two more parameters than the
+ * usual xQueueCreate() function. The first new parameter is a pointer to the
+ * pre-allocated queue storage area. The second new parameter is a pointer to
+ * the StaticQueue_t structure that will hold the queue state information in
+ * an anonymous way. If the two pointers are passed as NULL then the data
+ * will be allocated dynamically as if xQueueCreate() had been called. */
+ xQueue = xQueueCreateStatic( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */
+ sizeof( uint64_t ), /* The size of each item. */
+ ucQueueStorageArea, /* The buffer used to hold items within the queue. */
+ &xStaticQueue ); /* The static queue structure that will hold the state of the queue. */
+
+ /* The queue handle should equal the static queue structure passed into the
+ * xQueueCreateStatic() function. */
+ configASSERT( xQueue == ( QueueHandle_t ) &xStaticQueue );
+
+ /* Ensure the queue passes a few sanity checks as a valid queue. */
+ prvSanityCheckCreatedQueue( xQueue );
+
+ /* Delete the queue again so the buffers can be reused. */
+ vQueueDelete( xQueue );
+
+ /* Now do the same using a dynamically allocated queue to ensure the delete
+ * function is working correctly in both the static and dynamic memory
+ * allocation cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ xQueue = xQueueCreate( staticQUEUE_LENGTH_IN_ITEMS, /* The maximum number of items the queue can hold. */
+ sizeof( uint64_t ) ); /* The size of each item. */
+
+ /* The queue handle should equal the static queue structure passed into the
+ * xQueueCreateStatic() function. */
+ configASSERT( xQueue != NULL );
+
+ /* Ensure the queue passes a few sanity checks as a valid queue. */
+ prvSanityCheckCreatedQueue( xQueue );
+
+ /* Delete the queue again so the buffers can be reused. */
+ vQueueDelete( xQueue );
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedMutexes( void )
-{
-SemaphoreHandle_t xSemaphore;
-BaseType_t xReturned;
+ static void prvCreateAndDeleteStaticallyAllocatedMutexes( void )
+ {
+ SemaphoreHandle_t xSemaphore;
+ BaseType_t xReturned;
/* StaticSemaphore_t is a publicly accessible structure that has the same size
-and alignment requirements as the real semaphore structure. It is provided as a
-mechanism for applications to know the size of the semaphore (which is dependent
-on the architecture and configuration file settings) without breaking the strict
-data hiding policy by exposing the real semaphore internals. This
-StaticSemaphore_t variable is passed into the xSemaphoreCreateMutexStatic()
-function calls within this function. */
-StaticSemaphore_t xSemaphoreBuffer;
-
- /* Create the semaphore. xSemaphoreCreateMutexStatic() has one more
- parameter than the usual xSemaphoreCreateMutex() function. The parameter
- is a pointer to the pre-allocated StaticSemaphore_t structure, which will
- hold information on the semaphore in an anonymous way. If the pointer is
- passed as NULL then the structure will be allocated dynamically, just as
- when xSemaphoreCreateMutex() is called. */
- xSemaphore = xSemaphoreCreateMutexStatic( &xSemaphoreBuffer );
-
- /* The semaphore handle should equal the static semaphore structure passed
- into the xSemaphoreCreateMutexStatic() function. */
- configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
-
- /* Take the mutex so the mutex is in the state expected by the
- prvSanityCheckCreatedSemaphore() function. */
- xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
- prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
-
- /* Delete the semaphore again so the buffers can be reused. */
- vSemaphoreDelete( xSemaphore );
-
- /* Now do the same using a dynamically allocated mutex to ensure the delete
- function is working correctly in both the static and dynamic allocation
- cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- xSemaphore = xSemaphoreCreateMutex();
-
- /* The semaphore handle should equal the static semaphore structure
- passed into the xSemaphoreCreateMutexStatic() function. */
- configASSERT( xSemaphore != NULL );
-
- /* Take the mutex so the mutex is in the state expected by the
- prvSanityCheckCreatedSemaphore() function. */
- xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
- prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
-
- /* Delete the semaphore again so the buffers can be reused. */
- vSemaphoreDelete( xSemaphore );
- }
- #endif
-}
+ * and alignment requirements as the real semaphore structure. It is provided as a
+ * mechanism for applications to know the size of the semaphore (which is dependent
+ * on the architecture and configuration file settings) without breaking the strict
+ * data hiding policy by exposing the real semaphore internals. This
+ * StaticSemaphore_t variable is passed into the xSemaphoreCreateMutexStatic()
+ * function calls within this function. */
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ /* Create the semaphore. xSemaphoreCreateMutexStatic() has one more
+ * parameter than the usual xSemaphoreCreateMutex() function. The parameter
+ * is a pointer to the pre-allocated StaticSemaphore_t structure, which will
+ * hold information on the semaphore in an anonymous way. If the pointer is
+ * passed as NULL then the structure will be allocated dynamically, just as
+ * when xSemaphoreCreateMutex() is called. */
+ xSemaphore = xSemaphoreCreateMutexStatic( &xSemaphoreBuffer );
+
+ /* The semaphore handle should equal the static semaphore structure passed
+ * into the xSemaphoreCreateMutexStatic() function. */
+ configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+ /* Take the mutex so the mutex is in the state expected by the
+ * prvSanityCheckCreatedSemaphore() function. */
+ xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+ prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+
+ /* Delete the semaphore again so the buffers can be reused. */
+ vSemaphoreDelete( xSemaphore );
+
+ /* Now do the same using a dynamically allocated mutex to ensure the delete
+ * function is working correctly in both the static and dynamic allocation
+ * cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ xSemaphore = xSemaphoreCreateMutex();
+
+ /* The semaphore handle should equal the static semaphore structure
+ * passed into the xSemaphoreCreateMutexStatic() function. */
+ configASSERT( xSemaphore != NULL );
+
+ /* Take the mutex so the mutex is in the state expected by the
+ * prvSanityCheckCreatedSemaphore() function. */
+ xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+ prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+
+ /* Delete the semaphore again so the buffers can be reused. */
+ vSemaphoreDelete( xSemaphore );
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void )
-{
-SemaphoreHandle_t xSemaphore;
+ static void prvCreateAndDeleteStaticallyAllocatedBinarySemaphores( void )
+ {
+ SemaphoreHandle_t xSemaphore;
/* StaticSemaphore_t is a publicly accessible structure that has the same size
-and alignment requirements as the real semaphore structure. It is provided as a
-mechanism for applications to know the size of the semaphore (which is dependent
-on the architecture and configuration file settings) without breaking the strict
-data hiding policy by exposing the real semaphore internals. This
-StaticSemaphore_t variable is passed into the xSemaphoreCreateBinaryStatic()
-function calls within this function. NOTE: In most usage scenarios now it is
-faster and more memory efficient to use a direct to task notification instead of
-a binary semaphore. http://www.freertos.org/RTOS-task-notifications.html */
-StaticSemaphore_t xSemaphoreBuffer;
-
- /* Create the semaphore. xSemaphoreCreateBinaryStatic() has one more
- parameter than the usual xSemaphoreCreateBinary() function. The parameter
- is a pointer to the pre-allocated StaticSemaphore_t structure, which will
- hold information on the semaphore in an anonymous way. If the pointer is
- passed as NULL then the structure will be allocated dynamically, just as
- when xSemaphoreCreateBinary() is called. */
- xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
-
- /* The semaphore handle should equal the static semaphore structure passed
- into the xSemaphoreCreateBinaryStatic() function. */
- configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
-
- /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
- prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
-
- /* Delete the semaphore again so the buffers can be reused. */
- vSemaphoreDelete( xSemaphore );
-
- /* Now do the same using a dynamically allocated semaphore to check the
- delete function is working correctly in both the static and dynamic
- allocation cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- xSemaphore = xSemaphoreCreateBinary();
- configASSERT( xSemaphore != NULL );
- prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
- vSemaphoreDelete( xSemaphore );
- }
- #endif
-
- /* There isn't a static version of the old and deprecated
- vSemaphoreCreateBinary() macro (because its deprecated!), but check it is
- still functioning correctly. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- vSemaphoreCreateBinary( xSemaphore );
-
- /* The macro starts with the binary semaphore available, but the test
- function expects it to be unavailable. */
- if( xSemaphoreTake( xSemaphore, staticDONT_BLOCK ) == pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
- vSemaphoreDelete( xSemaphore );
- }
- #endif
-}
+* and alignment requirements as the real semaphore structure. It is provided as a
+* mechanism for applications to know the size of the semaphore (which is dependent
+* on the architecture and configuration file settings) without breaking the strict
+* data hiding policy by exposing the real semaphore internals. This
+* StaticSemaphore_t variable is passed into the xSemaphoreCreateBinaryStatic()
+* function calls within this function. NOTE: In most usage scenarios now it is
+* faster and more memory efficient to use a direct to task notification instead of
+* a binary semaphore. http://www.freertos.org/RTOS-task-notifications.html */
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ /* Create the semaphore. xSemaphoreCreateBinaryStatic() has one more
+ * parameter than the usual xSemaphoreCreateBinary() function. The parameter
+ * is a pointer to the pre-allocated StaticSemaphore_t structure, which will
+ * hold information on the semaphore in an anonymous way. If the pointer is
+ * passed as NULL then the structure will be allocated dynamically, just as
+ * when xSemaphoreCreateBinary() is called. */
+ xSemaphore = xSemaphoreCreateBinaryStatic( &xSemaphoreBuffer );
+
+ /* The semaphore handle should equal the static semaphore structure passed
+ * into the xSemaphoreCreateBinaryStatic() function. */
+ configASSERT( xSemaphore == ( SemaphoreHandle_t ) &xSemaphoreBuffer );
+
+ /* Ensure the semaphore passes a few sanity checks as a valid semaphore. */
+ prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+
+ /* Delete the semaphore again so the buffers can be reused. */
+ vSemaphoreDelete( xSemaphore );
+
+ /* Now do the same using a dynamically allocated semaphore to check the
+ * delete function is working correctly in both the static and dynamic
+ * allocation cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ xSemaphore = xSemaphoreCreateBinary();
+ configASSERT( xSemaphore != NULL );
+ prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+ vSemaphoreDelete( xSemaphore );
+ }
+ #endif
+
+ /* There isn't a static version of the old and deprecated
+ * vSemaphoreCreateBinary() macro (because its deprecated!), but check it is
+ * still functioning correctly. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ vSemaphoreCreateBinary( xSemaphore );
+
+ /* The macro starts with the binary semaphore available, but the test
+ * function expects it to be unavailable. */
+ if( xSemaphoreTake( xSemaphore, staticDONT_BLOCK ) == pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ prvSanityCheckCreatedSemaphore( xSemaphore, staticBINARY_SEMAPHORE_MAX_COUNT );
+ vSemaphoreDelete( xSemaphore );
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ }
/*-----------------------------------------------------------*/
-static void prvTimerCallback( TimerHandle_t xExpiredTimer )
-{
-UBaseType_t *puxVariableToIncrement;
-BaseType_t xReturned;
-
- /* The timer callback just demonstrates it is executing by incrementing a
- variable - the address of which is passed into the timer as its ID. Obtain
- the address of the variable to increment. */
- puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
-
- /* Increment the variable to show the timer callback has executed. */
- ( *puxVariableToIncrement )++;
-
- /* If this callback has executed the required number of times, stop the
- timer. */
- if( *puxVariableToIncrement == staticMAX_TIMER_CALLBACK_EXECUTIONS )
- {
- /* This is called from a timer callback so must not block. See
- http://www.FreeRTOS.org/FreeRTOS-timers-xTimerStop.html */
- xReturned = xTimerStop( xExpiredTimer, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-}
+ static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ {
+ UBaseType_t * puxVariableToIncrement;
+ BaseType_t xReturned;
+
+ /* The timer callback just demonstrates it is executing by incrementing a
+ * variable - the address of which is passed into the timer as its ID. Obtain
+ * the address of the variable to increment. */
+ puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+
+ /* Increment the variable to show the timer callback has executed. */
+ ( *puxVariableToIncrement )++;
+
+ /* If this callback has executed the required number of times, stop the
+ * timer. */
+ if( *puxVariableToIncrement == staticMAX_TIMER_CALLBACK_EXECUTIONS )
+ {
+ /* This is called from a timer callback so must not block. See
+ * http://www.FreeRTOS.org/FreeRTOS-timers-xTimerStop.html */
+ xReturned = xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedTimers( void )
-{
-TimerHandle_t xTimer;
-UBaseType_t uxVariableToIncrement;
-const TickType_t xTimerPeriod = pdMS_TO_TICKS( 20 );
-BaseType_t xReturned;
+ static void prvCreateAndDeleteStaticallyAllocatedTimers( void )
+ {
+ TimerHandle_t xTimer;
+ UBaseType_t uxVariableToIncrement;
+ const TickType_t xTimerPeriod = pdMS_TO_TICKS( 20 );
+ BaseType_t xReturned;
/* StaticTimer_t is a publicly accessible structure that has the same size
-and alignment requirements as the real timer structure. It is provided as a
-mechanism for applications to know the size of the timer structure (which is
-dependent on the architecture and configuration file settings) without breaking
-the strict data hiding policy by exposing the real timer internals. This
-StaticTimer_t variable is passed into the xTimerCreateStatic() function calls
-within this function. */
-StaticTimer_t xTimerBuffer;
-
- /* Create the software time. xTimerCreateStatic() has an extra parameter
- than the normal xTimerCreate() API function. The parameter is a pointer to
- the StaticTimer_t structure that will hold the software timer structure. If
- the parameter is passed as NULL then the structure will be allocated
- dynamically, just as if xTimerCreate() had been called. */
- xTimer = xTimerCreateStatic( "T1", /* Text name for the task. Helps debugging only. Not used by FreeRTOS. */
- xTimerPeriod, /* The period of the timer in ticks. */
- pdTRUE, /* This is an auto-reload timer. */
- ( void * ) &uxVariableToIncrement, /* The variable incremented by the test is passed into the timer callback using the timer ID. */
- prvTimerCallback, /* The function to execute when the timer expires. */
- &xTimerBuffer ); /* The buffer that will hold the software timer structure. */
-
- /* The timer handle should equal the static timer structure passed into the
- xTimerCreateStatic() function. */
- configASSERT( xTimer == ( TimerHandle_t ) &xTimerBuffer );
-
- /* Set the variable to 0, wait for a few timer periods to expire, then check
- the timer callback has incremented the variable to the expected value. */
- uxVariableToIncrement = 0;
-
- /* This is a low priority so a block time should not be needed. */
- xReturned = xTimerStart( xTimer, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS );
-
- /* By now the timer should have expired staticMAX_TIMER_CALLBACK_EXECUTIONS
- times, and then stopped itself. */
- if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Finished with the timer, delete it. */
- xReturned = xTimerDelete( xTimer, staticDONT_BLOCK );
-
- /* Again, as this is a low priority task it is expected that the timer
- command will have been sent even without a block time being used. */
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Just to show the check task that this task is still executing. */
- uxCycleCounter++;
-
- /* Now do the same using a dynamically allocated software timer to ensure
- the delete function is working correctly in both the static and dynamic
- allocation cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- xTimer = xTimerCreate( "T1", /* Text name for the task. Helps debugging only. Not used by FreeRTOS. */
- xTimerPeriod, /* The period of the timer in ticks. */
- pdTRUE, /* This is an auto-reload timer. */
- ( void * ) &uxVariableToIncrement, /* The variable incremented by the test is passed into the timer callback using the timer ID. */
- prvTimerCallback ); /* The function to execute when the timer expires. */
-
- configASSERT( xTimer != NULL );
-
- uxVariableToIncrement = 0;
- xReturned = xTimerStart( xTimer, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS );
-
- if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- xReturned = xTimerDelete( xTimer, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- }
- #endif
-}
+ * and alignment requirements as the real timer structure. It is provided as a
+ * mechanism for applications to know the size of the timer structure (which is
+ * dependent on the architecture and configuration file settings) without breaking
+ * the strict data hiding policy by exposing the real timer internals. This
+ * StaticTimer_t variable is passed into the xTimerCreateStatic() function calls
+ * within this function. */
+ StaticTimer_t xTimerBuffer;
+
+ /* Create the software time. xTimerCreateStatic() has an extra parameter
+ * than the normal xTimerCreate() API function. The parameter is a pointer to
+ * the StaticTimer_t structure that will hold the software timer structure. If
+ * the parameter is passed as NULL then the structure will be allocated
+ * dynamically, just as if xTimerCreate() had been called. */
+ xTimer = xTimerCreateStatic( "T1", /* Text name for the task. Helps debugging only. Not used by FreeRTOS. */
+ xTimerPeriod, /* The period of the timer in ticks. */
+ pdTRUE, /* This is an auto-reload timer. */
+ ( void * ) &uxVariableToIncrement, /* The variable incremented by the test is passed into the timer callback using the timer ID. */
+ prvTimerCallback, /* The function to execute when the timer expires. */
+ &xTimerBuffer ); /* The buffer that will hold the software timer structure. */
+
+ /* The timer handle should equal the static timer structure passed into the
+ * xTimerCreateStatic() function. */
+ configASSERT( xTimer == ( TimerHandle_t ) &xTimerBuffer );
+
+ /* Set the variable to 0, wait for a few timer periods to expire, then check
+ * the timer callback has incremented the variable to the expected value. */
+ uxVariableToIncrement = 0;
+
+ /* This is a low priority so a block time should not be needed. */
+ xReturned = xTimerStart( xTimer, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS );
+
+ /* By now the timer should have expired staticMAX_TIMER_CALLBACK_EXECUTIONS
+ * times, and then stopped itself. */
+ if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Finished with the timer, delete it. */
+ xReturned = xTimerDelete( xTimer, staticDONT_BLOCK );
+
+ /* Again, as this is a low priority task it is expected that the timer
+ * command will have been sent even without a block time being used. */
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Just to show the check task that this task is still executing. */
+ uxCycleCounter++;
+
+ /* Now do the same using a dynamically allocated software timer to ensure
+ * the delete function is working correctly in both the static and dynamic
+ * allocation cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ xTimer = xTimerCreate( "T1", /* Text name for the task. Helps debugging only. Not used by FreeRTOS. */
+ xTimerPeriod, /* The period of the timer in ticks. */
+ pdTRUE, /* This is an auto-reload timer. */
+ ( void * ) &uxVariableToIncrement, /* The variable incremented by the test is passed into the timer callback using the timer ID. */
+ prvTimerCallback ); /* The function to execute when the timer expires. */
+
+ configASSERT( xTimer != NULL );
+
+ uxVariableToIncrement = 0;
+ xReturned = xTimerStart( xTimer, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ vTaskDelay( xTimerPeriod * staticMAX_TIMER_CALLBACK_EXECUTIONS );
+
+ if( uxVariableToIncrement != staticMAX_TIMER_CALLBACK_EXECUTIONS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ xReturned = xTimerDelete( xTimer, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void )
-{
-EventGroupHandle_t xEventGroup;
+ static void prvCreateAndDeleteStaticallyAllocatedEventGroups( void )
+ {
+ EventGroupHandle_t xEventGroup;
/* StaticEventGroup_t is a publicly accessible structure that has the same size
-and alignment requirements as the real event group structure. It is provided as
-a mechanism for applications to know the size of the event group (which is
-dependent on the architecture and configuration file settings) without breaking
-the strict data hiding policy by exposing the real event group internals. This
-StaticEventGroup_t variable is passed into the xSemaphoreCreateEventGroupStatic()
-function calls within this function. */
-StaticEventGroup_t xEventGroupBuffer;
-
- /* Create the event group. xEventGroupCreateStatic() has an extra parameter
- than the normal xEventGroupCreate() API function. The parameter is a
- pointer to the StaticEventGroup_t structure that will hold the event group
- structure. */
- xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
-
- /* The event group handle should equal the static event group structure
- passed into the xEventGroupCreateStatic() function. */
- configASSERT( xEventGroup == ( EventGroupHandle_t ) &xEventGroupBuffer );
-
- /* Ensure the event group passes a few sanity checks as a valid event
- group. */
- prvSanityCheckCreatedEventGroup( xEventGroup );
-
- /* Delete the event group again so the buffers can be reused. */
- vEventGroupDelete( xEventGroup );
-
- /* Now do the same using a dynamically allocated event group to ensure the
- delete function is working correctly in both the static and dynamic
- allocation cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- xEventGroup = xEventGroupCreate();
- configASSERT( xEventGroup != NULL );
- prvSanityCheckCreatedEventGroup( xEventGroup );
- vEventGroupDelete( xEventGroup );
- }
- #endif
-}
+ * and alignment requirements as the real event group structure. It is provided as
+ * a mechanism for applications to know the size of the event group (which is
+ * dependent on the architecture and configuration file settings) without breaking
+ * the strict data hiding policy by exposing the real event group internals. This
+ * StaticEventGroup_t variable is passed into the xSemaphoreCreateEventGroupStatic()
+ * function calls within this function. */
+ StaticEventGroup_t xEventGroupBuffer;
+
+ /* Create the event group. xEventGroupCreateStatic() has an extra parameter
+ * than the normal xEventGroupCreate() API function. The parameter is a
+ * pointer to the StaticEventGroup_t structure that will hold the event group
+ * structure. */
+ xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+ /* The event group handle should equal the static event group structure
+ * passed into the xEventGroupCreateStatic() function. */
+ configASSERT( xEventGroup == ( EventGroupHandle_t ) &xEventGroupBuffer );
+
+ /* Ensure the event group passes a few sanity checks as a valid event
+ * group. */
+ prvSanityCheckCreatedEventGroup( xEventGroup );
+
+ /* Delete the event group again so the buffers can be reused. */
+ vEventGroupDelete( xEventGroup );
+
+ /* Now do the same using a dynamically allocated event group to ensure the
+ * delete function is working correctly in both the static and dynamic
+ * allocation cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ xEventGroup = xEventGroupCreate();
+ configASSERT( xEventGroup != NULL );
+ prvSanityCheckCreatedEventGroup( xEventGroup );
+ vEventGroupDelete( xEventGroup );
+ }
+ #endif
+ }
/*-----------------------------------------------------------*/
-static void prvCreateAndDeleteStaticallyAllocatedTasks( void )
-{
-TaskHandle_t xCreatedTask;
+ static void prvCreateAndDeleteStaticallyAllocatedTasks( void )
+ {
+ TaskHandle_t xCreatedTask;
/* The variable that will hold the TCB of tasks created by this function. See
-the comments above the declaration of the xCreatorTaskTCBBuffer variable for
-more information. NOTE: This is not static so relies on the tasks that use it
-being deleted before this function returns and deallocates its stack. That will
-only be the case if configUSE_PREEMPTION is set to 1. */
-StaticTask_t xTCBBuffer;
+ * the comments above the declaration of the xCreatorTaskTCBBuffer variable for
+ * more information. NOTE: This is not static so relies on the tasks that use it
+ * being deleted before this function returns and deallocates its stack. That will
+ * only be the case if configUSE_PREEMPTION is set to 1. */
+ StaticTask_t xTCBBuffer;
/* This buffer that will be used as the stack of tasks created by this function.
-See the comments above the declaration of the uxCreatorTaskStackBuffer[] array
-above for more information. */
-static StackType_t uxStackBuffer[ configMINIMAL_STACK_SIZE ];
-
- /* Create the task. xTaskCreateStatic() has two more parameters than
- the usual xTaskCreate() function. The first new parameter is a pointer to
- the pre-allocated stack. The second new parameter is a pointer to the
- StaticTask_t structure that will hold the task's TCB. If both pointers are
- passed as NULL then the respective object will be allocated dynamically as
- if xTaskCreate() had been called. */
- xCreatedTask = xTaskCreateStatic(
- prvStaticallyAllocatedTask, /* Function that implements the task. */
- "Static", /* Human readable name for the task. */
- configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */
- NULL, /* Parameter to pass into the task. */
- uxTaskPriorityGet( NULL ) + 1, /* The priority of the task. */
- &( uxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */
- &xTCBBuffer ); /* The variable that will hold that task's TCB. */
-
- /* Check the task was created correctly, then delete the task. */
- if( xCreatedTask == NULL )
- {
- xErrorOccurred = pdTRUE;
- }
- else if( eTaskGetState( xCreatedTask ) != eSuspended )
- {
- /* The created task had a higher priority so should have executed and
- suspended itself by now. */
- xErrorOccurred = pdTRUE;
- }
- else
- {
- vTaskDelete( xCreatedTask );
- }
-
- /* Now do the same using a dynamically allocated task to ensure the delete
- function is working correctly in both the static and dynamic allocation
- cases. */
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- BaseType_t xReturned;
-
- xReturned = xTaskCreate(
- prvStaticallyAllocatedTask, /* Function that implements the task - the same function is used but is actually dynamically allocated this time. */
- "Static", /* Human readable name for the task. */
- configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */
- NULL, /* Parameter to pass into the task. */
- uxTaskPriorityGet( NULL ) + 1, /* The priority of the task. */
- &xCreatedTask ); /* Handle of the task being created. */
-
- if( eTaskGetState( xCreatedTask ) != eSuspended )
- {
- xErrorOccurred = pdTRUE;
- }
-
- configASSERT( xReturned == pdPASS );
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- vTaskDelete( xCreatedTask );
- }
- #endif
-}
+ * See the comments above the declaration of the uxCreatorTaskStackBuffer[] array
+ * above for more information. */
+ static StackType_t uxStackBuffer[ configMINIMAL_STACK_SIZE ];
+
+ /* Create the task. xTaskCreateStatic() has two more parameters than
+ * the usual xTaskCreate() function. The first new parameter is a pointer to
+ * the pre-allocated stack. The second new parameter is a pointer to the
+ * StaticTask_t structure that will hold the task's TCB. If both pointers are
+ * passed as NULL then the respective object will be allocated dynamically as
+ * if xTaskCreate() had been called. */
+ xCreatedTask = xTaskCreateStatic(
+ prvStaticallyAllocatedTask, /* Function that implements the task. */
+ "Static", /* Human readable name for the task. */
+ configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */
+ NULL, /* Parameter to pass into the task. */
+ uxTaskPriorityGet( NULL ) + 1, /* The priority of the task. */
+ &( uxStackBuffer[ 0 ] ), /* The buffer to use as the task's stack. */
+ &xTCBBuffer ); /* The variable that will hold that task's TCB. */
+
+ /* Check the task was created correctly, then delete the task. */
+ if( xCreatedTask == NULL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ else if( eTaskGetState( xCreatedTask ) != eSuspended )
+ {
+ /* The created task had a higher priority so should have executed and
+ * suspended itself by now. */
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ vTaskDelete( xCreatedTask );
+ }
+
+ /* Now do the same using a dynamically allocated task to ensure the delete
+ * function is working correctly in both the static and dynamic allocation
+ * cases. */
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ BaseType_t xReturned;
+
+ xReturned = xTaskCreate(
+ prvStaticallyAllocatedTask, /* Function that implements the task - the same function is used but is actually dynamically allocated this time. */
+ "Static", /* Human readable name for the task. */
+ configMINIMAL_STACK_SIZE, /* Task's stack size, in words (not bytes!). */
+ NULL, /* Parameter to pass into the task. */
+ uxTaskPriorityGet( NULL ) + 1, /* The priority of the task. */
+ &xCreatedTask ); /* Handle of the task being created. */
+
+ if( eTaskGetState( xCreatedTask ) != eSuspended )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ configASSERT( xReturned == pdPASS );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ vTaskDelete( xCreatedTask );
+ }
+ #endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+ }
/*-----------------------------------------------------------*/
-static void prvStaticallyAllocatedTask( void *pvParameters )
-{
- ( void ) pvParameters;
+ static void prvStaticallyAllocatedTask( void * pvParameters )
+ {
+ ( void ) pvParameters;
- /* The created task just suspends itself to wait to get deleted. The task
- that creates this task checks this task is in the expected Suspended state
- before deleting it. */
- vTaskSuspend( NULL );
-}
+ /* The created task just suspends itself to wait to get deleted. The task
+ * that creates this task checks this task is in the expected Suspended state
+ * before deleting it. */
+ vTaskSuspend( NULL );
+ }
/*-----------------------------------------------------------*/
-static UBaseType_t prvRand( void )
-{
-const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL;
+ static UBaseType_t prvRand( void )
+ {
+ const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL;
- /* Utility function to generate a pseudo random number. */
- ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;
- return( ( ulNextRand >> 16UL ) & 0x7fffUL );
-}
+ /* Utility function to generate a pseudo random number. */
+ ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;
+ return( ( ulNextRand >> 16UL ) & 0x7fffUL );
+ }
/*-----------------------------------------------------------*/
-static TickType_t prvGetNextDelayTime( void )
-{
-TickType_t xNextDelay;
-const TickType_t xMaxDelay = pdMS_TO_TICKS( ( TickType_t ) 150 );
-const TickType_t xMinDelay = pdMS_TO_TICKS( ( TickType_t ) 75 );
-const TickType_t xTinyDelay = pdMS_TO_TICKS( ( TickType_t ) 2 );
-
- /* Generate the next delay time. This is kept within a narrow band so as
- not to disturb the timing of other tests - but does add in some pseudo
- randomisation into the tests. */
- do
- {
- xNextDelay = prvRand() % xMaxDelay;
-
- /* Just in case this loop is executed lots of times. */
- vTaskDelay( xTinyDelay );
-
- } while ( xNextDelay < xMinDelay );
-
- return xNextDelay;
-}
+ static TickType_t prvGetNextDelayTime( void )
+ {
+ TickType_t xNextDelay;
+ const TickType_t xMaxDelay = pdMS_TO_TICKS( ( TickType_t ) 150 );
+ const TickType_t xMinDelay = pdMS_TO_TICKS( ( TickType_t ) 75 );
+ const TickType_t xTinyDelay = pdMS_TO_TICKS( ( TickType_t ) 2 );
+
+ /* Generate the next delay time. This is kept within a narrow band so as
+ * not to disturb the timing of other tests - but does add in some pseudo
+ * randomisation into the tests. */
+ do
+ {
+ xNextDelay = prvRand() % xMaxDelay;
+
+ /* Just in case this loop is executed lots of times. */
+ vTaskDelay( xTinyDelay );
+ } while( xNextDelay < xMinDelay );
+
+ return xNextDelay;
+ }
/*-----------------------------------------------------------*/
-static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup )
-{
-EventBits_t xEventBits;
-const EventBits_t xFirstTestBits = ( EventBits_t ) 0xaa, xSecondTestBits = ( EventBits_t ) 0x55;
+ static void prvSanityCheckCreatedEventGroup( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t xEventBits;
+ const EventBits_t xFirstTestBits = ( EventBits_t ) 0xaa, xSecondTestBits = ( EventBits_t ) 0x55;
- /* The event group should not have any bits set yet. */
- xEventBits = xEventGroupGetBits( xEventGroup );
+ /* The event group should not have any bits set yet. */
+ xEventBits = xEventGroupGetBits( xEventGroup );
- if( xEventBits != ( EventBits_t ) 0 )
- {
- xErrorOccurred = pdTRUE;
- }
+ if( xEventBits != ( EventBits_t ) 0 )
+ {
+ xErrorOccurred = pdTRUE;
+ }
- /* Some some bits, then read them back to check they are as expected. */
- xEventGroupSetBits( xEventGroup, xFirstTestBits );
+ /* Some some bits, then read them back to check they are as expected. */
+ xEventGroupSetBits( xEventGroup, xFirstTestBits );
- xEventBits = xEventGroupGetBits( xEventGroup );
+ xEventBits = xEventGroupGetBits( xEventGroup );
- if( xEventBits != xFirstTestBits )
- {
- xErrorOccurred = pdTRUE;
- }
+ if( xEventBits != xFirstTestBits )
+ {
+ xErrorOccurred = pdTRUE;
+ }
- xEventGroupSetBits( xEventGroup, xSecondTestBits );
+ xEventGroupSetBits( xEventGroup, xSecondTestBits );
- xEventBits = xEventGroupGetBits( xEventGroup );
+ xEventBits = xEventGroupGetBits( xEventGroup );
- if( xEventBits != ( xFirstTestBits | xSecondTestBits ) )
- {
- xErrorOccurred = pdTRUE;
- }
+ if( xEventBits != ( xFirstTestBits | xSecondTestBits ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
- /* Finally try clearing some bits too and check that operation proceeds as
- expected. */
- xEventGroupClearBits( xEventGroup, xFirstTestBits );
+ /* Finally try clearing some bits too and check that operation proceeds as
+ * expected. */
+ xEventGroupClearBits( xEventGroup, xFirstTestBits );
- xEventBits = xEventGroupGetBits( xEventGroup );
+ xEventBits = xEventGroupGetBits( xEventGroup );
- if( xEventBits != xSecondTestBits )
- {
- xErrorOccurred = pdTRUE;
- }
-}
+ if( xEventBits != xSecondTestBits )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore, UBaseType_t uxMaxCount )
-{
-BaseType_t xReturned;
-UBaseType_t x;
-const TickType_t xShortBlockTime = pdMS_TO_TICKS( 10 );
-TickType_t xTickCount;
-
- /* The binary semaphore should start 'empty', so a call to xSemaphoreTake()
- should fail. */
- xTickCount = xTaskGetTickCount();
- xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime );
-
- if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime )
- {
- /* Did not block on the semaphore as long as expected. */
- xErrorOccurred = pdTRUE;
- }
-
- if( xReturned != pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Should be possible to 'give' the semaphore up to a maximum of uxMaxCount
- times. */
- for( x = 0; x < uxMaxCount; x++ )
- {
- xReturned = xSemaphoreGive( xSemaphore );
-
- if( xReturned == pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* Giving the semaphore again should fail, as it is 'full'. */
- xReturned = xSemaphoreGive( xSemaphore );
-
- if( xReturned != pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- configASSERT( uxSemaphoreGetCount( xSemaphore ) == uxMaxCount );
-
- /* Should now be possible to 'take' the semaphore up to a maximum of
- uxMaxCount times without blocking. */
- for( x = 0; x < uxMaxCount; x++ )
- {
- xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
-
- if( xReturned == pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* Back to the starting condition, where the semaphore should not be
- available. */
- xTickCount = xTaskGetTickCount();
- xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime );
-
- if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime )
- {
- /* Did not block on the semaphore as long as expected. */
- xErrorOccurred = pdTRUE;
- }
-
- if( xReturned != pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );
-}
+ static void prvSanityCheckCreatedSemaphore( SemaphoreHandle_t xSemaphore,
+ UBaseType_t uxMaxCount )
+ {
+ BaseType_t xReturned;
+ UBaseType_t x;
+ const TickType_t xShortBlockTime = pdMS_TO_TICKS( 10 );
+ TickType_t xTickCount;
+
+ /* The binary semaphore should start 'empty', so a call to xSemaphoreTake()
+ * should fail. */
+ xTickCount = xTaskGetTickCount();
+ xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime );
+
+ if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime )
+ {
+ /* Did not block on the semaphore as long as expected. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( xReturned != pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Should be possible to 'give' the semaphore up to a maximum of uxMaxCount
+ * times. */
+ for( x = 0; x < uxMaxCount; x++ )
+ {
+ xReturned = xSemaphoreGive( xSemaphore );
+
+ if( xReturned == pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* Giving the semaphore again should fail, as it is 'full'. */
+ xReturned = xSemaphoreGive( xSemaphore );
+
+ if( xReturned != pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == uxMaxCount );
+
+ /* Should now be possible to 'take' the semaphore up to a maximum of
+ * uxMaxCount times without blocking. */
+ for( x = 0; x < uxMaxCount; x++ )
+ {
+ xReturned = xSemaphoreTake( xSemaphore, staticDONT_BLOCK );
+
+ if( xReturned == pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* Back to the starting condition, where the semaphore should not be
+ * available. */
+ xTickCount = xTaskGetTickCount();
+ xReturned = xSemaphoreTake( xSemaphore, xShortBlockTime );
+
+ if( ( ( TickType_t ) ( xTaskGetTickCount() - xTickCount ) ) < xShortBlockTime )
+ {
+ /* Did not block on the semaphore as long as expected. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( xReturned != pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );
+ }
/*-----------------------------------------------------------*/
-static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue )
-{
-uint64_t ull, ullRead;
-BaseType_t xReturned, xLoop;
-
- /* This test is done twice to ensure the queue storage area wraps. */
- for( xLoop = 0; xLoop < 2; xLoop++ )
- {
- /* A very basic test that the queue can be written to and read from as
- expected. First the queue should be empty. */
- xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK );
- if( xReturned != errQUEUE_EMPTY )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now it should be possible to write to the queue staticQUEUE_LENGTH_IN_ITEMS
- times. */
- for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ )
- {
- xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK );
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* Should not now be possible to write to the queue again. */
- xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK );
- if( xReturned != errQUEUE_FULL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now read back from the queue to ensure the data read back matches that
- written. */
- for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ )
- {
- xReturned = xQueueReceive( xQueue, &ullRead, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- if( ullRead != ull )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* The queue should be empty again. */
- xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK );
- if( xReturned != errQUEUE_EMPTY )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-}
+ static void prvSanityCheckCreatedQueue( QueueHandle_t xQueue )
+ {
+ uint64_t ull, ullRead;
+ BaseType_t xReturned, xLoop;
+
+ /* This test is done twice to ensure the queue storage area wraps. */
+ for( xLoop = 0; xLoop < 2; xLoop++ )
+ {
+ /* A very basic test that the queue can be written to and read from as
+ * expected. First the queue should be empty. */
+ xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK );
+
+ if( xReturned != errQUEUE_EMPTY )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now it should be possible to write to the queue staticQUEUE_LENGTH_IN_ITEMS
+ * times. */
+ for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ )
+ {
+ xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* Should not now be possible to write to the queue again. */
+ xReturned = xQueueSend( xQueue, &ull, staticDONT_BLOCK );
+
+ if( xReturned != errQUEUE_FULL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now read back from the queue to ensure the data read back matches that
+ * written. */
+ for( ull = 0; ull < staticQUEUE_LENGTH_IN_ITEMS; ull++ )
+ {
+ xReturned = xQueueReceive( xQueue, &ullRead, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( ullRead != ull )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* The queue should be empty again. */
+ xReturned = xQueueReceive( xQueue, &ull, staticDONT_BLOCK );
+
+ if( xReturned != errQUEUE_EMPTY )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+ }
/*-----------------------------------------------------------*/
-static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore )
-{
-const BaseType_t xLoops = 5;
-BaseType_t x, xReturned;
-
- /* A very basic test that the recursive semaphore behaved like a recursive
- semaphore. First the semaphore should not be able to be given, as it has not
- yet been taken. */
- xReturned = xSemaphoreGiveRecursive( xSemaphore );
-
- if( xReturned != pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now it should be possible to take the mutex a number of times. */
- for( x = 0; x < xLoops; x++ )
- {
- xReturned = xSemaphoreTakeRecursive( xSemaphore, staticDONT_BLOCK );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* Should be possible to give the semaphore the same number of times as it
- was given in the loop above. */
- for( x = 0; x < xLoops; x++ )
- {
- xReturned = xSemaphoreGiveRecursive( xSemaphore );
-
- if( xReturned != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* No more gives should be possible though. */
- xReturned = xSemaphoreGiveRecursive( xSemaphore );
-
- if( xReturned != pdFAIL )
- {
- xErrorOccurred = pdTRUE;
- }
-}
+ static void prvSanityCheckCreatedRecursiveMutex( SemaphoreHandle_t xSemaphore )
+ {
+ const BaseType_t xLoops = 5;
+ BaseType_t x, xReturned;
+
+ /* A very basic test that the recursive semaphore behaved like a recursive
+ * semaphore. First the semaphore should not be able to be given, as it has not
+ * yet been taken. */
+ xReturned = xSemaphoreGiveRecursive( xSemaphore );
+
+ if( xReturned != pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now it should be possible to take the mutex a number of times. */
+ for( x = 0; x < xLoops; x++ )
+ {
+ xReturned = xSemaphoreTakeRecursive( xSemaphore, staticDONT_BLOCK );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* Should be possible to give the semaphore the same number of times as it
+ * was given in the loop above. */
+ for( x = 0; x < xLoops; x++ )
+ {
+ xReturned = xSemaphoreGiveRecursive( xSemaphore );
+
+ if( xReturned != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* No more gives should be possible though. */
+ xReturned = xSemaphoreGiveRecursive( xSemaphore );
+
+ if( xReturned != pdFAIL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
/*-----------------------------------------------------------*/
-BaseType_t xAreStaticAllocationTasksStillRunning( void )
-{
-static UBaseType_t uxLastCycleCounter = 0;
-BaseType_t xReturn;
-
- if( uxCycleCounter == uxLastCycleCounter )
- {
- xErrorOccurred = pdTRUE;
- }
- else
- {
- uxLastCycleCounter = uxCycleCounter;
- }
-
- if( xErrorOccurred != pdFALSE )
- {
- xReturn = pdFAIL;
- }
- else
- {
- xReturn = pdPASS;
- }
-
- return xReturn;
-}
+ BaseType_t xAreStaticAllocationTasksStillRunning( void )
+ {
+ static UBaseType_t uxLastCycleCounter = 0;
+ BaseType_t xReturn;
+
+ if( uxCycleCounter == uxLastCycleCounter )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ uxLastCycleCounter = uxCycleCounter;
+ }
+
+ if( xErrorOccurred != pdFALSE )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+ }
/*-----------------------------------------------------------*/
/* Exclude the entire file if configSUPPORT_STATIC_ALLOCATION is 0. */
diff --git a/Demo/Common/Minimal/StreamBufferDemo.c b/Demo/Common/Minimal/StreamBufferDemo.c
index ec73e316b..7f691f23a 100644
--- a/Demo/Common/Minimal/StreamBufferDemo.c
+++ b/Demo/Common/Minimal/StreamBufferDemo.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -37,47 +37,47 @@
#include "StreamBufferDemo.h"
/* The number of bytes of storage in the stream buffers used in this test. */
-#define sbSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 30 )
+#define sbSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 30 )
/* Stream buffer length one. */
-#define sbSTREAM_BUFFER_LENGTH_ONE ( ( size_t ) 1 )
+#define sbSTREAM_BUFFER_LENGTH_ONE ( ( size_t ) 1 )
/* Start and end ASCII characters used in data sent to the buffers. */
-#define sbASCII_SPACE 32
-#define sbASCII_TILDA 126
+#define sbASCII_SPACE 32
+#define sbASCII_TILDA 126
/* Defines the number of tasks to create in this test and demo. */
-#define sbNUMBER_OF_ECHO_CLIENTS ( 2 )
-#define sbNUMBER_OF_SENDER_TASKS ( 2 )
+#define sbNUMBER_OF_ECHO_CLIENTS ( 2 )
+#define sbNUMBER_OF_SENDER_TASKS ( 2 )
/* Priority of the test tasks. The send and receive go from low to high
-priority tasks, and from high to low priority tasks. */
-#define sbLOWER_PRIORITY ( tskIDLE_PRIORITY )
-#define sbHIGHER_PRIORITY ( tskIDLE_PRIORITY + 1 )
+ * priority tasks, and from high to low priority tasks. */
+#define sbLOWER_PRIORITY ( tskIDLE_PRIORITY )
+#define sbHIGHER_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* Block times used when sending and receiving from the stream buffers. */
-#define sbRX_TX_BLOCK_TIME pdMS_TO_TICKS( 125UL )
+#define sbRX_TX_BLOCK_TIME pdMS_TO_TICKS( 125UL )
/* A block time of 0 means "don't block". */
-#define sbDONT_BLOCK ( 0 )
+#define sbDONT_BLOCK ( 0 )
/* The trigger level sets the number of bytes that must be present in the
-stream buffer before a task that is blocked on the stream buffer is moved out of
-the Blocked state so it can read the bytes. */
-#define sbTRIGGER_LEVEL_1 ( 1 )
+ * stream buffer before a task that is blocked on the stream buffer is moved out of
+ * the Blocked state so it can read the bytes. */
+#define sbTRIGGER_LEVEL_1 ( 1 )
/* The size of the stack allocated to the tasks that run as part of this demo/
-test. The stack size is over generous in most cases. */
+ * test. The stack size is over generous in most cases. */
#ifndef configSTREAM_BUFFER_SENDER_TASK_STACK_SIZE
- #define sbSTACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) )
+ #define sbSTACK_SIZE ( configMINIMAL_STACK_SIZE + ( configMINIMAL_STACK_SIZE >> 1 ) )
#else
- #define sbSTACK_SIZE configSTREAM_BUFFER_SENDER_TASK_STACK_SIZE
+ #define sbSTACK_SIZE configSTREAM_BUFFER_SENDER_TASK_STACK_SIZE
#endif
#ifndef configSTREAM_BUFFER_SMALLER_TASK_STACK_SIZE
- #define sbSMALLER_STACK_SIZE sbSTACK_SIZE
+ #define sbSMALLER_STACK_SIZE sbSTACK_SIZE
#else
- #define sbSMALLER_STACK_SIZE configSTREAM_BUFFER_SMALLER_TASK_STACK_SIZE
+ #define sbSMALLER_STACK_SIZE configSTREAM_BUFFER_SMALLER_TASK_STACK_SIZE
#endif
/*-----------------------------------------------------------*/
@@ -93,19 +93,19 @@ static void prvSingleTaskTests( StreamBufferHandle_t xStreamBuffer );
* data back to the echo client, which checks it receives exactly what it
* sent.
*/
-static void prvEchoClient( void *pvParameters );
-static void prvEchoServer( void *pvParameters );
+static void prvEchoClient( void * pvParameters );
+static void prvEchoServer( void * pvParameters );
/*
* Tasks that send and receive to a stream buffer at a low priority and without
* blocking, so the send and receive functions interleave in time as the tasks
* are switched in and out.
*/
-static void prvNonBlockingReceiverTask( void *pvParameters );
-static void prvNonBlockingSenderTask( void *pvParameters );
+static void prvNonBlockingReceiverTask( void * pvParameters );
+static void prvNonBlockingSenderTask( void * pvParameters );
/* Performs an assert() like check in a way that won't get removed when
-performing a code coverage analysis. */
+ * performing a code coverage analysis. */
static void prvCheckExpectedState( BaseType_t xState );
/*
@@ -113,24 +113,25 @@ static void prvCheckExpectedState( BaseType_t xState );
* receives a string from an interrupt (the RTOS tick hook) byte by byte to
* check it is only unblocked when the specified trigger level is reached.
*/
-static void prvInterruptTriggerLevelTest( void *pvParameters );
+static void prvInterruptTriggerLevelTest( void * pvParameters );
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- /* This file tests both statically and dynamically allocated stream buffers.
- Allocate the structures and buffers to be used by the statically allocated
- objects, which get used in the echo tests. */
- static void prvReceiverTask( void *pvParameters );
- static void prvSenderTask( void *pvParameters );
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
- static StaticStreamBuffer_t xStaticStreamBuffers[ sbNUMBER_OF_ECHO_CLIENTS ];
- static uint32_t ulSenderLoopCounters[ sbNUMBER_OF_SENDER_TASKS ] = { 0 };
+/* This file tests both statically and dynamically allocated stream buffers.
+ * Allocate the structures and buffers to be used by the statically allocated
+ * objects, which get used in the echo tests. */
+ static void prvReceiverTask( void * pvParameters );
+ static void prvSenderTask( void * pvParameters );
+
+ static StaticStreamBuffer_t xStaticStreamBuffers[ sbNUMBER_OF_ECHO_CLIENTS ];
+ static uint32_t ulSenderLoopCounters[ sbNUMBER_OF_SENDER_TASKS ] = { 0 };
#endif /* configSUPPORT_STATIC_ALLOCATION */
/* The +1 is to make the test logic easier as the function that calculates the
-free space will return one less than the actual free space - adding a 1 to the
-actual length makes it appear to the tests as if the free space is returned as
-it might logically be expected. Returning 1 less than the actual free space is
-fine as it can never result in an overrun. */
+ * free space will return one less than the actual free space - adding a 1 to the
+ * actual length makes it appear to the tests as if the free space is returned as
+ * it might logically be expected. Returning 1 less than the actual free space is
+ * fine as it can never result in an overrun. */
static uint8_t ucBufferStorage[ sbNUMBER_OF_SENDER_TASKS ][ sbSTREAM_BUFFER_LENGTH_BYTES + 1 ];
/*-----------------------------------------------------------*/
@@ -138,1104 +139,1109 @@ static uint8_t ucBufferStorage[ sbNUMBER_OF_SENDER_TASKS ][ sbSTREAM_BUFFER_LENG
/* The buffers used by the echo client and server tasks. */
typedef struct ECHO_STREAM_BUFFERS
{
- /* Handles to the data structures that describe the stream buffers. */
- StreamBufferHandle_t xEchoClientBuffer;
- StreamBufferHandle_t xEchoServerBuffer;
+ /* Handles to the data structures that describe the stream buffers. */
+ StreamBufferHandle_t xEchoClientBuffer;
+ StreamBufferHandle_t xEchoServerBuffer;
} EchoStreamBuffers_t;
static volatile uint32_t ulEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
/* The non-blocking tasks monitor their operation, and if no errors have been
-found, increment ulNonBlockingRxCounter. xAreStreamBufferTasksStillRunning()
-then checks ulNonBlockingRxCounter and only returns pdPASS if
-ulNonBlockingRxCounter is still incrementing. */
+ * found, increment ulNonBlockingRxCounter. xAreStreamBufferTasksStillRunning()
+ * then checks ulNonBlockingRxCounter and only returns pdPASS if
+ * ulNonBlockingRxCounter is still incrementing. */
static volatile uint32_t ulNonBlockingRxCounter = 0;
/* The task that receives characters from the tick interrupt in order to test
-different trigger levels monitors its own behaviour. If it has not detected any
-error then it increments ulInterruptTriggerCounter to indicate to the check task
-that it is still operating correctly. */
+ * different trigger levels monitors its own behaviour. If it has not detected any
+ * error then it increments ulInterruptTriggerCounter to indicate to the check task
+ * that it is still operating correctly. */
static volatile uint32_t ulInterruptTriggerCounter = 0UL;
/* The stream buffer used from the tick interrupt. This sends one byte at a time
-to a test task to test the trigger level operation. The variable is set to NULL
-in between test runs. */
+ * to a test task to test the trigger level operation. The variable is set to NULL
+ * in between test runs. */
static volatile StreamBufferHandle_t xInterruptStreamBuffer = NULL;
/* The data sent from the tick interrupt to the task that tests the trigger
-level functionality. */
-static const char *pcDataSentFromInterrupt = "0123456789";
+ * level functionality. */
+static const char * pcDataSentFromInterrupt = "0123456789";
/* Data that is longer than the buffer that is sent to the buffers as a stream
-of bytes. Parts of which are written to the stream buffer to test writing
-different lengths at different offsets, to many bytes, part streams, streams
-that wrap, etc.. Two messages are defined to ensure left over data is not
-accidentally read out of the buffer. */
-static const char *pc55ByteString = "One two three four five six seven eight nine ten eleven";
-static const char *pc54ByteString = "01234567891abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQ";
+ * of bytes. Parts of which are written to the stream buffer to test writing
+ * different lengths at different offsets, to many bytes, part streams, streams
+ * that wrap, etc.. Two messages are defined to ensure left over data is not
+ * accidentally read out of the buffer. */
+static const char * pc55ByteString = "One two three four five six seven eight nine ten eleven";
+static const char * pc54ByteString = "01234567891abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQ";
/* Used to log the status of the tests contained within this file for reporting
-to a monitoring task ('check' task). */
+ * to a monitoring task ('check' task). */
static BaseType_t xErrorStatus = pdPASS;
/*-----------------------------------------------------------*/
void vStartStreamBufferTasks( void )
{
-StreamBufferHandle_t xStreamBuffer;
-
- /* The echo servers sets up the stream buffers before creating the echo
- client tasks. One set of tasks has the server as the higher priority, and
- the other has the client as the higher priority. */
- xTaskCreate( prvEchoServer, "1StrEchoServer", sbSMALLER_STACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL );
- xTaskCreate( prvEchoServer, "2StrEchoServer", sbSMALLER_STACK_SIZE, NULL, sbLOWER_PRIORITY, NULL );
-
- /* The non blocking tasks run continuously and will interleave with each
- other, so must be created at the lowest priority. The stream buffer they
- use is created and passed in using the task's parameter. */
- xStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
- xTaskCreate( prvNonBlockingReceiverTask, "StrNonBlkRx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL );
- xTaskCreate( prvNonBlockingSenderTask, "StrNonBlkTx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL );
-
- /* The task that receives bytes from an interrupt to test that it unblocks
- at a specific trigger level must run at a high priority to minimise the risk
- of it receiving more characters before it can execute again after being
- unblocked. */
- xTaskCreate( prvInterruptTriggerLevelTest, "StrTrig", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* The sender tasks set up the stream buffers before creating the
- receiver tasks. Priorities must be 0 and 1 as the priority is used to
- index into the xStaticStreamBuffers and ucBufferStorage arrays. */
- xTaskCreate( prvSenderTask, "Str1Sender", sbSMALLER_STACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL );
- xTaskCreate( prvSenderTask, "Str2Sender", sbSMALLER_STACK_SIZE, NULL, sbLOWER_PRIORITY, NULL );
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ StreamBufferHandle_t xStreamBuffer;
+
+ /* The echo servers sets up the stream buffers before creating the echo
+ * client tasks. One set of tasks has the server as the higher priority, and
+ * the other has the client as the higher priority. */
+ xTaskCreate( prvEchoServer, "1StrEchoServer", sbSMALLER_STACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL );
+ xTaskCreate( prvEchoServer, "2StrEchoServer", sbSMALLER_STACK_SIZE, NULL, sbLOWER_PRIORITY, NULL );
+
+ /* The non blocking tasks run continuously and will interleave with each
+ * other, so must be created at the lowest priority. The stream buffer they
+ * use is created and passed in using the task's parameter. */
+ xStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+ xTaskCreate( prvNonBlockingReceiverTask, "StrNonBlkRx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvNonBlockingSenderTask, "StrNonBlkTx", configMINIMAL_STACK_SIZE, ( void * ) xStreamBuffer, tskIDLE_PRIORITY, NULL );
+
+ /* The task that receives bytes from an interrupt to test that it unblocks
+ * at a specific trigger level must run at a high priority to minimise the risk
+ * of it receiving more characters before it can execute again after being
+ * unblocked. */
+ xTaskCreate( prvInterruptTriggerLevelTest, "StrTrig", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL );
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ /* The sender tasks set up the stream buffers before creating the
+ * receiver tasks. Priorities must be 0 and 1 as the priority is used to
+ * index into the xStaticStreamBuffers and ucBufferStorage arrays. */
+ xTaskCreate( prvSenderTask, "Str1Sender", sbSMALLER_STACK_SIZE, NULL, sbHIGHER_PRIORITY, NULL );
+ xTaskCreate( prvSenderTask, "Str2Sender", sbSMALLER_STACK_SIZE, NULL, sbLOWER_PRIORITY, NULL );
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
}
/*-----------------------------------------------------------*/
static void prvCheckExpectedState( BaseType_t xState )
{
- configASSERT( xState );
- if( xState == pdFAIL )
- {
- xErrorStatus = pdFAIL;
- }
+ configASSERT( xState );
+
+ if( xState == pdFAIL )
+ {
+ xErrorStatus = pdFAIL;
+ }
}
/*-----------------------------------------------------------*/
static void prvSingleTaskTests( StreamBufferHandle_t xStreamBuffer )
{
-size_t xReturned, xItem, xExpected, xExpectedSpaces, xExpectedBytes;
-const size_t xMax6ByteMessages = sbSTREAM_BUFFER_LENGTH_BYTES / 6;
-const size_t xTrueSize = ( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS );
-const size_t x6ByteLength = 6, x17ByteLength = 17, xFullBufferSize = sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2;
-uint8_t *pucFullBuffer, *pucData, *pucReadData;
-TickType_t xTimeBeforeCall, xTimeAfterCall;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 15 ), xAllowableMargin = pdMS_TO_TICKS( 3 ), xMinimalBlockTime = 2;
-UBaseType_t uxOriginalPriority;
-
- /* Remove warning in case configASSERT() is not defined. */
- ( void ) xAllowableMargin;
-
- /* To minimise stack and heap usage a full size buffer is allocated from the
- heap, then buffers which hold smaller amounts of data are overlayed with the
- larger buffer - just make sure not to use both at once! */
- pucFullBuffer = pvPortMalloc( xFullBufferSize );
- configASSERT( pucFullBuffer );
-
- pucData = pucFullBuffer;
- pucReadData = pucData + x17ByteLength;
-
- /* Nothing has been added or removed yet, so expect the free space to be
- exactly as created. Head and tail are both at 0. */
- xExpectedSpaces = sbSTREAM_BUFFER_LENGTH_BYTES;
- xExpectedBytes = 0;
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Add a single item - number of bytes available should go up by one and spaces
- available down by one. Head is in front of tail. */
- xExpectedSpaces--;
- xExpectedBytes++;
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == sizeof( *pucData ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Now fill the buffer by adding another 29 bytes. Head is 30 tail is at 0. */
- xExpectedSpaces -= 29;
- xExpectedBytes += 29;
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, ( sbSTREAM_BUFFER_LENGTH_BYTES - 1 ), ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - 1 ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
-
- /* Should not be able to add another byte now. */
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == ( size_t ) 0 );
-
- /* Remove a byte so the tail pointer moves off 0. Head pointer remains at the
- end of the buffer. */
- xExpectedSpaces += 1;
- xExpectedBytes -= 1;
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == sizeof( *pucData ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Should be able to add another byte to fill the buffer again now. */
- xExpectedSpaces -= 1;
- xExpectedBytes += 1;
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == sizeof( *pucData ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
-
- /* Now the head pointer is behind the tail pointer. Read another 29 bytes so
- the tail pointer moves to the end of the buffer. */
- xExpectedSpaces += 29;
- xExpectedBytes -= 29;
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, ( size_t ) 29, ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == ( size_t ) 29 );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Read out one more byte to wrap the tail back around to the start, to get back
- to where we started. */
- xExpectedSpaces += 1;
- xExpectedBytes -= 1;
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
- prvCheckExpectedState( xReturned == sizeof( *pucData ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedBytes );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Try filling the message buffer in one write, blocking indefinitely. Expect to
- have written one byte less. */
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, xTrueSize, portMAX_DELAY );
- xExpectedSpaces = ( size_t ) 0;
- prvCheckExpectedState( xReturned == ( xTrueSize - ( size_t ) 1 ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == xExpectedSpaces );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
-
- /* Empty the buffer again ready for the rest of the tests. Again block
- indefinitely to ensure reading more than there can possible be won't lock this
- task up, so expect to actually receive one byte less than requested. */
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, xTrueSize, portMAX_DELAY );
- prvCheckExpectedState( xReturned == ( xTrueSize - ( size_t ) 1 ) );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == sbSTREAM_BUFFER_LENGTH_BYTES );
- xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == ( size_t ) 0 );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
-
- /* The buffer is 30 bytes long. 6 5 byte messages should fit before the
- buffer is completely full. */
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
- {
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Generate recognisable data to write to the buffer. This is just
- ascii characters that shows which loop iteration the data was written
- in. The 'FromISR' version is used to give it some exercise as a block
- time is not used, so the call must be inside a critical section so it
- runs with ports that don't support interrupt nesting (and therefore
- don't have interrupt safe critical sections). */
- memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
- taskENTER_CRITICAL();
- {
- xReturned = xStreamBufferSendFromISR( xStreamBuffer, ( void * ) pucData, x6ByteLength, NULL );
- }
- taskEXIT_CRITICAL();
- prvCheckExpectedState( xReturned == x6ByteLength );
-
- /* The space in the buffer will have reduced by the amount of user data
- written into the buffer. */
- xExpected -= x6ByteLength;
- xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == xExpected );
- xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
- /* +1 as it is zero indexed. */
- prvCheckExpectedState( xReturned == ( ( xItem + 1 ) * x6ByteLength ) );
- }
-
- /* Now the buffer should be full, and attempting to add anything should fail. */
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), sbDONT_BLOCK );
- prvCheckExpectedState( xReturned == 0 );
-
- /* Adding with a timeout should also fail after the appropriate time. The
- priority is temporarily boosted in this part of the test to keep the
- allowable margin to a minimum. */
- uxOriginalPriority = uxTaskPriorityGet( NULL );
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
- xTimeBeforeCall = xTaskGetTickCount();
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime );
- xTimeAfterCall = xTaskGetTickCount();
- vTaskPrioritySet( NULL, uxOriginalPriority );
- prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime );
- prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) );
- prvCheckExpectedState( xReturned == 0 );
-
- /* The buffer is now full of data in the form "000000", "111111", etc. Make
- sure the data is read out as expected. */
- for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
- {
- /* Generate the data that is expected to be read out for this loop
- iteration. */
- memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
-
- /* Read the next 6 bytes out. The 'FromISR' version is used to give it
- some exercise as a block time is not used, so a it must be called from
- a critical section so this will work on ports that don't support
- interrupt nesting (so don't have interrupt safe critical sections). */
- taskENTER_CRITICAL();
- {
- xReturned = xStreamBufferReceiveFromISR( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, NULL );
- }
- taskEXIT_CRITICAL();
- prvCheckExpectedState( xReturned == x6ByteLength );
-
- /* Does the data read out match that expected? */
- prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 );
-
- /* The space in the buffer will have increased by the amount of user
- data removed from the buffer. */
- xExpected += x6ByteLength;
- xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == xExpected );
- xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - xExpected ) );
- }
-
- /* The buffer should be empty again. */
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
- xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xExpected == sbSTREAM_BUFFER_LENGTH_BYTES );
-
- /* Reading with a timeout should also fail after the appropriate time. The
- priority is temporarily boosted in this part of the test to keep the
- allowable margin to a minimum. */
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
- xTimeBeforeCall = xTaskGetTickCount();
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime );
- xTimeAfterCall = xTaskGetTickCount();
- vTaskPrioritySet( NULL, uxOriginalPriority );
- prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime );
- prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) );
- prvCheckExpectedState( xReturned == 0 );
-
-
- /* In the next loop 17 bytes are written to then read out on each
- iteration. As 30 is not divisible by 17 the data will wrap around. */
- xExpected = sbSTREAM_BUFFER_LENGTH_BYTES - x17ByteLength;
-
- for( xItem = 0; xItem < 100; xItem++ )
- {
- /* Generate recognisable data to write to the queue. This is just
- ascii characters that shows which loop iteration the data was written
- in. */
- memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength );
- xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, x17ByteLength, sbDONT_BLOCK );
- prvCheckExpectedState( xReturned == x17ByteLength );
-
- /* The space in the buffer will have reduced by the amount of user data
- written into the buffer. */
- xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == xExpected );
- xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == x17ByteLength );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
-
- /* Read the 17 bytes out again. */
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x17ByteLength, sbDONT_BLOCK );
- prvCheckExpectedState( xReturned == x17ByteLength );
-
- /* Does the data read out match that expected? */
- prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 );
-
- /* Full buffer space available again. */
- xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
- xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
- prvCheckExpectedState( xReturned == 0 );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
- }
-
- /* Fill the buffer with one message, check it is full, then read it back
- again and check the correct data is received. */
- xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK );
- xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK );
- prvCheckExpectedState( memcmp( pc55ByteString, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
-
- /* Fill the buffer one bytes at a time. */
- for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ )
- {
- /* Block time is only for test coverage, the task should never actually
- block here. */
- xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xItem ] ), sizeof( char ), sbRX_TX_BLOCK_TIME );
- }
-
- /* The buffer should now be full. */
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
-
- /* Read the message out in one go, even though it was written in individual
- bytes. Try reading much more data than is actually available to ensure only
- the available bytes are returned (otherwise this read will write outside of
- the memory allocated anyway!). */
- xReturned = xStreamBufferReceive( xStreamBuffer, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, sbRX_TX_BLOCK_TIME );
- prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
- prvCheckExpectedState( memcmp( ( const void * ) pc54ByteString, ( const void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
-
- /* Now do the opposite, write in one go and read out in single bytes. */
- xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbRX_TX_BLOCK_TIME );
- prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferBytesAvailable( xStreamBuffer ) == sbSTREAM_BUFFER_LENGTH_BYTES );
- prvCheckExpectedState( xStreamBufferSpacesAvailable( xStreamBuffer ) == 0 );
-
- /* Read from the buffer one byte at a time. */
- for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ )
- {
- /* Block time is only for test coverage, the task should never actually
- block here. */
- xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sizeof( char ), sbRX_TX_BLOCK_TIME );
- prvCheckExpectedState( pc55ByteString[ xItem ] == pucFullBuffer[ 0 ] );
- }
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
-
- /* Try writing more bytes than there is space. */
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
- xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime );
- vTaskPrioritySet( NULL, uxOriginalPriority );
- prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
-
- /* No space now though. */
- xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime );
- prvCheckExpectedState( xReturned == 0 );
-
- /* Ensure data was written as expected even when there was an attempt to
- write more than was available. This also tries to read more bytes than are
- available. */
- xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, xFullBufferSize, xMinimalBlockTime );
- prvCheckExpectedState( memcmp( ( const void * ) pucFullBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
- prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
- prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
-
- /* Clean up with data in the buffer to ensure the tests that follow don't
- see the data (the data should be discarded). */
- ( void ) xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES / ( size_t ) 2, sbDONT_BLOCK );
- vPortFree( pucFullBuffer );
- xStreamBufferReset( xStreamBuffer );
+ size_t xReturned, xItem, xExpected, xExpectedSpaces, xExpectedBytes;
+ const size_t xMax6ByteMessages = sbSTREAM_BUFFER_LENGTH_BYTES / 6;
+ const size_t xTrueSize = ( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS );
+ const size_t x6ByteLength = 6, x17ByteLength = 17, xFullBufferSize = sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2;
+ uint8_t * pucFullBuffer, * pucData, * pucReadData;
+ TickType_t xTimeBeforeCall, xTimeAfterCall;
+ const TickType_t xBlockTime = pdMS_TO_TICKS( 15 ), xAllowableMargin = pdMS_TO_TICKS( 3 ), xMinimalBlockTime = 2;
+ UBaseType_t uxOriginalPriority;
+
+ /* Remove warning in case configASSERT() is not defined. */
+ ( void ) xAllowableMargin;
+
+ /* To minimise stack and heap usage a full size buffer is allocated from the
+ * heap, then buffers which hold smaller amounts of data are overlayed with the
+ * larger buffer - just make sure not to use both at once! */
+ pucFullBuffer = pvPortMalloc( xFullBufferSize );
+ configASSERT( pucFullBuffer );
+
+ pucData = pucFullBuffer;
+ pucReadData = pucData + x17ByteLength;
+
+ /* Nothing has been added or removed yet, so expect the free space to be
+ * exactly as created. Head and tail are both at 0. */
+ xExpectedSpaces = sbSTREAM_BUFFER_LENGTH_BYTES;
+ xExpectedBytes = 0;
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Add a single item - number of bytes available should go up by one and spaces
+ * available down by one. Head is in front of tail. */
+ xExpectedSpaces--;
+ xExpectedBytes++;
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == sizeof( *pucData ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Now fill the buffer by adding another 29 bytes. Head is 30 tail is at 0. */
+ xExpectedSpaces -= 29;
+ xExpectedBytes += 29;
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, ( sbSTREAM_BUFFER_LENGTH_BYTES - 1 ), ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - 1 ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+
+ /* Should not be able to add another byte now. */
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == ( size_t ) 0 );
+
+ /* Remove a byte so the tail pointer moves off 0. Head pointer remains at the
+ * end of the buffer. */
+ xExpectedSpaces += 1;
+ xExpectedBytes -= 1;
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == sizeof( *pucData ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Should be able to add another byte to fill the buffer again now. */
+ xExpectedSpaces -= 1;
+ xExpectedBytes += 1;
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == sizeof( *pucData ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+
+ /* Now the head pointer is behind the tail pointer. Read another 29 bytes so
+ * the tail pointer moves to the end of the buffer. */
+ xExpectedSpaces += 29;
+ xExpectedBytes -= 29;
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, ( size_t ) 29, ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == ( size_t ) 29 );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Read out one more byte to wrap the tail back around to the start, to get back
+ * to where we started. */
+ xExpectedSpaces += 1;
+ xExpectedBytes -= 1;
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, sizeof( *pucData ), ( TickType_t ) 0 );
+ prvCheckExpectedState( xReturned == sizeof( *pucData ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedBytes );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Try filling the message buffer in one write, blocking indefinitely. Expect to
+ * have written one byte less. */
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, xTrueSize, portMAX_DELAY );
+ xExpectedSpaces = ( size_t ) 0;
+ prvCheckExpectedState( xReturned == ( xTrueSize - ( size_t ) 1 ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == xExpectedSpaces );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+
+ /* Empty the buffer again ready for the rest of the tests. Again block
+ * indefinitely to ensure reading more than there can possible be won't lock this
+ * task up, so expect to actually receive one byte less than requested. */
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucData, xTrueSize, portMAX_DELAY );
+ prvCheckExpectedState( xReturned == ( xTrueSize - ( size_t ) 1 ) );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == sbSTREAM_BUFFER_LENGTH_BYTES );
+ xExpected = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == ( size_t ) 0 );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+
+ /* The buffer is 30 bytes long. 6 5 byte messages should fit before the
+ * buffer is completely full. */
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+
+ for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+ {
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Generate recognisable data to write to the buffer. This is just
+ * ascii characters that shows which loop iteration the data was written
+ * in. The 'FromISR' version is used to give it some exercise as a block
+ * time is not used, so the call must be inside a critical section so it
+ * runs with ports that don't support interrupt nesting (and therefore
+ * don't have interrupt safe critical sections). */
+ memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+ taskENTER_CRITICAL();
+ {
+ xReturned = xStreamBufferSendFromISR( xStreamBuffer, ( void * ) pucData, x6ByteLength, NULL );
+ }
+ taskEXIT_CRITICAL();
+ prvCheckExpectedState( xReturned == x6ByteLength );
+
+ /* The space in the buffer will have reduced by the amount of user data
+ * written into the buffer. */
+ xExpected -= x6ByteLength;
+ xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == xExpected );
+ xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+ /* +1 as it is zero indexed. */
+ prvCheckExpectedState( xReturned == ( ( xItem + 1 ) * x6ByteLength ) );
+ }
+
+ /* Now the buffer should be full, and attempting to add anything should fail. */
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), sbDONT_BLOCK );
+ prvCheckExpectedState( xReturned == 0 );
+
+ /* Adding with a timeout should also fail after the appropriate time. The
+ * priority is temporarily boosted in this part of the test to keep the
+ * allowable margin to a minimum. */
+ uxOriginalPriority = uxTaskPriorityGet( NULL );
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+ xTimeBeforeCall = xTaskGetTickCount();
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, sizeof( pucData[ 0 ] ), xBlockTime );
+ xTimeAfterCall = xTaskGetTickCount();
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+ prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime );
+ prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) );
+ prvCheckExpectedState( xReturned == 0 );
+
+ /* The buffer is now full of data in the form "000000", "111111", etc. Make
+ * sure the data is read out as expected. */
+ for( xItem = 0; xItem < xMax6ByteMessages; xItem++ )
+ {
+ /* Generate the data that is expected to be read out for this loop
+ * iteration. */
+ memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x6ByteLength );
+
+ /* Read the next 6 bytes out. The 'FromISR' version is used to give it
+ * some exercise as a block time is not used, so a it must be called from
+ * a critical section so this will work on ports that don't support
+ * interrupt nesting (so don't have interrupt safe critical sections). */
+ taskENTER_CRITICAL();
+ {
+ xReturned = xStreamBufferReceiveFromISR( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, NULL );
+ }
+ taskEXIT_CRITICAL();
+ prvCheckExpectedState( xReturned == x6ByteLength );
+
+ /* Does the data read out match that expected? */
+ prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x6ByteLength ) == 0 );
+
+ /* The space in the buffer will have increased by the amount of user
+ * data removed from the buffer. */
+ xExpected += x6ByteLength;
+ xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == xExpected );
+ xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == ( sbSTREAM_BUFFER_LENGTH_BYTES - xExpected ) );
+ }
+
+ /* The buffer should be empty again. */
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+ xExpected = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xExpected == sbSTREAM_BUFFER_LENGTH_BYTES );
+
+ /* Reading with a timeout should also fail after the appropriate time. The
+ * priority is temporarily boosted in this part of the test to keep the
+ * allowable margin to a minimum. */
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+ xTimeBeforeCall = xTaskGetTickCount();
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x6ByteLength, xBlockTime );
+ xTimeAfterCall = xTaskGetTickCount();
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+ prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) >= xBlockTime );
+ prvCheckExpectedState( ( ( TickType_t ) ( xTimeAfterCall - xTimeBeforeCall ) ) < ( xBlockTime + xAllowableMargin ) );
+ prvCheckExpectedState( xReturned == 0 );
+
+
+ /* In the next loop 17 bytes are written to then read out on each
+ * iteration. As 30 is not divisible by 17 the data will wrap around. */
+ xExpected = sbSTREAM_BUFFER_LENGTH_BYTES - x17ByteLength;
+
+ for( xItem = 0; xItem < 100; xItem++ )
+ {
+ /* Generate recognisable data to write to the queue. This is just
+ * ascii characters that shows which loop iteration the data was written
+ * in. */
+ memset( ( void * ) pucData, ( ( int ) '0' ) + ( int ) xItem, x17ByteLength );
+ xReturned = xStreamBufferSend( xStreamBuffer, ( void * ) pucData, x17ByteLength, sbDONT_BLOCK );
+ prvCheckExpectedState( xReturned == x17ByteLength );
+
+ /* The space in the buffer will have reduced by the amount of user data
+ * written into the buffer. */
+ xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == xExpected );
+ xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == x17ByteLength );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+
+ /* Read the 17 bytes out again. */
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucReadData, x17ByteLength, sbDONT_BLOCK );
+ prvCheckExpectedState( xReturned == x17ByteLength );
+
+ /* Does the data read out match that expected? */
+ prvCheckExpectedState( memcmp( ( void * ) pucData, ( void * ) pucReadData, x17ByteLength ) == 0 );
+
+ /* Full buffer space available again. */
+ xReturned = xStreamBufferSpacesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+ xReturned = xStreamBufferBytesAvailable( xStreamBuffer );
+ prvCheckExpectedState( xReturned == 0 );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+ }
+
+ /* Fill the buffer with one message, check it is full, then read it back
+ * again and check the correct data is received. */
+ xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK );
+ xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES, sbDONT_BLOCK );
+ prvCheckExpectedState( memcmp( pc55ByteString, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
+
+ /* Fill the buffer one bytes at a time. */
+ for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ )
+ {
+ /* Block time is only for test coverage, the task should never actually
+ * block here. */
+ xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xItem ] ), sizeof( char ), sbRX_TX_BLOCK_TIME );
+ }
+
+ /* The buffer should now be full. */
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+
+ /* Read the message out in one go, even though it was written in individual
+ * bytes. Try reading much more data than is actually available to ensure only
+ * the available bytes are returned (otherwise this read will write outside of
+ * the memory allocated anyway!). */
+ xReturned = xStreamBufferReceive( xStreamBuffer, pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, sbRX_TX_BLOCK_TIME );
+ prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+ prvCheckExpectedState( memcmp( ( const void * ) pc54ByteString, ( const void * ) pucFullBuffer, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
+
+ /* Now do the opposite, write in one go and read out in single bytes. */
+ xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES, sbRX_TX_BLOCK_TIME );
+ prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferBytesAvailable( xStreamBuffer ) == sbSTREAM_BUFFER_LENGTH_BYTES );
+ prvCheckExpectedState( xStreamBufferSpacesAvailable( xStreamBuffer ) == 0 );
+
+ /* Read from the buffer one byte at a time. */
+ for( xItem = 0; xItem < sbSTREAM_BUFFER_LENGTH_BYTES; xItem++ )
+ {
+ /* Block time is only for test coverage, the task should never actually
+ * block here. */
+ xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, sizeof( char ), sbRX_TX_BLOCK_TIME );
+ prvCheckExpectedState( pc55ByteString[ xItem ] == pucFullBuffer[ 0 ] );
+ }
+
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+
+ /* Try writing more bytes than there is space. */
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+ xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime );
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+ prvCheckExpectedState( xReturned == sbSTREAM_BUFFER_LENGTH_BYTES );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdTRUE );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdFALSE );
+
+ /* No space now though. */
+ xReturned = xStreamBufferSend( xStreamBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES * ( size_t ) 2, xMinimalBlockTime );
+ prvCheckExpectedState( xReturned == 0 );
+
+ /* Ensure data was written as expected even when there was an attempt to
+ * write more than was available. This also tries to read more bytes than are
+ * available. */
+ xReturned = xStreamBufferReceive( xStreamBuffer, ( void * ) pucFullBuffer, xFullBufferSize, xMinimalBlockTime );
+ prvCheckExpectedState( memcmp( ( const void * ) pucFullBuffer, ( const void * ) pc54ByteString, sbSTREAM_BUFFER_LENGTH_BYTES ) == 0 );
+ prvCheckExpectedState( xStreamBufferIsFull( xStreamBuffer ) == pdFALSE );
+ prvCheckExpectedState( xStreamBufferIsEmpty( xStreamBuffer ) == pdTRUE );
+
+ /* Clean up with data in the buffer to ensure the tests that follow don't
+ * see the data (the data should be discarded). */
+ ( void ) xStreamBufferSend( xStreamBuffer, ( const void * ) pc55ByteString, sbSTREAM_BUFFER_LENGTH_BYTES / ( size_t ) 2, sbDONT_BLOCK );
+ vPortFree( pucFullBuffer );
+ xStreamBufferReset( xStreamBuffer );
}
/*-----------------------------------------------------------*/
-static void prvNonBlockingSenderTask( void *pvParameters )
+static void prvNonBlockingSenderTask( void * pvParameters )
{
-StreamBufferHandle_t xStreamBuffer;
-size_t xNextChar = 0, xBytesToSend, xBytesActuallySent;
-const size_t xStringLength = strlen( pc54ByteString );
-
- /* In this case the stream buffer has already been created and is passed
- into the task using the task's parameter. */
- xStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
-
- /* Keep sending the string to the stream buffer as many bytes as possible in
- each go. Doesn't block so calls can interleave with the non-blocking
- receives performed by prvNonBlockingReceiverTask(). */
- for( ;; )
- {
- /* The whole string cannot be sent at once, so xNextChar is an index to
- the position within the string that has been sent so far. How many
- bytes are there left to send before the end of the string? */
- xBytesToSend = xStringLength - xNextChar;
-
- /* Attempt to send right up to the end of the string. */
- xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xNextChar ] ), xBytesToSend, sbDONT_BLOCK );
- prvCheckExpectedState( xBytesActuallySent <= xBytesToSend );
-
- /* Move the index up the string to the next character to be sent,
- wrapping if the end of the string has been reached. */
- xNextChar += xBytesActuallySent;
- prvCheckExpectedState( xNextChar <= xStringLength );
-
- if( xNextChar == xStringLength )
- {
- xNextChar = 0;
- }
- }
+ StreamBufferHandle_t xStreamBuffer;
+ size_t xNextChar = 0, xBytesToSend, xBytesActuallySent;
+ const size_t xStringLength = strlen( pc54ByteString );
+
+ /* In this case the stream buffer has already been created and is passed
+ * into the task using the task's parameter. */
+ xStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
+
+ /* Keep sending the string to the stream buffer as many bytes as possible in
+ * each go. Doesn't block so calls can interleave with the non-blocking
+ * receives performed by prvNonBlockingReceiverTask(). */
+ for( ; ; )
+ {
+ /* The whole string cannot be sent at once, so xNextChar is an index to
+ * the position within the string that has been sent so far. How many
+ * bytes are there left to send before the end of the string? */
+ xBytesToSend = xStringLength - xNextChar;
+
+ /* Attempt to send right up to the end of the string. */
+ xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc54ByteString[ xNextChar ] ), xBytesToSend, sbDONT_BLOCK );
+ prvCheckExpectedState( xBytesActuallySent <= xBytesToSend );
+
+ /* Move the index up the string to the next character to be sent,
+ * wrapping if the end of the string has been reached. */
+ xNextChar += xBytesActuallySent;
+ prvCheckExpectedState( xNextChar <= xStringLength );
+
+ if( xNextChar == xStringLength )
+ {
+ xNextChar = 0;
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvNonBlockingReceiverTask( void *pvParameters )
+static void prvNonBlockingReceiverTask( void * pvParameters )
{
-StreamBufferHandle_t xStreamBuffer;
-size_t xNextChar = 0, xReceiveLength, xBytesToTest, xStartIndex;
-const size_t xStringLength = strlen( pc54ByteString );
-char cRxString[ 12 ]; /* Holds received characters. */
-BaseType_t xNonBlockingReceiveError = pdFALSE;
-
- /* In this case the stream buffer has already been created and is passed
- into the task using the task's parameter. */
- xStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
-
- /* Expects to receive the pc54ByteString over and over again. Sends and
- receives are not blocking so will interleave. */
- for( ;; )
- {
- /* Attempt to receive as many bytes as possible, up to the limit of the
- Rx buffer size. */
- xReceiveLength = xStreamBufferReceive( xStreamBuffer, ( void * ) cRxString, sizeof( cRxString ), sbDONT_BLOCK );
-
- if( xReceiveLength > 0 )
- {
- /* xNextChar is the index into pc54ByteString that has been received
- already. If xReceiveLength bytes are added to that, will it go off
- the end of the string? If so, then first test up to the end of the
- string, then go back to the start of pc54ByteString to test the
- remains of the received data. */
- xBytesToTest = xReceiveLength;
- if( ( xNextChar + xBytesToTest ) > xStringLength )
- {
- /* Cap to test the received data to the end of the string. */
- xBytesToTest = xStringLength - xNextChar;
-
- if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) cRxString, xBytesToTest ) != 0 )
- {
- xNonBlockingReceiveError = pdTRUE;
- }
-
- /* Then move back to the start of the string to test the
- remaining received bytes. */
- xNextChar = 0;
- xStartIndex = xBytesToTest;
- xBytesToTest = xReceiveLength - xBytesToTest;
- }
- else
- {
- /* The string didn't wrap in the buffer, so start comparing from
- the start of the received data. */
- xStartIndex = 0;
- }
-
- /* Test the received bytes are as expected, then move the index
- along the string to the next expected char to receive. */
- if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) &( cRxString[ xStartIndex ] ), xBytesToTest ) != 0 )
- {
- xNonBlockingReceiveError = pdTRUE;
- }
-
- if( xNonBlockingReceiveError == pdFALSE )
- {
- /* No errors detected so increment the counter that lets the
- check task know this test is still functioning correctly. */
- ulNonBlockingRxCounter++;
- }
-
- xNextChar += xBytesToTest;
- if( xNextChar >= xStringLength )
- {
- xNextChar = 0;
- }
- }
- }
+ StreamBufferHandle_t xStreamBuffer;
+ size_t xNextChar = 0, xReceiveLength, xBytesToTest, xStartIndex;
+ const size_t xStringLength = strlen( pc54ByteString );
+ char cRxString[ 12 ]; /* Holds received characters. */
+ BaseType_t xNonBlockingReceiveError = pdFALSE;
+
+ /* In this case the stream buffer has already been created and is passed
+ * into the task using the task's parameter. */
+ xStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
+
+ /* Expects to receive the pc54ByteString over and over again. Sends and
+ * receives are not blocking so will interleave. */
+ for( ; ; )
+ {
+ /* Attempt to receive as many bytes as possible, up to the limit of the
+ * Rx buffer size. */
+ xReceiveLength = xStreamBufferReceive( xStreamBuffer, ( void * ) cRxString, sizeof( cRxString ), sbDONT_BLOCK );
+
+ if( xReceiveLength > 0 )
+ {
+ /* xNextChar is the index into pc54ByteString that has been received
+ * already. If xReceiveLength bytes are added to that, will it go off
+ * the end of the string? If so, then first test up to the end of the
+ * string, then go back to the start of pc54ByteString to test the
+ * remains of the received data. */
+ xBytesToTest = xReceiveLength;
+
+ if( ( xNextChar + xBytesToTest ) > xStringLength )
+ {
+ /* Cap to test the received data to the end of the string. */
+ xBytesToTest = xStringLength - xNextChar;
+
+ if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) cRxString, xBytesToTest ) != 0 )
+ {
+ xNonBlockingReceiveError = pdTRUE;
+ }
+
+ /* Then move back to the start of the string to test the
+ * remaining received bytes. */
+ xNextChar = 0;
+ xStartIndex = xBytesToTest;
+ xBytesToTest = xReceiveLength - xBytesToTest;
+ }
+ else
+ {
+ /* The string didn't wrap in the buffer, so start comparing from
+ * the start of the received data. */
+ xStartIndex = 0;
+ }
+
+ /* Test the received bytes are as expected, then move the index
+ * along the string to the next expected char to receive. */
+ if( memcmp( ( const void * ) &( pc54ByteString[ xNextChar ] ), ( const void * ) &( cRxString[ xStartIndex ] ), xBytesToTest ) != 0 )
+ {
+ xNonBlockingReceiveError = pdTRUE;
+ }
+
+ if( xNonBlockingReceiveError == pdFALSE )
+ {
+ /* No errors detected so increment the counter that lets the
+ * check task know this test is still functioning correctly. */
+ ulNonBlockingRxCounter++;
+ }
+
+ xNextChar += xBytesToTest;
+
+ if( xNextChar >= xStringLength )
+ {
+ xNextChar = 0;
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
- static void prvSenderTask( void *pvParameters )
- {
- StreamBufferHandle_t xStreamBuffer, xTempStreamBuffer;
- static uint8_t ucTempBuffer[ 10 ]; /* Just used to exercise stream buffer creating and deletion. */
- const TickType_t xTicksToWait = sbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 );
- StaticStreamBuffer_t xStaticStreamBuffer;
- size_t xNextChar = 0, xBytesToSend, xBytesActuallySent;
- const size_t xStringLength = strlen( pc55ByteString );
-
- /* The task's priority is used as an index into the loop counters used to
- indicate this task is still running. */
- UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
-
- /* Make sure a change in priority does not inadvertently result in an
- invalid array index. */
- prvCheckExpectedState( uxIndex < sbNUMBER_OF_ECHO_CLIENTS );
-
- /* Avoid compiler warnings about unused parameters. */
- ( void ) pvParameters;
-
- xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */
- sbTRIGGER_LEVEL_1, /* The number of bytes to be in the buffer before a task blocked to wait for data is unblocked. */
- &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */
- &( xStaticStreamBuffers[ uxIndex ] ) ); /* The static stream buffer structure to use within the array. */
-
- /* Now the stream buffer has been created the receiver task can be
- created. If this sender task has the higher priority then the receiver
- task is created at the lower priority - if this sender task has the
- lower priority then the receiver task is created at the higher
- priority. */
- if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY )
- {
- /* Here prvSingleTaskTests() performs various tests on a stream buffer
- that was created statically. */
- prvSingleTaskTests( xStreamBuffer );
- xTaskCreate( prvReceiverTask, "StrReceiver", sbSMALLER_STACK_SIZE, ( void * ) xStreamBuffer, sbHIGHER_PRIORITY, NULL );
- }
- else
- {
- xTaskCreate( prvReceiverTask, "StrReceiver", sbSMALLER_STACK_SIZE, ( void * ) xStreamBuffer, sbLOWER_PRIORITY, NULL );
- }
-
- for( ;; )
- {
- /* The whole string cannot be sent at once, so xNextChar is an index
- to the position within the string that has been sent so far. How
- many bytes are there left to send before the end of the string? */
- xBytesToSend = xStringLength - xNextChar;
-
- /* Attempt to send right up to the end of the string. */
- xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc55ByteString[ xNextChar ] ), xBytesToSend, xTicksToWait );
- prvCheckExpectedState( xBytesActuallySent <= xBytesToSend );
-
- /* Move the index up the string to the next character to be sent,
- wrapping if the end of the string has been reached. */
- xNextChar += xBytesActuallySent;
- prvCheckExpectedState( xNextChar <= xStringLength );
-
- if( xNextChar == xStringLength )
- {
- xNextChar = 0;
- }
-
- /* Increment a loop counter so a check task can tell this task is
- still running as expected. */
- ulSenderLoopCounters[ uxIndex ]++;
-
- if( uxTaskPriorityGet( NULL ) == sbHIGHER_PRIORITY )
- {
- /* Allow other tasks to run. */
- vTaskDelay( xShortDelay );
- }
-
- /* This stream buffer is just created and deleted to ensure no
- issues when attempting to delete a stream buffer that was
- created using statically allocated memory. To save stack space
- the buffer is set to point to the pc55ByteString, which is a const
- string, but no data is written into the buffer so any valid address
- will do. */
- xTempStreamBuffer = xStreamBufferCreateStatic( sizeof( ucTempBuffer ), sbTRIGGER_LEVEL_1, ucTempBuffer, &xStaticStreamBuffer );
- xStreamBufferReset( xTempStreamBuffer );
- vStreamBufferDelete( xTempStreamBuffer );
- }
- }
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ static void prvSenderTask( void * pvParameters )
+ {
+ StreamBufferHandle_t xStreamBuffer, xTempStreamBuffer;
+ static uint8_t ucTempBuffer[ 10 ]; /* Just used to exercise stream buffer creating and deletion. */
+ const TickType_t xTicksToWait = sbRX_TX_BLOCK_TIME, xShortDelay = pdMS_TO_TICKS( 50 );
+ StaticStreamBuffer_t xStaticStreamBuffer;
+ size_t xNextChar = 0, xBytesToSend, xBytesActuallySent;
+ const size_t xStringLength = strlen( pc55ByteString );
+
+ /* The task's priority is used as an index into the loop counters used to
+ * indicate this task is still running. */
+ UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+
+ /* Make sure a change in priority does not inadvertently result in an
+ * invalid array index. */
+ prvCheckExpectedState( uxIndex < sbNUMBER_OF_ECHO_CLIENTS );
+
+ /* Avoid compiler warnings about unused parameters. */
+ ( void ) pvParameters;
+
+ xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ) / sbNUMBER_OF_SENDER_TASKS, /* The number of bytes in each buffer in the array. */
+ sbTRIGGER_LEVEL_1, /* The number of bytes to be in the buffer before a task blocked to wait for data is unblocked. */
+ &( ucBufferStorage[ uxIndex ][ 0 ] ), /* The address of the buffer to use within the array. */
+ &( xStaticStreamBuffers[ uxIndex ] ) ); /* The static stream buffer structure to use within the array. */
+
+ /* Now the stream buffer has been created the receiver task can be
+ * created. If this sender task has the higher priority then the receiver
+ * task is created at the lower priority - if this sender task has the
+ * lower priority then the receiver task is created at the higher
+ * priority. */
+ if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY )
+ {
+ /* Here prvSingleTaskTests() performs various tests on a stream buffer
+ * that was created statically. */
+ prvSingleTaskTests( xStreamBuffer );
+ xTaskCreate( prvReceiverTask, "StrReceiver", sbSMALLER_STACK_SIZE, ( void * ) xStreamBuffer, sbHIGHER_PRIORITY, NULL );
+ }
+ else
+ {
+ xTaskCreate( prvReceiverTask, "StrReceiver", sbSMALLER_STACK_SIZE, ( void * ) xStreamBuffer, sbLOWER_PRIORITY, NULL );
+ }
+
+ for( ; ; )
+ {
+ /* The whole string cannot be sent at once, so xNextChar is an index
+ * to the position within the string that has been sent so far. How
+ * many bytes are there left to send before the end of the string? */
+ xBytesToSend = xStringLength - xNextChar;
+
+ /* Attempt to send right up to the end of the string. */
+ xBytesActuallySent = xStreamBufferSend( xStreamBuffer, ( const void * ) &( pc55ByteString[ xNextChar ] ), xBytesToSend, xTicksToWait );
+ prvCheckExpectedState( xBytesActuallySent <= xBytesToSend );
+
+ /* Move the index up the string to the next character to be sent,
+ * wrapping if the end of the string has been reached. */
+ xNextChar += xBytesActuallySent;
+ prvCheckExpectedState( xNextChar <= xStringLength );
+
+ if( xNextChar == xStringLength )
+ {
+ xNextChar = 0;
+ }
+
+ /* Increment a loop counter so a check task can tell this task is
+ * still running as expected. */
+ ulSenderLoopCounters[ uxIndex ]++;
+
+ if( uxTaskPriorityGet( NULL ) == sbHIGHER_PRIORITY )
+ {
+ /* Allow other tasks to run. */
+ vTaskDelay( xShortDelay );
+ }
+
+ /* This stream buffer is just created and deleted to ensure no
+ * issues when attempting to delete a stream buffer that was
+ * created using statically allocated memory. To save stack space
+ * the buffer is set to point to the pc55ByteString, which is a const
+ * string, but no data is written into the buffer so any valid address
+ * will do. */
+ xTempStreamBuffer = xStreamBufferCreateStatic( sizeof( ucTempBuffer ), sbTRIGGER_LEVEL_1, ucTempBuffer, &xStaticStreamBuffer );
+ xStreamBufferReset( xTempStreamBuffer );
+ vStreamBufferDelete( xTempStreamBuffer );
+ }
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
- static void prvReceiverTask( void *pvParameters )
- {
- StreamBufferHandle_t const pxStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
- char cRxString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
- const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL );
- const size_t xStringLength = strlen( pc55ByteString );
- size_t xNextChar = 0, xReceivedLength, xBytesToReceive;
-
- for( ;; )
- {
- /* Attempt to receive the number of bytes to the end of the string,
- or the number of byte that can be placed into the rx buffer,
- whichever is smallest. */
- xBytesToReceive = configMIN( ( xStringLength - xNextChar ), sizeof( cRxString ) );
-
- do
- {
- xReceivedLength = xStreamBufferReceive( pxStreamBuffer, ( void * ) cRxString, xBytesToReceive, xTicksToWait );
-
- } while( xReceivedLength == 0 );
-
- /* Ensure the received string matches the expected string. */
- prvCheckExpectedState( memcmp( ( void * ) cRxString, ( const void * ) &( pc55ByteString[ xNextChar ] ), xReceivedLength ) == 0 );
-
- /* Move the index into the string up to the end of the bytes
- received so far - wrapping if the end of the string has been
- reached. */
- xNextChar += xReceivedLength;
- if( xNextChar >= xStringLength )
- {
- xNextChar = 0;
- }
- }
- }
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ static void prvReceiverTask( void * pvParameters )
+ {
+ StreamBufferHandle_t const pxStreamBuffer = ( StreamBufferHandle_t ) pvParameters;
+ char cRxString[ 12 ]; /* Large enough to hold a 32-bit number in ASCII. */
+ const TickType_t xTicksToWait = pdMS_TO_TICKS( 5UL );
+ const size_t xStringLength = strlen( pc55ByteString );
+ size_t xNextChar = 0, xReceivedLength, xBytesToReceive;
+
+ for( ; ; )
+ {
+ /* Attempt to receive the number of bytes to the end of the string,
+ * or the number of byte that can be placed into the rx buffer,
+ * whichever is smallest. */
+ xBytesToReceive = configMIN( ( xStringLength - xNextChar ), sizeof( cRxString ) );
+
+ do
+ {
+ xReceivedLength = xStreamBufferReceive( pxStreamBuffer, ( void * ) cRxString, xBytesToReceive, xTicksToWait );
+ } while( xReceivedLength == 0 );
+
+ /* Ensure the received string matches the expected string. */
+ prvCheckExpectedState( memcmp( ( void * ) cRxString, ( const void * ) &( pc55ByteString[ xNextChar ] ), xReceivedLength ) == 0 );
+
+ /* Move the index into the string up to the end of the bytes
+ * received so far - wrapping if the end of the string has been
+ * reached. */
+ xNextChar += xReceivedLength;
+
+ if( xNextChar >= xStringLength )
+ {
+ xNextChar = 0;
+ }
+ }
+ }
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
-static void prvEchoClient( void *pvParameters )
+static void prvEchoClient( void * pvParameters )
{
-size_t xSendLength = 0, ux;
-char *pcStringToSend, *pcStringReceived, cNextChar = sbASCII_SPACE;
-const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 );
-StreamBufferHandle_t xTempStreamBuffer;
+ size_t xSendLength = 0, ux;
+ char * pcStringToSend, * pcStringReceived, cNextChar = sbASCII_SPACE;
+ const TickType_t xTicksToWait = pdMS_TO_TICKS( 50 );
+ StreamBufferHandle_t xTempStreamBuffer;
/* The task's priority is used as an index into the loop counters used to
-indicate this task is still running. */
-UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
+ * indicate this task is still running. */
+ UBaseType_t uxIndex = uxTaskPriorityGet( NULL );
/* Pointers to the client and server stream buffers are passed into this task
-using the task's parameter. */
-EchoStreamBuffers_t *pxStreamBuffers = ( EchoStreamBuffers_t * ) pvParameters;
-
- /* Prevent compiler warnings. */
- ( void ) pvParameters;
-
- /* Create the buffer into which strings to send to the server will be
- created, and the buffer into which strings echoed back from the server will
- be copied. */
- pcStringToSend = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
- pcStringReceived = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
-
- configASSERT( pcStringToSend );
- configASSERT( pcStringReceived );
-
- for( ;; )
- {
- /* Generate the length of the next string to send. */
- xSendLength++;
-
- /* The stream buffer is being used to hold variable length data, so
- each data item requires sizeof( size_t ) bytes to hold the data's
- length, hence the sizeof() in the if() condition below. */
- if( xSendLength > ( sbSTREAM_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) )
- {
- /* Back to a string length of 1. */
- xSendLength = sizeof( char );
- }
-
- memset( pcStringToSend, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
-
- for( ux = 0; ux < xSendLength; ux++ )
- {
- pcStringToSend[ ux ] = cNextChar;
-
- cNextChar++;
-
- if( cNextChar > sbASCII_TILDA )
- {
- cNextChar = sbASCII_SPACE;
- }
- }
-
- /* Send the generated string to the buffer. */
- do
- {
- ux = xStreamBufferSend( pxStreamBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait );
-
- } while( ux == 0 );
-
- /* Wait for the string to be echoed back. */
- memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
- xStreamBufferReceive( pxStreamBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY );
-
- prvCheckExpectedState( strcmp( pcStringToSend, pcStringReceived ) == 0 );
-
- /* Maintain a count of the number of times this code executes so a
- check task can determine if this task is still functioning as
- expected or not. As there are two client tasks, and the priorities
- used are 0 and 1, the task's priority is used as an index into the
- loop count array. */
- ulEchoLoopCounters[ uxIndex ]++;
-
- /* This stream buffer is just created and deleted to ensure no memory
- leaks. */
- xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
- vStreamBufferDelete( xTempStreamBuffer );
-
- /* The following are tests for a stream buffer of size one. */
- /* Create a buffer of size one. */
- xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_ONE, sbTRIGGER_LEVEL_1 );
- /* Ensure that the buffer was created successfully. */
- configASSERT( xTempStreamBuffer );
-
- /* Send one byte to the buffer. */
- ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );
- /* Ensure that the byte was sent successfully. */
- configASSERT( ux == 1 );
- /* Try sending another byte to the buffer. */
- ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );
- /* Make sure that send failed as the buffer is full. */
- configASSERT( ux == 0 );
-
- /* Receive one byte from the buffer. */
- memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
- ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );
- /* Ensure that the receive was successful. */
- configASSERT( ux == 1 );
- /* Ensure that the correct data was received. */
- configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );
- /* Try receiving another byte from the buffer. */
- ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );
- /* Ensure that the receive failed as the buffer is empty. */
- configASSERT( ux == 0 );
-
- /* Try sending two bytes to the buffer. Since the size of the
- * buffer is one, we must not be able to send more than one. */
- ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 2, sbDONT_BLOCK );
- /* Ensure that only one byte was sent. */
- configASSERT( ux == 1 );
-
- /* Try receiving two bytes from the buffer. Since the size of the
- * buffer is one, we must not be able to get more than one. */
- memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
- ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 2, sbDONT_BLOCK );
- /* Ensure that only one byte was received. */
- configASSERT( ux == 1 );
- /* Ensure that the correct data was received. */
- configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );
-
- /* Delete the buffer. */
- vStreamBufferDelete( xTempStreamBuffer );
- }
+ * using the task's parameter. */
+ EchoStreamBuffers_t * pxStreamBuffers = ( EchoStreamBuffers_t * ) pvParameters;
+
+ /* Prevent compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Create the buffer into which strings to send to the server will be
+ * created, and the buffer into which strings echoed back from the server will
+ * be copied. */
+ pcStringToSend = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
+ pcStringReceived = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
+
+ configASSERT( pcStringToSend );
+ configASSERT( pcStringReceived );
+
+ for( ; ; )
+ {
+ /* Generate the length of the next string to send. */
+ xSendLength++;
+
+ /* The stream buffer is being used to hold variable length data, so
+ * each data item requires sizeof( size_t ) bytes to hold the data's
+ * length, hence the sizeof() in the if() condition below. */
+ if( xSendLength > ( sbSTREAM_BUFFER_LENGTH_BYTES - sizeof( size_t ) ) )
+ {
+ /* Back to a string length of 1. */
+ xSendLength = sizeof( char );
+ }
+
+ memset( pcStringToSend, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+
+ for( ux = 0; ux < xSendLength; ux++ )
+ {
+ pcStringToSend[ ux ] = cNextChar;
+
+ cNextChar++;
+
+ if( cNextChar > sbASCII_TILDA )
+ {
+ cNextChar = sbASCII_SPACE;
+ }
+ }
+
+ /* Send the generated string to the buffer. */
+ do
+ {
+ ux = xStreamBufferSend( pxStreamBuffers->xEchoClientBuffer, ( void * ) pcStringToSend, xSendLength, xTicksToWait );
+ } while( ux == 0 );
+
+ /* Wait for the string to be echoed back. */
+ memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+ xStreamBufferReceive( pxStreamBuffers->xEchoServerBuffer, ( void * ) pcStringReceived, xSendLength, portMAX_DELAY );
+
+ prvCheckExpectedState( strcmp( pcStringToSend, pcStringReceived ) == 0 );
+
+ /* Maintain a count of the number of times this code executes so a
+ * check task can determine if this task is still functioning as
+ * expected or not. As there are two client tasks, and the priorities
+ * used are 0 and 1, the task's priority is used as an index into the
+ * loop count array. */
+ ulEchoLoopCounters[ uxIndex ]++;
+
+ /* This stream buffer is just created and deleted to ensure no memory
+ * leaks. */
+ xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+ vStreamBufferDelete( xTempStreamBuffer );
+
+ /* The following are tests for a stream buffer of size one. */
+ /* Create a buffer of size one. */
+ xTempStreamBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_ONE, sbTRIGGER_LEVEL_1 );
+ /* Ensure that the buffer was created successfully. */
+ configASSERT( xTempStreamBuffer );
+
+ /* Send one byte to the buffer. */
+ ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );
+ /* Ensure that the byte was sent successfully. */
+ configASSERT( ux == 1 );
+ /* Try sending another byte to the buffer. */
+ ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 1, sbDONT_BLOCK );
+ /* Make sure that send failed as the buffer is full. */
+ configASSERT( ux == 0 );
+
+ /* Receive one byte from the buffer. */
+ memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+ ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );
+ /* Ensure that the receive was successful. */
+ configASSERT( ux == 1 );
+ /* Ensure that the correct data was received. */
+ configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );
+ /* Try receiving another byte from the buffer. */
+ ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 1, sbDONT_BLOCK );
+ /* Ensure that the receive failed as the buffer is empty. */
+ configASSERT( ux == 0 );
+
+ /* Try sending two bytes to the buffer. Since the size of the
+ * buffer is one, we must not be able to send more than one. */
+ ux = xStreamBufferSend( xTempStreamBuffer, ( void * ) pcStringToSend, ( size_t ) 2, sbDONT_BLOCK );
+ /* Ensure that only one byte was sent. */
+ configASSERT( ux == 1 );
+
+ /* Try receiving two bytes from the buffer. Since the size of the
+ * buffer is one, we must not be able to get more than one. */
+ memset( pcStringReceived, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+ ux = xStreamBufferReceive( xTempStreamBuffer, ( void * ) pcStringReceived, ( size_t ) 2, sbDONT_BLOCK );
+ /* Ensure that only one byte was received. */
+ configASSERT( ux == 1 );
+ /* Ensure that the correct data was received. */
+ configASSERT( pcStringToSend[ 0 ] == pcStringReceived[ 0 ] );
+
+ /* Delete the buffer. */
+ vStreamBufferDelete( xTempStreamBuffer );
+ }
}
/*-----------------------------------------------------------*/
-static void prvEchoServer( void *pvParameters )
+static void prvEchoServer( void * pvParameters )
{
-size_t xReceivedLength;
-char *pcReceivedString;
-EchoStreamBuffers_t xStreamBuffers;
-TickType_t xTimeOnEntering;
-const TickType_t xTicksToBlock = pdMS_TO_TICKS( 350UL );
-
- /* Prevent compiler warnings about unused parameters. */
- ( void ) pvParameters;
-
- /* Create the stream buffer used to send data from the client to the server,
- and the stream buffer used to echo the data from the server back to the
- client. */
- xStreamBuffers.xEchoClientBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
- xStreamBuffers.xEchoServerBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
- configASSERT( xStreamBuffers.xEchoClientBuffer );
- configASSERT( xStreamBuffers.xEchoServerBuffer );
-
- /* Create the buffer into which received strings will be copied. */
- pcReceivedString = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
- configASSERT( pcReceivedString );
-
- /* Don't expect to receive anything yet! */
- xTimeOnEntering = xTaskGetTickCount();
- xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, xTicksToBlock );
- prvCheckExpectedState( ( ( TickType_t ) ( xTaskGetTickCount() - xTimeOnEntering ) ) >= xTicksToBlock );
- prvCheckExpectedState( xReceivedLength == 0 );
-
- /* Now the stream buffers have been created the echo client task can be
- created. If this server task has the higher priority then the client task
- is created at the lower priority - if this server task has the lower
- priority then the client task is created at the higher priority. */
- if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY )
- {
- xTaskCreate( prvEchoClient, "EchoClient", sbSMALLER_STACK_SIZE, ( void * ) &xStreamBuffers, sbHIGHER_PRIORITY, NULL );
- }
- else
- {
- /* Here prvSingleTaskTests() performs various tests on a stream buffer
- that was created dynamically. */
- prvSingleTaskTests( xStreamBuffers.xEchoClientBuffer );
- xTaskCreate( prvEchoClient, "EchoClient", sbSMALLER_STACK_SIZE, ( void * ) &xStreamBuffers, sbLOWER_PRIORITY, NULL );
- }
-
- for( ;; )
- {
- memset( pcReceivedString, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
-
- /* Has any data been sent by the client? */
- xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, portMAX_DELAY );
-
- /* Should always receive data as max delay was used. */
- prvCheckExpectedState( xReceivedLength > 0 );
-
- /* Echo the received data back to the client. */
- xStreamBufferSend( xStreamBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY );
- }
+ size_t xReceivedLength;
+ char * pcReceivedString;
+ EchoStreamBuffers_t xStreamBuffers;
+ TickType_t xTimeOnEntering;
+ const TickType_t xTicksToBlock = pdMS_TO_TICKS( 350UL );
+
+ /* Prevent compiler warnings about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Create the stream buffer used to send data from the client to the server,
+ * and the stream buffer used to echo the data from the server back to the
+ * client. */
+ xStreamBuffers.xEchoClientBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+ xStreamBuffers.xEchoServerBuffer = xStreamBufferCreate( sbSTREAM_BUFFER_LENGTH_BYTES, sbTRIGGER_LEVEL_1 );
+ configASSERT( xStreamBuffers.xEchoClientBuffer );
+ configASSERT( xStreamBuffers.xEchoServerBuffer );
+
+ /* Create the buffer into which received strings will be copied. */
+ pcReceivedString = ( char * ) pvPortMalloc( sbSTREAM_BUFFER_LENGTH_BYTES );
+ configASSERT( pcReceivedString );
+
+ /* Don't expect to receive anything yet! */
+ xTimeOnEntering = xTaskGetTickCount();
+ xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, xTicksToBlock );
+ prvCheckExpectedState( ( ( TickType_t ) ( xTaskGetTickCount() - xTimeOnEntering ) ) >= xTicksToBlock );
+ prvCheckExpectedState( xReceivedLength == 0 );
+
+ /* Now the stream buffers have been created the echo client task can be
+ * created. If this server task has the higher priority then the client task
+ * is created at the lower priority - if this server task has the lower
+ * priority then the client task is created at the higher priority. */
+ if( uxTaskPriorityGet( NULL ) == sbLOWER_PRIORITY )
+ {
+ xTaskCreate( prvEchoClient, "EchoClient", sbSMALLER_STACK_SIZE, ( void * ) &xStreamBuffers, sbHIGHER_PRIORITY, NULL );
+ }
+ else
+ {
+ /* Here prvSingleTaskTests() performs various tests on a stream buffer
+ * that was created dynamically. */
+ prvSingleTaskTests( xStreamBuffers.xEchoClientBuffer );
+ xTaskCreate( prvEchoClient, "EchoClient", sbSMALLER_STACK_SIZE, ( void * ) &xStreamBuffers, sbLOWER_PRIORITY, NULL );
+ }
+
+ for( ; ; )
+ {
+ memset( pcReceivedString, 0x00, sbSTREAM_BUFFER_LENGTH_BYTES );
+
+ /* Has any data been sent by the client? */
+ xReceivedLength = xStreamBufferReceive( xStreamBuffers.xEchoClientBuffer, ( void * ) pcReceivedString, sbSTREAM_BUFFER_LENGTH_BYTES, portMAX_DELAY );
+
+ /* Should always receive data as max delay was used. */
+ prvCheckExpectedState( xReceivedLength > 0 );
+
+ /* Echo the received data back to the client. */
+ xStreamBufferSend( xStreamBuffers.xEchoServerBuffer, ( void * ) pcReceivedString, xReceivedLength, portMAX_DELAY );
+ }
}
/*-----------------------------------------------------------*/
void vPeriodicStreamBufferProcessing( void )
{
-static size_t xNextChar = 0;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-
- /* Called from the tick interrupt hook. If the global stream buffer
- variable is not NULL then the prvInterruptTriggerTest() task expects a byte
- to be sent to the stream buffer on each tick interrupt. */
- if( xInterruptStreamBuffer != NULL )
- {
- /* One character from the pcDataSentFromInterrupt string is sent on each
- interrupt. The task blocked on the stream buffer should not be
- unblocked until the defined trigger level is hit. */
- xStreamBufferSendFromISR( xInterruptStreamBuffer, ( const void * ) &( pcDataSentFromInterrupt[ xNextChar ] ), sizeof( char ), &xHigherPriorityTaskWoken );
-
- if( xNextChar < strlen( pcDataSentFromInterrupt ) )
- {
- xNextChar++;
- }
- }
- else
- {
- /* Start at the beginning of the string being sent again. */
- xNextChar = 0;
- }
+ static size_t xNextChar = 0;
+ BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+
+ /* Called from the tick interrupt hook. If the global stream buffer
+ * variable is not NULL then the prvInterruptTriggerTest() task expects a byte
+ * to be sent to the stream buffer on each tick interrupt. */
+ if( xInterruptStreamBuffer != NULL )
+ {
+ /* One character from the pcDataSentFromInterrupt string is sent on each
+ * interrupt. The task blocked on the stream buffer should not be
+ * unblocked until the defined trigger level is hit. */
+ xStreamBufferSendFromISR( xInterruptStreamBuffer, ( const void * ) &( pcDataSentFromInterrupt[ xNextChar ] ), sizeof( char ), &xHigherPriorityTaskWoken );
+
+ if( xNextChar < strlen( pcDataSentFromInterrupt ) )
+ {
+ xNextChar++;
+ }
+ }
+ else
+ {
+ /* Start at the beginning of the string being sent again. */
+ xNextChar = 0;
+ }
}
/*-----------------------------------------------------------*/
-static void prvInterruptTriggerLevelTest( void *pvParameters )
+static void prvInterruptTriggerLevelTest( void * pvParameters )
{
-StreamBufferHandle_t xStreamBuffer;
-size_t xTriggerLevel = 1, xBytesReceived;
-const size_t xStreamBufferSizeBytes = ( size_t ) 9, xMaxTriggerLevel = ( size_t ) 7, xMinTriggerLevel = ( size_t ) 2;
-const TickType_t xReadBlockTime = 5, xCycleBlockTime = pdMS_TO_TICKS( 100 );
-uint8_t ucRxData[ 9 ];
-BaseType_t xErrorDetected = pdFALSE;
-#ifndef configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN
- const size_t xAllowableMargin = ( size_t ) 0;
-#else
- const size_t xAllowableMargin = ( size_t ) configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN;
-#endif
-
- /* Remove compiler warning about unused parameter. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- for( xTriggerLevel = xMinTriggerLevel; xTriggerLevel < xMaxTriggerLevel; xTriggerLevel++ )
- {
- /* This test is very time sensitive so delay at the beginning to ensure
- the rest of the system is up and running before starting. Delay between
- each loop to ensure the interrupt that sends to the stream buffer
- detects it needs to start sending from the start of the strin again.. */
- vTaskDelay( xCycleBlockTime );
-
- /* Create the stream buffer that will be used from inside the tick
- interrupt. */
- memset( ucRxData, 0x00, sizeof( ucRxData ) );
- xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
- configASSERT( xStreamBuffer );
-
- /* Now the stream buffer has been created it can be assigned to the
- file scope variable, which will allow the tick interrupt to start
- using it. */
- taskENTER_CRITICAL();
- {
- xInterruptStreamBuffer = xStreamBuffer;
- }
- taskEXIT_CRITICAL();
-
- xBytesReceived = xStreamBufferReceive( xStreamBuffer, ( void * ) ucRxData, sizeof( ucRxData ), xReadBlockTime );
-
- /* Set the file scope variable back to NULL so the interrupt doesn't
- try to use it again. */
- taskENTER_CRITICAL();
- {
- xInterruptStreamBuffer = NULL;
- }
- taskEXIT_CRITICAL();
-
- /* Now check the number of bytes received equals the trigger level,
- except in the case that the read timed out before the trigger level
- was reached. */
- if( xTriggerLevel > xReadBlockTime )
- {
- /* Trigger level was greater than the block time so expect to
- time out having received xReadBlockTime bytes. */
- if( xBytesReceived > xReadBlockTime )
- {
- /* Received more bytes than expected. That could happen if
- this task unblocked at the right time, but an interrupt
- added another byte to the stream buffer before this task was
- able to run. */
- if( ( xBytesReceived - xReadBlockTime ) > xAllowableMargin )
- {
- xErrorDetected = pdTRUE;
- }
- }
- else if( xReadBlockTime != xBytesReceived )
- {
- /* It is possible the interrupt placed an item in the stream
- buffer before this task called xStreamBufferReceive(), but
- if that is the case then xBytesReceived will only every be
- 0 as the interrupt will only have executed once. */
- if( xBytesReceived != 1 )
- {
- xErrorDetected = pdTRUE;
- }
- }
- }
- else if( xTriggerLevel < xReadBlockTime )
- {
- /* Trigger level was less than the block time so we expect to
- have received the trigger level number of bytes - could be more
- though depending on other activity between the task being
- unblocked and the task reading the number of bytes received. It
- could also be less if the interrupt already put something in the
- stream buffer before this task attempted to read it - in which
- case the task would have returned the available bytes immediately
- without ever blocking - in that case the bytes received will
- only ever be 1 as the interrupt would not have executed more
- than one in that time unless this task has too low a priority. */
- if( xBytesReceived < xTriggerLevel )
- {
- if( xBytesReceived != 1 )
- {
- xErrorDetected = pdTRUE;
- }
- }
- else if( ( xBytesReceived - xTriggerLevel ) > xAllowableMargin )
- {
- xErrorDetected = pdTRUE;
- }
- }
- else
- {
- /* The trigger level equalled the block time, so expect to
- receive no greater than the block time. It could also be less
- if the interrupt already put something in the stream buffer
- before this task attempted to read it - in which case the task
- would have returned the available bytes immediately without ever
- blocking - in that case the bytes received would only ever be 1
- because the interrupt is not going to execute twice in that time
- unless this task is running a too low a priority. */
- if( xBytesReceived < xReadBlockTime )
- {
- if( xBytesReceived != 1 )
- {
- xErrorDetected = pdTRUE;
- }
- }
- else if( ( xBytesReceived - xReadBlockTime ) > xAllowableMargin )
- {
- xErrorDetected = pdTRUE;
- }
- }
-
- if( xBytesReceived > sizeof( ucRxData ) )
- {
- xErrorDetected = pdTRUE;
- }
- else if( memcmp( ( void * ) ucRxData, ( const void * ) pcDataSentFromInterrupt, xBytesReceived ) != 0 )
- {
- /* Received data didn't match that expected. */
- xErrorDetected = pdTRUE;
- }
-
- if( xErrorDetected == pdFALSE )
- {
- /* Increment the cycle counter so the 'check' task knows this test
- is still running without error. */
- ulInterruptTriggerCounter++;
- }
-
- /* Tidy up ready for the next loop. */
- vStreamBufferDelete( xStreamBuffer );
- }
- }
+ StreamBufferHandle_t xStreamBuffer;
+ size_t xTriggerLevel = 1, xBytesReceived;
+ const size_t xStreamBufferSizeBytes = ( size_t ) 9, xMaxTriggerLevel = ( size_t ) 7, xMinTriggerLevel = ( size_t ) 2;
+ const TickType_t xReadBlockTime = 5, xCycleBlockTime = pdMS_TO_TICKS( 100 );
+ uint8_t ucRxData[ 9 ];
+ BaseType_t xErrorDetected = pdFALSE;
+
+ #ifndef configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN
+ const size_t xAllowableMargin = ( size_t ) 0;
+ #else
+ const size_t xAllowableMargin = ( size_t ) configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN;
+ #endif
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ for( xTriggerLevel = xMinTriggerLevel; xTriggerLevel < xMaxTriggerLevel; xTriggerLevel++ )
+ {
+ /* This test is very time sensitive so delay at the beginning to ensure
+ * the rest of the system is up and running before starting. Delay between
+ * each loop to ensure the interrupt that sends to the stream buffer
+ * detects it needs to start sending from the start of the strin again.. */
+ vTaskDelay( xCycleBlockTime );
+
+ /* Create the stream buffer that will be used from inside the tick
+ * interrupt. */
+ memset( ucRxData, 0x00, sizeof( ucRxData ) );
+ xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ configASSERT( xStreamBuffer );
+
+ /* Now the stream buffer has been created it can be assigned to the
+ * file scope variable, which will allow the tick interrupt to start
+ * using it. */
+ taskENTER_CRITICAL();
+ {
+ xInterruptStreamBuffer = xStreamBuffer;
+ }
+ taskEXIT_CRITICAL();
+
+ xBytesReceived = xStreamBufferReceive( xStreamBuffer, ( void * ) ucRxData, sizeof( ucRxData ), xReadBlockTime );
+
+ /* Set the file scope variable back to NULL so the interrupt doesn't
+ * try to use it again. */
+ taskENTER_CRITICAL();
+ {
+ xInterruptStreamBuffer = NULL;
+ }
+ taskEXIT_CRITICAL();
+
+ /* Now check the number of bytes received equals the trigger level,
+ * except in the case that the read timed out before the trigger level
+ * was reached. */
+ if( xTriggerLevel > xReadBlockTime )
+ {
+ /* Trigger level was greater than the block time so expect to
+ * time out having received xReadBlockTime bytes. */
+ if( xBytesReceived > xReadBlockTime )
+ {
+ /* Received more bytes than expected. That could happen if
+ * this task unblocked at the right time, but an interrupt
+ * added another byte to the stream buffer before this task was
+ * able to run. */
+ if( ( xBytesReceived - xReadBlockTime ) > xAllowableMargin )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+ else if( xReadBlockTime != xBytesReceived )
+ {
+ /* It is possible the interrupt placed an item in the stream
+ * buffer before this task called xStreamBufferReceive(), but
+ * if that is the case then xBytesReceived will only every be
+ * 0 as the interrupt will only have executed once. */
+ if( xBytesReceived != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+ }
+ else if( xTriggerLevel < xReadBlockTime )
+ {
+ /* Trigger level was less than the block time so we expect to
+ * have received the trigger level number of bytes - could be more
+ * though depending on other activity between the task being
+ * unblocked and the task reading the number of bytes received. It
+ * could also be less if the interrupt already put something in the
+ * stream buffer before this task attempted to read it - in which
+ * case the task would have returned the available bytes immediately
+ * without ever blocking - in that case the bytes received will
+ * only ever be 1 as the interrupt would not have executed more
+ * than one in that time unless this task has too low a priority. */
+ if( xBytesReceived < xTriggerLevel )
+ {
+ if( xBytesReceived != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+ else if( ( xBytesReceived - xTriggerLevel ) > xAllowableMargin )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+ else
+ {
+ /* The trigger level equalled the block time, so expect to
+ * receive no greater than the block time. It could also be less
+ * if the interrupt already put something in the stream buffer
+ * before this task attempted to read it - in which case the task
+ * would have returned the available bytes immediately without ever
+ * blocking - in that case the bytes received would only ever be 1
+ * because the interrupt is not going to execute twice in that time
+ * unless this task is running a too low a priority. */
+ if( xBytesReceived < xReadBlockTime )
+ {
+ if( xBytesReceived != 1 )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+ else if( ( xBytesReceived - xReadBlockTime ) > xAllowableMargin )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ }
+
+ if( xBytesReceived > sizeof( ucRxData ) )
+ {
+ xErrorDetected = pdTRUE;
+ }
+ else if( memcmp( ( void * ) ucRxData, ( const void * ) pcDataSentFromInterrupt, xBytesReceived ) != 0 )
+ {
+ /* Received data didn't match that expected. */
+ xErrorDetected = pdTRUE;
+ }
+
+ if( xErrorDetected == pdFALSE )
+ {
+ /* Increment the cycle counter so the 'check' task knows this test
+ * is still running without error. */
+ ulInterruptTriggerCounter++;
+ }
+
+ /* Tidy up ready for the next loop. */
+ vStreamBufferDelete( xStreamBuffer );
+ }
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xAreStreamBufferTasksStillRunning( void )
{
-static uint32_t ulLastEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
-static uint32_t ulLastNonBlockingRxCounter = 0;
-static uint32_t ulLastInterruptTriggerCounter = 0;
-BaseType_t x;
-
- for( x = 0; x < sbNUMBER_OF_ECHO_CLIENTS; x++ )
- {
- if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ];
- }
- }
-
- if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastNonBlockingRxCounter = ulNonBlockingRxCounter;
- }
-
- if( ulLastInterruptTriggerCounter == ulInterruptTriggerCounter )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastInterruptTriggerCounter = ulInterruptTriggerCounter;
- }
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- static uint32_t ulLastSenderLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
-
- for( x = 0; x < sbNUMBER_OF_SENDER_TASKS; x++ )
- {
- if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ];
- }
- }
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
-
- return xErrorStatus;
+ static uint32_t ulLastEchoLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+ static uint32_t ulLastNonBlockingRxCounter = 0;
+ static uint32_t ulLastInterruptTriggerCounter = 0;
+ BaseType_t x;
+
+ for( x = 0; x < sbNUMBER_OF_ECHO_CLIENTS; x++ )
+ {
+ if( ulLastEchoLoopCounters[ x ] == ulEchoLoopCounters[ x ] )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastEchoLoopCounters[ x ] = ulEchoLoopCounters[ x ];
+ }
+ }
+
+ if( ulNonBlockingRxCounter == ulLastNonBlockingRxCounter )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastNonBlockingRxCounter = ulNonBlockingRxCounter;
+ }
+
+ if( ulLastInterruptTriggerCounter == ulInterruptTriggerCounter )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastInterruptTriggerCounter = ulInterruptTriggerCounter;
+ }
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ static uint32_t ulLastSenderLoopCounters[ sbNUMBER_OF_ECHO_CLIENTS ] = { 0 };
+
+ for( x = 0; x < sbNUMBER_OF_SENDER_TASKS; x++ )
+ {
+ if( ulLastSenderLoopCounters[ x ] == ulSenderLoopCounters[ x ] )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastSenderLoopCounters[ x ] = ulSenderLoopCounters[ x ];
+ }
+ }
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ return xErrorStatus;
}
/*-----------------------------------------------------------*/
diff --git a/Demo/Common/Minimal/StreamBufferInterrupt.c b/Demo/Common/Minimal/StreamBufferInterrupt.c
index fb4e23e80..b7e7237e8 100644
--- a/Demo/Common/Minimal/StreamBufferInterrupt.c
+++ b/Demo/Common/Minimal/StreamBufferInterrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -48,13 +48,13 @@
/* Demo app includes. */
#include "StreamBufferInterrupt.h"
-#define sbiSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 100 )
-#define sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 ( ( BaseType_t ) 10 )
+#define sbiSTREAM_BUFFER_LENGTH_BYTES ( ( size_t ) 100 )
+#define sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 ( ( BaseType_t ) 10 )
/*-----------------------------------------------------------*/
/* Implements the task that receives a stream of bytes from the interrupt. */
-static void prvReceivingTask( void *pvParameters );
+static void prvReceivingTask( void * pvParameters );
/*-----------------------------------------------------------*/
@@ -62,167 +62,168 @@ static void prvReceivingTask( void *pvParameters );
static StreamBufferHandle_t xStreamBuffer = NULL;
/* The string that is sent from the interrupt to the task four bytes at a
-time. Must be multiple of 4 bytes long as the ISR sends 4 bytes at a time*/
+ * time. Must be multiple of 4 bytes long as the ISR sends 4 bytes at a time*/
static const char * pcStringToSend = "_____Hello FreeRTOS_____";
/* The string to task is looking for, which must be a substring of
-pcStringToSend. */
+ * pcStringToSend. */
static const char * pcStringToReceive = "Hello FreeRTOS";
/* Set to pdFAIL if anything unexpected happens. */
static BaseType_t xDemoStatus = pdPASS;
/* Incremented each time pcStringToReceive is correctly received, provided no
-errors have occurred. Used so the check task can check this task is still
-running as expected. */
+ * errors have occurred. Used so the check task can check this task is still
+ * running as expected. */
static uint32_t ulCycleCount = 0;
/*-----------------------------------------------------------*/
void vStartStreamBufferInterruptDemo( void )
{
- /* Create the stream buffer that sends data from the interrupt to the
- task, and create the task. */
- xStreamBuffer = xStreamBufferCreate( /* The buffer length in bytes. */
- sbiSTREAM_BUFFER_LENGTH_BYTES,
- /* The stream buffer's trigger level. */
- sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 );
-
- xTaskCreate( prvReceivingTask, /* The function that implements the task. */
- "StrIntRx", /* Human readable name for the task. */
- configMINIMAL_STACK_SIZE, /* Stack size (in words!). */
- NULL, /* Task parameter is not used. */
- tskIDLE_PRIORITY + 2, /* The priority at which the task is created. */
- NULL ); /* No use for the task handle. */
+ /* Create the stream buffer that sends data from the interrupt to the
+ * task, and create the task. */
+ xStreamBuffer = xStreamBufferCreate( /* The buffer length in bytes. */
+ sbiSTREAM_BUFFER_LENGTH_BYTES,
+ /* The stream buffer's trigger level. */
+ sbiSTREAM_BUFFER_TRIGGER_LEVEL_10 );
+
+ xTaskCreate( prvReceivingTask, /* The function that implements the task. */
+ "StrIntRx", /* Human readable name for the task. */
+ configMINIMAL_STACK_SIZE, /* Stack size (in words!). */
+ NULL, /* Task parameter is not used. */
+ tskIDLE_PRIORITY + 2, /* The priority at which the task is created. */
+ NULL ); /* No use for the task handle. */
}
/*-----------------------------------------------------------*/
-static void prvReceivingTask( void *pvParameters )
+static void prvReceivingTask( void * pvParameters )
{
-char cRxBuffer[ 20 ];
-BaseType_t xNextByte = 0;
-
- /* Remove warning about unused parameters. */
- ( void ) pvParameters;
-
- /* Make sure the string will fit in the Rx buffer, including the NULL
- terminator. */
- configASSERT( sizeof( cRxBuffer ) > strlen( pcStringToReceive ) );
-
- /* Make sure the stream buffer has been created. */
- configASSERT( xStreamBuffer != NULL );
-
- /* Start with the Rx buffer in a known state. */
- memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) );
-
- for( ;; )
- {
- /* Keep receiving characters until the end of the string is received.
- Note: An infinite block time is used to simplify the example. Infinite
- block times are not recommended in production code as they do not allow
- for error recovery. */
- xStreamBufferReceive( /* The stream buffer data is being received from. */
- xStreamBuffer,
- /* Where to place received data. */
- ( void * ) &( cRxBuffer[ xNextByte ] ),
- /* The number of bytes to receive. */
- sizeof( char ),
- /* The time to wait for the next data if the buffer
- is empty. */
- portMAX_DELAY );
-
- /* If xNextByte is 0 then this task is looking for the start of the
- string, which is 'H'. */
- if( xNextByte == 0 )
- {
- if( cRxBuffer[ xNextByte ] == 'H' )
- {
- /* The start of the string has been found. Now receive
- characters until the end of the string is found. */
- xNextByte++;
- }
- }
- else
- {
- /* Receiving characters while looking for the end of the string,
- which is an 'S'. */
- if( cRxBuffer[ xNextByte ] == 'S' )
- {
- /* The string has now been received. Check its validity. */
- if( strcmp( cRxBuffer, pcStringToReceive ) != 0 )
- {
- xDemoStatus = pdFAIL;
- }
-
- /* Return to start looking for the beginning of the string
- again. */
- memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) );
- xNextByte = 0;
-
- /* Increment the cycle count as an indication to the check task
- that this demo is still running. */
- if( xDemoStatus == pdPASS )
- {
- ulCycleCount++;
- }
- }
- else
- {
- /* Receive the next character the next time around, while
- continuing to look for the end of the string. */
- xNextByte++;
-
- configASSERT( ( size_t ) xNextByte < sizeof( cRxBuffer ) );
- }
- }
- }
+ char cRxBuffer[ 20 ];
+ BaseType_t xNextByte = 0;
+
+ /* Remove warning about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Make sure the string will fit in the Rx buffer, including the NULL
+ * terminator. */
+ configASSERT( sizeof( cRxBuffer ) > strlen( pcStringToReceive ) );
+
+ /* Make sure the stream buffer has been created. */
+ configASSERT( xStreamBuffer != NULL );
+
+ /* Start with the Rx buffer in a known state. */
+ memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) );
+
+ for( ; ; )
+ {
+ /* Keep receiving characters until the end of the string is received.
+ * Note: An infinite block time is used to simplify the example. Infinite
+ * block times are not recommended in production code as they do not allow
+ * for error recovery. */
+ xStreamBufferReceive( /* The stream buffer data is being received from. */
+ xStreamBuffer,
+ /* Where to place received data. */
+ ( void * ) &( cRxBuffer[ xNextByte ] ),
+ /* The number of bytes to receive. */
+ sizeof( char ),
+
+ /* The time to wait for the next data if the buffer
+ * is empty. */
+ portMAX_DELAY );
+
+ /* If xNextByte is 0 then this task is looking for the start of the
+ * string, which is 'H'. */
+ if( xNextByte == 0 )
+ {
+ if( cRxBuffer[ xNextByte ] == 'H' )
+ {
+ /* The start of the string has been found. Now receive
+ * characters until the end of the string is found. */
+ xNextByte++;
+ }
+ }
+ else
+ {
+ /* Receiving characters while looking for the end of the string,
+ * which is an 'S'. */
+ if( cRxBuffer[ xNextByte ] == 'S' )
+ {
+ /* The string has now been received. Check its validity. */
+ if( strcmp( cRxBuffer, pcStringToReceive ) != 0 )
+ {
+ xDemoStatus = pdFAIL;
+ }
+
+ /* Return to start looking for the beginning of the string
+ * again. */
+ memset( cRxBuffer, 0x00, sizeof( cRxBuffer ) );
+ xNextByte = 0;
+
+ /* Increment the cycle count as an indication to the check task
+ * that this demo is still running. */
+ if( xDemoStatus == pdPASS )
+ {
+ ulCycleCount++;
+ }
+ }
+ else
+ {
+ /* Receive the next character the next time around, while
+ * continuing to look for the end of the string. */
+ xNextByte++;
+
+ configASSERT( ( size_t ) xNextByte < sizeof( cRxBuffer ) );
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
void vBasicStreamBufferSendFromISR( void )
{
-static size_t xNextByteToSend = 0;
-const BaseType_t xCallsBetweenSends = 100, xBytesToSend = 4;
-static BaseType_t xCallCount = 0;
-
- /* Is it time to write to the stream buffer again? */
- xCallCount++;
- if( xCallCount > xCallsBetweenSends )
- {
- xCallCount = 0;
-
- /* Send the next four bytes to the stream buffer. */
- xStreamBufferSendFromISR( xStreamBuffer,
- ( const void * ) ( pcStringToSend + xNextByteToSend ),
- xBytesToSend,
- NULL );
-
- /* Send the next four bytes the next time around, wrapping to the start
- of the string if necessary. */
- xNextByteToSend += xBytesToSend;
-
- if( xNextByteToSend >= strlen( pcStringToSend ) )
- {
- xNextByteToSend = 0;
- }
- }
+ static size_t xNextByteToSend = 0;
+ const BaseType_t xCallsBetweenSends = 100, xBytesToSend = 4;
+ static BaseType_t xCallCount = 0;
+
+ /* Is it time to write to the stream buffer again? */
+ xCallCount++;
+
+ if( xCallCount > xCallsBetweenSends )
+ {
+ xCallCount = 0;
+
+ /* Send the next four bytes to the stream buffer. */
+ xStreamBufferSendFromISR( xStreamBuffer,
+ ( const void * ) ( pcStringToSend + xNextByteToSend ),
+ xBytesToSend,
+ NULL );
+
+ /* Send the next four bytes the next time around, wrapping to the start
+ * of the string if necessary. */
+ xNextByteToSend += xBytesToSend;
+
+ if( xNextByteToSend >= strlen( pcStringToSend ) )
+ {
+ xNextByteToSend = 0;
+ }
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xIsInterruptStreamBufferDemoStillRunning( void )
{
-uint32_t ulLastCycleCount = 0;
-
- /* Check the demo is still running. */
- if( ulLastCycleCount == ulCycleCount )
- {
- xDemoStatus = pdFAIL;
- }
- else
- {
- ulLastCycleCount = ulCycleCount;
- }
-
- return xDemoStatus;
+ uint32_t ulLastCycleCount = 0;
+
+ /* Check the demo is still running. */
+ if( ulLastCycleCount == ulCycleCount )
+ {
+ xDemoStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastCycleCount = ulCycleCount;
+ }
+
+ return xDemoStatus;
}
-
diff --git a/Demo/Common/Minimal/TaskNotify.c b/Demo/Common/Minimal/TaskNotify.c
index a1250e5a6..11554dfca 100644
--- a/Demo/Common/Minimal/TaskNotify.c
+++ b/Demo/Common/Minimal/TaskNotify.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -43,24 +43,24 @@
/* Allow parameters to be overridden on a demo by demo basis. */
#ifndef notifyNOTIFIED_TASK_STACK_SIZE
- #define notifyNOTIFIED_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define notifyNOTIFIED_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
-#define notifyTASK_PRIORITY ( tskIDLE_PRIORITY )
+#define notifyTASK_PRIORITY ( tskIDLE_PRIORITY )
/* Constants used in tests when setting/clearing bits. */
-#define notifyUINT32_MAX ( ( uint32_t ) 0xffffffff )
-#define notifyUINT32_HIGH_BYTE ( ( uint32_t ) 0xff000000 )
-#define notifyUINT32_LOW_BYTE ( ( uint32_t ) 0x000000ff )
+#define notifyUINT32_MAX ( ( uint32_t ) 0xffffffff )
+#define notifyUINT32_HIGH_BYTE ( ( uint32_t ) 0xff000000 )
+#define notifyUINT32_LOW_BYTE ( ( uint32_t ) 0x000000ff )
-#define notifySUSPENDED_TEST_TIMER_PERIOD pdMS_TO_TICKS( 50 )
+#define notifySUSPENDED_TEST_TIMER_PERIOD pdMS_TO_TICKS( 50 )
/*-----------------------------------------------------------*/
/*
* Implementation of the task that gets notified.
*/
-static void prvNotifiedTask( void *pvParameters );
+static void prvNotifiedTask( void * pvParameters );
/*
* Performs a few initial tests that can be done prior to creating the second
@@ -98,8 +98,8 @@ static volatile uint32_t ulNotifyCycleCount = 0;
static TaskHandle_t xTaskToNotify = NULL;
/* Used to count the notifications sent to the task from a software timer and
-the number of notifications received by the task from the software timer. The
-two should stay synchronised. */
+ * the number of notifications received by the task from the software timer. The
+ * two should stay synchronised. */
static uint32_t ulTimerNotificationsReceived = 0UL, ulTimerNotificationsSent = 0UL;
/* The timer used to notify the task. */
@@ -110,623 +110,612 @@ static size_t uxNextRand = 0;
/*-----------------------------------------------------------*/
-void vStartTaskNotifyTask( void )
+void vStartTaskNotifyTask( void )
{
- /* Create the task that performs some tests by itself, then loops around
- being notified by both a software timer and an interrupt. */
- xTaskCreate( prvNotifiedTask, /* Function that implements the task. */
- "Notified", /* Text name for the task - for debugging only - not used by the kernel. */
- notifyNOTIFIED_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */
- NULL, /* Task parameter, not used in this case. */
- notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */
- &xTaskToNotify ); /* Used to pass a handle to the task out is needed, otherwise set to NULL. */
-
- /* Pseudo seed the random number generator. */
- uxNextRand = ( size_t ) prvRand;
+ /* Create the task that performs some tests by itself, then loops around
+ * being notified by both a software timer and an interrupt. */
+ xTaskCreate( prvNotifiedTask, /* Function that implements the task. */
+ "Notified", /* Text name for the task - for debugging only - not used by the kernel. */
+ notifyNOTIFIED_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */
+ NULL, /* Task parameter, not used in this case. */
+ notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */
+ &xTaskToNotify ); /* Used to pass a handle to the task out is needed, otherwise set to NULL. */
+
+ /* Pseudo seed the random number generator. */
+ uxNextRand = ( size_t ) prvRand;
}
/*-----------------------------------------------------------*/
static void prvSingleTaskTests( void )
{
-const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL );
-BaseType_t xReturned;
-uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue;
-TickType_t xTimeOnEntering;
-const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL;
-const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
-TimerHandle_t xSingleTaskTimer;
-
+ const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL );
+ BaseType_t xReturned;
+ uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue;
+ TickType_t xTimeOnEntering;
+ const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL;
+ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
+ TimerHandle_t xSingleTaskTimer;
+
+
+ /* ------------------------------------------------------------------------
+ * Check blocking when there are no notifications. */
+ xTimeOnEntering = xTaskGetTickCount();
+ xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Should have blocked for the entire block time. */
+ if( ( xTaskGetTickCount() - xTimeOnEntering ) < xTicksToWait )
+ {
+ xErrorStatus = pdFAIL;
+ }
+
+ configASSERT( xReturned == pdFAIL );
+ configASSERT( ulNotifiedValue == 0UL );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+
+
+ /* ------------------------------------------------------------------------
+ * Check no blocking when notifications are pending. First notify itself -
+ * this would not be a normal thing to do and is done here for test purposes
+ * only. */
+ xReturned = xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+
+ /* Even through the 'without overwrite' action was used the update should
+ * have been successful. */
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* No bits should have been pending previously. */
+ configASSERT( ulPreviousValue == 0 );
+ ( void ) ulPreviousValue;
+
+ /* The task should now have a notification pending, and so not time out. */
+ xTimeOnEntering = xTaskGetTickCount();
+ xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
+
+ if( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToWait )
+ {
+ xErrorStatus = pdFAIL;
+ }
+
+ /* The task should have been notified, and the notified value should
+ * be equal to ulFirstNotifiedConst. */
+ configASSERT( xReturned == pdPASS );
+ configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+ /* Incremented to show the task is still running. */
+ ulNotifyCycleCount++;
+
+
+
+ /*-------------------------------------------------------------------------
+ * Check the non-overwriting functionality. The notification is done twice
+ * using two different notification values. The action says don't overwrite so
+ * only the first notification should pass and the value read back should also
+ * be that used with the first notification. */
+ xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Waiting for the notification should now return immediately so a block
+ * time of zero is used. */
+ xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+ configASSERT( xReturned == pdPASS );
+ configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+
+
+ /*-------------------------------------------------------------------------
+ * Do the same again, only this time use the overwriting version. This time
+ * both notifications should pass, and the value written the second time should
+ * overwrite the value written the first time, and so be the value that is read
+ * back. */
+ xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+ ( void ) ulNotifiedValue;
+
+
+
+ /*-------------------------------------------------------------------------
+ * Check notifications with no action pass without updating the value. Even
+ * though ulFirstNotifiedConst is used as the value the value read back should
+ * remain at ulSecondNotifiedConst. */
+ xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eNoAction );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+ configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+ ( void ) ulNotifiedValue; /* In case configASSERT() is not defined. */
+
+ /*-------------------------------------------------------------------------
+ * Check incrementing values. Send ulMaxLoop increment notifications, then
+ * ensure the received value is as expected - which should be
+ * ulSecondNotificationValueConst plus how ever many times to loop iterated. */
+ for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ )
+ {
+ xReturned = xTaskNotify( xTaskToNotify, 0, eIncrement );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ }
+
+ xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdPASS );
+ configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+ /* Should not be any notifications pending now. */
+ xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+
+
+ /*-------------------------------------------------------------------------
+ * Check all bits can be set by notifying the task with one additional bit set
+ * on each notification, and exiting the loop when all the bits are found to be
+ * set. As there are 32-bits the loop should execute 32 times before all the
+ * bits are found to be set. */
+ ulNotifyingValue = 0x01;
+ ulLoop = 0;
+
+ /* Start with all bits clear. */
+ xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+ do
+ {
+ /* Set the next bit in the task's notified value. */
+ xTaskNotify( xTaskToNotify, ulNotifyingValue, eSetBits );
+
+ /* Wait for the notified value - which of course will already be
+ * available. Don't clear the bits on entry or exit as this loop is exited
+ * when all the bits are set. */
+ xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ ulLoop++;
+
+ /* Use the next bit on the next iteration around this loop. */
+ ulNotifyingValue <<= 1UL;
+ } while( ulNotifiedValue != notifyUINT32_MAX );
+
+ /* As a 32-bit value was used the loop should have executed 32 times before
+ * all the bits were set. */
+ configASSERT( ulLoop == 32 );
+
+
+
+ /*-------------------------------------------------------------------------
+ * Check bits are cleared on entry but not on exit when a notification fails
+ * to arrive before timing out - both with and without a timeout value. Wait
+ * for the notification again - but this time it is not given by anything and
+ * should return pdFAIL. The parameters are set to clear bit zero on entry and
+ * bit one on exit. As no notification was received only the bit cleared on
+ * entry should actually get cleared. */
+ xReturned = xTaskNotifyWait( ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+ /* Notify the task with no action so as not to update the bits even though
+ * notifyUINT32_MAX is used as the notification value. */
+ xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eNoAction );
+
+ /* Reading back the value should should find bit 0 is clear, as this was
+ * cleared on entry, but bit 1 is not clear as it will not have been cleared on
+ * exit as no notification was received. */
+ xReturned = xTaskNotifyWait( 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdPASS );
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+
+
+ /*-------------------------------------------------------------------------
+ * Now try clearing the bit on exit. For that to happen a notification must be
+ * received, so the task is notified first. */
+ xTaskNotify( xTaskToNotify, 0, eNoAction );
+ xTaskNotifyWait( 0x00, ulBit1, &ulNotifiedValue, 0 );
+
+ /* However as the bit is cleared on exit, after the returned notification
+ * value is set, the returned notification value should not have the bit
+ * cleared... */
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
+
+ /* ...but reading the value back again should find that the bit was indeed
+ * cleared internally. The returned value should be pdFAIL however as nothing
+ * has notified the task in the mean time. */
+ xReturned = xTaskNotifyWait( 0x00, 0x00, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFAIL );
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+
+
+
+ /*-------------------------------------------------------------------------
+ * Now try querying the previous value while notifying a task. */
+ xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
- /* ------------------------------------------------------------------------
- Check blocking when there are no notifications. */
- xTimeOnEntering = xTaskGetTickCount();
- xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
+ /* Clear all bits. */
+ xTaskNotifyWait( 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 );
+ xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
+ configASSERT( ulPreviousValue == 0 );
- /* Should have blocked for the entire block time. */
- if( ( xTaskGetTickCount() - xTimeOnEntering ) < xTicksToWait )
- {
- xErrorStatus = pdFAIL;
- }
- configASSERT( xReturned == pdFAIL );
- configASSERT( ulNotifiedValue == 0UL );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
+ ulExpectedValue = 0;
+
+ for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL )
+ {
+ /* Set the next bit up, and expect to receive the last bits set (so
+ * the previous value will not yet have the bit being set this time
+ * around). */
+ xTaskNotifyAndQuery( xTaskToNotify, ulLoop, eSetBits, &ulPreviousValue );
+ configASSERT( ulExpectedValue == ulPreviousValue );
+ ulExpectedValue |= ulLoop;
+ }
+
+ /* ------------------------------------------------------------------------
+ * Clear the previous notifications. */
+ xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+ /* The task should not have any notifications pending, so an attempt to clear
+ * the notification state should fail. */
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
+
+ /* Get the task to notify itself. This is not a normal thing to do, and is
+ * only done here for test purposes. */
+ xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+
+ /* Now the notification state should be eNotified, so it should now be
+ * possible to clear the notification state. */
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE );
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
+ /* ------------------------------------------------------------------------
+ * Clear bits in the notification value. */
- /* ------------------------------------------------------------------------
- Check no blocking when notifications are pending. First notify itself -
- this would not be a normal thing to do and is done here for test purposes
- only. */
- xReturned = xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+ /* Get the task to set all bits its own notification value. This is not a
+ * normal thing to do, and is only done here for test purposes. */
+ xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eSetBits );
- /* Even through the 'without overwrite' action was used the update should
- have been successful. */
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
+ /* Now clear the top bytes - the returned value from the first call should
+ * indicate that previously all bits were set. */
+ configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_HIGH_BYTE ) == notifyUINT32_MAX );
- /* No bits should have been pending previously. */
- configASSERT( ulPreviousValue == 0 );
- ( void ) ulPreviousValue;
+ /* Next clear the bottom bytes - the returned value this time should indicate
+ * that the top byte was clear (before the bottom byte was cleared. */
+ configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_LOW_BYTE ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE ) );
+
+ /* Next clear all bytes - the returned value should indicate that previously the
+ * high and low bytes were clear. */
+ configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE & ~notifyUINT32_LOW_BYTE ) );
+
+ /* Now all bits should be clear. */
+ configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == 0 );
+ configASSERT( ulTaskNotifyValueClear( xTaskToNotify, 0UL ) == 0 );
+ configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == 0 );
+
+ /* Now the notification state should be eNotified, so it should now be
+ * possible to clear the notification state. */
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE );
+ configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
- /* The task should now have a notification pending, and so not time out. */
- xTimeOnEntering = xTaskGetTickCount();
- xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
- if( ( xTaskGetTickCount() - xTimeOnEntering ) >= xTicksToWait )
- {
- xErrorStatus = pdFAIL;
- }
- /* The task should have been notified, and the notified value should
- be equal to ulFirstNotifiedConst. */
- configASSERT( xReturned == pdPASS );
- configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
+ /* ------------------------------------------------------------------------
+ * Create a timer that will try notifying this task while it is suspended. */
+ xSingleTaskTimer = xTimerCreate( "SingleNotify", notifySUSPENDED_TEST_TIMER_PERIOD, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback );
+ configASSERT( xSingleTaskTimer );
- /* Incremented to show the task is still running. */
- ulNotifyCycleCount++;
+ /* Incremented to show the task is still running. */
+ ulNotifyCycleCount++;
+
+ /* Ensure no notifications are pending. */
+ xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
+ /* Raise the task's priority so it can suspend itself before the timer
+ * expires. */
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+ /* Start the timer that will try notifying this task while it is
+ * suspended, then wait for a notification. The first time the callback
+ * executes the timer will suspend the task, then resume the task, without
+ * ever sending a notification to the task. */
+ ulNotifiedValue = 0;
+ xTimerStart( xSingleTaskTimer, portMAX_DELAY );
+ /* Check a notification is not received. */
+ xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY );
+ configASSERT( xReturned == pdFALSE );
+ configASSERT( ulNotifiedValue == 0 );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ /* Incremented to show the task is still running. */
+ ulNotifyCycleCount++;
- /*-------------------------------------------------------------------------
- Check the non-overwriting functionality. The notification is done twice
- using two different notification values. The action says don't overwrite so
- only the first notification should pass and the value read back should also
- be that used with the first notification. */
- xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
+ /* Start the timer that will try notifying this task while it is
+ * suspended, then wait for a notification. The second time the callback
+ * executes the timer will suspend the task, notify the task, then resume the
+ * task (previously it was suspended and resumed without being notified). */
+ xTimerStart( xSingleTaskTimer, portMAX_DELAY );
- xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
+ /* Check a notification is received. */
+ xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* In case configASSERT() is not defined. */
+ configASSERT( ulNotifiedValue != 0 );
- /* Waiting for the notification should now return immediately so a block
- time of zero is used. */
- xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+ /* Return the task to its proper priority and delete the timer as it is
+ * not used again. */
+ vTaskPrioritySet( NULL, notifyTASK_PRIORITY );
+ xTimerDelete( xSingleTaskTimer, portMAX_DELAY );
- configASSERT( xReturned == pdPASS );
- configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
+ /* Incremented to show the task is still running. */
+ ulNotifyCycleCount++;
-
-
-
-
- /*-------------------------------------------------------------------------
- Do the same again, only this time use the overwriting version. This time
- both notifications should pass, and the value written the second time should
- overwrite the value written the first time, and so be the value that is read
- back. */
- xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- xReturned = xTaskNotify( xTaskToNotify, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
- ( void ) ulNotifiedValue;
-
-
-
-
- /*-------------------------------------------------------------------------
- Check notifications with no action pass without updating the value. Even
- though ulFirstNotifiedConst is used as the value the value read back should
- remain at ulSecondNotifiedConst. */
- xReturned = xTaskNotify( xTaskToNotify, ulFirstNotifiedConst, eNoAction );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
- configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
- ( void ) ulNotifiedValue; /* In case configASSERT() is not defined. */
-
-
-
-
- /*-------------------------------------------------------------------------
- Check incrementing values. Send ulMaxLoop increment notifications, then
- ensure the received value is as expected - which should be
- ulSecondNotificationValueConst plus how ever many times to loop iterated. */
- for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ )
- {
- xReturned = xTaskNotify( xTaskToNotify, 0, eIncrement );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- }
-
- xReturned = xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdPASS );
- configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
-
- /* Should not be any notifications pending now. */
- xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
-
-
-
-
- /*-------------------------------------------------------------------------
- Check all bits can be set by notifying the task with one additional bit set
- on each notification, and exiting the loop when all the bits are found to be
- set. As there are 32-bits the loop should execute 32 times before all the
- bits are found to be set. */
- ulNotifyingValue = 0x01;
- ulLoop = 0;
-
- /* Start with all bits clear. */
- xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
-
- do
- {
- /* Set the next bit in the task's notified value. */
- xTaskNotify( xTaskToNotify, ulNotifyingValue, eSetBits );
-
- /* Wait for the notified value - which of course will already be
- available. Don't clear the bits on entry or exit as this loop is exited
- when all the bits are set. */
- xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- ulLoop++;
-
- /* Use the next bit on the next iteration around this loop. */
- ulNotifyingValue <<= 1UL;
-
- } while ( ulNotifiedValue != notifyUINT32_MAX );
-
- /* As a 32-bit value was used the loop should have executed 32 times before
- all the bits were set. */
- configASSERT( ulLoop == 32 );
-
-
-
-
- /*-------------------------------------------------------------------------
- Check bits are cleared on entry but not on exit when a notification fails
- to arrive before timing out - both with and without a timeout value. Wait
- for the notification again - but this time it is not given by anything and
- should return pdFAIL. The parameters are set to clear bit zero on entry and
- bit one on exit. As no notification was received only the bit cleared on
- entry should actually get cleared. */
- xReturned = xTaskNotifyWait( ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Notify the task with no action so as not to update the bits even though
- notifyUINT32_MAX is used as the notification value. */
- xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eNoAction );
-
- /* Reading back the value should should find bit 0 is clear, as this was
- cleared on entry, but bit 1 is not clear as it will not have been cleared on
- exit as no notification was received. */
- xReturned = xTaskNotifyWait( 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdPASS );
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
-
-
-
-
- /*-------------------------------------------------------------------------
- Now try clearing the bit on exit. For that to happen a notification must be
- received, so the task is notified first. */
- xTaskNotify( xTaskToNotify, 0, eNoAction );
- xTaskNotifyWait( 0x00, ulBit1, &ulNotifiedValue, 0 );
-
- /* However as the bit is cleared on exit, after the returned notification
- value is set, the returned notification value should not have the bit
- cleared... */
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
-
- /* ...but reading the value back again should find that the bit was indeed
- cleared internally. The returned value should be pdFAIL however as nothing
- has notified the task in the mean time. */
- xReturned = xTaskNotifyWait( 0x00, 0x00, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFAIL );
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
-
-
-
- /*-------------------------------------------------------------------------
- Now try querying the previous value while notifying a task. */
- xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
-
- /* Clear all bits. */
- xTaskNotifyWait( 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 );
- xTaskNotifyAndQuery( xTaskToNotify, 0x00, eSetBits, &ulPreviousValue );
- configASSERT( ulPreviousValue == 0 );
-
- ulExpectedValue = 0;
- for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL )
- {
- /* Set the next bit up, and expect to receive the last bits set (so
- the previous value will not yet have the bit being set this time
- around). */
- xTaskNotifyAndQuery( xTaskToNotify, ulLoop, eSetBits, &ulPreviousValue );
- configASSERT( ulExpectedValue == ulPreviousValue );
- ulExpectedValue |= ulLoop;
- }
-
-
-
- /* ------------------------------------------------------------------------
- Clear the previous notifications. */
- xTaskNotifyWait( notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
-
- /* The task should not have any notifications pending, so an attempt to clear
- the notification state should fail. */
- configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
-
- /* Get the task to notify itself. This is not a normal thing to do, and is
- only done here for test purposes. */
- xTaskNotifyAndQuery( xTaskToNotify, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
-
- /* Now the notification state should be eNotified, so it should now be
- possible to clear the notification state. */
- configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE );
- configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
-
-
-
- /* ------------------------------------------------------------------------
- Clear bits in the notification value. */
-
- /* Get the task to set all bits its own notification value. This is not a
- normal thing to do, and is only done here for test purposes. */
- xTaskNotify( xTaskToNotify, notifyUINT32_MAX, eSetBits );
-
- /* Now clear the top bytes - the returned value from the first call should
- indicate that previously all bits were set. */
- configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_HIGH_BYTE ) == notifyUINT32_MAX );
-
- /* Next clear the bottom bytes - the returned value this time should indicate
- that the top byte was clear (before the bottom byte was cleared. */
- configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_LOW_BYTE ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE ) );
-
- /* Next clear all bytes - the returned value should indicate that previously the
- high and low bytes were clear. */
- configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE & ~notifyUINT32_LOW_BYTE ) );
-
- /* Now all bits should be clear. */
- configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == 0 );
- configASSERT( ulTaskNotifyValueClear( xTaskToNotify, 0UL ) == 0 );
- configASSERT( ulTaskNotifyValueClear( xTaskToNotify, notifyUINT32_MAX ) == 0 );
-
- /* Now the notification state should be eNotified, so it should now be
- possible to clear the notification state. */
- configASSERT( xTaskNotifyStateClear( NULL ) == pdTRUE );
- configASSERT( xTaskNotifyStateClear( NULL ) == pdFALSE );
-
-
-
- /* ------------------------------------------------------------------------
- Create a timer that will try notifying this task while it is suspended. */
- xSingleTaskTimer = xTimerCreate( "SingleNotify", notifySUSPENDED_TEST_TIMER_PERIOD, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback );
- configASSERT( xSingleTaskTimer );
-
- /* Incremented to show the task is still running. */
- ulNotifyCycleCount++;
-
- /* Ensure no notifications are pending. */
- xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
-
- /* Raise the task's priority so it can suspend itself before the timer
- expires. */
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
-
- /* Start the timer that will try notifying this task while it is
- suspended, then wait for a notification. The first time the callback
- executes the timer will suspend the task, then resume the task, without
- ever sending a notification to the task. */
- ulNotifiedValue = 0;
- xTimerStart( xSingleTaskTimer, portMAX_DELAY );
-
- /* Check a notification is not received. */
- xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY );
- configASSERT( xReturned == pdFALSE );
- configASSERT( ulNotifiedValue == 0 );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
-
- /* Incremented to show the task is still running. */
- ulNotifyCycleCount++;
-
- /* Start the timer that will try notifying this task while it is
- suspended, then wait for a notification. The second time the callback
- executes the timer will suspend the task, notify the task, then resume the
- task (previously it was suspended and resumed without being notified). */
- xTimerStart( xSingleTaskTimer, portMAX_DELAY );
-
- /* Check a notification is received. */
- xReturned = xTaskNotifyWait( 0, 0, &ulNotifiedValue, portMAX_DELAY );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* In case configASSERT() is not defined. */
- configASSERT( ulNotifiedValue != 0 );
-
- /* Return the task to its proper priority and delete the timer as it is
- not used again. */
- vTaskPrioritySet( NULL, notifyTASK_PRIORITY );
- xTimerDelete( xSingleTaskTimer, portMAX_DELAY );
-
- /* Incremented to show the task is still running. */
- ulNotifyCycleCount++;
-
- /* Leave all bits cleared. */
- xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
+ /* Leave all bits cleared. */
+ xTaskNotifyWait( notifyUINT32_MAX, 0, NULL, 0 );
}
/*-----------------------------------------------------------*/
static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer )
{
-static uint32_t ulCallCount = 0;
-
- /* Remove compiler warnings about unused parameters. */
- ( void ) xExpiredTimer;
-
- /* Callback for a timer that is used during preliminary testing. The timer
- tests the behaviour when 1: a task waiting for a notification is suspended
- and then resumed without ever receiving a notification, and 2: when a task
- waiting for a notification receives a notification while it is suspended. */
-
- if( ulCallCount == 0 )
- {
- vTaskSuspend( xTaskToNotify );
- configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
- vTaskResume( xTaskToNotify );
- }
- else
- {
- vTaskSuspend( xTaskToNotify );
-
- /* Sending a notification while the task is suspended should pass, but
- not cause the task to resume. ulCallCount is just used as a convenient
- non-zero value. */
- xTaskNotify( xTaskToNotify, ulCallCount, eSetValueWithOverwrite );
-
- /* Make sure giving the notification didn't resume the task. */
- configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
-
- vTaskResume( xTaskToNotify );
- }
-
- ulCallCount++;
+ static uint32_t ulCallCount = 0;
+
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) xExpiredTimer;
+
+ /* Callback for a timer that is used during preliminary testing. The timer
+ * tests the behaviour when 1: a task waiting for a notification is suspended
+ * and then resumed without ever receiving a notification, and 2: when a task
+ * waiting for a notification receives a notification while it is suspended. */
+
+ if( ulCallCount == 0 )
+ {
+ vTaskSuspend( xTaskToNotify );
+ configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
+ vTaskResume( xTaskToNotify );
+ }
+ else
+ {
+ vTaskSuspend( xTaskToNotify );
+
+ /* Sending a notification while the task is suspended should pass, but
+ * not cause the task to resume. ulCallCount is just used as a convenient
+ * non-zero value. */
+ xTaskNotify( xTaskToNotify, ulCallCount, eSetValueWithOverwrite );
+
+ /* Make sure giving the notification didn't resume the task. */
+ configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
+
+ vTaskResume( xTaskToNotify );
+ }
+
+ ulCallCount++;
}
/*-----------------------------------------------------------*/
static void prvNotifyingTimer( TimerHandle_t xNotUsed )
{
- ( void ) xNotUsed;
+ ( void ) xNotUsed;
- xTaskNotifyGive( xTaskToNotify );
+ xTaskNotifyGive( xTaskToNotify );
- /* This value is also incremented from an interrupt. */
- taskENTER_CRITICAL();
- {
- ulTimerNotificationsSent++;
- }
- taskEXIT_CRITICAL();
+ /* This value is also incremented from an interrupt. */
+ taskENTER_CRITICAL();
+ {
+ ulTimerNotificationsSent++;
+ }
+ taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
-static void prvNotifiedTask( void *pvParameters )
+static void prvNotifiedTask( void * pvParameters )
{
-const TickType_t xMaxPeriod = pdMS_TO_TICKS( 90 ), xMinPeriod = pdMS_TO_TICKS( 10 ), xDontBlock = 0;
-TickType_t xPeriod;
-const uint32_t ulCyclesToRaisePriority = 50UL;
-
- /* Remove compiler warnings about unused parameters. */
- ( void ) pvParameters;
-
- /* Run a few tests that can be done from a single task before entering the
- main loop. */
- prvSingleTaskTests();
-
- /* Create the software timer that is used to send notifications to this
- task. Notifications are also received from an interrupt. */
- xTimer = xTimerCreate( "Notifier", xMaxPeriod, pdFALSE, NULL, prvNotifyingTimer );
-
- for( ;; )
- {
- /* Start the timer again with a different period. Sometimes the period
- will be higher than the task's block time, sometimes it will be lower
- than the task's block time. */
- xPeriod = prvRand() % xMaxPeriod;
- if( xPeriod < xMinPeriod )
- {
- xPeriod = xMinPeriod;
- }
-
- /* Change the timer period and start the timer. */
- xTimerChangePeriod( xTimer, xPeriod, portMAX_DELAY );
-
- /* Block waiting for the notification again with a different period.
- Sometimes the period will be higher than the task's block time,
- sometimes it will be lower than the task's block time. */
- xPeriod = prvRand() % xMaxPeriod;
- if( xPeriod < xMinPeriod )
- {
- xPeriod = xMinPeriod;
- }
-
- /* Block to wait for a notification but without clearing the
- notification count, so only add one to the count of received
- notifications as any other notifications will remain pending. */
- if( ulTaskNotifyTake( pdFALSE, xPeriod ) != 0 )
- {
- ulTimerNotificationsReceived++;
- }
-
-
- /* Take a notification without clearing again, but this time without a
- block time specified. */
- if( ulTaskNotifyTake( pdFALSE, xDontBlock ) != 0 )
- {
- ulTimerNotificationsReceived++;
- }
-
- /* Wait for the next notification from the timer, clearing all
- notifications if one is received, so this time adding the total number
- of notifications that were pending as none will be left pending after
- the function call. */
- ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, xPeriod );
-
- /* Occasionally raise the priority of the task being notified to test
- the path where the task is notified from an ISR and becomes the highest
- priority ready state task, but the pxHigherPriorityTaskWoken parameter
- is NULL (which it is in the tick hook that sends notifications to this
- task). */
- if( ( ulNotifyCycleCount % ulCyclesToRaisePriority ) == 0 )
- {
- vTaskPrioritySet( xTaskToNotify, configMAX_PRIORITIES - 1 );
-
- /* Wait for the next notification again, clearing all notifications
- if one is received, but this time blocking indefinitely. */
- ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
-
- /* Reset the priority. */
- vTaskPrioritySet( xTaskToNotify, notifyTASK_PRIORITY );
- }
- else
- {
- /* Wait for the next notification again, clearing all notifications
- if one is received, but this time blocking indefinitely. */
- ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
- }
-
- /* Incremented to show the task is still running. */
- ulNotifyCycleCount++;
- }
+ const TickType_t xMaxPeriod = pdMS_TO_TICKS( 90 ), xMinPeriod = pdMS_TO_TICKS( 10 ), xDontBlock = 0;
+ TickType_t xPeriod;
+ const uint32_t ulCyclesToRaisePriority = 50UL;
+
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Run a few tests that can be done from a single task before entering the
+ * main loop. */
+ prvSingleTaskTests();
+
+ /* Create the software timer that is used to send notifications to this
+ * task. Notifications are also received from an interrupt. */
+ xTimer = xTimerCreate( "Notifier", xMaxPeriod, pdFALSE, NULL, prvNotifyingTimer );
+
+ for( ; ; )
+ {
+ /* Start the timer again with a different period. Sometimes the period
+ * will be higher than the task's block time, sometimes it will be lower
+ * than the task's block time. */
+ xPeriod = prvRand() % xMaxPeriod;
+
+ if( xPeriod < xMinPeriod )
+ {
+ xPeriod = xMinPeriod;
+ }
+
+ /* Change the timer period and start the timer. */
+ xTimerChangePeriod( xTimer, xPeriod, portMAX_DELAY );
+
+ /* Block waiting for the notification again with a different period.
+ * Sometimes the period will be higher than the task's block time,
+ * sometimes it will be lower than the task's block time. */
+ xPeriod = prvRand() % xMaxPeriod;
+
+ if( xPeriod < xMinPeriod )
+ {
+ xPeriod = xMinPeriod;
+ }
+
+ /* Block to wait for a notification but without clearing the
+ * notification count, so only add one to the count of received
+ * notifications as any other notifications will remain pending. */
+ if( ulTaskNotifyTake( pdFALSE, xPeriod ) != 0 )
+ {
+ ulTimerNotificationsReceived++;
+ }
+
+ /* Take a notification without clearing again, but this time without a
+ * block time specified. */
+ if( ulTaskNotifyTake( pdFALSE, xDontBlock ) != 0 )
+ {
+ ulTimerNotificationsReceived++;
+ }
+
+ /* Wait for the next notification from the timer, clearing all
+ * notifications if one is received, so this time adding the total number
+ * of notifications that were pending as none will be left pending after
+ * the function call. */
+ ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, xPeriod );
+
+ /* Occasionally raise the priority of the task being notified to test
+ * the path where the task is notified from an ISR and becomes the highest
+ * priority ready state task, but the pxHigherPriorityTaskWoken parameter
+ * is NULL (which it is in the tick hook that sends notifications to this
+ * task). */
+ if( ( ulNotifyCycleCount % ulCyclesToRaisePriority ) == 0 )
+ {
+ vTaskPrioritySet( xTaskToNotify, configMAX_PRIORITIES - 1 );
+
+ /* Wait for the next notification again, clearing all notifications
+ * if one is received, but this time blocking indefinitely. */
+ ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+
+ /* Reset the priority. */
+ vTaskPrioritySet( xTaskToNotify, notifyTASK_PRIORITY );
+ }
+ else
+ {
+ /* Wait for the next notification again, clearing all notifications
+ * if one is received, but this time blocking indefinitely. */
+ ulTimerNotificationsReceived += ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+ }
+
+ /* Incremented to show the task is still running. */
+ ulNotifyCycleCount++;
+ }
}
/*-----------------------------------------------------------*/
void xNotifyTaskFromISR( void )
{
-static BaseType_t xCallCount = 0, xAPIToUse = 0;
-const BaseType_t xCallInterval = pdMS_TO_TICKS( 50 );
-uint32_t ulPreviousValue;
-const uint32_t ulUnexpectedValue = 0xff;
-
- /* Check the task notification demo tasks were actually created. */
- configASSERT( xTaskToNotify );
-
- /* The task performs some tests before starting the timer that gives the
- notification from this interrupt. If the timer has not been created yet
- then the initial tests have not yet completed and the notification should
- not be sent. */
- if( xTimer != NULL )
- {
- xCallCount++;
-
- if( xCallCount >= xCallInterval )
- {
- /* It is time to 'give' the notification again. */
- xCallCount = 0;
-
- /* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR()
- and xTaskNotifyAndQueryFromISR(). */
- switch( xAPIToUse )
- {
- case 0: vTaskNotifyGiveFromISR( xTaskToNotify, NULL );
- xAPIToUse++;
- break;
-
- case 1: xTaskNotifyFromISR( xTaskToNotify, 0, eIncrement, NULL );
- xAPIToUse++;
- break;
-
- case 2: ulPreviousValue = ulUnexpectedValue;
- xTaskNotifyAndQueryFromISR( xTaskToNotify, 0, eIncrement, &ulPreviousValue, NULL );
- configASSERT( ulPreviousValue != ulUnexpectedValue );
- xAPIToUse = 0;
- break;
-
- default:/* Should never get here!. */
- break;
- }
-
- ulTimerNotificationsSent++;
- }
- }
+ static BaseType_t xCallCount = 0, xAPIToUse = 0;
+ const BaseType_t xCallInterval = pdMS_TO_TICKS( 50 );
+ uint32_t ulPreviousValue;
+ const uint32_t ulUnexpectedValue = 0xff;
+
+ /* Check the task notification demo tasks were actually created. */
+ configASSERT( xTaskToNotify );
+
+ /* The task performs some tests before starting the timer that gives the
+ * notification from this interrupt. If the timer has not been created yet
+ * then the initial tests have not yet completed and the notification should
+ * not be sent. */
+ if( xTimer != NULL )
+ {
+ xCallCount++;
+
+ if( xCallCount >= xCallInterval )
+ {
+ /* It is time to 'give' the notification again. */
+ xCallCount = 0;
+
+ /* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR()
+ * and xTaskNotifyAndQueryFromISR(). */
+ switch( xAPIToUse )
+ {
+ case 0:
+ vTaskNotifyGiveFromISR( xTaskToNotify, NULL );
+ xAPIToUse++;
+ break;
+
+ case 1:
+ xTaskNotifyFromISR( xTaskToNotify, 0, eIncrement, NULL );
+ xAPIToUse++;
+ break;
+
+ case 2:
+ ulPreviousValue = ulUnexpectedValue;
+ xTaskNotifyAndQueryFromISR( xTaskToNotify, 0, eIncrement, &ulPreviousValue, NULL );
+ configASSERT( ulPreviousValue != ulUnexpectedValue );
+ xAPIToUse = 0;
+ break;
+
+ default: /* Should never get here!. */
+ break;
+ }
+
+ ulTimerNotificationsSent++;
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check the created tasks are still running and have not
-detected any errors. */
+ * detected any errors. */
BaseType_t xAreTaskNotificationTasksStillRunning( void )
{
-static uint32_t ulLastNotifyCycleCount = 0;
-const uint32_t ulMaxSendReceiveDeviation = 5UL;
-
- /* Check the cycle count is still incrementing to ensure the task is still
- actually running. */
- if( ulLastNotifyCycleCount == ulNotifyCycleCount )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastNotifyCycleCount = ulNotifyCycleCount;
- }
-
- /* Check the count of 'takes' from the software timer is keeping track with
- the amount of 'gives'. */
- if( ulTimerNotificationsSent > ulTimerNotificationsReceived )
- {
- if( ( ulTimerNotificationsSent - ulTimerNotificationsReceived ) > ulMaxSendReceiveDeviation )
- {
- xErrorStatus = pdFAIL;
- }
- }
-
- return xErrorStatus;
+ static uint32_t ulLastNotifyCycleCount = 0;
+ const uint32_t ulMaxSendReceiveDeviation = 5UL;
+
+ /* Check the cycle count is still incrementing to ensure the task is still
+ * actually running. */
+ if( ulLastNotifyCycleCount == ulNotifyCycleCount )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastNotifyCycleCount = ulNotifyCycleCount;
+ }
+
+ /* Check the count of 'takes' from the software timer is keeping track with
+ * the amount of 'gives'. */
+ if( ulTimerNotificationsSent > ulTimerNotificationsReceived )
+ {
+ if( ( ulTimerNotificationsSent - ulTimerNotificationsReceived ) > ulMaxSendReceiveDeviation )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ }
+
+ return xErrorStatus;
}
/*-----------------------------------------------------------*/
static UBaseType_t prvRand( void )
{
-const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1;
+ const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1;
- /* Utility function to generate a pseudo random number. */
- uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement;
- return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) );
+ /* Utility function to generate a pseudo random number. */
+ uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement;
+ return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) );
}
/*-----------------------------------------------------------*/
diff --git a/Demo/Common/Minimal/TaskNotifyArray.c b/Demo/Common/Minimal/TaskNotifyArray.c
index f8ef34876..6e8a0507f 100644
--- a/Demo/Common/Minimal/TaskNotifyArray.c
+++ b/Demo/Common/Minimal/TaskNotifyArray.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
@@ -42,21 +41,21 @@
/* Demo program include files. */
#include "TaskNotifyArray.h"
-#if( configTASK_NOTIFICATION_ARRAY_ENTRIES < 3 )
- #error This file tests direct to task notification arrays and needs configTASK_NOTIFICATION_ARRAY_ENTRIES to be at least 3.
+#if ( configTASK_NOTIFICATION_ARRAY_ENTRIES < 3 )
+ #error This file tests direct to task notification arrays and needs configTASK_NOTIFICATION_ARRAY_ENTRIES to be at least 3.
#endif
/* Allow parameters to be overridden on a demo by demo basis. */
#ifndef notifyNOTIFY_ARRAY_TASK_STACK_SIZE
- #define notifyNOTIFY_ARRAY_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define notifyNOTIFY_ARRAY_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
-#define notifyTASK_PRIORITY ( tskIDLE_PRIORITY )
+#define notifyTASK_PRIORITY ( tskIDLE_PRIORITY )
/* Constants used in tests when setting/clearing bits. */
-#define notifyUINT32_MAX ( ( uint32_t ) 0xffffffff )
-#define notifyUINT32_HIGH_BYTE ( ( uint32_t ) 0xff000000 )
-#define notifyUINT32_LOW_BYTE ( ( uint32_t ) 0x000000ff )
+#define notifyUINT32_MAX ( ( uint32_t ) 0xffffffff )
+#define notifyUINT32_HIGH_BYTE ( ( uint32_t ) 0xff000000 )
+#define notifyUINT32_LOW_BYTE ( ( uint32_t ) 0x000000ff )
/*-----------------------------------------------------------*/
@@ -65,7 +64,7 @@
* itself, and others where notifications are sent from a software timer or
* an interrupt (specifically the tick hook function).
*/
-static void prvNotifiedTask( void *pvParameters );
+static void prvNotifiedTask( void * pvParameters );
/*
* Performs the tests that don't require notifications to be sent from a
@@ -123,14 +122,14 @@ static UBaseType_t prvRand( void );
/*-----------------------------------------------------------*/
/* Counters used to check the task has not stalled. ulFineCycleCount is
-incremented within each test. ulCourseCycleCounter is incremented one every
-loop of all the tests to ensure each test is actually executing. The check task
-calls xAreTaskNotificationArrayTasksStillRunning() (implemented within this
-file) to check both counters are changing. */
+ * incremented within each test. ulCourseCycleCounter is incremented one every
+ * loop of all the tests to ensure each test is actually executing. The check task
+ * calls xAreTaskNotificationArrayTasksStillRunning() (implemented within this
+ * file) to check both counters are changing. */
static volatile uint32_t ulFineCycleCount = 0, ulCourseCycleCounter = 0;
/* The handle of the task that runs the tests and receives the notifications
-from the software timers and interrupts. */
+ * from the software timers and interrupts. */
static TaskHandle_t xTaskToNotify = NULL;
/* The software timers used to send notifications to the main test task. */
@@ -145,1094 +144,1075 @@ static volatile BaseType_t xSendNotificationFromISR = pdFALSE;
/*-----------------------------------------------------------*/
-void vStartTaskNotifyArrayTask( void )
+void vStartTaskNotifyArrayTask( void )
{
-const TickType_t xIncrementingIndexTimerPeriod = pdMS_TO_TICKS( 100 );
-const TickType_t xSuspendTimerPeriod = pdMS_TO_TICKS( 50 );
-
- /* Create the software timers used for these tests. The timer callbacks send
- notifications to this task. */
- xNotifyWhileSuspendedTimer = xTimerCreate( "SingleNotify", xSuspendTimerPeriod, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback );
- xIncrementingIndexTimer = xTimerCreate( "Notifier", xIncrementingIndexTimerPeriod, pdFALSE, NULL, prvNotifyingTimerCallback );
- configASSERT( xNotifyWhileSuspendedTimer );
- configASSERT( xIncrementingIndexTimer );
-
- /* Create the task that performs some tests by itself, then loops around
- being notified by both a software timer and an interrupt. */
- xTaskCreate( prvNotifiedTask, /* Function that implements the task. */
- "ArrayNotifed", /* Text name for the task - for debugging only - not used by the kernel. */
- notifyNOTIFY_ARRAY_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */
- NULL, /* Task parameter, not used in this case. */
- notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */
- &xTaskToNotify ); /* Used to pass a handle to the task out if needed, otherwise set to NULL. */
-
- /* Pseudo seed the random number generator. */
- uxNextRand = ( size_t ) prvRand;
+ const TickType_t xIncrementingIndexTimerPeriod = pdMS_TO_TICKS( 100 );
+ const TickType_t xSuspendTimerPeriod = pdMS_TO_TICKS( 50 );
+
+ /* Create the software timers used for these tests. The timer callbacks send
+ * notifications to this task. */
+ xNotifyWhileSuspendedTimer = xTimerCreate( "SingleNotify", xSuspendTimerPeriod, pdFALSE, NULL, prvSuspendedTaskTimerTestCallback );
+ xIncrementingIndexTimer = xTimerCreate( "Notifier", xIncrementingIndexTimerPeriod, pdFALSE, NULL, prvNotifyingTimerCallback );
+ configASSERT( xNotifyWhileSuspendedTimer );
+ configASSERT( xIncrementingIndexTimer );
+
+ /* Create the task that performs some tests by itself, then loops around
+ * being notified by both a software timer and an interrupt. */
+ xTaskCreate( prvNotifiedTask, /* Function that implements the task. */
+ "ArrayNotifed", /* Text name for the task - for debugging only - not used by the kernel. */
+ notifyNOTIFY_ARRAY_TASK_STACK_SIZE, /* Task's stack size in words, not bytes!. */
+ NULL, /* Task parameter, not used in this case. */
+ notifyTASK_PRIORITY, /* Task priority, 0 is the lowest. */
+ &xTaskToNotify ); /* Used to pass a handle to the task out if needed, otherwise set to NULL. */
+
+ /* Pseudo seed the random number generator. */
+ uxNextRand = ( size_t ) prvRand;
}
/*-----------------------------------------------------------*/
-static void prvNotifiedTask( void *pvParameters )
+static void prvNotifiedTask( void * pvParameters )
{
- /* Remove compiler warnings about unused parameters. */
- ( void ) pvParameters;
-
- /* Loop through each set of test functions in turn. See the comments above
- the respective function prototypes above for more details. */
- for( ;; )
- {
- prvSingleTaskTests();
- prvTestNotifyTaskWhileSuspended();
- prvBlockOnTheNotifiedIndexed();
- prvBlockOnANonNotifiedIndexed();
- prvBlockOnNotificationsComingFromInterrupts();
- ulCourseCycleCounter++;
- }
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) pvParameters;
+
+ /* Loop through each set of test functions in turn. See the comments above
+ * the respective function prototypes above for more details. */
+ for( ; ; )
+ {
+ prvSingleTaskTests();
+ prvTestNotifyTaskWhileSuspended();
+ prvBlockOnTheNotifiedIndexed();
+ prvBlockOnANonNotifiedIndexed();
+ prvBlockOnNotificationsComingFromInterrupts();
+ ulCourseCycleCounter++;
+ }
}
/*-----------------------------------------------------------*/
static void prvSingleTaskTests( void )
{
-const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL );
-BaseType_t xReturned;
-uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue;
-TickType_t xTimeOnEntering, xTimeNow, xTimeDifference;
-const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL;
-const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
-UBaseType_t uxIndexToTest, uxOtherIndexes;
-
-
- /* ------------------------------------------------------------------------
- Check blocking when there are no notifications. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Send notifications to the task notification in each index of the
- task notification array other than the one on which this task will
- block. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, 0, eNoAction );
- }
- }
-
- xTimeOnEntering = xTaskGetTickCount();
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* Should have blocked for the entire block time. */
- xTimeNow = xTaskGetTickCount();
- xTimeDifference = xTimeNow - xTimeOnEntering;
- configASSERT( xTimeDifference >= xTicksToWait );
- configASSERT( xReturned == pdFAIL );
- configASSERT( ulNotifiedValue == 0UL );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
-
- /* Clear all the other notifications within the array of task
- notifications again ready for the next round. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes );
-
- /* The notification state was set above so expect it to still be
- set. */
- configASSERT( xReturned == pdTRUE );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
- }
-
-
-
- /* ------------------------------------------------------------------------
- Check no blocking when notifications are pending. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* First notify the task notification at index uxIndexToTest within this
- task's own array of task notifications - this would not be a normal
- thing to do and is done here for test purposes only. */
- xReturned = xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
-
- /* Even through the 'without overwrite' action was used the update should
- have been successful. */
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* No bits should have been pending previously. */
- configASSERT( ulPreviousValue == 0 );
- ( void ) ulPreviousValue;
-
- /* The task should now have a notification pending in the task
- notification at index uxIndexToTest within the task notification array,
- and so not time out. */
- xTimeOnEntering = xTaskGetTickCount();
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
- xTimeNow = xTaskGetTickCount();
- xTimeDifference = xTimeNow - xTimeOnEntering;
- configASSERT( xTimeDifference < xTicksToWait );
-
- /* The task should have been notified, and the notified value should
- be equal to ulFirstNotifiedConst. */
- configASSERT( xReturned == pdPASS );
- configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
- }
-
-
-
-
- /*-------------------------------------------------------------------------
- Check the non-overwriting functionality. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Send notifications to all indexes with the array of task
- notificaitons other than the one on which this task will block. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, ulFirstNotifiedConst, eSetValueWithOverwrite );
- configASSERT(xReturned == pdPASS);
- (void)xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
-
- /* The notification is performed twice using two different notification
- values. The action says don't overwrite so only the first notification
- should pass and the value read back should also be that used with the
- first notification. The notification is sent to the task notification at
- index uxIndexToTest within the array of task notifications. */
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* Waiting for the notification should now return immediately so a block
- time of zero is used. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
-
- configASSERT( xReturned == pdPASS );
- configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
-
- /* Clear all the other task notifications within the array of task
- notifications again ready for the next round. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes );
- configASSERT( xReturned == pdTRUE );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- ulNotifiedValue = ulTaskNotifyValueClearIndexed( xTaskToNotify, uxOtherIndexes, notifyUINT32_MAX );
-
- /* The notification value was set to ulFirstNotifiedConst in all
- the other indexes, so expect it to still have that value. */
- configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
- }
-
-
-
-
- /*-------------------------------------------------------------------------
- Do the same again, only this time use the overwriting version. This time
- both notifications should pass, and the value written the second time should
- overwrite the value written the first time, and so be the value that is read
- back. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, ulFirstNotifiedConst, eSetValueWithOverwrite );
- }
- }
-
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, notifyUINT32_MAX, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
- ( void ) ulNotifiedValue;
-
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes );
- configASSERT( xReturned == pdTRUE );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- ulNotifiedValue = ulTaskNotifyValueClearIndexed( xTaskToNotify, uxOtherIndexes, notifyUINT32_MAX );
- configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
- }
-
-
-
-
- /*-------------------------------------------------------------------------
- For each task notification within the array of task notifications, check
- notifications with no action pass without updating the value. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* First set the notification values of the task notification at index
- uxIndexToTest of the array of task notification to
- ulSecondNotifiedValueConst. */
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* Even though ulFirstNotifiedConst is used as the value next, the value
- read back should remain at ulSecondNotifiedConst as the action is set
- to eNoAction. */
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eNoAction );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* All task notifications in the array of task notifications up to and
- including index uxIndexToTest should still contain the same value. */
- for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
- {
- /* First zero is bits to clear on entry, the second is bits to clear on
- exist, the last 0 is the block time. */
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* All array indexes in the array of task notifications after index
- uxIndexToTest should still contain 0 as they have not been set in this
- loop yet. This time use ulTaskNotifyValueClearIndexed() instead of
- xTaskNotifyWaitIndexed(), just for test coverage. */
- for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- /* This time 0 is the bits to clear parameter - so clearing no bits. */
- ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
- configASSERT( ulNotifiedValue == 0 );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
-
-
-
-
- /*-------------------------------------------------------------------------
- Check incrementing values. For each task notification in the array of task
- notifications in turn, send ulMaxLoop increment notifications, then ensure
- the received value is as expected - which should be
- ulSecondNotificationValueConst plus how ever many times to loop iterated. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ )
- {
- /* Increment the value of the task notification at index
- uxIndexToTest within the array of task notifications. */
- xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, 0, eIncrement );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* All array indexes up to and including uxIndexToTest should still
- contain the updated value. */
- for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
- {
- /* First zero is bits to clear on entry, the second is bits to clear on
- exist, the last 0 is the block time. */
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* Should not be any notifications pending now. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
-
- /* All notifications values in the array of task notifications after
- index uxIndexToTest should still contain the un-incremented
- ulSecondNotifiedValueConst as they have not been set in this loop yet.
- This time use ulTaskNotifyValueClearIndexed() instead of xTaskNotifyWaitIndexed(),
- just for test coverage. */
- for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- /* This time 0 is the bits to clear parameter - so clearing no bits. */
- ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
- configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
-
- /* Clear all bits ready for next test. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Start with all bits clear. */
- ulTaskNotifyValueClearIndexed( NULL, uxIndexToTest, notifyUINT32_MAX );
- }
-
-
-
- /*-------------------------------------------------------------------------
- For each task notification in the array of task notifications in turn, check
- all bits in the notification's value can be set by notifying the task with
- one additional bit set on each notification, and exiting the loop when all
- the bits are found to be set. As there are 32-bits the loop should execute
- 32 times before all the bits are found to be set. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- ulNotifyingValue = 0x01;
- ulLoop = 0;
-
- do
- {
- /* Set the next bit in the value of the task notification at index
- uxIndexToTest within the array of task notifications. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulNotifyingValue, eSetBits );
-
- /* Wait for the notified value - which of course will already be
- available. Don't clear the bits on entry or exit as this loop is
- exited when all the bits are set. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- ulLoop++;
-
- /* Use the next bit on the next iteration around this loop. */
- ulNotifyingValue <<= 1UL;
-
- } while ( ulNotifiedValue != notifyUINT32_MAX );
-
- /* As a 32-bit value was used the loop should have executed 32 times before
- all the bits were set. */
- configASSERT( ulLoop == 32 );
-
- /* The value of each task notification within the array of task
- notifications up to and including index uxIndexToTest should still have
- all bits set. */
- for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
- {
- /* First zero is bits to clear on entry, the second is bits to clear on
- exist, the last 0 is the block time. */
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( ulNotifiedValue == notifyUINT32_MAX );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* The value of each task notification within the array of task
- notifications after index uxIndexToTest should still contain 0 as they
- have not been set in this loop yet. This time use ulTaskNotifyValueClearIndexed()
- instead of xTaskNotifyWaitIndexed(), just for test coverage. */
- for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- /* This time 0 is the bits to clear parameter - so clearing no bits. */
- ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
- configASSERT( ulNotifiedValue == 0 );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
-
-
-
- /*-------------------------------------------------------------------------
- For each task notification within the array of task notifications in turn,
- check bits are cleared on entry but not on exit when a notification fails
- to arrive before timing out - both with and without a timeout value. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Wait for the notification - but this time it is not given by anything
- and should return pdFAIL. The parameters are set to clear bit zero on
- entry and bit one on exit. As no notification was received only the bit
- cleared on entry should actually get cleared. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* Send a notification with no action to the task notification at index
- uxIndexToTest within the array of task notifications. This should not
- update the bits even though notifyUINT32_MAX is used as the notification
- value. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX, eNoAction );
-
- /* All array indexes up to and including uxIndexToTest within the array
- of task notifications should have the modified value. */
- for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
- {
- /* Reading back the value should find bit 0 is clear, as this was cleared
- on entry, but bit 1 is not clear as it will not have been cleared on exit
- as no notification was received. */
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
- if( uxOtherIndexes == uxIndexToTest )
- {
- /* This is the index being used this time round the loop and its
- notification state was set immediately above. */
- configASSERT( xReturned == pdPASS );
- }
- else
- {
- /* Nothing should have set this index's notification state again. */
- configASSERT( xReturned == pdFAIL );
- }
-
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* All array indexes after uxIndexToTest should still contain notifyUINT32_MAX
- left over from the previous test. This time use xTaskNotifyValueClear()
- instead of xTaskNotifyWaitIndexed(), just for test coverage. */
- for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- /* This time 0 is the bits to clear parameter - so clearing no bits. */
- ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
- configASSERT( ulNotifiedValue == notifyUINT32_MAX );
- ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
-
-
-
-
- /*-------------------------------------------------------------------------
- Now try clearing the bit on exit. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* The task is notified first using the task notification at index
- uxIndexToTest within the array of task notifications. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, 0, eNoAction );
- xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, ulBit1, &ulNotifiedValue, 0 );
-
- /* However as the bit is cleared on exit, after the returned notification
- value is set, the returned notification value should not have the bit
- cleared... */
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
-
- /* ...but reading the value back again should find that the bit was indeed
- cleared internally. The returned value should be pdFAIL however as nothing
- has notified the task in the mean time. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, 0x00, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFAIL );
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* No other indexes should have a notification pending. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes != uxIndexToTest )
- {
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFAIL );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
- }
- }
-
-
-
- /*-------------------------------------------------------------------------
- For each task notification within the array of task notifications, try
- querying the previous value while notifying a task. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, 0x00, eSetBits, &ulPreviousValue );
- configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
-
- /* Clear all bits. */
- xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 );
- xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, 0x00, eSetBits, &ulPreviousValue );
- configASSERT( ulPreviousValue == 0 );
-
- ulExpectedValue = 0;
- for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL )
- {
- /* Set the next bit up, and expect to receive the last bits set (so
- the previous value will not yet have the bit being set this time
- around). */
- xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulLoop, eSetBits, &ulPreviousValue );
- configASSERT( ulExpectedValue == ulPreviousValue );
- ulExpectedValue |= ulLoop;
- }
- }
-
-
- /* ---------------------------------------------------------------------- */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Clear the previous notifications. */
- xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
- }
-
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* No task notification within the array of task notifications should
- have any notification pending, so an attempt to clear the notification
- state should fail. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdFALSE );
- }
-
- /* Get the task to notify itself using the task notification at index
- uxIndexToTest within the array of task notifications. This is not a
- normal thing to do, and is only done here for test purposes. */
- xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
-
- /* Now the notification state should be eNotified, so it should now be
- possible to clear the notification state. Other indexes should still
- not have a notification pending - likewise uxIndexToTest should not have
- a notification pending once it has been cleared. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- if( uxOtherIndexes == uxIndexToTest )
- {
- configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdTRUE );
- }
-
- configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdFALSE );
- }
- }
-
-
- /* ------------------------------------------------------------------------
- For each task notification within the array of task notifications, clear
- bits in the notification value. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Get the task to set all bits in its task notification at index
- uxIndexToTest within its array of task notifications. This is not a
- normal thing to do, and is only done here for test purposes. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX, eSetBits );
-
- /* Now clear the top bytes - the returned value from the first call
- should indicate that previously all bits were set. */
- configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_HIGH_BYTE ) == notifyUINT32_MAX );
-
- /* Next clear the bottom bytes - the returned value this time should
- indicate that the top byte was clear (before the bottom byte was
- cleared. */
- configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_LOW_BYTE ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE ) );
-
- /* Next clear all bytes - the returned value should indicate that previously the
- high and low bytes were clear. */
- configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE & ~notifyUINT32_LOW_BYTE ) );
-
- /* Now all bits should be clear. */
- configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == 0 );
- configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, 0UL ) == 0 );
- configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == 0 );
-
- /* Now the notification state should be eNotified, so it should now be
- possible to clear the notification state. */
- configASSERT( xTaskNotifyStateClearIndexed( NULL, uxIndexToTest ) == pdTRUE );
- configASSERT( xTaskNotifyStateClearIndexed( NULL, uxIndexToTest ) == pdFALSE );
- }
-
-
-
-
- /* Incremented to show the task is still running. */
- ulFineCycleCount++;
-
- /* Leave all bits cleared. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, NULL, 0 );
- }
+ const TickType_t xTicksToWait = pdMS_TO_TICKS( 100UL );
+ BaseType_t xReturned;
+ uint32_t ulNotifiedValue, ulLoop, ulNotifyingValue, ulPreviousValue, ulExpectedValue;
+ TickType_t xTimeOnEntering, xTimeNow, xTimeDifference;
+ const uint32_t ulFirstNotifiedConst = 100001UL, ulSecondNotifiedValueConst = 5555UL, ulMaxLoops = 5UL;
+ const uint32_t ulBit0 = 0x01UL, ulBit1 = 0x02UL;
+ UBaseType_t uxIndexToTest, uxOtherIndexes;
+
+
+ /* ------------------------------------------------------------------------
+ * Check blocking when there are no notifications. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Send notifications to the task notification in each index of the
+ * task notification array other than the one on which this task will
+ * block. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, 0, eNoAction );
+ }
+ }
+
+ xTimeOnEntering = xTaskGetTickCount();
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* Should have blocked for the entire block time. */
+ xTimeNow = xTaskGetTickCount();
+ xTimeDifference = xTimeNow - xTimeOnEntering;
+ configASSERT( xTimeDifference >= xTicksToWait );
+ configASSERT( xReturned == pdFAIL );
+ configASSERT( ulNotifiedValue == 0UL );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+ /* Clear all the other notifications within the array of task
+ * notifications again ready for the next round. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes );
+
+ /* The notification state was set above so expect it to still be
+ * set. */
+ configASSERT( xReturned == pdTRUE );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+ }
+
+ /* ------------------------------------------------------------------------
+ * Check no blocking when notifications are pending. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* First notify the task notification at index uxIndexToTest within this
+ * task's own array of task notifications - this would not be a normal
+ * thing to do and is done here for test purposes only. */
+ xReturned = xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+
+ /* Even through the 'without overwrite' action was used the update should
+ * have been successful. */
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* No bits should have been pending previously. */
+ configASSERT( ulPreviousValue == 0 );
+ ( void ) ulPreviousValue;
+
+ /* The task should now have a notification pending in the task
+ * notification at index uxIndexToTest within the task notification array,
+ * and so not time out. */
+ xTimeOnEntering = xTaskGetTickCount();
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, xTicksToWait );
+ xTimeNow = xTaskGetTickCount();
+ xTimeDifference = xTimeNow - xTimeOnEntering;
+ configASSERT( xTimeDifference < xTicksToWait );
+
+ /* The task should have been notified, and the notified value should
+ * be equal to ulFirstNotifiedConst. */
+ configASSERT( xReturned == pdPASS );
+ configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+ }
+
+ /*-------------------------------------------------------------------------
+ * Check the non-overwriting functionality. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Send notifications to all indexes with the array of task
+ * notifications other than the one on which this task will block. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, ulFirstNotifiedConst, eSetValueWithOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+
+ /* The notification is performed twice using two different notification
+ * values. The action says don't overwrite so only the first notification
+ * should pass and the value read back should also be that used with the
+ * first notification. The notification is sent to the task notification at
+ * index uxIndexToTest within the array of task notifications. */
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithoutOverwrite );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* Waiting for the notification should now return immediately so a block
+ * time of zero is used. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+
+ configASSERT( xReturned == pdPASS );
+ configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+ /* Clear all the other task notifications within the array of task
+ * notifications again ready for the next round. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes );
+ configASSERT( xReturned == pdTRUE );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ ulNotifiedValue = ulTaskNotifyValueClearIndexed( xTaskToNotify, uxOtherIndexes, notifyUINT32_MAX );
+
+ /* The notification value was set to ulFirstNotifiedConst in all
+ * the other indexes, so expect it to still have that value. */
+ configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+ }
+
+ /*-------------------------------------------------------------------------
+ * Do the same again, only this time use the overwriting version. This time
+ * both notifications should pass, and the value written the second time should
+ * overwrite the value written the first time, and so be the value that is read
+ * back. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xTaskNotifyIndexed( xTaskToNotify, uxOtherIndexes, ulFirstNotifiedConst, eSetValueWithOverwrite );
+ }
+ }
+
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, notifyUINT32_MAX, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+ ( void ) ulNotifiedValue;
+
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xReturned = xTaskNotifyStateClearIndexed( xTaskToNotify, uxOtherIndexes );
+ configASSERT( xReturned == pdTRUE );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ulNotifiedValue = ulTaskNotifyValueClearIndexed( xTaskToNotify, uxOtherIndexes, notifyUINT32_MAX );
+ configASSERT( ulNotifiedValue == ulFirstNotifiedConst );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+ }
+
+ /*-------------------------------------------------------------------------
+ * For each task notification within the array of task notifications, check
+ * notifications with no action pass without updating the value. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* First set the notification values of the task notification at index
+ * uxIndexToTest of the array of task notification to
+ * ulSecondNotifiedValueConst. */
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulSecondNotifiedValueConst, eSetValueWithOverwrite );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* Even though ulFirstNotifiedConst is used as the value next, the value
+ * read back should remain at ulSecondNotifiedConst as the action is set
+ * to eNoAction. */
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eNoAction );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* All task notifications in the array of task notifications up to and
+ * including index uxIndexToTest should still contain the same value. */
+ for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
+ {
+ /* First zero is bits to clear on entry, the second is bits to clear on
+ * exist, the last 0 is the block time. */
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* All array indexes in the array of task notifications after index
+ * uxIndexToTest should still contain 0 as they have not been set in this
+ * loop yet. This time use ulTaskNotifyValueClearIndexed() instead of
+ * xTaskNotifyWaitIndexed(), just for test coverage. */
+ for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ /* This time 0 is the bits to clear parameter - so clearing no bits. */
+ ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
+ configASSERT( ulNotifiedValue == 0 );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+
+ /*-------------------------------------------------------------------------
+ * Check incrementing values. For each task notification in the array of task
+ * notifications in turn, send ulMaxLoop increment notifications, then ensure
+ * the received value is as expected - which should be
+ * ulSecondNotificationValueConst plus how ever many times to loop iterated. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ for( ulLoop = 0; ulLoop < ulMaxLoops; ulLoop++ )
+ {
+ /* Increment the value of the task notification at index
+ * uxIndexToTest within the array of task notifications. */
+ xReturned = xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, 0, eIncrement );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* All array indexes up to and including uxIndexToTest should still
+ * contain the updated value. */
+ for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
+ {
+ /* First zero is bits to clear on entry, the second is bits to clear on
+ * exist, the last 0 is the block time. */
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( ulNotifiedValue == ( ulSecondNotifiedValueConst + ulMaxLoops ) );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* Should not be any notifications pending now. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+
+ /* All notifications values in the array of task notifications after
+ * index uxIndexToTest should still contain the un-incremented
+ * ulSecondNotifiedValueConst as they have not been set in this loop yet.
+ * This time use ulTaskNotifyValueClearIndexed() instead of xTaskNotifyWaitIndexed(),
+ * just for test coverage. */
+ for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ /* This time 0 is the bits to clear parameter - so clearing no bits. */
+ ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
+ configASSERT( ulNotifiedValue == ulSecondNotifiedValueConst );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+
+ /* Clear all bits ready for next test. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Start with all bits clear. */
+ ulTaskNotifyValueClearIndexed( NULL, uxIndexToTest, notifyUINT32_MAX );
+ }
+
+ /*-------------------------------------------------------------------------
+ * For each task notification in the array of task notifications in turn, check
+ * all bits in the notification's value can be set by notifying the task with
+ * one additional bit set on each notification, and exiting the loop when all
+ * the bits are found to be set. As there are 32-bits the loop should execute
+ * 32 times before all the bits are found to be set. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ ulNotifyingValue = 0x01;
+ ulLoop = 0;
+
+ do
+ {
+ /* Set the next bit in the value of the task notification at index
+ * uxIndexToTest within the array of task notifications. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, ulNotifyingValue, eSetBits );
+
+ /* Wait for the notified value - which of course will already be
+ * available. Don't clear the bits on entry or exit as this loop is
+ * exited when all the bits are set. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ ulLoop++;
+
+ /* Use the next bit on the next iteration around this loop. */
+ ulNotifyingValue <<= 1UL;
+ } while( ulNotifiedValue != notifyUINT32_MAX );
+
+ /* As a 32-bit value was used the loop should have executed 32 times before
+ * all the bits were set. */
+ configASSERT( ulLoop == 32 );
+
+ /* The value of each task notification within the array of task
+ * notifications up to and including index uxIndexToTest should still have
+ * all bits set. */
+ for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
+ {
+ /* First zero is bits to clear on entry, the second is bits to clear on
+ * exist, the last 0 is the block time. */
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( ulNotifiedValue == notifyUINT32_MAX );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* The value of each task notification within the array of task
+ * notifications after index uxIndexToTest should still contain 0 as they
+ * have not been set in this loop yet. This time use ulTaskNotifyValueClearIndexed()
+ * instead of xTaskNotifyWaitIndexed(), just for test coverage. */
+ for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ /* This time 0 is the bits to clear parameter - so clearing no bits. */
+ ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
+ configASSERT( ulNotifiedValue == 0 );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+
+ /*-------------------------------------------------------------------------
+ * For each task notification within the array of task notifications in turn,
+ * check bits are cleared on entry but not on exit when a notification fails
+ * to arrive before timing out - both with and without a timeout value. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Wait for the notification - but this time it is not given by anything
+ * and should return pdFAIL. The parameters are set to clear bit zero on
+ * entry and bit one on exit. As no notification was received only the bit
+ * cleared on entry should actually get cleared. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, ulBit0, ulBit1, &ulNotifiedValue, xTicksToWait );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* Send a notification with no action to the task notification at index
+ * uxIndexToTest within the array of task notifications. This should not
+ * update the bits even though notifyUINT32_MAX is used as the notification
+ * value. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX, eNoAction );
+
+ /* All array indexes up to and including uxIndexToTest within the array
+ * of task notifications should have the modified value. */
+ for( uxOtherIndexes = 0; uxOtherIndexes <= uxIndexToTest; uxOtherIndexes++ )
+ {
+ /* Reading back the value should find bit 0 is clear, as this was cleared
+ * on entry, but bit 1 is not clear as it will not have been cleared on exit
+ * as no notification was received. */
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
+
+ if( uxOtherIndexes == uxIndexToTest )
+ {
+ /* This is the index being used this time round the loop and its
+ * notification state was set immediately above. */
+ configASSERT( xReturned == pdPASS );
+ }
+ else
+ {
+ /* Nothing should have set this index's notification state again. */
+ configASSERT( xReturned == pdFAIL );
+ }
+
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* All array indexes after uxIndexToTest should still contain notifyUINT32_MAX
+ * left over from the previous test. This time use xTaskNotifyValueClear()
+ * instead of xTaskNotifyWaitIndexed(), just for test coverage. */
+ for( uxOtherIndexes = uxIndexToTest + 1; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ /* This time 0 is the bits to clear parameter - so clearing no bits. */
+ ulNotifiedValue = ulTaskNotifyValueClearIndexed( NULL, uxOtherIndexes, 0 );
+ configASSERT( ulNotifiedValue == notifyUINT32_MAX );
+ ( void ) ulNotifiedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+
+ /*-------------------------------------------------------------------------
+ * Now try clearing the bit on exit. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* The task is notified first using the task notification at index
+ * uxIndexToTest within the array of task notifications. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, 0, eNoAction );
+ xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, ulBit1, &ulNotifiedValue, 0 );
+
+ /* However as the bit is cleared on exit, after the returned notification
+ * value is set, the returned notification value should not have the bit
+ * cleared... */
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~ulBit0 ) );
+
+ /* ...but reading the value back again should find that the bit was indeed
+ * cleared internally. The returned value should be pdFAIL however as nothing
+ * has notified the task in the mean time. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, 0x00, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFAIL );
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* No other indexes should have a notification pending. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes != uxIndexToTest )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0x00UL, 0x00UL, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFAIL );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+ }
+ }
+
+ /*-------------------------------------------------------------------------
+ * For each task notification within the array of task notifications, try
+ * querying the previous value while notifying a task. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, 0x00, eSetBits, &ulPreviousValue );
+ configASSERT( ulNotifiedValue == ( notifyUINT32_MAX & ~( ulBit0 | ulBit1 ) ) );
+
+ /* Clear all bits. */
+ xTaskNotifyWaitIndexed( uxIndexToTest, 0x00, notifyUINT32_MAX, &ulNotifiedValue, 0 );
+ xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, 0x00, eSetBits, &ulPreviousValue );
+ configASSERT( ulPreviousValue == 0 );
+
+ ulExpectedValue = 0;
+
+ for( ulLoop = 0x01; ulLoop < 0x80UL; ulLoop <<= 1UL )
+ {
+ /* Set the next bit up, and expect to receive the last bits set (so
+ * the previous value will not yet have the bit being set this time
+ * around). */
+ xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulLoop, eSetBits, &ulPreviousValue );
+ configASSERT( ulExpectedValue == ulPreviousValue );
+ ulExpectedValue |= ulLoop;
+ }
+ }
+
+ /* ---------------------------------------------------------------------- */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Clear the previous notifications. */
+ xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, &ulNotifiedValue, 0 );
+ }
+
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* No task notification within the array of task notifications should
+ * have any notification pending, so an attempt to clear the notification
+ * state should fail. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdFALSE );
+ }
+
+ /* Get the task to notify itself using the task notification at index
+ * uxIndexToTest within the array of task notifications. This is not a
+ * normal thing to do, and is only done here for test purposes. */
+ xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToTest, ulFirstNotifiedConst, eSetValueWithoutOverwrite, &ulPreviousValue );
+
+ /* Now the notification state should be eNotified, so it should now be
+ * possible to clear the notification state. Other indexes should still
+ * not have a notification pending - likewise uxIndexToTest should not have
+ * a notification pending once it has been cleared. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ if( uxOtherIndexes == uxIndexToTest )
+ {
+ configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdTRUE );
+ }
+
+ configASSERT( xTaskNotifyStateClearIndexed( NULL, uxOtherIndexes ) == pdFALSE );
+ }
+ }
+
+ /* ------------------------------------------------------------------------
+ * For each task notification within the array of task notifications, clear
+ * bits in the notification value. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Get the task to set all bits in its task notification at index
+ * uxIndexToTest within its array of task notifications. This is not a
+ * normal thing to do, and is only done here for test purposes. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX, eSetBits );
+
+ /* Now clear the top bytes - the returned value from the first call
+ * should indicate that previously all bits were set. */
+ configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_HIGH_BYTE ) == notifyUINT32_MAX );
+
+ /* Next clear the bottom bytes - the returned value this time should
+ * indicate that the top byte was clear (before the bottom byte was
+ * cleared. */
+ configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_LOW_BYTE ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE ) );
+
+ /* Next clear all bytes - the returned value should indicate that previously the
+ * high and low bytes were clear. */
+ configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == ( notifyUINT32_MAX & ~notifyUINT32_HIGH_BYTE & ~notifyUINT32_LOW_BYTE ) );
+
+ /* Now all bits should be clear. */
+ configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == 0 );
+ configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, 0UL ) == 0 );
+ configASSERT( ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToTest, notifyUINT32_MAX ) == 0 );
+
+ /* Now the notification state should be eNotified, so it should now be
+ * possible to clear the notification state. */
+ configASSERT( xTaskNotifyStateClearIndexed( NULL, uxIndexToTest ) == pdTRUE );
+ configASSERT( xTaskNotifyStateClearIndexed( NULL, uxIndexToTest ) == pdFALSE );
+ }
+
+ /* Incremented to show the task is still running. */
+ ulFineCycleCount++;
+
+ /* Leave all bits cleared. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, NULL, 0 );
+ }
}
/*-----------------------------------------------------------*/
static void prvSuspendedTaskTimerTestCallback( TimerHandle_t xExpiredTimer )
{
-static uint32_t ulCallCount = 0;
-static UBaseType_t uxIndexToNotify = 0;
-
- /* Remove compiler warnings about unused parameters. */
- ( void ) xExpiredTimer;
-
- /* Callback for a timer that is used to send notifications to a task while
- it is suspended. The timer tests the behaviour when 1: a task waiting for a
- notification is suspended and then resumed without ever receiving a
- notification, and 2: when a task waiting for a notification receives a
- notification while it is suspended. Run one of two tests on every other
- invocation of this callback. The notification is sent to the task
- notification at index uxIndexToNotify. */
- if( ( ulCallCount & 0x01 ) == 0 )
- {
- vTaskSuspend( xTaskToNotify );
- configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
- vTaskResume( xTaskToNotify );
- }
- else
- {
- vTaskSuspend( xTaskToNotify );
-
- /* Sending a notification while the task is suspended should pass, but
- not cause the task to resume. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, 1, eSetValueWithOverwrite );
-
- /* Use the next task notification within the array of task notifications
- the next time around. */
- uxIndexToNotify++;
- if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES )
- {
- uxIndexToNotify = 0;
- }
-
- /* Make sure giving the notification didn't resume the task. */
- configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
-
- vTaskResume( xTaskToNotify );
- }
-
- ulCallCount++;
+ static uint32_t ulCallCount = 0;
+ static UBaseType_t uxIndexToNotify = 0;
+
+ /* Remove compiler warnings about unused parameters. */
+ ( void ) xExpiredTimer;
+
+ /* Callback for a timer that is used to send notifications to a task while
+ * it is suspended. The timer tests the behaviour when 1: a task waiting for a
+ * notification is suspended and then resumed without ever receiving a
+ * notification, and 2: when a task waiting for a notification receives a
+ * notification while it is suspended. Run one of two tests on every other
+ * invocation of this callback. The notification is sent to the task
+ * notification at index uxIndexToNotify. */
+ if( ( ulCallCount & 0x01 ) == 0 )
+ {
+ vTaskSuspend( xTaskToNotify );
+ configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
+ vTaskResume( xTaskToNotify );
+ }
+ else
+ {
+ vTaskSuspend( xTaskToNotify );
+
+ /* Sending a notification while the task is suspended should pass, but
+ * not cause the task to resume. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, 1, eSetValueWithOverwrite );
+
+ /* Use the next task notification within the array of task notifications
+ * the next time around. */
+ uxIndexToNotify++;
+
+ if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES )
+ {
+ uxIndexToNotify = 0;
+ }
+
+ /* Make sure giving the notification didn't resume the task. */
+ configASSERT( eTaskGetState( xTaskToNotify ) == eSuspended );
+
+ vTaskResume( xTaskToNotify );
+ }
+
+ ulCallCount++;
}
/*-----------------------------------------------------------*/
static void prvNotifyingTimerCallback( TimerHandle_t xNotUsed )
{
-static BaseType_t uxIndexToNotify = 0;
-
- ( void ) xNotUsed;
-
- /* "Give" the task notification (which increments the target task
- notification value) at index uxIndexToNotify within the array of task
- notifications. */
- xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify );
-
- /* Use the next task notification within the array of task notifications the
- next time around. */
- uxIndexToNotify++;
- if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES )
- {
- uxIndexToNotify = 0;
- }
+ static BaseType_t uxIndexToNotify = 0;
+
+ ( void ) xNotUsed;
+
+ /* "Give" the task notification (which increments the target task
+ * notification value) at index uxIndexToNotify within the array of task
+ * notifications. */
+ xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify );
+
+ /* Use the next task notification within the array of task notifications the
+ * next time around. */
+ uxIndexToNotify++;
+
+ if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES )
+ {
+ uxIndexToNotify = 0;
+ }
}
/*-----------------------------------------------------------*/
static void prvTestNotifyTaskWhileSuspended( void )
{
-UBaseType_t uxIndexToTest, uxOtherIndexes;
-BaseType_t xReturned;
-uint32_t ulNotifiedValue;
-
- /* Raise the task's priority so it can suspend itself before the timer
- expires. */
- vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
-
- /* Perform the test on each task notification within the array or task
- notifications. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- /* Ensure no notifications within the array of task notifications are
- pending. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, NULL, 0 );
- configASSERT( xReturned == pdFALSE );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* Start the timer that will try notifying this task while it is
- suspended, then wait for a notification. The first time the callback
- executes the timer will suspend the task, then resume the task, without
- ever sending a notification to the task. */
- ulNotifiedValue = 0;
- xTimerStart( xNotifyWhileSuspendedTimer, portMAX_DELAY );
-
- /* Check a notification is not received on the task notification at
- index uxIndexToTest within the array of task notifications. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, portMAX_DELAY );
- configASSERT( xReturned == pdFALSE );
- configASSERT( ulNotifiedValue == 0 );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* Check none of the task notifications within the array of task
- notifications as been notified. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFALSE );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- }
-
- /* Start the timer that will try notifying this task while it is
- suspended, then wait for a notification at index uxIndexToTest within
- the array of task notifications. The second time the callback executes
- the timer will suspend the task, notify the task, then resume the task
- (previously it was suspended and resumed without being notified). */
- xTimerStart( xNotifyWhileSuspendedTimer, portMAX_DELAY );
-
- /* Check a notification is only received in the index within the array
- of task notifications under test. */
- xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, portMAX_DELAY );
- configASSERT( xReturned == pdPASS );
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- configASSERT( ulNotifiedValue != 0 );
-
- /* Check a notification is not received in any index within the array
- of task notifications at and below the index being tested have a notification
- value, and that indexes above the index being tested to not have
- notification values. */
- for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
- {
- xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
- configASSERT( xReturned == pdFALSE );
-
- if( uxOtherIndexes <= uxIndexToTest )
- {
- configASSERT( ulNotifiedValue == 1 );
- }
- else
- {
- configASSERT( ulNotifiedValue == 0 );
- }
- ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) ulNotifiedValue;
- }
- }
-
- /* Return the task to its proper priority */
- vTaskPrioritySet( NULL, notifyTASK_PRIORITY );
-
- /* Incremented to show the task is still running. */
- ulFineCycleCount++;
-
- /* Leave all bits cleared. */
- for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
- {
- xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, NULL, 0 );
- }
+ UBaseType_t uxIndexToTest, uxOtherIndexes;
+ BaseType_t xReturned;
+ uint32_t ulNotifiedValue;
+
+ /* Raise the task's priority so it can suspend itself before the timer
+ * expires. */
+ vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+
+ /* Perform the test on each task notification within the array or task
+ * notifications. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ /* Ensure no notifications within the array of task notifications are
+ * pending. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, NULL, 0 );
+ configASSERT( xReturned == pdFALSE );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* Start the timer that will try notifying this task while it is
+ * suspended, then wait for a notification. The first time the callback
+ * executes the timer will suspend the task, then resume the task, without
+ * ever sending a notification to the task. */
+ ulNotifiedValue = 0;
+ xTimerStart( xNotifyWhileSuspendedTimer, portMAX_DELAY );
+
+ /* Check a notification is not received on the task notification at
+ * index uxIndexToTest within the array of task notifications. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, portMAX_DELAY );
+ configASSERT( xReturned == pdFALSE );
+ configASSERT( ulNotifiedValue == 0 );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* Check none of the task notifications within the array of task
+ * notifications as been notified. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFALSE );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ }
+
+ /* Start the timer that will try notifying this task while it is
+ * suspended, then wait for a notification at index uxIndexToTest within
+ * the array of task notifications. The second time the callback executes
+ * the timer will suspend the task, notify the task, then resume the task
+ * (previously it was suspended and resumed without being notified). */
+ xTimerStart( xNotifyWhileSuspendedTimer, portMAX_DELAY );
+
+ /* Check a notification is only received in the index within the array
+ * of task notifications under test. */
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToTest, 0, 0, &ulNotifiedValue, portMAX_DELAY );
+ configASSERT( xReturned == pdPASS );
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ configASSERT( ulNotifiedValue != 0 );
+
+ /* Check a notification is not received in any index within the array
+ * of task notifications at and below the index being tested have a notification
+ * value, and that indexes above the index being tested to not have
+ * notification values. */
+ for( uxOtherIndexes = 0; uxOtherIndexes < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxOtherIndexes++ )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxOtherIndexes, 0, 0, &ulNotifiedValue, 0 );
+ configASSERT( xReturned == pdFALSE );
+
+ if( uxOtherIndexes <= uxIndexToTest )
+ {
+ configASSERT( ulNotifiedValue == 1 );
+ }
+ else
+ {
+ configASSERT( ulNotifiedValue == 0 );
+ }
+
+ ( void ) xReturned; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) ulNotifiedValue;
+ }
+ }
+
+ /* Return the task to its proper priority */
+ vTaskPrioritySet( NULL, notifyTASK_PRIORITY );
+
+ /* Incremented to show the task is still running. */
+ ulFineCycleCount++;
+
+ /* Leave all bits cleared. */
+ for( uxIndexToTest = 0; uxIndexToTest < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToTest++ )
+ {
+ xTaskNotifyWaitIndexed( uxIndexToTest, notifyUINT32_MAX, 0, NULL, 0 );
+ }
}
/* ------------------------------------------------------------------------ */
static void prvBlockOnTheNotifiedIndexed( void )
{
-const TickType_t xTimerPeriod = pdMS_TO_TICKS( 100 ), xMargin = pdMS_TO_TICKS( 50 ), xDontBlock = 0;
-UBaseType_t uxIndex, uxIndexToNotify;
-uint32_t ulReceivedValue;
-BaseType_t xReturned;
-
- /* Set the value of each notification in the array of task notifications to
- the value of its index position plus 1 so everything starts in a known
- state, then clear the notification state ready for the next test. Plus 1 is
- used because the index under test will use 0. */
- for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
- {
- xTaskNotifyIndexed( xTaskToNotify, uxIndex, uxIndex + 1, eSetValueWithOverwrite );
- xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndex );
- }
-
- /* Peform the test on each task notification within the array of task
- notifications. */
- for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
- {
- /* Set the notification value of the index being tested to 0 so the
- notification value increment/decrement functions can be tested. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, 0, eSetValueWithOverwrite );
- xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndexToNotify );
-
- /* Start the software timer then wait for it to notify this task. Block
- on the notification index we expect to receive the notification on. The
- margin is to ensure the task blocks longer than the timer period. */
- xTimerStart( xIncrementingIndexTimer, portMAX_DELAY );
- ulReceivedValue = ulTaskNotifyTakeIndexed( uxIndexToNotify, pdFALSE, xTimerPeriod + xMargin );
-
- /* The notification value was initially zero, and should have been
- incremented by the software timer, so now one. It will also have been
- decremented again by the call to ulTaskNotifyTakeIndexed() so gone back
- to 0. */
- configASSERT( ulReceivedValue == 1UL );
- ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* No other notification indexes should have changed, and therefore should
- still have their value set to their index plus 1 within the array of
- notifications. */
- for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
- {
- if( uxIndex != uxIndexToNotify )
- {
- xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xDontBlock );
- configASSERT( xReturned == pdFALSE );
- configASSERT( ulReceivedValue == ( uxIndex + 1 ) );
- ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) xReturned;
- }
- }
-
- /* Reset the notification value for the index just tested back to the
- index value plus 1 ready for the next iteration around this loop. */
- xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, uxIndexToNotify + 1, eSetValueWithOverwrite );
- xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndexToNotify );
-
- /* Incremented to show the task is still running. */
- ulFineCycleCount++;
- }
+ const TickType_t xTimerPeriod = pdMS_TO_TICKS( 100 ), xMargin = pdMS_TO_TICKS( 50 ), xDontBlock = 0;
+ UBaseType_t uxIndex, uxIndexToNotify;
+ uint32_t ulReceivedValue;
+ BaseType_t xReturned;
+
+ /* Set the value of each notification in the array of task notifications to
+ * the value of its index position plus 1 so everything starts in a known
+ * state, then clear the notification state ready for the next test. Plus 1 is
+ * used because the index under test will use 0. */
+ for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
+ {
+ xTaskNotifyIndexed( xTaskToNotify, uxIndex, uxIndex + 1, eSetValueWithOverwrite );
+ xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndex );
+ }
+
+ /* Peform the test on each task notification within the array of task
+ * notifications. */
+ for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
+ {
+ /* Set the notification value of the index being tested to 0 so the
+ * notification value increment/decrement functions can be tested. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, 0, eSetValueWithOverwrite );
+ xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndexToNotify );
+
+ /* Start the software timer then wait for it to notify this task. Block
+ * on the notification index we expect to receive the notification on. The
+ * margin is to ensure the task blocks longer than the timer period. */
+ xTimerStart( xIncrementingIndexTimer, portMAX_DELAY );
+ ulReceivedValue = ulTaskNotifyTakeIndexed( uxIndexToNotify, pdFALSE, xTimerPeriod + xMargin );
+
+ /* The notification value was initially zero, and should have been
+ * incremented by the software timer, so now one. It will also have been
+ * decremented again by the call to ulTaskNotifyTakeIndexed() so gone back
+ * to 0. */
+ configASSERT( ulReceivedValue == 1UL );
+ ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* No other notification indexes should have changed, and therefore should
+ * still have their value set to their index plus 1 within the array of
+ * notifications. */
+ for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
+ {
+ if( uxIndex != uxIndexToNotify )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xDontBlock );
+ configASSERT( xReturned == pdFALSE );
+ configASSERT( ulReceivedValue == ( uxIndex + 1 ) );
+ ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) xReturned;
+ }
+ }
+
+ /* Reset the notification value for the index just tested back to the
+ * index value plus 1 ready for the next iteration around this loop. */
+ xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, uxIndexToNotify + 1, eSetValueWithOverwrite );
+ xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndexToNotify );
+
+ /* Incremented to show the task is still running. */
+ ulFineCycleCount++;
+ }
}
/* ------------------------------------------------------------------------ */
static void prvBlockOnANonNotifiedIndexed( void )
{
-const TickType_t xTimerPeriod = pdMS_TO_TICKS( 100 ), xMargin = pdMS_TO_TICKS( 50 ), xDontBlock = 0;
-UBaseType_t uxIndex, uxIndexToNotify;
-uint32_t ulReceivedValue;
-BaseType_t xReturned;
-TickType_t xTimeBeforeBlocking, xTimeNow, xTimeDifference;
-
- /* Set all notify values within the array of tasks notifications to zero
- ready for the next test. */
- for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
- {
- ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToNotify, notifyUINT32_MAX );
- }
-
- /* Perform the test for each notification within the array of task
- notifications. */
- for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
- {
- /* Start the software timer then wait for it to notify this task. Block
- on a notification index that we do not expect to receive the notification
- on. The margin is to ensure the task blocks longer than the timer period. */
- xTimerStart( xIncrementingIndexTimer, portMAX_DELAY );
- xTimeBeforeBlocking = xTaskGetTickCount();
-
-
- if( uxIndexToNotify == ( configTASK_NOTIFICATION_ARRAY_ENTRIES - 1 ) )
- {
- /* configTASK_NOTIFICATION_ARRAY_ENTRIES - 1 is to be notified, so
- block on index 0. */
- uxIndex = 0;
- }
- else
- {
- /* The next index to get notified will be uxIndexToNotify, so block
- on uxIndexToNotify + 1 */
- uxIndex = uxIndexToNotify + 1;
- }
-
- xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xTimerPeriod + xMargin );
-
- /* The notification will have been sent to task notification at index
- uxIndexToNotify in this task by the timer callback after xTimerPeriodTicks.
- The notification should not have woken this task, so xReturned should
- be false and at least xTimerPeriod + xMargin ticks should have passed. */
- configASSERT( xReturned == pdFALSE );
- xTimeNow = xTaskGetTickCount();
- xTimeDifference = xTimeNow - xTimeBeforeBlocking;
- configASSERT( xTimeDifference >= ( xTimerPeriod + xMargin ) );
- ( void ) xReturned; /* Remove compiler warnings if configASSERT() is not defined. */
- ( void ) xTimeBeforeBlocking;
- ( void ) xTimeDifference;
-
- /* Only the notification at index position uxIndexToNotify should be
- set. Calling this function will clear it again. */
- for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
- {
- xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xDontBlock );
-
- if( uxIndex == uxIndexToNotify )
- {
- /* Expect the notification state to be set and the notification
- value to have been incremented. */
- configASSERT( xReturned == pdTRUE );
- configASSERT( ulReceivedValue == 1 );
-
- /* Set the notification value for this array index back to 0. */
- ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndex, notifyUINT32_MAX );
- }
- else
- {
- /* Expect the notification state to be clear and the notification
- value to remain at zer0. */
- configASSERT( xReturned == pdFALSE );
- configASSERT( ulReceivedValue == 0 );
- }
- }
-
- /* Incremented to show the task is still running. */
- ulFineCycleCount++;
- }
+ const TickType_t xTimerPeriod = pdMS_TO_TICKS( 100 ), xMargin = pdMS_TO_TICKS( 50 ), xDontBlock = 0;
+ UBaseType_t uxIndex, uxIndexToNotify;
+ uint32_t ulReceivedValue;
+ BaseType_t xReturned;
+ TickType_t xTimeBeforeBlocking, xTimeNow, xTimeDifference;
+
+ /* Set all notify values within the array of tasks notifications to zero
+ * ready for the next test. */
+ for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
+ {
+ ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndexToNotify, notifyUINT32_MAX );
+ }
+
+ /* Perform the test for each notification within the array of task
+ * notifications. */
+ for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
+ {
+ /* Start the software timer then wait for it to notify this task. Block
+ * on a notification index that we do not expect to receive the notification
+ * on. The margin is to ensure the task blocks longer than the timer period. */
+ xTimerStart( xIncrementingIndexTimer, portMAX_DELAY );
+ xTimeBeforeBlocking = xTaskGetTickCount();
+
+ if( uxIndexToNotify == ( configTASK_NOTIFICATION_ARRAY_ENTRIES - 1 ) )
+ {
+ /* configTASK_NOTIFICATION_ARRAY_ENTRIES - 1 is to be notified, so
+ * block on index 0. */
+ uxIndex = 0;
+ }
+ else
+ {
+ /* The next index to get notified will be uxIndexToNotify, so block
+ * on uxIndexToNotify + 1 */
+ uxIndex = uxIndexToNotify + 1;
+ }
+
+ xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xTimerPeriod + xMargin );
+
+ /* The notification will have been sent to task notification at index
+ * uxIndexToNotify in this task by the timer callback after xTimerPeriodTicks.
+ * The notification should not have woken this task, so xReturned should
+ * be false and at least xTimerPeriod + xMargin ticks should have passed. */
+ configASSERT( xReturned == pdFALSE );
+ xTimeNow = xTaskGetTickCount();
+ xTimeDifference = xTimeNow - xTimeBeforeBlocking;
+ configASSERT( xTimeDifference >= ( xTimerPeriod + xMargin ) );
+ ( void ) xReturned; /* Remove compiler warnings if configASSERT() is not defined. */
+ ( void ) xTimeBeforeBlocking;
+ ( void ) xTimeDifference;
+
+ /* Only the notification at index position uxIndexToNotify should be
+ * set. Calling this function will clear it again. */
+ for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxIndex, 0, 0, &ulReceivedValue, xDontBlock );
+
+ if( uxIndex == uxIndexToNotify )
+ {
+ /* Expect the notification state to be set and the notification
+ * value to have been incremented. */
+ configASSERT( xReturned == pdTRUE );
+ configASSERT( ulReceivedValue == 1 );
+
+ /* Set the notification value for this array index back to 0. */
+ ulTaskNotifyValueClearIndexed( xTaskToNotify, uxIndex, notifyUINT32_MAX );
+ }
+ else
+ {
+ /* Expect the notification state to be clear and the notification
+ * value to remain at zer0. */
+ configASSERT( xReturned == pdFALSE );
+ configASSERT( ulReceivedValue == 0 );
+ }
+ }
+
+ /* Incremented to show the task is still running. */
+ ulFineCycleCount++;
+ }
}
/* ------------------------------------------------------------------------ */
static void prvBlockOnNotificationsComingFromInterrupts( void )
{
-UBaseType_t uxIndex, uxIndexToNotify;
-uint32_t ulReceivedValue;
-BaseType_t xReturned;
-const TickType_t xDontBlock = 0;
-
- /* Set the value of each notification within the array of task notifications
- to zero so the task can block on xTaskNotifyTake(). */
- for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
- {
- xTaskNotifyIndexed( xTaskToNotify, uxIndex, 0, eSetValueWithOverwrite );
- xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndex );
- }
-
- /* Perform the test on each task notification within the array of task
- notifications. */
- for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
- {
- /* Tell the interrupt to send the next notification. */
- taskENTER_CRITICAL();
- {
- /* Don't expect to find xSendNotificationFromISR set at this time as
- the interrupt should have cleared it back to pdFALSE last time it
- executed. */
- configASSERT( xSendNotificationFromISR == pdFALSE );
- xSendNotificationFromISR = pdTRUE;
- }
- taskEXIT_CRITICAL();
-
- /* Wait for a notification on the task notification at index
- uxIndexToNotify within the array of task notifications. */
- ulReceivedValue = ulTaskNotifyTakeIndexed( uxIndexToNotify, pdTRUE, portMAX_DELAY );
-
- /* Interrupt should have reset xSendNotificationFromISR after it sent
- the notificatino. */
- configASSERT( xSendNotificationFromISR == pdFALSE );
-
- /* The notification value was initially zero, and should have been
- incremented by the interrupt, so now one. */
- configASSERT( ulReceivedValue == 1UL );
- ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
-
- /* No other notification indexes should have changed, and therefore should
- still have their value set to 0. The value in array index uxIndexToNotify
- should also have been decremented back to zero by the call to
- ulTaskNotifyTakeIndexed(). */
- for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
- {
- xReturned = xTaskNotifyWaitIndexed( uxIndexToNotify, 0, 0, &ulReceivedValue, xDontBlock );
- configASSERT( xReturned == pdFALSE );
- configASSERT( ulReceivedValue == 0 );
- ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) xReturned;
- }
-
- /* Incremented to show the task is still running. */
- ulFineCycleCount++;
- }
+ UBaseType_t uxIndex, uxIndexToNotify;
+ uint32_t ulReceivedValue;
+ BaseType_t xReturned;
+ const TickType_t xDontBlock = 0;
+
+ /* Set the value of each notification within the array of task notifications
+ * to zero so the task can block on xTaskNotifyTake(). */
+ for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
+ {
+ xTaskNotifyIndexed( xTaskToNotify, uxIndex, 0, eSetValueWithOverwrite );
+ xTaskNotifyStateClearIndexed( xTaskToNotify, uxIndex );
+ }
+
+ /* Perform the test on each task notification within the array of task
+ * notifications. */
+ for( uxIndexToNotify = 0; uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndexToNotify++ )
+ {
+ /* Tell the interrupt to send the next notification. */
+ taskENTER_CRITICAL();
+ {
+ /* Don't expect to find xSendNotificationFromISR set at this time as
+ * the interrupt should have cleared it back to pdFALSE last time it
+ * executed. */
+ configASSERT( xSendNotificationFromISR == pdFALSE );
+ xSendNotificationFromISR = pdTRUE;
+ }
+ taskEXIT_CRITICAL();
+
+ /* Wait for a notification on the task notification at index
+ * uxIndexToNotify within the array of task notifications. */
+ ulReceivedValue = ulTaskNotifyTakeIndexed( uxIndexToNotify, pdTRUE, portMAX_DELAY );
+
+ /* Interrupt should have reset xSendNotificationFromISR after it sent
+ * the notification. */
+ configASSERT( xSendNotificationFromISR == pdFALSE );
+
+ /* The notification value was initially zero, and should have been
+ * incremented by the interrupt, so now one. */
+ configASSERT( ulReceivedValue == 1UL );
+ ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+
+ /* No other notification indexes should have changed, and therefore should
+ * still have their value set to 0. The value in array index uxIndexToNotify
+ * should also have been decremented back to zero by the call to
+ * ulTaskNotifyTakeIndexed(). */
+ for( uxIndex = 0; uxIndex < configTASK_NOTIFICATION_ARRAY_ENTRIES; uxIndex++ )
+ {
+ xReturned = xTaskNotifyWaitIndexed( uxIndexToNotify, 0, 0, &ulReceivedValue, xDontBlock );
+ configASSERT( xReturned == pdFALSE );
+ configASSERT( ulReceivedValue == 0 );
+ ( void ) ulReceivedValue; /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) xReturned;
+ }
+
+ /* Incremented to show the task is still running. */
+ ulFineCycleCount++;
+ }
}
/*-----------------------------------------------------------*/
void xNotifyArrayTaskFromISR( void )
{
-static BaseType_t xAPIToUse = 0;
-uint32_t ulPreviousValue;
-const uint32_t ulUnexpectedValue = 0xff;
-static UBaseType_t uxIndexToNotify = 0;
-
- /* Check the task notification demo task was actually created. */
- configASSERT( xTaskToNotify );
-
- /* The task sets xSendNotificationFromISR to pdTRUE each time it wants this
- interrupt (this function runs in the RTOS tick hook) to send the next
- notification. */
- if( xSendNotificationFromISR == pdTRUE )
- {
- xSendNotificationFromISR = pdFALSE;
-
- /* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR()
- and xTaskNotifyAndQueryFromISR(). The notification is set to the task
- notification at index uxIndexToNotify within the array of task
- notifications. */
- switch( xAPIToUse )
- {
- case 0: vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, NULL );
- xAPIToUse++;
- break;
-
- case 1: xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, 0, eIncrement, NULL );
- xAPIToUse++;
- break;
-
- case 2: ulPreviousValue = ulUnexpectedValue;
- xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, 0, eIncrement, &ulPreviousValue, NULL );
- configASSERT( ulPreviousValue == 0 );
- xAPIToUse = 0;
- break;
-
- default:/* Should never get here!. */
- break;
- }
-
- /* Use the next index in the array of task notifications the next time
- around. */
- uxIndexToNotify++;
- if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES )
- {
- uxIndexToNotify = 0;
- }
- }
+ static BaseType_t xAPIToUse = 0;
+ uint32_t ulPreviousValue;
+ const uint32_t ulUnexpectedValue = 0xff;
+ static UBaseType_t uxIndexToNotify = 0;
+
+ /* Check the task notification demo task was actually created. */
+ configASSERT( xTaskToNotify );
+
+ /* The task sets xSendNotificationFromISR to pdTRUE each time it wants this
+ * interrupt (this function runs in the RTOS tick hook) to send the next
+ * notification. */
+ if( xSendNotificationFromISR == pdTRUE )
+ {
+ xSendNotificationFromISR = pdFALSE;
+
+ /* Test using both vTaskNotifyGiveFromISR(), xTaskNotifyFromISR()
+ * and xTaskNotifyAndQueryFromISR(). The notification is set to the task
+ * notification at index uxIndexToNotify within the array of task
+ * notifications. */
+ switch( xAPIToUse )
+ {
+ case 0:
+ vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, NULL );
+ xAPIToUse++;
+ break;
+
+ case 1:
+ xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, 0, eIncrement, NULL );
+ xAPIToUse++;
+ break;
+
+ case 2:
+ ulPreviousValue = ulUnexpectedValue;
+ xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, 0, eIncrement, &ulPreviousValue, NULL );
+ configASSERT( ulPreviousValue == 0 );
+ xAPIToUse = 0;
+ break;
+
+ default: /* Should never get here!. */
+ break;
+ }
+
+ /* Use the next index in the array of task notifications the next time
+ * around. */
+ uxIndexToNotify++;
+
+ if( uxIndexToNotify >= configTASK_NOTIFICATION_ARRAY_ENTRIES )
+ {
+ uxIndexToNotify = 0;
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check the created tasks are still running and have not
-detected any errors. */
+ * detected any errors. */
BaseType_t xAreTaskNotificationArrayTasksStillRunning( void )
{
-static uint32_t ulLastFineCycleCount = 0, ulLastCourseCycleCount = 0, ulCallCount = 0;
-const uint32_t ulCallsBetweenCourseCycleCountChecks = 3UL;
-static BaseType_t xErrorStatus = pdPASS;
-
- /* Check the cycle count is still incrementing to ensure the task is still
- actually running. The fine counter is incremented within individual test
- functions. The course counter is incremented one each time all the test
- functions have been executed to ensure all the tests are running. */
- if( ulLastFineCycleCount == ulFineCycleCount )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastFineCycleCount = ulFineCycleCount;
- }
-
- ulCallCount++;
- if( ulCallCount >= ulCallsBetweenCourseCycleCountChecks )
- {
- ulCallCount = 0;
- if( ulLastCourseCycleCount == ulCourseCycleCounter )
- {
- xErrorStatus = pdFAIL;
- }
- else
- {
- ulLastCourseCycleCount = ulCourseCycleCounter;
- }
- }
-
- return xErrorStatus;
+ static uint32_t ulLastFineCycleCount = 0, ulLastCourseCycleCount = 0, ulCallCount = 0;
+ const uint32_t ulCallsBetweenCourseCycleCountChecks = 3UL;
+ static BaseType_t xErrorStatus = pdPASS;
+
+ /* Check the cycle count is still incrementing to ensure the task is still
+ * actually running. The fine counter is incremented within individual test
+ * functions. The course counter is incremented one each time all the test
+ * functions have been executed to ensure all the tests are running. */
+ if( ulLastFineCycleCount == ulFineCycleCount )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastFineCycleCount = ulFineCycleCount;
+ }
+
+ ulCallCount++;
+
+ if( ulCallCount >= ulCallsBetweenCourseCycleCountChecks )
+ {
+ ulCallCount = 0;
+
+ if( ulLastCourseCycleCount == ulCourseCycleCounter )
+ {
+ xErrorStatus = pdFAIL;
+ }
+ else
+ {
+ ulLastCourseCycleCount = ulCourseCycleCounter;
+ }
+ }
+
+ return xErrorStatus;
}
/*-----------------------------------------------------------*/
static UBaseType_t prvRand( void )
{
-const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1;
+ const size_t uxMultiplier = ( size_t ) 0x015a4e35, uxIncrement = ( size_t ) 1;
- /* Utility function to generate a pseudo random number. */
- uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement;
- return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) );
+ /* Utility function to generate a pseudo random number. */
+ uxNextRand = ( uxMultiplier * uxNextRand ) + uxIncrement;
+ return( ( uxNextRand >> 16 ) & ( ( size_t ) 0x7fff ) );
}
/*-----------------------------------------------------------*/
diff --git a/Demo/Common/Minimal/TimerDemo.c b/Demo/Common/Minimal/TimerDemo.c
index 3f364de02..66b5acfad 100644
--- a/Demo/Common/Minimal/TimerDemo.c
+++ b/Demo/Common/Minimal/TimerDemo.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
@@ -43,976 +42,1062 @@
#include "TimerDemo.h"
#if ( configTIMER_TASK_PRIORITY < 1 )
- #error configTIMER_TASK_PRIORITY must be set to at least 1 for this test/demo to function correctly.
+ #error configTIMER_TASK_PRIORITY must be set to at least 1 for this test/demo to function correctly.
#endif
-#define tmrdemoDONT_BLOCK ( ( TickType_t ) 0 )
-#define tmrdemoONE_SHOT_TIMER_PERIOD ( xBasePeriod * ( TickType_t ) 3 )
-#define tmrdemoNUM_TIMER_RESETS ( ( uint8_t ) 10 )
+#define tmrdemoDONT_BLOCK ( ( TickType_t ) 0 )
+#define tmrdemoONE_SHOT_TIMER_PERIOD ( xBasePeriod * ( TickType_t ) 3 )
+#define tmrdemoNUM_TIMER_RESETS ( ( uint8_t ) 10 )
#ifndef tmrTIMER_TEST_TASK_STACK_SIZE
- #define tmrTIMER_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define tmrTIMER_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
/*-----------------------------------------------------------*/
/* The callback functions used by the timers. These each increment a counter
-to indicate which timer has expired. The auto-reload timers that are used by
-the test task (as opposed to being used from an ISR) all share the same
-prvAutoReloadTimerCallback() callback function, and use the ID of the
-pxExpiredTimer parameter passed into that function to know which counter to
-increment. The other timers all have their own unique callback function and
-simply increment their counters without using the callback function parameter. */
+ * to indicate which timer has expired. The auto-reload timers that are used by
+ * the test task (as opposed to being used from an ISR) all share the same
+ * prvAutoReloadTimerCallback() callback function, and use the ID of the
+ * pxExpiredTimer parameter passed into that function to know which counter to
+ * increment. The other timers all have their own unique callback function and
+ * simply increment their counters without using the callback function parameter. */
static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer );
static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer );
-static void prvTimerTestTask( void *pvParameters );
+static void prvTimerTestTask( void * pvParameters );
static void prvISRAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer );
static void prvISROneShotTimerCallback( TimerHandle_t pxExpiredTimer );
/* The test functions used by the timer test task. These manipulate the auto
-reload and one-shot timers in various ways, then delay, then inspect the timers
-to ensure they have behaved as expected. */
+ * reload and one-shot timers in various ways, then delay, then inspect the timers
+ * to ensure they have behaved as expected. */
static void prvTest1_CreateTimersWithoutSchedulerRunning( void );
static void prvTest2_CheckTaskAndTimersInitialState( void );
-static void prvTest3_CheckAutoReloadExpireRates( void );
+static void prvTest3_CheckAutoReloadExpireRates( void );
static void prvTest4_CheckAutoReloadTimersCanBeStopped( void );
static void prvTest5_CheckBasicOneShotTimerBehaviour( void );
static void prvTest6_CheckAutoReloadResetBehaviour( void );
+static void prvTest7_CheckBacklogBehaviour( void );
static void prvResetStartConditionsForNextIteration( void );
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdFAIL should any unexpected behaviour be
-detected in any of the demo tests. */
+ * detected in any of the demo tests. */
static volatile BaseType_t xTestStatus = pdPASS;
+/* Flag indicating whether the testing includes the backlog demo. The backlog
+ * demo can be disruptive to other demos because the timer backlog is created by
+ * calling xTaskCatchUpTicks(). */
+static uint8_t ucIsBacklogDemoEnabled = ( uint8_t ) pdFALSE;
+
/* Counter that is incremented on each cycle of a test. This is used to
-detect a stalled task - a test that is no longer running. */
+ * detect a stalled task - a test that is no longer running. */
static volatile uint32_t ulLoopCounter = 0;
/* A set of auto-reload timers - each of which use the same callback function.
-The callback function uses the timer ID to index into, and then increment, a
-counter in the ucAutoReloadTimerCounters[] array. The auto-reload timers
-referenced from xAutoReloadTimers[] are used by the prvTimerTestTask task. */
+ * The callback function uses the timer ID to index into, and then increment, a
+ * counter in the ucAutoReloadTimerCounters[] array. The callback function stops
+ * xAutoReloadTimers[0] during its callback if ucIsStopNeededInTimerZeroCallback is
+ * pdTRUE. The auto-reload timers referenced from xAutoReloadTimers[] are used by
+ * the prvTimerTestTask task. */
static TimerHandle_t xAutoReloadTimers[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 };
static uint8_t ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH + 1 ] = { 0 };
+static uint8_t ucIsStopNeededInTimerZeroCallback = ( uint8_t ) pdFALSE;
/* The one-shot timer is configured to use a callback function that increments
-ucOneShotTimerCounter each time it gets called. */
+ * ucOneShotTimerCounter each time it gets called. */
static TimerHandle_t xOneShotTimer = NULL;
static uint8_t ucOneShotTimerCounter = ( uint8_t ) 0;
/* The ISR reload timer is controlled from the tick hook to exercise the timer
-API functions that can be used from an ISR. It is configured to increment
-ucISRReloadTimerCounter each time its callback function is executed. */
+ * API functions that can be used from an ISR. It is configured to increment
+ * ucISRReloadTimerCounter each time its callback function is executed. */
static TimerHandle_t xISRAutoReloadTimer = NULL;
static uint8_t ucISRAutoReloadTimerCounter = ( uint8_t ) 0;
/* The ISR one-shot timer is controlled from the tick hook to exercise the timer
-API functions that can be used from an ISR. It is configured to increment
-ucISRReloadTimerCounter each time its callback function is executed. */
+ * API functions that can be used from an ISR. It is configured to increment
+ * ucISRReloadTimerCounter each time its callback function is executed. */
static TimerHandle_t xISROneShotTimer = NULL;
static uint8_t ucISROneShotTimerCounter = ( uint8_t ) 0;
/* The period of all the timers are a multiple of the base period. The base
-period is configured by the parameter to vStartTimerDemoTask(). */
+ * period is configured by the parameter to vStartTimerDemoTask(). */
static TickType_t xBasePeriod = 0;
/*-----------------------------------------------------------*/
void vStartTimerDemoTask( TickType_t xBasePeriodIn )
{
- /* Start with the timer and counter arrays clear - this is only necessary
- where the compiler does not clear them automatically on start up. */
- memset( ucAutoReloadTimerCounters, 0x00, sizeof( ucAutoReloadTimerCounters ) );
- memset( xAutoReloadTimers, 0x00, sizeof( xAutoReloadTimers ) );
-
- /* Store the period from which all the timer periods will be generated from
- (multiples of). */
- xBasePeriod = xBasePeriodIn;
-
- /* Create a set of timers for use by this demo/test. */
- prvTest1_CreateTimersWithoutSchedulerRunning();
-
- /* Create the task that will control and monitor the timers. This is
- created at a lower priority than the timer service task to ensure, as
- far as it is concerned, commands on timers are actioned immediately
- (sending a command to the timer service task will unblock the timer service
- task, which will then preempt this task). */
- if( xTestStatus != pdFAIL )
- {
- xTaskCreate( prvTimerTestTask, "Tmr Tst", tmrTIMER_TEST_TASK_STACK_SIZE, NULL, configTIMER_TASK_PRIORITY - 1, NULL );
- }
+ /* Start with the timer and counter arrays clear - this is only necessary
+ * where the compiler does not clear them automatically on start up. */
+ memset( ucAutoReloadTimerCounters, 0x00, sizeof( ucAutoReloadTimerCounters ) );
+ memset( xAutoReloadTimers, 0x00, sizeof( xAutoReloadTimers ) );
+
+ /* Store the period from which all the timer periods will be generated from
+ * (multiples of). */
+ xBasePeriod = xBasePeriodIn;
+
+ /* Create a set of timers for use by this demo/test. */
+ prvTest1_CreateTimersWithoutSchedulerRunning();
+
+ /* Create the task that will control and monitor the timers. This is
+ * created at a lower priority than the timer service task to ensure, as
+ * far as it is concerned, commands on timers are acted on immediately
+ * (sending a command to the timer service task will unblock the timer service
+ * task, which will then preempt this task). */
+ if( xTestStatus != pdFAIL )
+ {
+ xTaskCreate( prvTimerTestTask, "Tmr Tst", tmrTIMER_TEST_TASK_STACK_SIZE, NULL, configTIMER_TASK_PRIORITY - 1, NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvTimerTestTask( void *pvParameters )
+void vTimerDemoIncludeBacklogTests( BaseType_t includeBacklogTests )
{
- ( void ) pvParameters;
-
- /* Create a one-shot timer for use later on in this test. For test purposes it
- is created as an auto-reload timer then converted to a one-shot timer. */
- xOneShotTimer = xTimerCreate( "Oneshot Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */
- tmrdemoONE_SHOT_TIMER_PERIOD, /* The period for the timer. */
- pdFALSE, /* Autorealod is false, so created as a one-shot timer. */
- ( void * ) 0, /* The timer identifier. Initialise to 0, then increment each time it is called. */
- prvOneShotTimerCallback ); /* The callback to be called when the timer expires. */
-
- if( xOneShotTimer == NULL )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Purely for test coverage purposes - change and query the reload mode to
- auto-reload then back to one-shot. */
-
- /* Change timer to auto-reload. */
- vTimerSetReloadMode( xOneShotTimer, pdTRUE );
-
- /* Timer should now be auto-reload. */
- configASSERT( uxTimerGetReloadMode( xOneShotTimer ) == pdTRUE );
-
- /* Change timer to one-shot, which is what is needed for this test. */
- vTimerSetReloadMode( xOneShotTimer, pdFALSE );
-
- /* Check change to one-shot was successful. */
- configASSERT( uxTimerGetReloadMode( xOneShotTimer ) == pdFALSE );
-
- /* Ensure all the timers are in their expected initial state. This
- depends on the timer service task having a higher priority than this task. */
- prvTest2_CheckTaskAndTimersInitialState();
-
- for( ;; )
- {
- /* Check the auto-reload timers expire at the expected/correct rates. */
- prvTest3_CheckAutoReloadExpireRates();
-
- /* Check the auto-reload timers can be stopped correctly, and correctly
- report their state. */
- prvTest4_CheckAutoReloadTimersCanBeStopped();
-
- /* Check the one-shot timer only calls its callback once after it has been
- started, and that it reports its state correctly. */
- prvTest5_CheckBasicOneShotTimerBehaviour();
-
- /* Check timer reset behaviour. */
- prvTest6_CheckAutoReloadResetBehaviour();
+ ucIsBacklogDemoEnabled = ( uint8_t ) includeBacklogTests;
+}
+/*-----------------------------------------------------------*/
- /* Start the timers again to restart all the tests over again. */
- prvResetStartConditionsForNextIteration();
- }
+static void prvTimerTestTask( void * pvParameters )
+{
+ ( void ) pvParameters;
+
+ /* Create a one-shot timer for use later on in this test. For test purposes it
+ * is created as an auto-reload timer then converted to a one-shot timer. */
+ xOneShotTimer = xTimerCreate( "Oneshot Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */
+ tmrdemoONE_SHOT_TIMER_PERIOD, /* The period for the timer. */
+ pdFALSE, /* Autoreload is false, so created as a one-shot timer. */
+ ( void * ) 0, /* The timer identifier. Initialise to 0, then increment each time it is called. */
+ prvOneShotTimerCallback ); /* The callback to be called when the timer expires. */
+
+ if( xOneShotTimer == NULL )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Purely for test coverage purposes - change and query the reload mode to
+ * auto-reload then back to one-shot. */
+
+ /* Change timer to auto-reload. */
+ vTimerSetReloadMode( xOneShotTimer, pdTRUE );
+
+ /* Timer should now be auto-reload. */
+ configASSERT( uxTimerGetReloadMode( xOneShotTimer ) == pdTRUE );
+
+ /* Change timer to one-shot, which is what is needed for this test. */
+ vTimerSetReloadMode( xOneShotTimer, pdFALSE );
+
+ /* Check change to one-shot was successful. */
+ configASSERT( uxTimerGetReloadMode( xOneShotTimer ) == pdFALSE );
+
+ /* Ensure all the timers are in their expected initial state. This
+ * depends on the timer service task having a higher priority than this task. */
+ prvTest2_CheckTaskAndTimersInitialState();
+
+ for( ; ; )
+ {
+ /* Check the auto-reload timers expire at the expected/correct rates. */
+ prvTest3_CheckAutoReloadExpireRates();
+
+ /* Check the auto-reload timers can be stopped correctly, and correctly
+ * report their state. */
+ prvTest4_CheckAutoReloadTimersCanBeStopped();
+
+ /* Check the one-shot timer only calls its callback once after it has been
+ * started, and that it reports its state correctly. */
+ prvTest5_CheckBasicOneShotTimerBehaviour();
+
+ /* Check timer reset behaviour. */
+ prvTest6_CheckAutoReloadResetBehaviour();
+
+ /* Check timer behaviour when the timer task gets behind in its work. */
+ if( ucIsBacklogDemoEnabled == ( uint8_t ) pdTRUE )
+ {
+ prvTest7_CheckBacklogBehaviour();
+ }
+
+ /* Start the timers again to restart all the tests over again. */
+ prvResetStartConditionsForNextIteration();
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that the created task is still running and has not
-detected any errors. */
+ * detected any errors. */
BaseType_t xAreTimerDemoTasksStillRunning( TickType_t xCycleFrequency )
{
-static uint32_t ulLastLoopCounter = 0UL;
-TickType_t xMaxBlockTimeUsedByTheseTests, xLoopCounterIncrementTimeMax;
-static TickType_t xIterationsWithoutCounterIncrement = ( TickType_t ) 0, xLastCycleFrequency;
-
- if( xLastCycleFrequency != xCycleFrequency )
- {
- /* The cycle frequency has probably become much faster due to an error
- elsewhere. Start counting Iterations again. */
- xIterationsWithoutCounterIncrement = ( TickType_t ) 0;
- xLastCycleFrequency = xCycleFrequency;
- }
-
- /* Calculate the maximum number of times that it is permissible for this
- function to be called without ulLoopCounter being incremented. This is
- necessary because the tests in this file block for extended periods, and the
- block period might be longer than the time between calls to this function. */
- xMaxBlockTimeUsedByTheseTests = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;
- xLoopCounterIncrementTimeMax = ( xMaxBlockTimeUsedByTheseTests / xCycleFrequency ) + 1;
-
- /* If the demo task is still running then the loop counter is expected to
- have incremented every xLoopCounterIncrementTimeMax calls. */
- if( ulLastLoopCounter == ulLoopCounter )
- {
- xIterationsWithoutCounterIncrement++;
- if( xIterationsWithoutCounterIncrement > xLoopCounterIncrementTimeMax )
- {
- /* The tests appear to be no longer running (stalled). */
- xTestStatus = pdFAIL;
- }
- }
- else
- {
- /* ulLoopCounter changed, so the count of times this function was called
- without a change can be reset to zero. */
- xIterationsWithoutCounterIncrement = ( TickType_t ) 0;
- }
-
- ulLastLoopCounter = ulLoopCounter;
-
- /* Errors detected in the task itself will have latched xTestStatus
- to pdFAIL. */
-
- return xTestStatus;
+ static uint32_t ulLastLoopCounter = 0UL;
+ TickType_t xMaxBlockTimeUsedByTheseTests, xLoopCounterIncrementTimeMax;
+ static TickType_t xIterationsWithoutCounterIncrement = ( TickType_t ) 0, xLastCycleFrequency;
+
+ if( xLastCycleFrequency != xCycleFrequency )
+ {
+ /* The cycle frequency has probably become much faster due to an error
+ * elsewhere. Start counting Iterations again. */
+ xIterationsWithoutCounterIncrement = ( TickType_t ) 0;
+ xLastCycleFrequency = xCycleFrequency;
+ }
+
+ /* Calculate the maximum number of times that it is permissible for this
+ * function to be called without ulLoopCounter being incremented. This is
+ * necessary because the tests in this file block for extended periods, and the
+ * block period might be longer than the time between calls to this function. */
+ xMaxBlockTimeUsedByTheseTests = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;
+ xLoopCounterIncrementTimeMax = ( xMaxBlockTimeUsedByTheseTests / xCycleFrequency ) + 1;
+
+ /* If the demo task is still running then the loop counter is expected to
+ * have incremented every xLoopCounterIncrementTimeMax calls. */
+ if( ulLastLoopCounter == ulLoopCounter )
+ {
+ xIterationsWithoutCounterIncrement++;
+
+ if( xIterationsWithoutCounterIncrement > xLoopCounterIncrementTimeMax )
+ {
+ /* The tests appear to be no longer running (stalled). */
+ xTestStatus = pdFAIL;
+ }
+ }
+ else
+ {
+ /* ulLoopCounter changed, so the count of times this function was called
+ * without a change can be reset to zero. */
+ xIterationsWithoutCounterIncrement = ( TickType_t ) 0;
+ }
+
+ ulLastLoopCounter = ulLoopCounter;
+
+ /* Errors detected in the task itself will have latched xTestStatus
+ * to pdFAIL. */
+
+ return xTestStatus;
}
/*-----------------------------------------------------------*/
static void prvTest1_CreateTimersWithoutSchedulerRunning( void )
{
-TickType_t xTimer;
-
- for( xTimer = 0; xTimer < configTIMER_QUEUE_LENGTH; xTimer++ )
- {
- /* As the timer queue is not yet full, it should be possible to both
- create and start a timer. These timers are being started before the
- scheduler has been started, so their block times should get set to zero
- within the timer API itself. */
- xAutoReloadTimers[ xTimer ] = xTimerCreate( "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */
- ( ( xTimer + ( TickType_t ) 1 ) * xBasePeriod ),/* The period for the timer. The plus 1 ensures a period of zero is not specified. */
- pdTRUE, /* Auto-reload is set to true. */
- ( void * ) xTimer, /* An identifier for the timer as all the auto-reload timers use the same callback. */
- prvAutoReloadTimerCallback ); /* The callback to be called when the timer expires. */
-
- if( xAutoReloadTimers[ xTimer ] == NULL )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- else
- {
- configASSERT( strcmp( pcTimerGetName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
-
- /* The scheduler has not yet started, so the block period of
- portMAX_DELAY should just get set to zero in xTimerStart(). Also,
- the timer queue is not yet full so xTimerStart() should return
- pdPASS. */
- if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) != pdPASS )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- }
-
- /* The timers queue should now be full, so it should be possible to create
- another timer, but not possible to start it (the timer queue will not get
- drained until the scheduler has been started. */
- xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] = xTimerCreate( "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */
- ( configTIMER_QUEUE_LENGTH * xBasePeriod ), /* The period for the timer. */
- pdTRUE, /* Auto-reload is set to true. */
- ( void * ) xTimer, /* An identifier for the timer as all the auto-reload timers use the same callback. */
- prvAutoReloadTimerCallback ); /* The callback executed when the timer expires. */
-
- if( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] == NULL )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- else
- {
- if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) == pdPASS )
- {
- /* This time it would not be expected that the timer could be
- started at this point. */
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
-
- /* Create the timers that are used from the tick interrupt to test the timer
- API functions that can be called from an ISR. */
- xISRAutoReloadTimer = xTimerCreate( "ISR AR", /* The text name given to the timer. */
- 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */
- pdTRUE, /* This is an auto-reload timer. */
- ( void * ) NULL, /* The identifier is not required. */
- prvISRAutoReloadTimerCallback ); /* The callback that is executed when the timer expires. */
-
- xISROneShotTimer = xTimerCreate( "ISR OS", /* The text name given to the timer. */
- 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */
- pdFALSE, /* This is a one-shot timer. */
- ( void * ) NULL, /* The identifier is not required. */
- prvISROneShotTimerCallback ); /* The callback that is executed when the timer expires. */
-
- if( ( xISRAutoReloadTimer == NULL ) || ( xISROneShotTimer == NULL ) )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
+ TickType_t xTimer;
+
+ for( xTimer = 0; xTimer < configTIMER_QUEUE_LENGTH; xTimer++ )
+ {
+ /* As the timer queue is not yet full, it should be possible to both
+ * create and start a timer. These timers are being started before the
+ * scheduler has been started, so their block times should get set to zero
+ * within the timer API itself. */
+ xAutoReloadTimers[ xTimer ] = xTimerCreate( "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */
+ ( ( xTimer + ( TickType_t ) 1 ) * xBasePeriod ), /* The period for the timer. The plus 1 ensures a period of zero is not specified. */
+ pdTRUE, /* Auto-reload is set to true. */
+ ( void * ) xTimer, /* An identifier for the timer as all the auto-reload timers use the same callback. */
+ prvAutoReloadTimerCallback ); /* The callback to be called when the timer expires. */
+
+ if( xAutoReloadTimers[ xTimer ] == NULL )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ else
+ {
+ configASSERT( strcmp( pcTimerGetName( xAutoReloadTimers[ xTimer ] ), "FR Timer" ) == 0 );
+
+ /* The scheduler has not yet started, so the block period of
+ * portMAX_DELAY should just get set to zero in xTimerStart(). Also,
+ * the timer queue is not yet full so xTimerStart() should return
+ * pdPASS. */
+ if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) != pdPASS )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ }
+
+ /* The timers queue should now be full, so it should be possible to create
+ * another timer, but not possible to start it (the timer queue will not get
+ * drained until the scheduler has been started. */
+ xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] = xTimerCreate( "FR Timer", /* Text name to facilitate debugging. The kernel does not use this itself. */
+ ( configTIMER_QUEUE_LENGTH * xBasePeriod ), /* The period for the timer. */
+ pdTRUE, /* Auto-reload is set to true. */
+ ( void * ) xTimer, /* An identifier for the timer as all the auto-reload timers use the same callback. */
+ prvAutoReloadTimerCallback ); /* The callback executed when the timer expires. */
+
+ if( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] == NULL )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ else
+ {
+ if( xTimerStart( xAutoReloadTimers[ xTimer ], portMAX_DELAY ) == pdPASS )
+ {
+ /* This time it would not be expected that the timer could be
+ * started at this point. */
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+
+ /* Create the timers that are used from the tick interrupt to test the timer
+ * API functions that can be called from an ISR. */
+ xISRAutoReloadTimer = xTimerCreate( "ISR AR", /* The text name given to the timer. */
+ 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */
+ pdTRUE, /* This is an auto-reload timer. */
+ ( void * ) NULL, /* The identifier is not required. */
+ prvISRAutoReloadTimerCallback ); /* The callback that is executed when the timer expires. */
+
+ xISROneShotTimer = xTimerCreate( "ISR OS", /* The text name given to the timer. */
+ 0xffff, /* The timer is not given a period yet - this will be done from the tick hook, but a period of 0 is invalid. */
+ pdFALSE, /* This is a one-shot timer. */
+ ( void * ) NULL, /* The identifier is not required. */
+ prvISROneShotTimerCallback ); /* The callback that is executed when the timer expires. */
+
+ if( ( xISRAutoReloadTimer == NULL ) || ( xISROneShotTimer == NULL ) )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
}
/*-----------------------------------------------------------*/
static void prvTest2_CheckTaskAndTimersInitialState( void )
{
-uint8_t ucTimer;
-
- /* Ensure all the timers are in their expected initial state. This depends
- on the timer service task having a higher priority than this task.
-
- auto-reload timers 0 to ( configTIMER_QUEUE_LENGTH - 1 ) should now be active,
- and auto-reload timer configTIMER_QUEUE_LENGTH should not yet be active (it
- could not be started prior to the scheduler being started when it was
- created). */
- for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
- {
- if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
-
- if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] ) != pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
+ uint8_t ucTimer;
+
+ /* Ensure all the timers are in their expected initial state. This depends
+ * on the timer service task having a higher priority than this task.
+ *
+ * auto-reload timers 0 to ( configTIMER_QUEUE_LENGTH - 1 ) should now be active,
+ * and auto-reload timer configTIMER_QUEUE_LENGTH should not yet be active (it
+ * could not be started prior to the scheduler being started when it was
+ * created). */
+ for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+ {
+ if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+
+ if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH ] ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
}
/*-----------------------------------------------------------*/
-static void prvTest3_CheckAutoReloadExpireRates( void )
+static void prvTest3_CheckAutoReloadExpireRates( void )
{
-uint8_t ucMaxAllowableValue, ucMinAllowableValue, ucTimer;
-TickType_t xBlockPeriod, xTimerPeriod, xExpectedNumber;
-UBaseType_t uxOriginalPriority;
-
- /* Check the auto-reload timers expire at the expected rates. Do this at a
- high priority for maximum accuracy. This is ok as most of the time is spent
- in the Blocked state. */
- uxOriginalPriority = uxTaskPriorityGet( NULL );
- vTaskPrioritySet( NULL, ( configMAX_PRIORITIES - 1 ) );
-
- /* Delaying for configTIMER_QUEUE_LENGTH * xBasePeriod ticks should allow
- all the auto-reload timers to expire at least once. */
- xBlockPeriod = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;
- vTaskDelay( xBlockPeriod );
-
- /* Check that all the auto-reload timers have called their callback
- function the expected number of times. */
- for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
- {
- /* The expected number of expiries is equal to the block period divided
- by the timer period. */
- xTimerPeriod = ( ( ( TickType_t ) ucTimer + ( TickType_t ) 1 ) * xBasePeriod );
- xExpectedNumber = xBlockPeriod / xTimerPeriod;
-
- ucMaxAllowableValue = ( ( uint8_t ) xExpectedNumber ) ;
- ucMinAllowableValue = ( uint8_t ) ( ( uint8_t ) xExpectedNumber - ( uint8_t ) 1 ); /* Weird casting to try and please all compilers. */
-
- if( ( ucAutoReloadTimerCounters[ ucTimer ] < ucMinAllowableValue ) ||
- ( ucAutoReloadTimerCounters[ ucTimer ] > ucMaxAllowableValue )
- )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
-
- /* Return to the original priority. */
- vTaskPrioritySet( NULL, uxOriginalPriority );
-
- if( xTestStatus == pdPASS )
- {
- /* No errors have been reported so increment the loop counter so the
- check task knows this task is still running. */
- ulLoopCounter++;
- }
+ uint8_t ucMaxAllowableValue, ucMinAllowableValue, ucTimer;
+ TickType_t xBlockPeriod, xTimerPeriod, xExpectedNumber;
+ UBaseType_t uxOriginalPriority;
+
+ /* Check the auto-reload timers expire at the expected rates. Do this at a
+ * high priority for maximum accuracy. This is ok as most of the time is spent
+ * in the Blocked state. */
+ uxOriginalPriority = uxTaskPriorityGet( NULL );
+ vTaskPrioritySet( NULL, ( configMAX_PRIORITIES - 1 ) );
+
+ /* Delaying for configTIMER_QUEUE_LENGTH * xBasePeriod ticks should allow
+ * all the auto-reload timers to expire at least once. */
+ xBlockPeriod = ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod;
+ vTaskDelay( xBlockPeriod );
+
+ /* Check that all the auto-reload timers have called their callback
+ * function the expected number of times. */
+ for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+ {
+ /* The expected number of expires is equal to the block period divided
+ * by the timer period. */
+ xTimerPeriod = ( ( ( TickType_t ) ucTimer + ( TickType_t ) 1 ) * xBasePeriod );
+ xExpectedNumber = xBlockPeriod / xTimerPeriod;
+
+ ucMaxAllowableValue = ( ( uint8_t ) xExpectedNumber );
+ ucMinAllowableValue = ( uint8_t ) ( ( uint8_t ) xExpectedNumber - ( uint8_t ) 1 ); /* Weird casting to try and please all compilers. */
+
+ if( ( ucAutoReloadTimerCounters[ ucTimer ] < ucMinAllowableValue ) ||
+ ( ucAutoReloadTimerCounters[ ucTimer ] > ucMaxAllowableValue )
+ )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+
+ /* Return to the original priority. */
+ vTaskPrioritySet( NULL, uxOriginalPriority );
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so the
+ * check task knows this task is still running. */
+ ulLoopCounter++;
+ }
}
/*-----------------------------------------------------------*/
static void prvTest4_CheckAutoReloadTimersCanBeStopped( void )
{
-uint8_t ucTimer;
-
- /* Check the auto-reload timers can be stopped correctly, and correctly
- report their state. */
-
- /* Stop all the active timers. */
- for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
- {
- /* The timer has not been stopped yet! */
- if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Now stop the timer. This will appear to happen immediately to
- this task because this task is running at a priority below the
- timer service task. */
- xTimerStop( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK );
-
- /* The timer should now be inactive. */
- if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
-
- taskENTER_CRITICAL();
- {
- /* The timer in array position configTIMER_QUEUE_LENGTH should not
- be active. The critical section is used to ensure the timer does
- not call its callback between the next line running and the array
- being cleared back to zero, as that would mask an error condition. */
- if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH ] != ( uint8_t ) 0 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Clear the timer callback count. */
- memset( ( void * ) ucAutoReloadTimerCounters, 0, sizeof( ucAutoReloadTimerCounters ) );
- }
- taskEXIT_CRITICAL();
-
- /* The timers are now all inactive, so this time, after delaying, none
- of the callback counters should have incremented. */
- vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod );
- for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
- {
- if( ucAutoReloadTimerCounters[ ucTimer ] != ( uint8_t ) 0 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
-
- if( xTestStatus == pdPASS )
- {
- /* No errors have been reported so increment the loop counter so
- the check task knows this task is still running. */
- ulLoopCounter++;
- }
+ uint8_t ucTimer;
+
+ /* Check the auto-reload timers can be stopped correctly, and correctly
+ * report their state. */
+
+ /* Stop all the active timers. */
+ for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+ {
+ /* The timer has not been stopped yet! */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Now stop the timer. This will appear to happen immediately to
+ * this task because this task is running at a priority below the
+ * timer service task. */
+ xTimerStop( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK );
+
+ /* The timer should now be inactive. */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+
+ taskENTER_CRITICAL();
+ {
+ /* The timer in array position configTIMER_QUEUE_LENGTH should not
+ * be active. The critical section is used to ensure the timer does
+ * not call its callback between the next line running and the array
+ * being cleared back to zero, as that would mask an error condition. */
+ if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH ] != ( uint8_t ) 0 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Clear the timer callback count. */
+ memset( ( void * ) ucAutoReloadTimerCounters, 0, sizeof( ucAutoReloadTimerCounters ) );
+ }
+ taskEXIT_CRITICAL();
+
+ /* The timers are now all inactive, so this time, after delaying, none
+ * of the callback counters should have incremented. */
+ vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod );
+
+ for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+ {
+ if( ucAutoReloadTimerCounters[ ucTimer ] != ( uint8_t ) 0 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so
+ * the check task knows this task is still running. */
+ ulLoopCounter++;
+ }
}
/*-----------------------------------------------------------*/
static void prvTest5_CheckBasicOneShotTimerBehaviour( void )
{
- /* Check the one-shot timer only calls its callback once after it has been
- started, and that it reports its state correctly. */
-
- /* The one-shot timer should not be active yet. */
- if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucOneShotTimerCounter != ( uint8_t ) 0 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Start the one-shot timer and check that it reports its state correctly. */
- xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK );
- if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Delay for three times as long as the one-shot timer period, then check
- to ensure it has only called its callback once, and is now not in the
- active state. */
- vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD * ( TickType_t ) 3 );
-
- if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucOneShotTimerCounter != ( uint8_t ) 1 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- else
- {
- /* Reset the one-shot timer callback count. */
- ucOneShotTimerCounter = ( uint8_t ) 0;
- }
-
- if( xTestStatus == pdPASS )
- {
- /* No errors have been reported so increment the loop counter so the
- check task knows this task is still running. */
- ulLoopCounter++;
- }
+ /* Check the one-shot timer only calls its callback once after it has been
+ * started, and that it reports its state correctly. */
+
+ /* The one-shot timer should not be active yet. */
+ if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucOneShotTimerCounter != ( uint8_t ) 0 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Start the one-shot timer and check that it reports its state correctly. */
+ xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK );
+
+ if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Delay for three times as long as the one-shot timer period, then check
+ * to ensure it has only called its callback once, and is now not in the
+ * active state. */
+ vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD * ( TickType_t ) 3 );
+
+ if( xTimerIsTimerActive( xOneShotTimer ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucOneShotTimerCounter != ( uint8_t ) 1 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ else
+ {
+ /* Reset the one-shot timer callback count. */
+ ucOneShotTimerCounter = ( uint8_t ) 0;
+ }
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so the
+ * check task knows this task is still running. */
+ ulLoopCounter++;
+ }
}
/*-----------------------------------------------------------*/
static void prvTest6_CheckAutoReloadResetBehaviour( void )
{
-uint8_t ucTimer;
-
- /* Check timer reset behaviour. */
-
- /* Restart the one-shot timer and check it reports its status correctly. */
- xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK );
- if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Restart one of the auto-reload timers and check that it reports its
- status correctly. */
- xTimerStart( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
- if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- for( ucTimer = 0; ucTimer < tmrdemoNUM_TIMER_RESETS; ucTimer++ )
- {
- /* Delay for half as long as the one-shot timer period, then reset it.
- It should never expire while this is done, so its callback count should
- never increment. */
- vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD / 2 );
-
- /* Check both running timers are still active, but have not called their
- callback functions. */
- if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucOneShotTimerCounter != ( uint8_t ) 0 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] != ( uint8_t ) 0 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Reset both running timers. */
- xTimerReset( xOneShotTimer, tmrdemoDONT_BLOCK );
- xTimerReset( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
-
- if( xTestStatus == pdPASS )
- {
- /* No errors have been reported so increment the loop counter so
- the check task knows this task is still running. */
- ulLoopCounter++;
- }
- }
-
- /* Finally delay long enough for both running timers to expire. */
- vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod );
-
- /* The timers were not reset during the above delay period so should now
- both have called their callback functions. */
- if( ucOneShotTimerCounter != ( uint8_t ) 1 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] == 0 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* The one-shot timer should no longer be active, while the auto-reload
- timer should still be active. */
- if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( xTimerIsTimerActive( xOneShotTimer ) == pdTRUE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Stop the auto-reload timer again. */
- xTimerStop( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
-
- if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) != pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Clear the timer callback counts, ready for another iteration of these
- tests. */
- ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] = ( uint8_t ) 0;
- ucOneShotTimerCounter = ( uint8_t ) 0;
-
- if( xTestStatus == pdPASS )
- {
- /* No errors have been reported so increment the loop counter so the check
- task knows this task is still running. */
- ulLoopCounter++;
- }
+ uint8_t ucTimer;
+
+ /* Check timer reset behaviour. */
+
+ /* Restart the one-shot timer and check it reports its status correctly. */
+ xTimerStart( xOneShotTimer, tmrdemoDONT_BLOCK );
+
+ if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Restart one of the auto-reload timers and check that it reports its
+ * status correctly. */
+ xTimerStart( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
+
+ if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ for( ucTimer = 0; ucTimer < tmrdemoNUM_TIMER_RESETS; ucTimer++ )
+ {
+ /* Delay for half as long as the one-shot timer period, then reset it.
+ * It should never expire while this is done, so its callback count should
+ * never increment. */
+ vTaskDelay( tmrdemoONE_SHOT_TIMER_PERIOD / 2 );
+
+ /* Check both running timers are still active, but have not called their
+ * callback functions. */
+ if( xTimerIsTimerActive( xOneShotTimer ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucOneShotTimerCounter != ( uint8_t ) 0 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] != ( uint8_t ) 0 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Reset both running timers. */
+ xTimerReset( xOneShotTimer, tmrdemoDONT_BLOCK );
+ xTimerReset( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so
+ * the check task knows this task is still running. */
+ ulLoopCounter++;
+ }
+ }
+
+ /* Finally delay long enough for both running timers to expire. */
+ vTaskDelay( ( ( TickType_t ) configTIMER_QUEUE_LENGTH ) * xBasePeriod );
+
+ /* The timers were not reset during the above delay period so should now
+ * both have called their callback functions. */
+ if( ucOneShotTimerCounter != ( uint8_t ) 1 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] == 0 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* The one-shot timer should no longer be active, while the auto-reload
+ * timer should still be active. */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( xTimerIsTimerActive( xOneShotTimer ) == pdTRUE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Stop the auto-reload timer again. */
+ xTimerStop( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ], tmrdemoDONT_BLOCK );
+
+ if( xTimerIsTimerActive( xAutoReloadTimers[ configTIMER_QUEUE_LENGTH - 1 ] ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Clear the timer callback counts, ready for another iteration of these
+ * tests. */
+ ucAutoReloadTimerCounters[ configTIMER_QUEUE_LENGTH - 1 ] = ( uint8_t ) 0;
+ ucOneShotTimerCounter = ( uint8_t ) 0;
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so the check
+ * task knows this task is still running. */
+ ulLoopCounter++;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvTest7_CheckBacklogBehaviour( void )
+{
+ /* Use the first auto-reload timer to test stopping a timer from a
+ * backlogged callback. */
+
+ /* The timer has not been started yet! */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ 0 ] ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Prompt the callback function to stop the timer. */
+ ucIsStopNeededInTimerZeroCallback = ( uint8_t ) pdTRUE;
+
+ /* Now start the timer. This will appear to happen immediately to
+ * this task because this task is running at a priority below the timer
+ * service task. Use a timer period of one tick so the call to
+ * xTaskCatchUpTicks() below has minimal impact on other tests that might
+ * be running. */
+#define tmrdemoBACKLOG_TIMER_PERIOD ( ( TickType_t ) 1 )
+ xTimerChangePeriod( xAutoReloadTimers[ 0 ], tmrdemoBACKLOG_TIMER_PERIOD, tmrdemoDONT_BLOCK );
+
+ /* The timer should now be active. */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ 0 ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Arrange for the callback to execute late enough that it will execute
+ * twice, back-to-back. The timer must handle the stop request properly
+ * in spite of the backlog of callbacks. */
+#define tmrdemoEXPECTED_BACKLOG_EXPIRES ( ( TickType_t ) 2 )
+ xTaskCatchUpTicks( tmrdemoBACKLOG_TIMER_PERIOD * tmrdemoEXPECTED_BACKLOG_EXPIRES );
+
+ /* The timer should now be inactive. */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ 0 ] ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Restore the standard timer period, and leave the timer inactive. */
+ xTimerChangePeriod( xAutoReloadTimers[ 0 ], xBasePeriod, tmrdemoDONT_BLOCK );
+ xTimerStop( xAutoReloadTimers[ 0 ], tmrdemoDONT_BLOCK );
+
+ /* Clear the reload count for the timer used in this test. */
+ ucAutoReloadTimerCounters[ 0 ] = ( uint8_t ) 0;
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so the check
+ * task knows this task is still running. */
+ ulLoopCounter++;
+ }
}
/*-----------------------------------------------------------*/
static void prvResetStartConditionsForNextIteration( void )
{
-uint8_t ucTimer;
-
- /* Start the timers again to start all the tests over again. */
-
- /* Start the timers again. */
- for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
- {
- /* The timer has not been started yet! */
- if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Now start the timer. This will appear to happen immediately to
- this task because this task is running at a priority below the timer
- service task. */
- xTimerStart( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK );
-
- /* The timer should now be active. */
- if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
-
- if( xTestStatus == pdPASS )
- {
- /* No errors have been reported so increment the loop counter so the
- check task knows this task is still running. */
- ulLoopCounter++;
- }
+ uint8_t ucTimer;
+
+ /* Start the timers again to start all the tests over again. */
+
+ /* Start the timers again. */
+ for( ucTimer = 0; ucTimer < ( uint8_t ) configTIMER_QUEUE_LENGTH; ucTimer++ )
+ {
+ /* The timer has not been started yet! */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) != pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Now start the timer. This will appear to happen immediately to
+ * this task because this task is running at a priority below the timer
+ * service task. */
+ xTimerStart( xAutoReloadTimers[ ucTimer ], tmrdemoDONT_BLOCK );
+
+ /* The timer should now be active. */
+ if( xTimerIsTimerActive( xAutoReloadTimers[ ucTimer ] ) == pdFALSE )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+
+ if( xTestStatus == pdPASS )
+ {
+ /* No errors have been reported so increment the loop counter so the
+ * check task knows this task is still running. */
+ ulLoopCounter++;
+ }
}
/*-----------------------------------------------------------*/
void vTimerPeriodicISRTests( void )
{
-static TickType_t uxTick = ( TickType_t ) -1;
-
-#if( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) )
- /* The timer service task is not the highest priority task, so it cannot
- be assumed that timings will be exact. Timers should never call their
- callback before their expiry time, but a margin is permissible for calling
- their callback after their expiry time. If exact timing is required then
- configTIMER_TASK_PRIORITY must be set to ensure the timer service task
- is the highest priority task in the system.
-
- This function is called from the tick hook. The tick hook is called
- even when the scheduler is suspended. Therefore it is possible that the
- uxTick count maintained in this function is temporarily ahead of the tick
- count maintained by the kernel. When this is the case a message posted from
- this function will assume a time stamp in advance of the real time stamp,
- which can result in a timer being processed before this function expects it
- to. For example, if the kernel's tick count was 100, and uxTick was 102,
- then this function will not expect the timer to have expired until the
- kernel's tick count is (102 + xBasePeriod), whereas in reality the timer
- will expire when the kernel's tick count is (100 + xBasePeriod). For this
- reason xMargin is used as an allowable margin for premature timer expiries
- as well as late timer expiries. */
- #ifdef _WINDOWS_
- /* Windows is not real real time. */
- const TickType_t xMargin = 20;
- #else
- const TickType_t xMargin = 6;
- #endif /* _WINDOWS_ */
-#else
- #ifdef _WINDOWS_
- /* Windows is not real real time. */
- const TickType_t xMargin = 20;
- #else
- const TickType_t xMargin = 4;
- #endif /* _WINDOWS_ */
-#endif
-
-
- uxTick++;
-
- if( uxTick == 0 )
- {
- /* The timers will have been created, but not started. Start them now
- by setting their period. */
- ucISRAutoReloadTimerCounter = 0;
- ucISROneShotTimerCounter = 0;
-
- /* It is possible that the timer task has not yet made room in the
- timer queue. If the timers cannot be started then reset uxTick so
- another attempt is made later. */
- uxTick = ( TickType_t ) -1;
-
- /* Try starting first timer. */
- if( xTimerChangePeriodFromISR( xISRAutoReloadTimer, xBasePeriod, NULL ) == pdPASS )
- {
- /* First timer was started, try starting the second timer. */
- if( xTimerChangePeriodFromISR( xISROneShotTimer, xBasePeriod, NULL ) == pdPASS )
- {
- /* Both timers were started, so set the uxTick back to its
- proper value. */
- uxTick = 0;
- }
- else
- {
- /* Second timer could not be started, so stop the first one
- again. */
- xTimerStopFromISR( xISRAutoReloadTimer, NULL );
- }
- }
- }
- else if( uxTick == ( xBasePeriod - xMargin ) )
- {
- /* Neither timer should have expired yet. */
- if( ( ucISRAutoReloadTimerCounter != 0 ) || ( ucISROneShotTimerCounter != 0 ) )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( xBasePeriod + xMargin ) )
- {
- /* Both timers should now have expired once. The auto-reload timer will
- still be active, but the one-shot timer should now have stopped. */
- if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( ( 2 * xBasePeriod ) - xMargin ) )
- {
- /* The auto-reload timer will still be active, but the one-shot timer
- should now have stopped - however, at this time neither of the timers
- should have expired again since the last test. */
- if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( ( 2 * xBasePeriod ) + xMargin ) )
- {
- /* The auto-reload timer will still be active, but the one-shot timer
- should now have stopped. At this time the auto-reload timer should have
- expired again, but the one-shot timer count should not have changed. */
- if( ucISRAutoReloadTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 1 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( ( 2 * xBasePeriod ) + ( xBasePeriod >> ( TickType_t ) 2U ) ) )
- {
- /* The auto-reload timer will still be active, but the one-shot timer
- should now have stopped. Again though, at this time, neither timer call
- back should have been called since the last test. */
- if( ucISRAutoReloadTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 1 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( 3 * xBasePeriod ) )
- {
- /* Start the one-shot timer again. */
- xTimerStartFromISR( xISROneShotTimer, NULL );
- }
- else if( uxTick == ( ( 3 * xBasePeriod ) + xMargin ) )
- {
- /* The auto-reload timer and one-shot timer will be active. At
- this time the auto-reload timer should have expired again, but the one
- shot timer count should not have changed yet. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 1 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Now stop the auto-reload timer. The one-shot timer was started
- a few ticks ago. */
- xTimerStopFromISR( xISRAutoReloadTimer, NULL );
- }
- else if( uxTick == ( 4 * ( xBasePeriod - xMargin ) ) )
- {
- /* The auto-reload timer is now stopped, and the one-shot timer is
- active, but at this time neither timer should have expired since the
- last test. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 1 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( ( 4 * xBasePeriod ) + xMargin ) )
- {
- /* The auto-reload timer is now stopped, and the one-shot timer is
- active. The one-shot timer should have expired again, but the auto
- reload timer should not have executed its callback. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( 8 * xBasePeriod ) )
- {
- /* The auto-reload timer is now stopped, and the one-shot timer has
- already expired and then stopped itself. Both callback counters should
- not have incremented since the last test. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- /* Now reset the one-shot timer. */
- xTimerResetFromISR( xISROneShotTimer, NULL );
- }
- else if( uxTick == ( ( 9 * xBasePeriod ) - xMargin ) )
- {
- /* Only the one-shot timer should be running, but it should not have
- expired since the last test. Check the callback counters have not
- incremented, then reset the one-shot timer again. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- xTimerResetFromISR( xISROneShotTimer, NULL );
- }
- else if( uxTick == ( ( 10 * xBasePeriod ) - ( 2 * xMargin ) ) )
- {
- /* Only the one-shot timer should be running, but it should not have
- expired since the last test. Check the callback counters have not
- incremented, then reset the one-shot timer again. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- xTimerResetFromISR( xISROneShotTimer, NULL );
- }
- else if( uxTick == ( ( 11 * xBasePeriod ) - ( 3 * xMargin ) ) )
- {
- /* Only the one-shot timer should be running, but it should not have
- expired since the last test. Check the callback counters have not
- incremented, then reset the one-shot timer once again. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 2 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- xTimerResetFromISR( xISROneShotTimer, NULL );
- }
- else if( uxTick == ( ( 12 * xBasePeriod ) - ( 2 * xMargin ) ) )
- {
- /* Only the one-shot timer should have been running and this time it
- should have expired. Check its callback count has been incremented.
- The auto-reload timer is still not running so should still have the same
- count value. This time the one-shot timer is not reset so should not
- restart from its expiry period again. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
- }
- else if( uxTick == ( 15 * xBasePeriod ) )
- {
- /* Neither timer should be running now. Check neither callback count
- has incremented, then go back to the start to run these tests all
- over again. */
- if( ucISRAutoReloadTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- if( ucISROneShotTimerCounter != 3 )
- {
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
-
- uxTick = ( TickType_t ) -1;
- }
+ static TickType_t uxTick = ( TickType_t ) -1;
+
+ #if ( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) )
+
+ /* The timer service task is not the highest priority task, so it cannot
+ * be assumed that timings will be exact. Timers should never call their
+ * callback before their expiry time, but a margin is permissible for calling
+ * their callback after their expiry time. If exact timing is required then
+ * configTIMER_TASK_PRIORITY must be set to ensure the timer service task
+ * is the highest priority task in the system.
+ *
+ * This function is called from the tick hook. The tick hook is called
+ * even when the scheduler is suspended. Therefore it is possible that the
+ * uxTick count maintained in this function is temporarily ahead of the tick
+ * count maintained by the kernel. When this is the case a message posted from
+ * this function will assume a time stamp in advance of the real time stamp,
+ * which can result in a timer being processed before this function expects it
+ * to. For example, if the kernel's tick count was 100, and uxTick was 102,
+ * then this function will not expect the timer to have expired until the
+ * kernel's tick count is (102 + xBasePeriod), whereas in reality the timer
+ * will expire when the kernel's tick count is (100 + xBasePeriod). For this
+ * reason xMargin is used as an allowable margin for premature timer expires
+ * as well as late timer expires. */
+ #ifdef _WINDOWS_
+ /* Windows is not real real time. */
+ const TickType_t xMargin = 20;
+ #else
+ const TickType_t xMargin = 6;
+ #endif /* _WINDOWS_ */
+ #else
+ #ifdef _WINDOWS_
+ /* Windows is not real real time. */
+ const TickType_t xMargin = 20;
+ #else
+ const TickType_t xMargin = 4;
+ #endif /* _WINDOWS_ */
+ #endif /* if ( configTIMER_TASK_PRIORITY != ( configMAX_PRIORITIES - 1 ) ) */
+
+
+ uxTick++;
+
+ if( uxTick == 0 )
+ {
+ /* The timers will have been created, but not started. Start them now
+ * by setting their period. */
+ ucISRAutoReloadTimerCounter = 0;
+ ucISROneShotTimerCounter = 0;
+
+ /* It is possible that the timer task has not yet made room in the
+ * timer queue. If the timers cannot be started then reset uxTick so
+ * another attempt is made later. */
+ uxTick = ( TickType_t ) -1;
+
+ /* Try starting first timer. */
+ if( xTimerChangePeriodFromISR( xISRAutoReloadTimer, xBasePeriod, NULL ) == pdPASS )
+ {
+ /* First timer was started, try starting the second timer. */
+ if( xTimerChangePeriodFromISR( xISROneShotTimer, xBasePeriod, NULL ) == pdPASS )
+ {
+ /* Both timers were started, so set the uxTick back to its
+ * proper value. */
+ uxTick = 0;
+ }
+ else
+ {
+ /* Second timer could not be started, so stop the first one
+ * again. */
+ xTimerStopFromISR( xISRAutoReloadTimer, NULL );
+ }
+ }
+ }
+ else if( uxTick == ( xBasePeriod - xMargin ) )
+ {
+ /* Neither timer should have expired yet. */
+ if( ( ucISRAutoReloadTimerCounter != 0 ) || ( ucISROneShotTimerCounter != 0 ) )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( xBasePeriod + xMargin ) )
+ {
+ /* Both timers should now have expired once. The auto-reload timer will
+ * still be active, but the one-shot timer should now have stopped. */
+ if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( ( 2 * xBasePeriod ) - xMargin ) )
+ {
+ /* The auto-reload timer will still be active, but the one-shot timer
+ * should now have stopped - however, at this time neither of the timers
+ * should have expired again since the last test. */
+ if( ( ucISRAutoReloadTimerCounter != 1 ) || ( ucISROneShotTimerCounter != 1 ) )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( ( 2 * xBasePeriod ) + xMargin ) )
+ {
+ /* The auto-reload timer will still be active, but the one-shot timer
+ * should now have stopped. At this time the auto-reload timer should have
+ * expired again, but the one-shot timer count should not have changed. */
+ if( ucISRAutoReloadTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 1 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( ( 2 * xBasePeriod ) + ( xBasePeriod >> ( TickType_t ) 2U ) ) )
+ {
+ /* The auto-reload timer will still be active, but the one-shot timer
+ * should now have stopped. Again though, at this time, neither timer call
+ * back should have been called since the last test. */
+ if( ucISRAutoReloadTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 1 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( 3 * xBasePeriod ) )
+ {
+ /* Start the one-shot timer again. */
+ xTimerStartFromISR( xISROneShotTimer, NULL );
+ }
+ else if( uxTick == ( ( 3 * xBasePeriod ) + xMargin ) )
+ {
+ /* The auto-reload timer and one-shot timer will be active. At
+ * this time the auto-reload timer should have expired again, but the one
+ * shot timer count should not have changed yet. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 1 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Now stop the auto-reload timer. The one-shot timer was started
+ * a few ticks ago. */
+ xTimerStopFromISR( xISRAutoReloadTimer, NULL );
+ }
+ else if( uxTick == ( 4 * ( xBasePeriod - xMargin ) ) )
+ {
+ /* The auto-reload timer is now stopped, and the one-shot timer is
+ * active, but at this time neither timer should have expired since the
+ * last test. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 1 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( ( 4 * xBasePeriod ) + xMargin ) )
+ {
+ /* The auto-reload timer is now stopped, and the one-shot timer is
+ * active. The one-shot timer should have expired again, but the auto
+ * reload timer should not have executed its callback. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( 8 * xBasePeriod ) )
+ {
+ /* The auto-reload timer is now stopped, and the one-shot timer has
+ * already expired and then stopped itself. Both callback counters should
+ * not have incremented since the last test. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ /* Now reset the one-shot timer. */
+ xTimerResetFromISR( xISROneShotTimer, NULL );
+ }
+ else if( uxTick == ( ( 9 * xBasePeriod ) - xMargin ) )
+ {
+ /* Only the one-shot timer should be running, but it should not have
+ * expired since the last test. Check the callback counters have not
+ * incremented, then reset the one-shot timer again. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ xTimerResetFromISR( xISROneShotTimer, NULL );
+ }
+ else if( uxTick == ( ( 10 * xBasePeriod ) - ( 2 * xMargin ) ) )
+ {
+ /* Only the one-shot timer should be running, but it should not have
+ * expired since the last test. Check the callback counters have not
+ * incremented, then reset the one-shot timer again. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ xTimerResetFromISR( xISROneShotTimer, NULL );
+ }
+ else if( uxTick == ( ( 11 * xBasePeriod ) - ( 3 * xMargin ) ) )
+ {
+ /* Only the one-shot timer should be running, but it should not have
+ * expired since the last test. Check the callback counters have not
+ * incremented, then reset the one-shot timer once again. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 2 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ xTimerResetFromISR( xISROneShotTimer, NULL );
+ }
+ else if( uxTick == ( ( 12 * xBasePeriod ) - ( 2 * xMargin ) ) )
+ {
+ /* Only the one-shot timer should have been running and this time it
+ * should have expired. Check its callback count has been incremented.
+ * The auto-reload timer is still not running so should still have the same
+ * count value. This time the one-shot timer is not reset so should not
+ * restart from its expiry period again. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+ }
+ else if( uxTick == ( 15 * xBasePeriod ) )
+ {
+ /* Neither timer should be running now. Check neither callback count
+ * has incremented, then go back to the start to run these tests all
+ * over again. */
+ if( ucISRAutoReloadTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ if( ucISROneShotTimerCounter != 3 )
+ {
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
+
+ uxTick = ( TickType_t ) -1;
+ }
}
/*-----------------------------------------------------------*/
@@ -1020,65 +1105,69 @@ static TickType_t uxTick = ( TickType_t ) -1;
static void prvAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer )
{
-size_t uxTimerID;
-
- uxTimerID = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
- if( uxTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) )
- {
- ( ucAutoReloadTimerCounters[ uxTimerID ] )++;
- }
- else
- {
- /* The timer ID appears to be unexpected (invalid). */
- xTestStatus = pdFAIL;
- configASSERT( xTestStatus );
- }
+ size_t uxTimerID;
+
+ uxTimerID = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
+
+ if( uxTimerID <= ( configTIMER_QUEUE_LENGTH + 1 ) )
+ {
+ ( ucAutoReloadTimerCounters[ uxTimerID ] )++;
+
+ /* Stop timer ID 0 if requested. */
+ if( ( uxTimerID == ( size_t ) 0 ) && ( ucIsStopNeededInTimerZeroCallback == ( uint8_t ) pdTRUE ) )
+ {
+ xTimerStop( pxExpiredTimer, tmrdemoDONT_BLOCK );
+ ucIsStopNeededInTimerZeroCallback = ( uint8_t ) pdFALSE;
+ }
+ }
+ else
+ {
+ /* The timer ID appears to be unexpected (invalid). */
+ xTestStatus = pdFAIL;
+ configASSERT( xTestStatus );
+ }
}
/*-----------------------------------------------------------*/
static void prvOneShotTimerCallback( TimerHandle_t pxExpiredTimer )
{
/* A count is kept of the number of times this callback function is executed.
-The count is stored as the timer's ID. This is only done to test the
-vTimerSetTimerID() function. */
-static size_t uxCallCount = 0;
-size_t uxLastCallCount;
-
- /* Obtain the timer's ID, which should be a count of the number of times
- this callback function has been executed. */
- uxLastCallCount = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
- configASSERT( uxLastCallCount == uxCallCount );
-
- /* Increment the call count, then save it back as the timer's ID. This is
- only done to test the vTimerSetTimerID() API function. */
- uxLastCallCount++;
- vTimerSetTimerID( pxExpiredTimer, ( void * ) uxLastCallCount );
- uxCallCount++;
-
- ucOneShotTimerCounter++;
+ * The count is stored as the timer's ID. This is only done to test the
+ * vTimerSetTimerID() function. */
+ static size_t uxCallCount = 0;
+ size_t uxLastCallCount;
+
+ /* Obtain the timer's ID, which should be a count of the number of times
+ * this callback function has been executed. */
+ uxLastCallCount = ( size_t ) pvTimerGetTimerID( pxExpiredTimer );
+ configASSERT( uxLastCallCount == uxCallCount );
+
+ /* Increment the call count, then save it back as the timer's ID. This is
+ * only done to test the vTimerSetTimerID() API function. */
+ uxLastCallCount++;
+ vTimerSetTimerID( pxExpiredTimer, ( void * ) uxLastCallCount );
+ uxCallCount++;
+
+ ucOneShotTimerCounter++;
}
/*-----------------------------------------------------------*/
static void prvISRAutoReloadTimerCallback( TimerHandle_t pxExpiredTimer )
{
- /* The parameter is not used in this case as only one timer uses this
- callback function. */
- ( void ) pxExpiredTimer;
+ /* The parameter is not used in this case as only one timer uses this
+ * callback function. */
+ ( void ) pxExpiredTimer;
- ucISRAutoReloadTimerCounter++;
+ ucISRAutoReloadTimerCounter++;
}
/*-----------------------------------------------------------*/
static void prvISROneShotTimerCallback( TimerHandle_t pxExpiredTimer )
{
- /* The parameter is not used in this case as only one timer uses this
- callback function. */
- ( void ) pxExpiredTimer;
+ /* The parameter is not used in this case as only one timer uses this
+ * callback function. */
+ ( void ) pxExpiredTimer;
- ucISROneShotTimerCounter++;
+ ucISROneShotTimerCounter++;
}
/*-----------------------------------------------------------*/
-
-
-
-
diff --git a/Demo/Common/Minimal/blocktim.c b/Demo/Common/Minimal/blocktim.c
index 5ea1792ab..ca8cc4afb 100644
--- a/Demo/Common/Minimal/blocktim.c
+++ b/Demo/Common/Minimal/blocktim.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -41,30 +41,30 @@
/* Task priorities and stack sizes. Allow these to be overridden. */
#ifndef bktPRIMARY_PRIORITY
- #define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
+ #define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
#endif
#ifndef bktSECONDARY_PRIORITY
- #define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 )
+ #define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 )
#endif
#ifndef bktBLOCK_TIME_TASK_STACK_SIZE
- #define bktBLOCK_TIME_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define bktBLOCK_TIME_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
/* Task behaviour. */
-#define bktQUEUE_LENGTH ( 5 )
-#define bktSHORT_WAIT pdMS_TO_TICKS( ( TickType_t ) 20 )
-#define bktPRIMARY_BLOCK_TIME ( 10 )
-#define bktALLOWABLE_MARGIN ( 15 )
-#define bktTIME_TO_BLOCK ( 175 )
-#define bktDONT_BLOCK ( ( TickType_t ) 0 )
-#define bktRUN_INDICATOR ( ( UBaseType_t ) 0x55 )
+#define bktQUEUE_LENGTH ( 5 )
+#define bktSHORT_WAIT pdMS_TO_TICKS( ( TickType_t ) 20 )
+#define bktPRIMARY_BLOCK_TIME ( 10 )
+#define bktALLOWABLE_MARGIN ( 15 )
+#define bktTIME_TO_BLOCK ( 175 )
+#define bktDONT_BLOCK ( ( TickType_t ) 0 )
+#define bktRUN_INDICATOR ( ( UBaseType_t ) 0x55 )
/* In case the demo does not have software timers enabled, as this file uses
-the configTIMER_TASK_PRIORITY setting. */
+ * the configTIMER_TASK_PRIORITY setting. */
#ifndef configTIMER_TASK_PRIORITY
- #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+ #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#endif
/*-----------------------------------------------------------*/
@@ -72,8 +72,8 @@ the configTIMER_TASK_PRIORITY setting. */
/*
* The two test tasks. Their behaviour is commented within the functions.
*/
-static void vPrimaryBlockTimeTestTask( void *pvParameters );
-static void vSecondaryBlockTimeTestTask( void *pvParameters );
+static void vPrimaryBlockTimeTestTask( void * pvParameters );
+static void vSecondaryBlockTimeTestTask( void * pvParameters );
/*
* Very basic tests to verify the block times are as expected.
@@ -86,7 +86,7 @@ static void prvBasicDelayTests( void );
static QueueHandle_t xTestQueue;
/* Handle to the secondary task is required by the primary task for calls
-to vTaskSuspend/Resume(). */
+ * to vTaskSuspend/Resume(). */
static TaskHandle_t xSecondary;
/* Used to ensure that tasks are still executing without error. */
@@ -94,495 +94,505 @@ static volatile BaseType_t xPrimaryCycles = 0, xSecondaryCycles = 0;
static volatile BaseType_t xErrorOccurred = pdFALSE;
/* Provides a simple mechanism for the primary task to know when the
-secondary task has executed. */
+ * secondary task has executed. */
static volatile UBaseType_t xRunIndicator;
/*-----------------------------------------------------------*/
void vCreateBlockTimeTasks( void )
{
- /* Create the queue on which the two tasks block. */
- xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( BaseType_t ) );
-
- if( xTestQueue != NULL )
- {
- /* vQueueAddToRegistry() adds the queue to the queue registry, if one
- is in use. The queue registry is provided as a means for kernel aware
- debuggers to locate queues and has no purpose if a kernel aware
- debugger is not being used. The call to vQueueAddToRegistry() will be
- removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
- defined or is defined to be less than 1. */
- vQueueAddToRegistry( xTestQueue, "Block_Time_Queue" );
-
- /* Create the two test tasks. */
- xTaskCreate( vPrimaryBlockTimeTestTask, "BTest1", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL );
- xTaskCreate( vSecondaryBlockTimeTestTask, "BTest2", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary );
- }
+ /* Create the queue on which the two tasks block. */
+ xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( BaseType_t ) );
+
+ if( xTestQueue != NULL )
+ {
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one
+ * is in use. The queue registry is provided as a means for kernel aware
+ * debuggers to locate queues and has no purpose if a kernel aware
+ * debugger is not being used. The call to vQueueAddToRegistry() will be
+ * removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+ * defined or is defined to be less than 1. */
+ vQueueAddToRegistry( xTestQueue, "Block_Time_Queue" );
+
+ /* Create the two test tasks. */
+ xTaskCreate( vPrimaryBlockTimeTestTask, "BTest1", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL );
+ xTaskCreate( vSecondaryBlockTimeTestTask, "BTest2", bktBLOCK_TIME_TASK_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary );
+ }
}
/*-----------------------------------------------------------*/
-static void vPrimaryBlockTimeTestTask( void *pvParameters )
+static void vPrimaryBlockTimeTestTask( void * pvParameters )
{
-BaseType_t xItem, xData;
-TickType_t xTimeWhenBlocking;
-TickType_t xTimeToBlock, xBlockedTime;
-
- ( void ) pvParameters;
-
- for( ;; )
- {
- /*********************************************************************
- Test 0
-
- Basic vTaskDelay() and vTaskDelayUntil() tests. */
- prvBasicDelayTests();
-
-
- /*********************************************************************
- Test 1
-
- Simple block time wakeup test on queue receives. */
- for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
- {
- /* The queue is empty. Attempt to read from the queue using a block
- time. When we wake, ensure the delta in time is as expected. */
- xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem );
-
- xTimeWhenBlocking = xTaskGetTickCount();
-
- /* We should unblock after xTimeToBlock having not received
- anything on the queue. */
- if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* How long were we blocked for? */
- xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
-
- if( xBlockedTime < xTimeToBlock )
- {
- /* Should not have blocked for less than we requested. */
- xErrorOccurred = pdTRUE;
- }
-
- if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
- {
- /* Should not have blocked for longer than we requested,
- although we would not necessarily run as soon as we were
- unblocked so a margin is allowed. */
- xErrorOccurred = pdTRUE;
- }
- }
-
- /*********************************************************************
- Test 2
-
- Simple block time wakeup test on queue sends.
-
- First fill the queue. It should be empty so all sends should pass. */
- for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
- {
- if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
- }
-
- for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
- {
- /* The queue is full. Attempt to write to the queue using a block
- time. When we wake, ensure the delta in time is as expected. */
- xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem );
-
- xTimeWhenBlocking = xTaskGetTickCount();
-
- /* We should unblock after xTimeToBlock having not received
- anything on the queue. */
- if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* How long were we blocked for? */
- xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
-
- if( xBlockedTime < xTimeToBlock )
- {
- /* Should not have blocked for less than we requested. */
- xErrorOccurred = pdTRUE;
- }
-
- if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
- {
- /* Should not have blocked for longer than we requested,
- although we would not necessarily run as soon as we were
- unblocked so a margin is allowed. */
- xErrorOccurred = pdTRUE;
- }
- }
-
- /*********************************************************************
- Test 3
-
- Wake the other task, it will block attempting to post to the queue.
- When we read from the queue the other task will wake, but before it
- can run we will post to the queue again. When the other task runs it
- will find the queue still full, even though it was woken. It should
- recognise that its block time has not expired and return to block for
- the remains of its block time.
-
- Wake the other task so it blocks attempting to post to the already
- full queue. */
- xRunIndicator = 0;
- vTaskResume( xSecondary );
-
- /* We need to wait a little to ensure the other task executes. */
- while( xRunIndicator != bktRUN_INDICATOR )
- {
- /* The other task has not yet executed. */
- vTaskDelay( bktSHORT_WAIT );
- }
- /* Make sure the other task is blocked on the queue. */
- vTaskDelay( bktSHORT_WAIT );
- xRunIndicator = 0;
-
- for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
- {
- /* Now when we make space on the queue the other task should wake
- but not execute as this task has higher priority. */
- if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now fill the queue again before the other task gets a chance to
- execute. If the other task had executed we would find the queue
- full ourselves, and the other task have set xRunIndicator. */
- if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- if( xRunIndicator == bktRUN_INDICATOR )
- {
- /* The other task should not have executed. */
- xErrorOccurred = pdTRUE;
- }
-
- /* Raise the priority of the other task so it executes and blocks
- on the queue again. */
- vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
-
- /* The other task should now have re-blocked without exiting the
- queue function. */
- if( xRunIndicator == bktRUN_INDICATOR )
- {
- /* The other task should not have executed outside of the
- queue function. */
- xErrorOccurred = pdTRUE;
- }
-
- /* Set the priority back down. */
- vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
- }
-
- /* Let the other task timeout. When it unblockes it will check that it
- unblocked at the correct time, then suspend itself. */
- while( xRunIndicator != bktRUN_INDICATOR )
- {
- vTaskDelay( bktSHORT_WAIT );
- }
- vTaskDelay( bktSHORT_WAIT );
- xRunIndicator = 0;
-
-
- /*********************************************************************
- Test 4
-
- As per test 3 - but with the send and receive the other way around.
- The other task blocks attempting to read from the queue.
-
- Empty the queue. We should find that it is full. */
- for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
- {
- if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
- }
-
- /* Wake the other task so it blocks attempting to read from the
- already empty queue. */
- vTaskResume( xSecondary );
-
- /* We need to wait a little to ensure the other task executes. */
- while( xRunIndicator != bktRUN_INDICATOR )
- {
- vTaskDelay( bktSHORT_WAIT );
- }
- vTaskDelay( bktSHORT_WAIT );
- xRunIndicator = 0;
-
- for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
- {
- /* Now when we place an item on the queue the other task should
- wake but not execute as this task has higher priority. */
- if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now empty the queue again before the other task gets a chance to
- execute. If the other task had executed we would find the queue
- empty ourselves, and the other task would be suspended. */
- if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- if( xRunIndicator == bktRUN_INDICATOR )
- {
- /* The other task should not have executed. */
- xErrorOccurred = pdTRUE;
- }
-
- /* Raise the priority of the other task so it executes and blocks
- on the queue again. */
- vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
-
- /* The other task should now have re-blocked without exiting the
- queue function. */
- if( xRunIndicator == bktRUN_INDICATOR )
- {
- /* The other task should not have executed outside of the
- queue function. */
- xErrorOccurred = pdTRUE;
- }
- vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
- }
-
- /* Let the other task timeout. When it unblockes it will check that it
- unblocked at the correct time, then suspend itself. */
- while( xRunIndicator != bktRUN_INDICATOR )
- {
- vTaskDelay( bktSHORT_WAIT );
- }
- vTaskDelay( bktSHORT_WAIT );
-
- xPrimaryCycles++;
- }
+ BaseType_t xItem, xData;
+ TickType_t xTimeWhenBlocking;
+ TickType_t xTimeToBlock, xBlockedTime;
+
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /*********************************************************************
+ * Test 0
+ *
+ * Basic vTaskDelay() and vTaskDelayUntil() tests. */
+ prvBasicDelayTests();
+
+ /*********************************************************************
+ * Test 1
+ *
+ * Simple block time wakeup test on queue receives. */
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+ {
+ /* The queue is empty. Attempt to read from the queue using a block
+ * time. When we wake, ensure the delta in time is as expected. */
+ xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem );
+
+ xTimeWhenBlocking = xTaskGetTickCount();
+
+ /* We should unblock after xTimeToBlock having not received
+ * anything on the queue. */
+ if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* How long were we blocked for? */
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+ if( xBlockedTime < xTimeToBlock )
+ {
+ /* Should not have blocked for less than we requested. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
+ {
+ /* Should not have blocked for longer than we requested,
+ * although we would not necessarily run as soon as we were
+ * unblocked so a margin is allowed. */
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /*********************************************************************
+ * Test 2
+ *
+ * Simple block time wakeup test on queue sends.
+ *
+ * First fill the queue. It should be empty so all sends should pass. */
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+ {
+ if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
+
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+ {
+ /* The queue is full. Attempt to write to the queue using a block
+ * time. When we wake, ensure the delta in time is as expected. */
+ xTimeToBlock = ( TickType_t ) ( bktPRIMARY_BLOCK_TIME << xItem );
+
+ xTimeWhenBlocking = xTaskGetTickCount();
+
+ /* We should unblock after xTimeToBlock having not received
+ * anything on the queue. */
+ if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* How long were we blocked for? */
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+ if( xBlockedTime < xTimeToBlock )
+ {
+ /* Should not have blocked for less than we requested. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )
+ {
+ /* Should not have blocked for longer than we requested,
+ * although we would not necessarily run as soon as we were
+ * unblocked so a margin is allowed. */
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /*********************************************************************
+ * Test 3
+ *
+ * Wake the other task, it will block attempting to post to the queue.
+ * When we read from the queue the other task will wake, but before it
+ * can run we will post to the queue again. When the other task runs it
+ * will find the queue still full, even though it was woken. It should
+ * recognise that its block time has not expired and return to block for
+ * the remains of its block time.
+ *
+ * Wake the other task so it blocks attempting to post to the already
+ * full queue. */
+ xRunIndicator = 0;
+ vTaskResume( xSecondary );
+
+ /* We need to wait a little to ensure the other task executes. */
+ while( xRunIndicator != bktRUN_INDICATOR )
+ {
+ /* The other task has not yet executed. */
+ vTaskDelay( bktSHORT_WAIT );
+ }
+
+ /* Make sure the other task is blocked on the queue. */
+ vTaskDelay( bktSHORT_WAIT );
+ xRunIndicator = 0;
+
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+ {
+ /* Now when we make space on the queue the other task should wake
+ * but not execute as this task has higher priority. */
+ if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now fill the queue again before the other task gets a chance to
+ * execute. If the other task had executed we would find the queue
+ * full ourselves, and the other task have set xRunIndicator. */
+ if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( xRunIndicator == bktRUN_INDICATOR )
+ {
+ /* The other task should not have executed. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Raise the priority of the other task so it executes and blocks
+ * on the queue again. */
+ vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
+
+ /* The other task should now have re-blocked without exiting the
+ * queue function. */
+ if( xRunIndicator == bktRUN_INDICATOR )
+ {
+ /* The other task should not have executed outside of the
+ * queue function. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Set the priority back down. */
+ vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
+ }
+
+ /* Let the other task timeout. When it unblockes it will check that it
+ * unblocked at the correct time, then suspend itself. */
+ while( xRunIndicator != bktRUN_INDICATOR )
+ {
+ vTaskDelay( bktSHORT_WAIT );
+ }
+
+ vTaskDelay( bktSHORT_WAIT );
+ xRunIndicator = 0;
+
+ /*********************************************************************
+ * Test 4
+ *
+ * As per test 3 - but with the send and receive the other way around.
+ * The other task blocks attempting to read from the queue.
+ *
+ * Empty the queue. We should find that it is full. */
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+ {
+ if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ }
+
+ /* Wake the other task so it blocks attempting to read from the
+ * already empty queue. */
+ vTaskResume( xSecondary );
+
+ /* We need to wait a little to ensure the other task executes. */
+ while( xRunIndicator != bktRUN_INDICATOR )
+ {
+ vTaskDelay( bktSHORT_WAIT );
+ }
+
+ vTaskDelay( bktSHORT_WAIT );
+ xRunIndicator = 0;
+
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )
+ {
+ /* Now when we place an item on the queue the other task should
+ * wake but not execute as this task has higher priority. */
+ if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now empty the queue again before the other task gets a chance to
+ * execute. If the other task had executed we would find the queue
+ * empty ourselves, and the other task would be suspended. */
+ if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ if( xRunIndicator == bktRUN_INDICATOR )
+ {
+ /* The other task should not have executed. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Raise the priority of the other task so it executes and blocks
+ * on the queue again. */
+ vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );
+
+ /* The other task should now have re-blocked without exiting the
+ * queue function. */
+ if( xRunIndicator == bktRUN_INDICATOR )
+ {
+ /* The other task should not have executed outside of the
+ * queue function. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );
+ }
+
+ /* Let the other task timeout. When it unblockes it will check that it
+ * unblocked at the correct time, then suspend itself. */
+ while( xRunIndicator != bktRUN_INDICATOR )
+ {
+ vTaskDelay( bktSHORT_WAIT );
+ }
+
+ vTaskDelay( bktSHORT_WAIT );
+
+ xPrimaryCycles++;
+ }
}
/*-----------------------------------------------------------*/
-static void vSecondaryBlockTimeTestTask( void *pvParameters )
+static void vSecondaryBlockTimeTestTask( void * pvParameters )
{
-TickType_t xTimeWhenBlocking, xBlockedTime;
-BaseType_t xData;
-
- ( void ) pvParameters;
-
- for( ;; )
- {
- /*********************************************************************
- Test 0, 1 and 2
-
- This task does not participate in these tests. */
- vTaskSuspend( NULL );
-
- /*********************************************************************
- Test 3
-
- The first thing we do is attempt to read from the queue. It should be
- full so we block. Note the time before we block so we can check the
- wake time is as per that expected. */
- xTimeWhenBlocking = xTaskGetTickCount();
-
- /* We should unblock after bktTIME_TO_BLOCK having not sent anything to
- the queue. */
- xData = 0;
- xRunIndicator = bktRUN_INDICATOR;
- if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* How long were we inside the send function? */
- xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
-
- /* We should not have blocked for less time than bktTIME_TO_BLOCK. */
- if( xBlockedTime < bktTIME_TO_BLOCK )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* We should of not blocked for much longer than bktALLOWABLE_MARGIN
- either. A margin is permitted as we would not necessarily run as
- soon as we unblocked. */
- if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Suspend ready for test 3. */
- xRunIndicator = bktRUN_INDICATOR;
- vTaskSuspend( NULL );
-
- /*********************************************************************
- Test 4
-
- As per test three, but with the send and receive reversed. */
- xTimeWhenBlocking = xTaskGetTickCount();
-
- /* We should unblock after bktTIME_TO_BLOCK having not received
- anything on the queue. */
- xRunIndicator = bktRUN_INDICATOR;
- if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY )
- {
- xErrorOccurred = pdTRUE;
- }
-
- xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
-
- /* We should not have blocked for less time than bktTIME_TO_BLOCK. */
- if( xBlockedTime < bktTIME_TO_BLOCK )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* We should of not blocked for much longer than bktALLOWABLE_MARGIN
- either. A margin is permitted as we would not necessarily run as soon
- as we unblocked. */
- if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
- {
- xErrorOccurred = pdTRUE;
- }
-
- xRunIndicator = bktRUN_INDICATOR;
-
- xSecondaryCycles++;
- }
+ TickType_t xTimeWhenBlocking, xBlockedTime;
+ BaseType_t xData;
+
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /*********************************************************************
+ * Test 0, 1 and 2
+ *
+ * This task does not participate in these tests. */
+ vTaskSuspend( NULL );
+
+ /*********************************************************************
+ * Test 3
+ *
+ * The first thing we do is attempt to read from the queue. It should be
+ * full so we block. Note the time before we block so we can check the
+ * wake time is as per that expected. */
+ xTimeWhenBlocking = xTaskGetTickCount();
+
+ /* We should unblock after bktTIME_TO_BLOCK having not sent anything to
+ * the queue. */
+ xData = 0;
+ xRunIndicator = bktRUN_INDICATOR;
+
+ if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* How long were we inside the send function? */
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+ /* We should not have blocked for less time than bktTIME_TO_BLOCK. */
+ if( xBlockedTime < bktTIME_TO_BLOCK )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* We should of not blocked for much longer than bktALLOWABLE_MARGIN
+ * either. A margin is permitted as we would not necessarily run as
+ * soon as we unblocked. */
+ if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Suspend ready for test 3. */
+ xRunIndicator = bktRUN_INDICATOR;
+ vTaskSuspend( NULL );
+
+ /*********************************************************************
+ * Test 4
+ *
+ * As per test three, but with the send and receive reversed. */
+ xTimeWhenBlocking = xTaskGetTickCount();
+
+ /* We should unblock after bktTIME_TO_BLOCK having not received
+ * anything on the queue. */
+ xRunIndicator = bktRUN_INDICATOR;
+
+ if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;
+
+ /* We should not have blocked for less time than bktTIME_TO_BLOCK. */
+ if( xBlockedTime < bktTIME_TO_BLOCK )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* We should of not blocked for much longer than bktALLOWABLE_MARGIN
+ * either. A margin is permitted as we would not necessarily run as soon
+ * as we unblocked. */
+ if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ xRunIndicator = bktRUN_INDICATOR;
+
+ xSecondaryCycles++;
+ }
}
/*-----------------------------------------------------------*/
static void prvBasicDelayTests( void )
{
-TickType_t xPreTime, xPostTime, x, xLastUnblockTime, xExpectedUnblockTime;
-const TickType_t xPeriod = 75, xCycles = 5, xAllowableMargin = ( bktALLOWABLE_MARGIN >> 1 ), xHalfPeriod = xPeriod / ( TickType_t ) 2;
-BaseType_t xDidBlock;
-
- /* Temporarily increase priority so the timing is more accurate, but not so
- high as to disrupt the timer tests. */
- vTaskPrioritySet( NULL, configTIMER_TASK_PRIORITY - 1 );
-
- /* Crude check to too see that vTaskDelay() blocks for the expected
- period. */
- xPreTime = xTaskGetTickCount();
- vTaskDelay( bktTIME_TO_BLOCK );
- xPostTime = xTaskGetTickCount();
-
- /* The priority is higher, so the allowable margin is halved when compared
- to the other tests in this file. */
- if( ( xPostTime - xPreTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now crude tests to check the vTaskDelayUntil() functionality. */
- xPostTime = xTaskGetTickCount();
- xLastUnblockTime = xPostTime;
-
- for( x = 0; x < xCycles; x++ )
- {
- /* Calculate the next expected unblock time from the time taken before
- this loop was entered. */
- xExpectedUnblockTime = xPostTime + ( x * xPeriod );
-
- vTaskDelayUntil( &xLastUnblockTime, xPeriod );
-
- if( ( xTaskGetTickCount() - xExpectedUnblockTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) )
- {
- xErrorOccurred = pdTRUE;
- }
-
- xPrimaryCycles++;
- }
-
- /* Crude tests for return value of xTaskDelayUntil(). First a standard block
- should return that the task does block. */
- xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
- if( xDidBlock != pdTRUE )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Now delay a few ticks so repeating the above block period will not block for
- the full amount of time, but will still block. */
- vTaskDelay( xHalfPeriod );
- xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
- if( xDidBlock != pdTRUE )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* This time block for longer than xPeriod before calling xTaskDelayUntil() so
- the call to xTaskDelayUntil() should not block. */
- vTaskDelay( xPeriod );
- xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
- if( xDidBlock != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Catch up. */
- xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
- if( xDidBlock != pdTRUE )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Again block for slightly longer than a period so ensure the time is in the
- past next time xTaskDelayUntil() gets called. */
- vTaskDelay( xPeriod + xAllowableMargin );
- xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
- if( xDidBlock != pdFALSE )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Reset to the original task priority ready for the other tests. */
- vTaskPrioritySet( NULL, bktPRIMARY_PRIORITY );
+ TickType_t xPreTime, xPostTime, x, xLastUnblockTime, xExpectedUnblockTime;
+ const TickType_t xPeriod = 75, xCycles = 5, xAllowableMargin = ( bktALLOWABLE_MARGIN >> 1 ), xHalfPeriod = xPeriod / ( TickType_t ) 2;
+ BaseType_t xDidBlock;
+
+ /* Temporarily increase priority so the timing is more accurate, but not so
+ * high as to disrupt the timer tests. */
+ vTaskPrioritySet( NULL, configTIMER_TASK_PRIORITY - 1 );
+
+ /* Crude check to too see that vTaskDelay() blocks for the expected
+ * period. */
+ xPreTime = xTaskGetTickCount();
+ vTaskDelay( bktTIME_TO_BLOCK );
+ xPostTime = xTaskGetTickCount();
+
+ /* The priority is higher, so the allowable margin is halved when compared
+ * to the other tests in this file. */
+ if( ( xPostTime - xPreTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now crude tests to check the vTaskDelayUntil() functionality. */
+ xPostTime = xTaskGetTickCount();
+ xLastUnblockTime = xPostTime;
+
+ for( x = 0; x < xCycles; x++ )
+ {
+ /* Calculate the next expected unblock time from the time taken before
+ * this loop was entered. */
+ xExpectedUnblockTime = xPostTime + ( x * xPeriod );
+
+ vTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+ if( ( xTaskGetTickCount() - xExpectedUnblockTime ) > ( bktTIME_TO_BLOCK + xAllowableMargin ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ xPrimaryCycles++;
+ }
+
+ /* Crude tests for return value of xTaskDelayUntil(). First a standard block
+ * should return that the task does block. */
+ xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+ if( xDidBlock != pdTRUE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Now delay a few ticks so repeating the above block period will not block for
+ * the full amount of time, but will still block. */
+ vTaskDelay( xHalfPeriod );
+ xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+ if( xDidBlock != pdTRUE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* This time block for longer than xPeriod before calling xTaskDelayUntil() so
+ * the call to xTaskDelayUntil() should not block. */
+ vTaskDelay( xPeriod );
+ xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+ if( xDidBlock != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Catch up. */
+ xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+ if( xDidBlock != pdTRUE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Again block for slightly longer than a period so ensure the time is in the
+ * past next time xTaskDelayUntil() gets called. */
+ vTaskDelay( xPeriod + xAllowableMargin );
+ xDidBlock = xTaskDelayUntil( &xLastUnblockTime, xPeriod );
+
+ if( xDidBlock != pdFALSE )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Reset to the original task priority ready for the other tests. */
+ vTaskPrioritySet( NULL, bktPRIMARY_PRIORITY );
}
/*-----------------------------------------------------------*/
BaseType_t xAreBlockTimeTestTasksStillRunning( void )
{
-static BaseType_t xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0;
-BaseType_t xReturn = pdPASS;
-
- /* Have both tasks performed at least one cycle since this function was
- last called? */
- if( xPrimaryCycles == xLastPrimaryCycleCount )
- {
- xReturn = pdFAIL;
- }
-
- if( xSecondaryCycles == xLastSecondaryCycleCount )
- {
- xReturn = pdFAIL;
- }
-
- if( xErrorOccurred == pdTRUE )
- {
- xReturn = pdFAIL;
- }
-
- xLastSecondaryCycleCount = xSecondaryCycles;
- xLastPrimaryCycleCount = xPrimaryCycles;
-
- return xReturn;
+ static BaseType_t xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0;
+ BaseType_t xReturn = pdPASS;
+
+ /* Have both tasks performed at least one cycle since this function was
+ * last called? */
+ if( xPrimaryCycles == xLastPrimaryCycleCount )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xSecondaryCycles == xLastSecondaryCycleCount )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xErrorOccurred == pdTRUE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ xLastSecondaryCycleCount = xSecondaryCycles;
+ xLastPrimaryCycleCount = xPrimaryCycles;
+
+ return xReturn;
}
diff --git a/Demo/Common/Minimal/comtest.c b/Demo/Common/Minimal/comtest.c
index 997a4029c..ab0ac523f 100644
--- a/Demo/Common/Minimal/comtest.c
+++ b/Demo/Common/Minimal/comtest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -67,30 +67,30 @@
#include "comtest.h"
#include "partest.h"
-#define comSTACK_SIZE configMINIMAL_STACK_SIZE
-#define comTX_LED_OFFSET ( 0 )
-#define comRX_LED_OFFSET ( 1 )
-#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )
+#define comSTACK_SIZE configMINIMAL_STACK_SIZE
+#define comTX_LED_OFFSET ( 0 )
+#define comRX_LED_OFFSET ( 1 )
+#define comTOTAL_PERMISSIBLE_ERRORS ( 2 )
/* The Tx task will transmit the sequence of characters at a pseudo random
-interval. This is the maximum and minimum block time between sends. */
-#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x96 )
-#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0x32 )
-#define comOFFSET_TIME ( ( TickType_t ) 3 )
+ * interval. This is the maximum and minimum block time between sends. */
+#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x96 )
+#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0x32 )
+#define comOFFSET_TIME ( ( TickType_t ) 3 )
/* We should find that each character can be queued for Tx immediately and we
-don't have to block to send. */
-#define comNO_BLOCK ( ( TickType_t ) 0 )
+ * don't have to block to send. */
+#define comNO_BLOCK ( ( TickType_t ) 0 )
/* The Rx task will block on the Rx queue for a long period. */
-#define comRX_BLOCK_TIME ( ( TickType_t ) 0xffff )
+#define comRX_BLOCK_TIME ( ( TickType_t ) 0xffff )
/* The sequence transmitted is from comFIRST_BYTE to and including comLAST_BYTE. */
-#define comFIRST_BYTE ( 'A' )
-#define comLAST_BYTE ( 'X' )
+#define comFIRST_BYTE ( 'A' )
+#define comLAST_BYTE ( 'X' )
-#define comBUFFER_LEN ( ( UBaseType_t ) ( comLAST_BYTE - comFIRST_BYTE ) + ( UBaseType_t ) 1 )
-#define comINITIAL_RX_COUNT_VALUE ( 0 )
+#define comBUFFER_LEN ( ( UBaseType_t ) ( comLAST_BYTE - comFIRST_BYTE ) + ( UBaseType_t ) 1 )
+#define comINITIAL_RX_COUNT_VALUE ( 0 )
/* Handle to the com port used by both tasks. */
static xComPortHandle xPort = NULL;
@@ -102,164 +102,165 @@ static portTASK_FUNCTION_PROTO( vComTxTask, pvParameters );
static portTASK_FUNCTION_PROTO( vComRxTask, pvParameters );
/* The LED that should be toggled by the Rx and Tx tasks. The Rx task will
-toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED
-( uxBaseLED + comTX_LED_OFFSET ). */
+ * toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task will toggle LED
+ * ( uxBaseLED + comTX_LED_OFFSET ). */
static UBaseType_t uxBaseLED = 0;
/* Check variable used to ensure no error have occurred. The Rx task will
-increment this variable after every successfully received sequence. If at any
-time the sequence is incorrect the the variable will stop being incremented. */
+ * increment this variable after every successfully received sequence. If at any
+ * time the sequence is incorrect the the variable will stop being incremented. */
static volatile UBaseType_t uxRxLoops = comINITIAL_RX_COUNT_VALUE;
/*-----------------------------------------------------------*/
-void vAltStartComTestTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED )
+void vAltStartComTestTasks( UBaseType_t uxPriority,
+ uint32_t ulBaudRate,
+ UBaseType_t uxLED )
{
- /* Initialise the com port then spawn the Rx and Tx tasks. */
- uxBaseLED = uxLED;
- xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );
+ /* Initialise the com port then spawn the Rx and Tx tasks. */
+ uxBaseLED = uxLED;
+ xSerialPortInitMinimal( ulBaudRate, comBUFFER_LEN );
- /* The Tx task is spawned with a lower priority than the Rx task. */
- xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( TaskHandle_t * ) NULL );
- xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+ /* The Tx task is spawned with a lower priority than the Rx task. */
+ xTaskCreate( vComTxTask, "COMTx", comSTACK_SIZE, NULL, uxPriority - 1, ( TaskHandle_t * ) NULL );
+ xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vComTxTask, pvParameters )
{
-char cByteToSend;
-TickType_t xTimeToWait;
-
- /* Just to stop compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Simply transmit a sequence of characters from comFIRST_BYTE to
- comLAST_BYTE. */
- for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )
- {
- if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )
- {
- vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
- }
- }
-
- /* Turn the LED off while we are not doing anything. */
- vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );
-
- /* We have posted all the characters in the string - wait before
- re-sending. Wait a pseudo-random time as this will provide a better
- test. */
- xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
-
- /* Make sure we don't wait too long... */
- xTimeToWait %= comTX_MAX_BLOCK_TIME;
-
- /* ...but we do want to wait. */
- if( xTimeToWait < comTX_MIN_BLOCK_TIME )
- {
- xTimeToWait = comTX_MIN_BLOCK_TIME;
- }
-
- vTaskDelay( xTimeToWait );
- }
+ char cByteToSend;
+ TickType_t xTimeToWait;
+
+ /* Just to stop compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Simply transmit a sequence of characters from comFIRST_BYTE to
+ * comLAST_BYTE. */
+ for( cByteToSend = comFIRST_BYTE; cByteToSend <= comLAST_BYTE; cByteToSend++ )
+ {
+ if( xSerialPutChar( xPort, cByteToSend, comNO_BLOCK ) == pdPASS )
+ {
+ vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
+ }
+ }
+
+ /* Turn the LED off while we are not doing anything. */
+ vParTestSetLED( uxBaseLED + comTX_LED_OFFSET, pdFALSE );
+
+ /* We have posted all the characters in the string - wait before
+ * re-sending. Wait a pseudo-random time as this will provide a better
+ * test. */
+ xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
+
+ /* Make sure we don't wait too long... */
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;
+
+ /* ...but we do want to wait. */
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )
+ {
+ xTimeToWait = comTX_MIN_BLOCK_TIME;
+ }
+
+ vTaskDelay( xTimeToWait );
+ }
} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vComRxTask, pvParameters )
{
-signed char cExpectedByte, cByteRxed;
-BaseType_t xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;
-
- /* Just to stop compiler warnings. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* We expect to receive the characters from comFIRST_BYTE to
- comLAST_BYTE in an incrementing order. Loop to receive each byte. */
- for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )
- {
- /* Block on the queue that contains received bytes until a byte is
- available. */
- if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )
- {
- /* Was this the byte we were expecting? If so, toggle the LED,
- otherwise we are out on sync and should break out of the loop
- until the expected character sequence is about to restart. */
- if( cByteRxed == cExpectedByte )
- {
- vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
- }
- else
- {
- xResyncRequired = pdTRUE;
- break; /*lint !e960 Non-switch break allowed. */
- }
- }
- }
-
- /* Turn the LED off while we are not doing anything. */
- vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );
-
- /* Did we break out of the loop because the characters were received in
- an unexpected order? If so wait here until the character sequence is
- about to restart. */
- if( xResyncRequired == pdTRUE )
- {
- while( cByteRxed != comLAST_BYTE )
- {
- /* Block until the next char is available. */
- xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );
- }
-
- /* Note that an error occurred which caused us to have to resync.
- We use this to stop incrementing the loop counter so
- sAreComTestTasksStillRunning() will return false - indicating an
- error. */
- xErrorOccurred++;
-
- /* We have now resynced with the Tx task and can continue. */
- xResyncRequired = pdFALSE;
- }
- else
- {
- if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )
- {
- /* Increment the count of successful loops. As error
- occurring (i.e. an unexpected character being received) will
- prevent this counter being incremented for the rest of the
- execution. Don't worry about mutual exclusion on this
- variable - it doesn't really matter as we just want it
- to change. */
- uxRxLoops++;
- }
- }
- }
+ signed char cExpectedByte, cByteRxed;
+ BaseType_t xResyncRequired = pdFALSE, xErrorOccurred = pdFALSE;
+
+ /* Just to stop compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* We expect to receive the characters from comFIRST_BYTE to
+ * comLAST_BYTE in an incrementing order. Loop to receive each byte. */
+ for( cExpectedByte = comFIRST_BYTE; cExpectedByte <= comLAST_BYTE; cExpectedByte++ )
+ {
+ /* Block on the queue that contains received bytes until a byte is
+ * available. */
+ if( xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME ) )
+ {
+ /* Was this the byte we were expecting? If so, toggle the LED,
+ * otherwise we are out on sync and should break out of the loop
+ * until the expected character sequence is about to restart. */
+ if( cByteRxed == cExpectedByte )
+ {
+ vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
+ }
+ else
+ {
+ xResyncRequired = pdTRUE;
+ break; /*lint !e960 Non-switch break allowed. */
+ }
+ }
+ }
+
+ /* Turn the LED off while we are not doing anything. */
+ vParTestSetLED( uxBaseLED + comRX_LED_OFFSET, pdFALSE );
+
+ /* Did we break out of the loop because the characters were received in
+ * an unexpected order? If so wait here until the character sequence is
+ * about to restart. */
+ if( xResyncRequired == pdTRUE )
+ {
+ while( cByteRxed != comLAST_BYTE )
+ {
+ /* Block until the next char is available. */
+ xSerialGetChar( xPort, &cByteRxed, comRX_BLOCK_TIME );
+ }
+
+ /* Note that an error occurred which caused us to have to resync.
+ * We use this to stop incrementing the loop counter so
+ * sAreComTestTasksStillRunning() will return false - indicating an
+ * error. */
+ xErrorOccurred++;
+
+ /* We have now resynced with the Tx task and can continue. */
+ xResyncRequired = pdFALSE;
+ }
+ else
+ {
+ if( xErrorOccurred < comTOTAL_PERMISSIBLE_ERRORS )
+ {
+ /* Increment the count of successful loops. As error
+ * occurring (i.e. an unexpected character being received) will
+ * prevent this counter being incremented for the rest of the
+ * execution. Don't worry about mutual exclusion on this
+ * variable - it doesn't really matter as we just want it
+ * to change. */
+ uxRxLoops++;
+ }
+ }
+ }
} /*lint !e715 !e818 pvParameters is required for a task function even if it is not referenced. */
/*-----------------------------------------------------------*/
BaseType_t xAreComTestTasksStillRunning( void )
{
-BaseType_t xReturn;
-
- /* If the count of successful reception loops has not changed than at
- some time an error occurred (i.e. a character was received out of sequence)
- and we will return false. */
- if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- /* Reset the count of successful Rx loops. When this function is called
- again we expect this to have been incremented. */
- uxRxLoops = comINITIAL_RX_COUNT_VALUE;
-
- return xReturn;
+ BaseType_t xReturn;
+
+ /* If the count of successful reception loops has not changed than at
+ * some time an error occurred (i.e. a character was received out of sequence)
+ * and we will return false. */
+ if( uxRxLoops == comINITIAL_RX_COUNT_VALUE )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ /* Reset the count of successful Rx loops. When this function is called
+ * again we expect this to have been incremented. */
+ uxRxLoops = comINITIAL_RX_COUNT_VALUE;
+
+ return xReturn;
}
-
diff --git a/Demo/Common/Minimal/comtest_strings.c b/Demo/Common/Minimal/comtest_strings.c
index 0c719cecf..6bca61b77 100644
--- a/Demo/Common/Minimal/comtest_strings.c
+++ b/Demo/Common/Minimal/comtest_strings.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
@@ -58,11 +57,11 @@
#include "timers.h"
#ifndef configUSE_TIMERS
- #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h.
+ #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h.
#endif
#if configUSE_TIMERS != 1
- #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h.
+ #error This demo uses timers. configUSE_TIMERS must be set to 1 in FreeRTOSConfig.h.
#endif
@@ -72,240 +71,246 @@
#include "partest.h"
/* The size of the stack given to the Rx task. */
-#define comSTACK_SIZE configMINIMAL_STACK_SIZE
+#define comSTACK_SIZE configMINIMAL_STACK_SIZE
-/* See the comment above the declaraction of the uxBaseLED variable. */
-#define comTX_LED_OFFSET ( 0 )
-#define comRX_LED_OFFSET ( 1 )
+/* See the comment above the declaration of the uxBaseLED variable. */
+#define comTX_LED_OFFSET ( 0 )
+#define comRX_LED_OFFSET ( 1 )
/* The Tx timer transmits the sequence of characters at a pseudo random
-interval that is capped between comTX_MAX_BLOCK_TIME and
-comTX_MIN_BLOCK_TIME. */
-#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x96 )
-#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0x32 )
-#define comOFFSET_TIME ( ( TickType_t ) 3 )
+ * interval that is capped between comTX_MAX_BLOCK_TIME and
+ * comTX_MIN_BLOCK_TIME. */
+#define comTX_MAX_BLOCK_TIME ( ( TickType_t ) 0x96 )
+#define comTX_MIN_BLOCK_TIME ( ( TickType_t ) 0x32 )
+#define comOFFSET_TIME ( ( TickType_t ) 3 )
/* States for the simple state machine implemented in the Rx task. */
-#define comtstWAITING_START_OF_STRING 0
-#define comtstWAITING_END_OF_STRING 1
+#define comtstWAITING_START_OF_STRING 0
+#define comtstWAITING_END_OF_STRING 1
/* A short delay in ticks - this delay is used to allow the Rx queue to fill up
-a bit so more than one character can be processed at a time. This is relative
-to comTX_MIN_BLOCK_TIME to ensure it is never longer than the shortest gap
-between transmissions. It could be worked out more scientifically from the
-baud rate being used. */
-#define comSHORT_DELAY ( comTX_MIN_BLOCK_TIME >> ( TickType_t ) 2 )
+ * a bit so more than one character can be processed at a time. This is relative
+ * to comTX_MIN_BLOCK_TIME to ensure it is never longer than the shortest gap
+ * between transmissions. It could be worked out more scientifically from the
+ * baud rate being used. */
+#define comSHORT_DELAY ( comTX_MIN_BLOCK_TIME >> ( TickType_t ) 2 )
/* The string that is transmitted and received. */
-#define comTRANSACTED_STRING "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ1234567890"
+#define comTRANSACTED_STRING "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ1234567890"
/* A block time of 0 simply means "don't block". */
-#define comtstDONT_BLOCK ( TickType_t ) 0
+#define comtstDONT_BLOCK ( TickType_t ) 0
/* Handle to the com port used by both tasks. */
static xComPortHandle xPort = NULL;
/* The callback function allocated to the transmit timer, as described in the
-comments at the top of this file. */
+ * comments at the top of this file. */
static void prvComTxTimerCallback( TimerHandle_t xTimer );
/* The receive task as described in the comments at the top of this file. */
-static void vComRxTask( void *pvParameters );
+static void vComRxTask( void * pvParameters );
/* The Rx task will toggle LED ( uxBaseLED + comRX_LED_OFFSET). The Tx task
-will toggle LED ( uxBaseLED + comTX_LED_OFFSET ). */
+ * will toggle LED ( uxBaseLED + comTX_LED_OFFSET ). */
static UBaseType_t uxBaseLED = 0;
/* The Rx task toggles uxRxLoops on each successful iteration of its defined
-function - provided no errors have ever been latched. If this variable stops
-incrementing, then an error has occurred. */
+ * function - provided no errors have ever been latched. If this variable stops
+ * incrementing, then an error has occurred. */
static volatile UBaseType_t uxRxLoops = 0UL;
/* The timer used to periodically transmit the string. This is the timer that
-has prvComTxTimerCallback allocated to it as its callback function. */
+ * has prvComTxTimerCallback allocated to it as its callback function. */
static TimerHandle_t xTxTimer = NULL;
/* The string length is held at file scope so the Tx timer does not need to
-calculate it each time it executes. */
+ * calculate it each time it executes. */
static size_t xStringLength = 0U;
/*-----------------------------------------------------------*/
-void vStartComTestStringsTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED )
+void vStartComTestStringsTasks( UBaseType_t uxPriority,
+ uint32_t ulBaudRate,
+ UBaseType_t uxLED )
{
- /* Store values that are used at run time. */
- uxBaseLED = uxLED;
-
- /* Calculate the string length here, rather than each time the Tx timer
- executes. */
- xStringLength = strlen( comTRANSACTED_STRING );
-
- /* Include the null terminator in the string length as this is used to
- detect the end of the string in the Rx task. */
- xStringLength++;
-
- /* Initialise the com port, then spawn the Rx task and create the Tx
- timer. */
- xSerialPortInitMinimal( ulBaudRate, ( xStringLength * 2U ) );
-
- /* Create the Rx task and the Tx timer. The timer is started from the
- Rx task. */
- xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
- xTxTimer = xTimerCreate( "TxTimer", comTX_MIN_BLOCK_TIME, pdFALSE, NULL, prvComTxTimerCallback );
- configASSERT( xTxTimer );
+ /* Store values that are used at run time. */
+ uxBaseLED = uxLED;
+
+ /* Calculate the string length here, rather than each time the Tx timer
+ * executes. */
+ xStringLength = strlen( comTRANSACTED_STRING );
+
+ /* Include the null terminator in the string length as this is used to
+ * detect the end of the string in the Rx task. */
+ xStringLength++;
+
+ /* Initialise the com port, then spawn the Rx task and create the Tx
+ * timer. */
+ xSerialPortInitMinimal( ulBaudRate, ( xStringLength * 2U ) );
+
+ /* Create the Rx task and the Tx timer. The timer is started from the
+ * Rx task. */
+ xTaskCreate( vComRxTask, "COMRx", comSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+ xTxTimer = xTimerCreate( "TxTimer", comTX_MIN_BLOCK_TIME, pdFALSE, NULL, prvComTxTimerCallback );
+ configASSERT( xTxTimer );
}
/*-----------------------------------------------------------*/
static void prvComTxTimerCallback( TimerHandle_t xTimer )
{
-TickType_t xTimeToWait;
+ TickType_t xTimeToWait;
- /* The parameter is not used in this case. */
- ( void ) xTimer;
+ /* The parameter is not used in this case. */
+ ( void ) xTimer;
- /* Send the string. How this is actually performed depends on the
- sample driver provided with this demo. However - as this is a timer,
- it executes in the context of the timer task and therefore must not
- block. */
- vSerialPutString( xPort, comTRANSACTED_STRING, xStringLength );
+ /* Send the string. How this is actually performed depends on the
+ * sample driver provided with this demo. However - as this is a timer,
+ * it executes in the context of the timer task and therefore must not
+ * block. */
+ vSerialPutString( xPort, comTRANSACTED_STRING, xStringLength );
- /* Toggle an LED to give a visible indication that another transmission
- has been performed. */
- vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
+ /* Toggle an LED to give a visible indication that another transmission
+ * has been performed. */
+ vParTestToggleLED( uxBaseLED + comTX_LED_OFFSET );
- /* Wait a pseudo random time before sending the string again. */
- xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
+ /* Wait a pseudo random time before sending the string again. */
+ xTimeToWait = xTaskGetTickCount() + comOFFSET_TIME;
- /* Ensure the time to wait is not greater than comTX_MAX_BLOCK_TIME. */
- xTimeToWait %= comTX_MAX_BLOCK_TIME;
+ /* Ensure the time to wait is not greater than comTX_MAX_BLOCK_TIME. */
+ xTimeToWait %= comTX_MAX_BLOCK_TIME;
- /* Ensure the time to wait is not less than comTX_MIN_BLOCK_TIME. */
- if( xTimeToWait < comTX_MIN_BLOCK_TIME )
- {
- xTimeToWait = comTX_MIN_BLOCK_TIME;
- }
+ /* Ensure the time to wait is not less than comTX_MIN_BLOCK_TIME. */
+ if( xTimeToWait < comTX_MIN_BLOCK_TIME )
+ {
+ xTimeToWait = comTX_MIN_BLOCK_TIME;
+ }
- /* Reset the timer to run again xTimeToWait ticks from now. This function
- is called from the context of the timer task, so the block time must not
- be anything other than zero. */
- xTimerChangePeriod( xTxTimer, xTimeToWait, comtstDONT_BLOCK );
+ /* Reset the timer to run again xTimeToWait ticks from now. This function
+ * is called from the context of the timer task, so the block time must not
+ * be anything other than zero. */
+ xTimerChangePeriod( xTxTimer, xTimeToWait, comtstDONT_BLOCK );
}
/*-----------------------------------------------------------*/
-static void vComRxTask( void *pvParameters )
+static void vComRxTask( void * pvParameters )
{
-BaseType_t xState = comtstWAITING_START_OF_STRING, xErrorOccurred = pdFALSE;
-char *pcExpectedByte, cRxedChar;
-const xComPortHandle xPort = NULL;
-
- /* The parameter is not used in this example. */
- ( void ) pvParameters;
-
- /* Start the Tx timer. This only needs to be started once, as it will
- reset itself thereafter. */
- xTimerStart( xTxTimer, portMAX_DELAY );
-
- /* The first expected Rx character is the first in the string that is
- transmitted. */
- pcExpectedByte = comTRANSACTED_STRING;
-
- for( ;; )
- {
- /* Wait for the next character. */
- if( xSerialGetChar( xPort, &cRxedChar, ( comTX_MAX_BLOCK_TIME * 2 ) ) == pdFALSE )
- {
- /* A character definitely should have been received by now. As a
- character was not received an error must have occurred (which might
- just be that the loopback connector is not fitted). */
- xErrorOccurred = pdTRUE;
- }
-
- switch( xState )
- {
- case comtstWAITING_START_OF_STRING:
- if( cRxedChar == *pcExpectedByte )
- {
- /* The received character was the first character of the
- string. Move to the next state to check each character
- as it comes in until the entire string has been received. */
- xState = comtstWAITING_END_OF_STRING;
- pcExpectedByte++;
-
- /* Block for a short period. This just allows the Rx queue
- to contain more than one character, and therefore prevent
- thrashing reads to the queue, and repetitive context
- switches as each character is received. */
- vTaskDelay( comSHORT_DELAY );
- }
- break;
-
- case comtstWAITING_END_OF_STRING:
- if( cRxedChar == *pcExpectedByte )
- {
- /* The received character was the expected character. Was
- it the last character in the string - i.e. the null
- terminator? */
- if( cRxedChar == 0x00 )
- {
- /* The entire string has been received. If no errors
- have been latched, then increment the loop counter to
- show this task is still healthy. */
- if( xErrorOccurred == pdFALSE )
- {
- uxRxLoops++;
-
- /* Toggle an LED to give a visible sign that a
- complete string has been received. */
- vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
- }
-
- /* Go back to wait for the start of the next string. */
- pcExpectedByte = comTRANSACTED_STRING;
- xState = comtstWAITING_START_OF_STRING;
- }
- else
- {
- /* Wait for the next character in the string. */
- pcExpectedByte++;
- }
- }
- else
- {
- /* The character received was not that expected. */
- xErrorOccurred = pdTRUE;
- }
- break;
-
- default:
- /* Should not get here. Stop the Rx loop counter from
- incrementing to latch the error. */
- xErrorOccurred = pdTRUE;
- break;
- }
- }
+ BaseType_t xState = comtstWAITING_START_OF_STRING, xErrorOccurred = pdFALSE;
+ char * pcExpectedByte, cRxedChar;
+ const xComPortHandle xPort = NULL;
+
+ /* The parameter is not used in this example. */
+ ( void ) pvParameters;
+
+ /* Start the Tx timer. This only needs to be started once, as it will
+ * reset itself thereafter. */
+ xTimerStart( xTxTimer, portMAX_DELAY );
+
+ /* The first expected Rx character is the first in the string that is
+ * transmitted. */
+ pcExpectedByte = comTRANSACTED_STRING;
+
+ for( ; ; )
+ {
+ /* Wait for the next character. */
+ if( xSerialGetChar( xPort, &cRxedChar, ( comTX_MAX_BLOCK_TIME * 2 ) ) == pdFALSE )
+ {
+ /* A character definitely should have been received by now. As a
+ * character was not received an error must have occurred (which might
+ * just be that the loopback connector is not fitted). */
+ xErrorOccurred = pdTRUE;
+ }
+
+ switch( xState )
+ {
+ case comtstWAITING_START_OF_STRING:
+
+ if( cRxedChar == *pcExpectedByte )
+ {
+ /* The received character was the first character of the
+ * string. Move to the next state to check each character
+ * as it comes in until the entire string has been received. */
+ xState = comtstWAITING_END_OF_STRING;
+ pcExpectedByte++;
+
+ /* Block for a short period. This just allows the Rx queue
+ * to contain more than one character, and therefore prevent
+ * thrashing reads to the queue, and repetitive context
+ * switches as each character is received. */
+ vTaskDelay( comSHORT_DELAY );
+ }
+
+ break;
+
+ case comtstWAITING_END_OF_STRING:
+
+ if( cRxedChar == *pcExpectedByte )
+ {
+ /* The received character was the expected character. Was
+ * it the last character in the string - i.e. the null
+ * terminator? */
+ if( cRxedChar == 0x00 )
+ {
+ /* The entire string has been received. If no errors
+ * have been latched, then increment the loop counter to
+ * show this task is still healthy. */
+ if( xErrorOccurred == pdFALSE )
+ {
+ uxRxLoops++;
+
+ /* Toggle an LED to give a visible sign that a
+ * complete string has been received. */
+ vParTestToggleLED( uxBaseLED + comRX_LED_OFFSET );
+ }
+
+ /* Go back to wait for the start of the next string. */
+ pcExpectedByte = comTRANSACTED_STRING;
+ xState = comtstWAITING_START_OF_STRING;
+ }
+ else
+ {
+ /* Wait for the next character in the string. */
+ pcExpectedByte++;
+ }
+ }
+ else
+ {
+ /* The character received was not that expected. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ break;
+
+ default:
+
+ /* Should not get here. Stop the Rx loop counter from
+ * incrementing to latch the error. */
+ xErrorOccurred = pdTRUE;
+ break;
+ }
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xAreComTestTasksStillRunning( void )
{
-BaseType_t xReturn;
-
- /* If the count of successful reception loops has not changed than at
- some time an error occurred (i.e. a character was received out of sequence)
- and false is returned. */
- if( uxRxLoops == 0UL )
- {
- xReturn = pdFALSE;
- }
- else
- {
- xReturn = pdTRUE;
- }
-
- /* Reset the count of successful Rx loops. When this function is called
- again it should have been incremented again. */
- uxRxLoops = 0UL;
-
- return xReturn;
+ BaseType_t xReturn;
+
+ /* If the count of successful reception loops has not changed than at
+ * some time an error occurred (i.e. a character was received out of sequence)
+ * and false is returned. */
+ if( uxRxLoops == 0UL )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ /* Reset the count of successful Rx loops. When this function is called
+ * again it should have been incremented again. */
+ uxRxLoops = 0UL;
+
+ return xReturn;
}
-
diff --git a/Demo/Common/Minimal/countsem.c b/Demo/Common/Minimal/countsem.c
index 14f59c387..ad52e50a1 100644
--- a/Demo/Common/Minimal/countsem.c
+++ b/Demo/Common/Minimal/countsem.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -39,24 +39,24 @@
#include "countsem.h"
/* The maximum count value that the semaphore used for the demo can hold. */
-#define countMAX_COUNT_VALUE ( 200 )
+#define countMAX_COUNT_VALUE ( 200 )
/* Constants used to indicate whether or not the semaphore should have been
-created with its maximum count value, or its minimum count value. These
-numbers are used to ensure that the pointers passed in as the task parameters
-are valid. */
-#define countSTART_AT_MAX_COUNT ( 0xaa )
-#define countSTART_AT_ZERO ( 0x55 )
+ * created with its maximum count value, or its minimum count value. These
+ * numbers are used to ensure that the pointers passed in as the task parameters
+ * are valid. */
+#define countSTART_AT_MAX_COUNT ( 0xaa )
+#define countSTART_AT_ZERO ( 0x55 )
/* Two tasks are created for the test. One uses a semaphore created with its
-count value set to the maximum, and one with the count value set to zero. */
-#define countNUM_TEST_TASKS ( 2 )
-#define countDONT_BLOCK ( 0 )
+ * count value set to the maximum, and one with the count value set to zero. */
+#define countNUM_TEST_TASKS ( 2 )
+#define countDONT_BLOCK ( 0 )
/*-----------------------------------------------------------*/
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
-detected in any of the tasks. */
+ * detected in any of the tasks. */
static volatile BaseType_t xErrorDetected = pdFALSE;
/*-----------------------------------------------------------*/
@@ -67,36 +67,38 @@ static volatile BaseType_t xErrorDetected = pdFALSE;
* 'take' is inspected, with an error being flagged if it is found not to be
* the expected result.
*/
-static void prvCountingSemaphoreTask( void *pvParameters );
+static void prvCountingSemaphoreTask( void * pvParameters );
/*
* Utility function to increment the semaphore count value up from zero to
* countMAX_COUNT_VALUE.
*/
-static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter );
+static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore,
+ volatile UBaseType_t * puxLoopCounter );
/*
* Utility function to decrement the semaphore count value up from
* countMAX_COUNT_VALUE to zero.
*/
-static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter );
+static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore,
+ volatile UBaseType_t * puxLoopCounter );
/*-----------------------------------------------------------*/
/* The structure that is passed into the task as the task parameter. */
typedef struct COUNT_SEM_STRUCT
{
- /* The semaphore to be used for the demo. */
- SemaphoreHandle_t xSemaphore;
+ /* The semaphore to be used for the demo. */
+ SemaphoreHandle_t xSemaphore;
- /* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with
- its count value set to its max count value, or countSTART_AT_ZERO if it
- should have been created with its count value set to 0. */
- UBaseType_t uxExpectedStartCount;
+ /* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with
+ * its count value set to its max count value, or countSTART_AT_ZERO if it
+ * should have been created with its count value set to 0. */
+ UBaseType_t uxExpectedStartCount;
- /* Incremented on each cycle of the demo task. Used to detect a stalled
- task. */
- volatile UBaseType_t uxLoopCounter;
+ /* Incremented on each cycle of the demo task. Used to detect a stalled
+ * task. */
+ volatile UBaseType_t uxLoopCounter;
} xCountSemStruct;
/* Two structures are defined, one is passed to each test task. */
@@ -106,183 +108,184 @@ static xCountSemStruct xParameters[ countNUM_TEST_TASKS ];
void vStartCountingSemaphoreTasks( void )
{
- /* Create the semaphores that we are going to use for the test/demo. The
- first should be created such that it starts at its maximum count value,
- the second should be created such that it starts with a count value of zero. */
- xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE );
- xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT;
- xParameters[ 0 ].uxLoopCounter = 0;
-
- xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 );
- xParameters[ 1 ].uxExpectedStartCount = 0;
- xParameters[ 1 ].uxLoopCounter = 0;
-
- /* Were the semaphores created? */
- if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) )
- {
- /* vQueueAddToRegistry() adds the semaphore to the registry, if one is
- in use. The registry is provided as a means for kernel aware
- debuggers to locate semaphores and has no purpose if a kernel aware
- debugger is not being used. The call to vQueueAddToRegistry() will be
- removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
- defined or is defined to be less than 1. */
- vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 0 ].xSemaphore, "Counting_Sem_1" );
- vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 1 ].xSemaphore, "Counting_Sem_2" );
-
- /* Create the demo tasks, passing in the semaphore to use as the parameter. */
- xTaskCreate( prvCountingSemaphoreTask, "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL );
- xTaskCreate( prvCountingSemaphoreTask, "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL );
- }
+ /* Create the semaphores that we are going to use for the test/demo. The
+ * first should be created such that it starts at its maximum count value,
+ * the second should be created such that it starts with a count value of zero. */
+ xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE );
+ xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT;
+ xParameters[ 0 ].uxLoopCounter = 0;
+
+ xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 );
+ xParameters[ 1 ].uxExpectedStartCount = 0;
+ xParameters[ 1 ].uxLoopCounter = 0;
+
+ /* Were the semaphores created? */
+ if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) )
+ {
+ /* vQueueAddToRegistry() adds the semaphore to the registry, if one is
+ * in use. The registry is provided as a means for kernel aware
+ * debuggers to locate semaphores and has no purpose if a kernel aware
+ * debugger is not being used. The call to vQueueAddToRegistry() will be
+ * removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+ * defined or is defined to be less than 1. */
+ vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 0 ].xSemaphore, "Counting_Sem_1" );
+ vQueueAddToRegistry( ( QueueHandle_t ) xParameters[ 1 ].xSemaphore, "Counting_Sem_2" );
+
+ /* Create the demo tasks, passing in the semaphore to use as the parameter. */
+ xTaskCreate( prvCountingSemaphoreTask, "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvCountingSemaphoreTask, "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter )
+static void prvDecrementSemaphoreCount( SemaphoreHandle_t xSemaphore,
+ volatile UBaseType_t * puxLoopCounter )
{
-UBaseType_t ux;
-
- /* If the semaphore count is at its maximum then we should not be able to
- 'give' the semaphore. */
- if( xSemaphoreGive( xSemaphore ) == pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */
- for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
- {
- configASSERT( uxSemaphoreGetCount( xSemaphore ) == ( countMAX_COUNT_VALUE - ux ) );
-
- if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS )
- {
- /* We expected to be able to take the semaphore. */
- xErrorDetected = pdTRUE;
- }
-
- ( *puxLoopCounter )++;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* If the semaphore count is zero then we should not be able to 'take'
- the semaphore. */
- configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );
- if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
+ UBaseType_t ux;
+
+ /* If the semaphore count is at its maximum then we should not be able to
+ * 'give' the semaphore. */
+ if( xSemaphoreGive( xSemaphore ) == pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */
+ for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
+ {
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == ( countMAX_COUNT_VALUE - ux ) );
+
+ if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS )
+ {
+ /* We expected to be able to take the semaphore. */
+ xErrorDetected = pdTRUE;
+ }
+
+ ( *puxLoopCounter )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the semaphore count is zero then we should not be able to 'take'
+ * the semaphore. */
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == 0 );
+
+ if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
}
/*-----------------------------------------------------------*/
-static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore, volatile UBaseType_t *puxLoopCounter )
+static void prvIncrementSemaphoreCount( SemaphoreHandle_t xSemaphore,
+ volatile UBaseType_t * puxLoopCounter )
{
-UBaseType_t ux;
-
- /* If the semaphore count is zero then we should not be able to 'take'
- the semaphore. */
- if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- /* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */
- for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
- {
- configASSERT( uxSemaphoreGetCount( xSemaphore ) == ux );
-
- if( xSemaphoreGive( xSemaphore ) != pdPASS )
- {
- /* We expected to be able to take the semaphore. */
- xErrorDetected = pdTRUE;
- }
-
- ( *puxLoopCounter )++;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* If the semaphore count is at its maximum then we should not be able to
- 'give' the semaphore. */
- if( xSemaphoreGive( xSemaphore ) == pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
+ UBaseType_t ux;
+
+ /* If the semaphore count is zero then we should not be able to 'take'
+ * the semaphore. */
+ if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ /* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */
+ for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )
+ {
+ configASSERT( uxSemaphoreGetCount( xSemaphore ) == ux );
+
+ if( xSemaphoreGive( xSemaphore ) != pdPASS )
+ {
+ /* We expected to be able to take the semaphore. */
+ xErrorDetected = pdTRUE;
+ }
+
+ ( *puxLoopCounter )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the semaphore count is at its maximum then we should not be able to
+ * 'give' the semaphore. */
+ if( xSemaphoreGive( xSemaphore ) == pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
}
/*-----------------------------------------------------------*/
-static void prvCountingSemaphoreTask( void *pvParameters )
+static void prvCountingSemaphoreTask( void * pvParameters )
{
-xCountSemStruct *pxParameter;
-
- #ifdef USE_STDIO
- void vPrintDisplayMessage( const char * const * ppcMessageToSend );
-
- const char * const pcTaskStartMsg = "Counting semaphore demo started.\r\n";
-
- /* Queue a message for printing to say the task has started. */
- vPrintDisplayMessage( &pcTaskStartMsg );
- #endif
-
- /* The semaphore to be used was passed as the parameter. */
- pxParameter = ( xCountSemStruct * ) pvParameters;
-
- /* Did we expect to find the semaphore already at its max count value, or
- at zero? */
- if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT )
- {
- prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
- }
-
- /* Now we expect the semaphore count to be 0, so this time there is an
- error if we can take the semaphore. */
- if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS )
- {
- xErrorDetected = pdTRUE;
- }
-
- for( ;; )
- {
- prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
- prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
- }
+ xCountSemStruct * pxParameter;
+
+ #ifdef USE_STDIO
+ void vPrintDisplayMessage( const char * const * ppcMessageToSend );
+
+ const char * const pcTaskStartMsg = "Counting semaphore demo started.\r\n";
+
+ /* Queue a message for printing to say the task has started. */
+ vPrintDisplayMessage( &pcTaskStartMsg );
+ #endif
+
+ /* The semaphore to be used was passed as the parameter. */
+ pxParameter = ( xCountSemStruct * ) pvParameters;
+
+ /* Did we expect to find the semaphore already at its max count value, or
+ * at zero? */
+ if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT )
+ {
+ prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
+ }
+
+ /* Now we expect the semaphore count to be 0, so this time there is an
+ * error if we can take the semaphore. */
+ if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS )
+ {
+ xErrorDetected = pdTRUE;
+ }
+
+ for( ; ; )
+ {
+ prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
+ prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );
+ }
}
/*-----------------------------------------------------------*/
BaseType_t xAreCountingSemaphoreTasksStillRunning( void )
{
-static UBaseType_t uxLastCount0 = 0, uxLastCount1 = 0;
-BaseType_t xReturn = pdPASS;
-
- /* Return fail if any 'give' or 'take' did not result in the expected
- behaviour. */
- if( xErrorDetected != pdFALSE )
- {
- xReturn = pdFAIL;
- }
-
- /* Return fail if either task is not still incrementing its loop counter. */
- if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter )
- {
- xReturn = pdFAIL;
- }
- else
- {
- uxLastCount0 = xParameters[ 0 ].uxLoopCounter;
- }
-
- if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter )
- {
- xReturn = pdFAIL;
- }
- else
- {
- uxLastCount1 = xParameters[ 1 ].uxLoopCounter;
- }
-
- return xReturn;
+ static UBaseType_t uxLastCount0 = 0, uxLastCount1 = 0;
+ BaseType_t xReturn = pdPASS;
+
+ /* Return fail if any 'give' or 'take' did not result in the expected
+ * behaviour. */
+ if( xErrorDetected != pdFALSE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Return fail if either task is not still incrementing its loop counter. */
+ if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ uxLastCount0 = xParameters[ 0 ].uxLoopCounter;
+ }
+
+ if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ uxLastCount1 = xParameters[ 1 ].uxLoopCounter;
+ }
+
+ return xReturn;
}
-
-
diff --git a/Demo/Common/Minimal/crflash.c b/Demo/Common/Minimal/crflash.c
index 366210565..6db03a1a0 100644
--- a/Demo/Common/Minimal/crflash.c
+++ b/Demo/Common/Minimal/crflash.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -61,34 +61,36 @@
#include "crflash.h"
/* The queue should only need to be of length 1. See the description at the
-top of the file. */
-#define crfQUEUE_LENGTH 1
+ * top of the file. */
+#define crfQUEUE_LENGTH 1
-#define crfFIXED_DELAY_PRIORITY 0
-#define crfFLASH_PRIORITY 1
+#define crfFIXED_DELAY_PRIORITY 0
+#define crfFLASH_PRIORITY 1
/* Only one flash co-routine is created so the index is not significant. */
-#define crfFLASH_INDEX 0
+#define crfFLASH_INDEX 0
/* Don't allow more than crfMAX_FLASH_TASKS 'fixed delay' co-routines to be
-created. */
-#define crfMAX_FLASH_TASKS 8
+ * created. */
+#define crfMAX_FLASH_TASKS 8
/* We don't want to block when posting to the queue. */
-#define crfPOSTING_BLOCK_TIME 0
+#define crfPOSTING_BLOCK_TIME 0
/*
* The 'fixed delay' co-routine as described at the top of the file.
*/
-static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex );
+static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex );
/*
* The 'flash' co-routine as described at the top of the file.
*/
-static void prvFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex );
+static void prvFlashCoRoutine( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex );
/* The queue used to pass data between the 'fixed delay' co-routines and the
-'flash' co-routine. */
+ * 'flash' co-routine. */
static QueueHandle_t xFlashQueue;
/* This will be set to pdFALSE if we detect an error. */
@@ -101,108 +103,113 @@ static BaseType_t xCoRoutineFlashStatus = pdPASS;
*/
void vStartFlashCoRoutines( UBaseType_t uxNumberToCreate )
{
-UBaseType_t uxIndex;
-
- if( uxNumberToCreate > crfMAX_FLASH_TASKS )
- {
- uxNumberToCreate = crfMAX_FLASH_TASKS;
- }
-
- /* Create the queue used to pass data between the co-routines. */
- xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( UBaseType_t ) );
-
- if( xFlashQueue )
- {
- /* Create uxNumberToCreate 'fixed delay' co-routines. */
- for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ )
- {
- xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex );
- }
-
- /* Create the 'flash' co-routine. */
- xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX );
- }
+ UBaseType_t uxIndex;
+
+ if( uxNumberToCreate > crfMAX_FLASH_TASKS )
+ {
+ uxNumberToCreate = crfMAX_FLASH_TASKS;
+ }
+
+ /* Create the queue used to pass data between the co-routines. */
+ xFlashQueue = xQueueCreate( crfQUEUE_LENGTH, sizeof( UBaseType_t ) );
+
+ if( xFlashQueue )
+ {
+ /* Create uxNumberToCreate 'fixed delay' co-routines. */
+ for( uxIndex = 0; uxIndex < uxNumberToCreate; uxIndex++ )
+ {
+ xCoRoutineCreate( prvFixedDelayCoRoutine, crfFIXED_DELAY_PRIORITY, uxIndex );
+ }
+
+ /* Create the 'flash' co-routine. */
+ xCoRoutineCreate( prvFlashCoRoutine, crfFLASH_PRIORITY, crfFLASH_INDEX );
+ }
}
/*-----------------------------------------------------------*/
-static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+static void prvFixedDelayCoRoutine( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex )
{
/* Even though this is a co-routine the xResult variable does not need to be
-static as we do not need it to maintain its state between blocks. */
-BaseType_t xResult;
+ * static as we do not need it to maintain its state between blocks. */
+ BaseType_t xResult;
+
/* The uxIndex parameter of the co-routine function is used as an index into
-the xFlashRates array to obtain the delay period to use. */
-static const TickType_t xFlashRates[ crfMAX_FLASH_TASKS ] = { 150 / portTICK_PERIOD_MS,
- 200 / portTICK_PERIOD_MS,
- 250 / portTICK_PERIOD_MS,
- 300 / portTICK_PERIOD_MS,
- 350 / portTICK_PERIOD_MS,
- 400 / portTICK_PERIOD_MS,
- 450 / portTICK_PERIOD_MS,
- 500 / portTICK_PERIOD_MS };
-
- /* Co-routines MUST start with a call to crSTART. */
- crSTART( xHandle );
-
- for( ;; )
- {
- /* Post our uxIndex value onto the queue. This is used as the LED to
- flash. */
- crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult );
-
- if( xResult != pdPASS )
- {
- /* For the reasons stated at the top of the file we should always
- find that we can post to the queue. If we could not then an error
- has occurred. */
- xCoRoutineFlashStatus = pdFAIL;
- }
-
- crDELAY( xHandle, xFlashRates[ uxIndex ] );
- }
-
- /* Co-routines MUST end with a call to crEND. */
- crEND();
+ * the xFlashRates array to obtain the delay period to use. */
+ static const TickType_t xFlashRates[ crfMAX_FLASH_TASKS ] =
+ {
+ 150 / portTICK_PERIOD_MS,
+ 200 / portTICK_PERIOD_MS,
+ 250 / portTICK_PERIOD_MS,
+ 300 / portTICK_PERIOD_MS,
+ 350 / portTICK_PERIOD_MS,
+ 400 / portTICK_PERIOD_MS,
+ 450 / portTICK_PERIOD_MS,
+ 500 / portTICK_PERIOD_MS
+ };
+
+ /* Co-routines MUST start with a call to crSTART. */
+ crSTART( xHandle );
+
+ for( ; ; )
+ {
+ /* Post our uxIndex value onto the queue. This is used as the LED to
+ * flash. */
+ crQUEUE_SEND( xHandle, xFlashQueue, ( void * ) &uxIndex, crfPOSTING_BLOCK_TIME, &xResult );
+
+ if( xResult != pdPASS )
+ {
+ /* For the reasons stated at the top of the file we should always
+ * find that we can post to the queue. If we could not then an error
+ * has occurred. */
+ xCoRoutineFlashStatus = pdFAIL;
+ }
+
+ crDELAY( xHandle, xFlashRates[ uxIndex ] );
+ }
+
+ /* Co-routines MUST end with a call to crEND. */
+ crEND();
}
/*-----------------------------------------------------------*/
-static void prvFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+static void prvFlashCoRoutine( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex )
{
/* Even though this is a co-routine the variable do not need to be
-static as we do not need it to maintain their state between blocks. */
-BaseType_t xResult;
-UBaseType_t uxLEDToFlash;
-
- /* Co-routines MUST start with a call to crSTART. */
- crSTART( xHandle );
- ( void ) uxIndex;
-
- for( ;; )
- {
- /* Block to wait for the number of the LED to flash. */
- crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
- if( xResult != pdPASS )
- {
- /* We would not expect to wake unless we received something. */
- xCoRoutineFlashStatus = pdFAIL;
- }
- else
- {
- /* We received the number of an LED to flash - flash it! */
- vParTestToggleLED( uxLEDToFlash );
- }
- }
-
- /* Co-routines MUST end with a call to crEND. */
- crEND();
+ * static as we do not need it to maintain their state between blocks. */
+ BaseType_t xResult;
+ UBaseType_t uxLEDToFlash;
+
+ /* Co-routines MUST start with a call to crSTART. */
+ crSTART( xHandle );
+ ( void ) uxIndex;
+
+ for( ; ; )
+ {
+ /* Block to wait for the number of the LED to flash. */
+ crQUEUE_RECEIVE( xHandle, xFlashQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+ if( xResult != pdPASS )
+ {
+ /* We would not expect to wake unless we received something. */
+ xCoRoutineFlashStatus = pdFAIL;
+ }
+ else
+ {
+ /* We received the number of an LED to flash - flash it! */
+ vParTestToggleLED( uxLEDToFlash );
+ }
+ }
+
+ /* Co-routines MUST end with a call to crEND. */
+ crEND();
}
/*-----------------------------------------------------------*/
BaseType_t xAreFlashCoRoutinesStillRunning( void )
{
- /* Return pdPASS or pdFAIL depending on whether an error has been detected
- or not. */
- return xCoRoutineFlashStatus;
+ /* Return pdPASS or pdFAIL depending on whether an error has been detected
+ * or not. */
+ return xCoRoutineFlashStatus;
}
-
diff --git a/Demo/Common/Minimal/crhook.c b/Demo/Common/Minimal/crhook.c
index fe7d4560c..150a8eec3 100644
--- a/Demo/Common/Minimal/crhook.c
+++ b/Demo/Common/Minimal/crhook.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -57,27 +57,28 @@
#include "crhook.h"
/* The number of 'hook' co-routines that are to be created. */
-#define hookNUM_HOOK_CO_ROUTINES ( 4 )
+#define hookNUM_HOOK_CO_ROUTINES ( 4 )
/* The number of times the tick hook should be called before a character is
-posted to the 'hook' co-routines. */
-#define hookTICK_CALLS_BEFORE_POST ( 500 )
+ * posted to the 'hook' co-routines. */
+#define hookTICK_CALLS_BEFORE_POST ( 500 )
/* There should never be more than one item in any queue at any time. */
-#define hookHOOK_QUEUE_LENGTH ( 1 )
+#define hookHOOK_QUEUE_LENGTH ( 1 )
/* Don't block when initially posting to the queue. */
-#define hookNO_BLOCK_TIME ( 0 )
+#define hookNO_BLOCK_TIME ( 0 )
/* The priority relative to other co-routines (rather than tasks) that the
-'hook' co-routines should take. */
-#define mainHOOK_CR_PRIORITY ( 1 )
+ * 'hook' co-routines should take. */
+#define mainHOOK_CR_PRIORITY ( 1 )
/*-----------------------------------------------------------*/
/*
* The co-routine function itself.
*/
-static void prvHookCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex );
+static void prvHookCoRoutine( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex );
/*
@@ -90,13 +91,13 @@ void vApplicationTickHook( void );
/*-----------------------------------------------------------*/
/* Queues used to send data FROM a co-routine TO the tick hook function.
-The hook functions received (Rx's) on these queues. One queue per
-'hook' co-routine. */
+ * The hook functions received (Rx's) on these queues. One queue per
+ * 'hook' co-routine. */
static QueueHandle_t xHookRxQueues[ hookNUM_HOOK_CO_ROUTINES ];
/* Queues used to send data FROM the tick hook TO a co-routine function.
-The hood function transmits (Tx's) on these queues. One queue per
-'hook' co-routine. */
+ * The hood function transmits (Tx's) on these queues. One queue per
+ * 'hook' co-routine. */
static QueueHandle_t xHookTxQueues[ hookNUM_HOOK_CO_ROUTINES ];
/* Set to true if an error is detected at any time. */
@@ -106,127 +107,128 @@ static BaseType_t xCoRoutineErrorDetected = pdFALSE;
void vStartHookCoRoutines( void )
{
-UBaseType_t uxIndex, uxValueToPost = 0;
-
- for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ )
- {
- /* Create a queue to transmit to and receive from each 'hook'
- co-routine. */
- xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) );
- xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) );
-
- /* To start things off the tick hook function expects the queue it
- uses to receive data to contain a value. */
- xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME );
-
- /* Create the 'hook' co-routine itself. */
- xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex );
- }
+ UBaseType_t uxIndex, uxValueToPost = 0;
+
+ for( uxIndex = 0; uxIndex < hookNUM_HOOK_CO_ROUTINES; uxIndex++ )
+ {
+ /* Create a queue to transmit to and receive from each 'hook'
+ * co-routine. */
+ xHookRxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) );
+ xHookTxQueues[ uxIndex ] = xQueueCreate( hookHOOK_QUEUE_LENGTH, sizeof( UBaseType_t ) );
+
+ /* To start things off the tick hook function expects the queue it
+ * uses to receive data to contain a value. */
+ xQueueSend( xHookRxQueues[ uxIndex ], &uxValueToPost, hookNO_BLOCK_TIME );
+
+ /* Create the 'hook' co-routine itself. */
+ xCoRoutineCreate( prvHookCoRoutine, mainHOOK_CR_PRIORITY, uxIndex );
+ }
}
/*-----------------------------------------------------------*/
static UBaseType_t uxCallCounter = 0, uxNumberToPost = 0;
void vApplicationTickHook( void )
{
-UBaseType_t uxReceivedNumber;
-BaseType_t xIndex, xCoRoutineWoken;
-
- /* Is it time to talk to the 'hook' co-routines again? */
- uxCallCounter++;
- if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST )
- {
- uxCallCounter = 0;
-
- for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
- {
- xCoRoutineWoken = pdFALSE;
- if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS )
- {
- /* There is no reason why we would not expect the queue to
- contain a value. */
- xCoRoutineErrorDetected = pdTRUE;
- }
- else
- {
- /* Each queue used to receive data from the 'hook' co-routines
- should contain the number we last posted to the same co-routine. */
- if( uxReceivedNumber != uxNumberToPost )
- {
- xCoRoutineErrorDetected = pdTRUE;
- }
-
- /* Nothing should be blocked waiting to post to the queue. */
- if( xCoRoutineWoken != pdFALSE )
- {
- xCoRoutineErrorDetected = pdTRUE;
- }
- }
- }
-
- /* Start the next cycle by posting the next number onto each Tx queue. */
- uxNumberToPost++;
-
- for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
- {
- if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE )
- {
- /* Posting to the queue should have woken the co-routine that
- was blocked on the queue. */
- xCoRoutineErrorDetected = pdTRUE;
- }
- }
- }
+ UBaseType_t uxReceivedNumber;
+ BaseType_t xIndex, xCoRoutineWoken;
+
+ /* Is it time to talk to the 'hook' co-routines again? */
+ uxCallCounter++;
+
+ if( uxCallCounter >= hookTICK_CALLS_BEFORE_POST )
+ {
+ uxCallCounter = 0;
+
+ for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
+ {
+ xCoRoutineWoken = pdFALSE;
+
+ if( crQUEUE_RECEIVE_FROM_ISR( xHookRxQueues[ xIndex ], &uxReceivedNumber, &xCoRoutineWoken ) != pdPASS )
+ {
+ /* There is no reason why we would not expect the queue to
+ * contain a value. */
+ xCoRoutineErrorDetected = pdTRUE;
+ }
+ else
+ {
+ /* Each queue used to receive data from the 'hook' co-routines
+ * should contain the number we last posted to the same co-routine. */
+ if( uxReceivedNumber != uxNumberToPost )
+ {
+ xCoRoutineErrorDetected = pdTRUE;
+ }
+
+ /* Nothing should be blocked waiting to post to the queue. */
+ if( xCoRoutineWoken != pdFALSE )
+ {
+ xCoRoutineErrorDetected = pdTRUE;
+ }
+ }
+ }
+
+ /* Start the next cycle by posting the next number onto each Tx queue. */
+ uxNumberToPost++;
+
+ for( xIndex = 0; xIndex < hookNUM_HOOK_CO_ROUTINES; xIndex++ )
+ {
+ if( crQUEUE_SEND_FROM_ISR( xHookTxQueues[ xIndex ], &uxNumberToPost, pdFALSE ) != pdTRUE )
+ {
+ /* Posting to the queue should have woken the co-routine that
+ * was blocked on the queue. */
+ xCoRoutineErrorDetected = pdTRUE;
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvHookCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+static void prvHookCoRoutine( CoRoutineHandle_t xHandle,
+ UBaseType_t uxIndex )
{
-static UBaseType_t uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ];
-BaseType_t xResult;
-
- /* Each co-routine MUST start with a call to crSTART(); */
- crSTART( xHandle );
-
- for( ;; )
- {
- /* Wait to receive a value from the tick hook. */
- xResult = pdFAIL;
- crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult );
-
- /* There is no reason why we should not have received something on
- the queue. */
- if( xResult != pdPASS )
- {
- xCoRoutineErrorDetected = pdTRUE;
- }
-
- /* Send the same number back to the idle hook so it can verify it. */
- xResult = pdFAIL;
- crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult );
- if( xResult != pdPASS )
- {
- /* There is no reason why we should not have been able to post to
- the queue. */
- xCoRoutineErrorDetected = pdTRUE;
- }
- }
-
- /* Each co-routine MUST end with a call to crEND(). */
- crEND();
+ static UBaseType_t uxReceivedValue[ hookNUM_HOOK_CO_ROUTINES ];
+ BaseType_t xResult;
+
+ /* Each co-routine MUST start with a call to crSTART(); */
+ crSTART( xHandle );
+
+ for( ; ; )
+ {
+ /* Wait to receive a value from the tick hook. */
+ xResult = pdFAIL;
+ crQUEUE_RECEIVE( xHandle, xHookTxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), portMAX_DELAY, &xResult );
+
+ /* There is no reason why we should not have received something on
+ * the queue. */
+ if( xResult != pdPASS )
+ {
+ xCoRoutineErrorDetected = pdTRUE;
+ }
+
+ /* Send the same number back to the idle hook so it can verify it. */
+ xResult = pdFAIL;
+ crQUEUE_SEND( xHandle, xHookRxQueues[ uxIndex ], &( uxReceivedValue[ uxIndex ] ), hookNO_BLOCK_TIME, &xResult );
+
+ if( xResult != pdPASS )
+ {
+ /* There is no reason why we should not have been able to post to
+ * the queue. */
+ xCoRoutineErrorDetected = pdTRUE;
+ }
+ }
+
+ /* Each co-routine MUST end with a call to crEND(). */
+ crEND();
}
/*-----------------------------------------------------------*/
BaseType_t xAreHookCoRoutinesStillRunning( void )
{
- if( xCoRoutineErrorDetected )
- {
- return pdFALSE;
- }
- else
- {
- return pdTRUE;
- }
+ if( xCoRoutineErrorDetected )
+ {
+ return pdFALSE;
+ }
+ else
+ {
+ return pdTRUE;
+ }
}
-
-
-
diff --git a/Demo/Common/Minimal/death.c b/Demo/Common/Minimal/death.c
index 312cce96c..3e2696c5b 100644
--- a/Demo/Common/Minimal/death.c
+++ b/Demo/Common/Minimal/death.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -54,150 +54,148 @@
/* Demo program include files. */
#include "death.h"
-#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 )
+#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 )
/* The task originally created which is responsible for periodically dynamically
-creating another four tasks. */
+ * creating another four tasks. */
static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters );
/* The task function of the dynamically created tasks. */
static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters );
/* A variable which is incremented every time the dynamic tasks are created. This
-is used to check that the task is still running. */
+ * is used to check that the task is still running. */
static volatile uint16_t usCreationCount = 0;
/* Used to store the number of tasks that were originally running so the creator
-task can tell if any of the suicidal tasks have failed to die.
-*/
+ * task can tell if any of the suicidal tasks have failed to die.
+ */
static volatile UBaseType_t uxTasksRunningAtStart = 0;
/* When a task deletes itself, it stack and TCB are cleaned up by the Idle task.
-Under heavy load the idle task might not get much processing time, so it would
-be legitimate for several tasks to remain undeleted for a short period. There
-may also be a few other unexpected tasks if, for example, the tasks that test
-static allocation are also being used. */
+ * Under heavy load the idle task might not get much processing time, so it would
+ * be legitimate for several tasks to remain undeleted for a short period. There
+ * may also be a few other unexpected tasks if, for example, the tasks that test
+ * static allocation are also being used. */
static const UBaseType_t uxMaxNumberOfExtraTasksRunning = 3;
/* Used to store a handle to the task that should be killed by a suicidal task,
-before it kills itself. */
+ * before it kills itself. */
TaskHandle_t xCreatedTask;
/*-----------------------------------------------------------*/
void vCreateSuicidalTasks( UBaseType_t uxPriority )
{
- xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) NULL, uxPriority, NULL );
+ xTaskCreate( vCreateTasks, "CREATOR", deathSTACK_SIZE, ( void * ) NULL, uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vSuicidalTask, pvParameters )
{
-volatile long l1, l2;
-TaskHandle_t xTaskToKill;
-const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 200 );
-
- /* Test deletion of a task's secure context, if any. */
- portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
-
- if( pvParameters != NULL )
- {
- /* This task is periodically created four times. Two created tasks are
- passed a handle to the other task so it can kill it before killing itself.
- The other task is passed in null. */
- xTaskToKill = *( TaskHandle_t* )pvParameters;
- }
- else
- {
- xTaskToKill = NULL;
- }
-
- for( ;; )
- {
- /* Do something random just to use some stack and registers. */
- l1 = 2;
- l2 = 89;
- l2 *= l1;
- vTaskDelay( xDelay );
-
- if( xTaskToKill != NULL )
- {
- /* Make sure the other task has a go before we delete it. */
- vTaskDelay( ( TickType_t ) 0 );
-
- /* Kill the other task that was created by vCreateTasks(). */
- vTaskDelete( xTaskToKill );
-
- /* Kill ourselves. */
- vTaskDelete( NULL );
- }
- }
-}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */
+ volatile long l1, l2;
+ TaskHandle_t xTaskToKill;
+ const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 200 );
+
+ /* Test deletion of a task's secure context, if any. */
+ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+ if( pvParameters != NULL )
+ {
+ /* This task is periodically created four times. Two created tasks are
+ * passed a handle to the other task so it can kill it before killing itself.
+ * The other task is passed in null. */
+ xTaskToKill = *( TaskHandle_t * ) pvParameters;
+ }
+ else
+ {
+ xTaskToKill = NULL;
+ }
+
+ for( ; ; )
+ {
+ /* Do something random just to use some stack and registers. */
+ l1 = 2;
+ l2 = 89;
+ l2 *= l1;
+ vTaskDelay( xDelay );
+
+ if( xTaskToKill != NULL )
+ {
+ /* Make sure the other task has a go before we delete it. */
+ vTaskDelay( ( TickType_t ) 0 );
+
+ /* Kill the other task that was created by vCreateTasks(). */
+ vTaskDelete( xTaskToKill );
+
+ /* Kill ourselves. */
+ vTaskDelete( NULL );
+ }
+ }
+} /*lint !e818 !e550 Function prototype must be as per standard for task functions. */
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCreateTasks, pvParameters )
{
-const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 1000 );
-UBaseType_t uxPriority;
+ const TickType_t xDelay = pdMS_TO_TICKS( ( TickType_t ) 1000 );
+ UBaseType_t uxPriority;
- /* Remove compiler warning about unused parameter. */
- ( void ) pvParameters;
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
- /* Delay at the start to ensure tasks created by other demos have been
- created before storing the current number of tasks. */
- vTaskDelay( xDelay );
- uxTasksRunningAtStart = ( UBaseType_t ) uxTaskGetNumberOfTasks();
+ /* Delay at the start to ensure tasks created by other demos have been
+ * created before storing the current number of tasks. */
+ vTaskDelay( xDelay );
+ uxTasksRunningAtStart = ( UBaseType_t ) uxTaskGetNumberOfTasks();
- uxPriority = uxTaskPriorityGet( NULL );
+ uxPriority = uxTaskPriorityGet( NULL );
- for( ;; )
- {
- /* Just loop round, delaying then creating the four suicidal tasks. */
- vTaskDelay( xDelay );
+ for( ; ; )
+ {
+ /* Just loop round, delaying then creating the four suicidal tasks. */
+ vTaskDelay( xDelay );
- xCreatedTask = NULL;
+ xCreatedTask = NULL;
- xTaskCreate( vSuicidalTask, "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask );
- xTaskCreate( vSuicidalTask, "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL );
+ xTaskCreate( vSuicidalTask, "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask );
+ xTaskCreate( vSuicidalTask, "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL );
- ++usCreationCount;
- }
+ ++usCreationCount;
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that the creator task is still running and that there
-are not any more than four extra tasks. */
+ * are not any more than four extra tasks. */
BaseType_t xIsCreateTaskStillRunning( void )
{
-static uint16_t usLastCreationCount = 0xfff;
-BaseType_t xReturn = pdTRUE;
-static UBaseType_t uxTasksRunningNow;
-
- if( usLastCreationCount == usCreationCount )
- {
- xReturn = pdFALSE;
- }
- else
- {
- usLastCreationCount = usCreationCount;
- }
-
- uxTasksRunningNow = ( UBaseType_t ) uxTaskGetNumberOfTasks();
-
- if( uxTasksRunningNow < uxTasksRunningAtStart )
- {
- xReturn = pdFALSE;
- }
- else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
- {
- xReturn = pdFALSE;
- }
- else
- {
- /* Everything is okay. */
- }
-
- return xReturn;
+ static uint16_t usLastCreationCount = 0xfff;
+ BaseType_t xReturn = pdTRUE;
+ static UBaseType_t uxTasksRunningNow;
+
+ if( usLastCreationCount == usCreationCount )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ usLastCreationCount = usCreationCount;
+ }
+
+ uxTasksRunningNow = ( UBaseType_t ) uxTaskGetNumberOfTasks();
+
+ if( uxTasksRunningNow < uxTasksRunningAtStart )
+ {
+ xReturn = pdFALSE;
+ }
+ else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ /* Everything is okay. */
+ }
+
+ return xReturn;
}
-
-
diff --git a/Demo/Common/Minimal/dynamic.c b/Demo/Common/Minimal/dynamic.c
index 19d3227b1..4d287b430 100644
--- a/Demo/Common/Minimal/dynamic.c
+++ b/Demo/Common/Minimal/dynamic.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -106,29 +106,29 @@ static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );
/* Demo task specific constants. */
#ifndef priSUSPENDED_RX_TASK_STACK_SIZE
- #define priSUSPENDED_RX_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE )
+ #define priSUSPENDED_RX_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE )
#endif
-#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE )
-#define priSLEEP_TIME pdMS_TO_TICKS( 128 )
-#define priLOOPS ( 5 )
-#define priMAX_COUNT ( ( uint32_t ) 0xff )
-#define priNO_BLOCK ( ( TickType_t ) 0 )
-#define priSUSPENDED_QUEUE_LENGTH ( 1 )
+#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE )
+#define priSLEEP_TIME pdMS_TO_TICKS( 128 )
+#define priLOOPS ( 5 )
+#define priMAX_COUNT ( ( uint32_t ) 0xff )
+#define priNO_BLOCK ( ( TickType_t ) 0 )
+#define priSUSPENDED_QUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/* Handles to the two counter tasks. These could be passed in as parameters
-to the controller task to prevent them having to be file scope. */
+ * to the controller task to prevent them having to be file scope. */
static TaskHandle_t xContinuousIncrementHandle, xLimitedIncrementHandle;
/* The shared counter variable. This is passed in as a parameter to the two
-counter variables for demonstration purposes. */
+ * counter variables for demonstration purposes. */
static uint32_t ulCounter;
/* Variables used to check that the tasks are still operating without error.
-Each complete iteration of the controller task increments this variable
-provided no errors have been found. The variable maintaining the same value
-is therefore indication of an error. */
+ * Each complete iteration of the controller task increments this variable
+ * provided no errors have been found. The variable maintaining the same value
+ * is therefore indication of an error. */
static volatile uint16_t usCheckVariable = ( uint16_t ) 0;
static volatile BaseType_t xSuspendedQueueSendError = pdFALSE;
static volatile BaseType_t xSuspendedQueueReceiveError = pdFALSE;
@@ -137,35 +137,36 @@ static volatile BaseType_t xSuspendedQueueReceiveError = pdFALSE;
QueueHandle_t xSuspendedTestQueue;
/* The value the queue receive task expects to receive next. This is file
-scope so xAreDynamicPriorityTasksStillRunning() can ensure it is still
-incrementing. */
+ * scope so xAreDynamicPriorityTasksStillRunning() can ensure it is still
+ * incrementing. */
static uint32_t ulExpectedValue = ( uint32_t ) 0;
/*-----------------------------------------------------------*/
+
/*
* Start the three tasks as described at the top of the file.
* Note that the limited count task is given a higher priority.
*/
void vStartDynamicPriorityTasks( void )
{
- xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( uint32_t ) );
-
- if( xSuspendedTestQueue != NULL )
- {
- /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
- in use. The queue registry is provided as a means for kernel aware
- debuggers to locate queues and has no purpose if a kernel aware debugger
- is not being used. The call to vQueueAddToRegistry() will be removed
- by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
- defined to be less than 1. */
- vQueueAddToRegistry( xSuspendedTestQueue, "Suspended_Test_Queue" );
-
- xTaskCreate( vContinuousIncrementTask, "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
- xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
- xTaskCreate( vCounterControlTask, "C_CTRL", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RX", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- }
+ xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xSuspendedTestQueue != NULL )
+ {
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is
+ * in use. The queue registry is provided as a means for kernel aware
+ * debuggers to locate queues and has no purpose if a kernel aware debugger
+ * is not being used. The call to vQueueAddToRegistry() will be removed
+ * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+ * defined to be less than 1. */
+ vQueueAddToRegistry( xSuspendedTestQueue, "Suspended_Test_Queue" );
+
+ xTaskCreate( vContinuousIncrementTask, "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinuousIncrementHandle );
+ xTaskCreate( vLimitedIncrementTask, "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );
+ xTaskCreate( vCounterControlTask, "C_CTRL", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vQueueSendWhenSuspendedTask, "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vQueueReceiveWhenSuspendedTask, "SUSP_RX", priSUSPENDED_RX_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ }
}
/*-----------------------------------------------------------*/
@@ -175,26 +176,26 @@ void vStartDynamicPriorityTasks( void )
*/
static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters )
{
-volatile uint32_t *pulCounter;
-
- /* Take a pointer to the shared variable from the parameters passed into
- the task. */
- pulCounter = ( volatile uint32_t * ) pvParameters;
-
- /* This will run before the control task, so the first thing it does is
- suspend - the control task will resume it when ready. */
- vTaskSuspend( NULL );
-
- for( ;; )
- {
- /* Just count up to a value then suspend. */
- ( *pulCounter )++;
-
- if( *pulCounter >= priMAX_COUNT )
- {
- vTaskSuspend( NULL );
- }
- }
+ volatile uint32_t * pulCounter;
+
+ /* Take a pointer to the shared variable from the parameters passed into
+ * the task. */
+ pulCounter = ( volatile uint32_t * ) pvParameters;
+
+ /* This will run before the control task, so the first thing it does is
+ * suspend - the control task will resume it when ready. */
+ vTaskSuspend( NULL );
+
+ for( ; ; )
+ {
+ /* Just count up to a value then suspend. */
+ ( *pulCounter )++;
+
+ if( *pulCounter >= priMAX_COUNT )
+ {
+ vTaskSuspend( NULL );
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -204,34 +205,34 @@ volatile uint32_t *pulCounter;
*/
static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters )
{
-volatile uint32_t *pulCounter;
-UBaseType_t uxOurPriority;
-
- /* Take a pointer to the shared variable from the parameters passed into
- the task. */
- pulCounter = ( volatile uint32_t * ) pvParameters;
-
- /* Query our priority so we can raise it when exclusive access to the
- shared variable is required. */
- uxOurPriority = uxTaskPriorityGet( NULL );
-
- for( ;; )
- {
- /* Raise the priority above the controller task to ensure a context
- switch does not occur while the variable is being accessed. */
- vTaskPrioritySet( NULL, uxOurPriority + 1 );
- {
- configASSERT( ( uxTaskPriorityGet( NULL ) == ( uxOurPriority + 1 ) ) );
- ( *pulCounter )++;
- }
- vTaskPrioritySet( NULL, uxOurPriority );
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- configASSERT( ( uxTaskPriorityGet( NULL ) == uxOurPriority ) );
- }
+ volatile uint32_t * pulCounter;
+ UBaseType_t uxOurPriority;
+
+ /* Take a pointer to the shared variable from the parameters passed into
+ * the task. */
+ pulCounter = ( volatile uint32_t * ) pvParameters;
+
+ /* Query our priority so we can raise it when exclusive access to the
+ * shared variable is required. */
+ uxOurPriority = uxTaskPriorityGet( NULL );
+
+ for( ; ; )
+ {
+ /* Raise the priority above the controller task to ensure a context
+ * switch does not occur while the variable is being accessed. */
+ vTaskPrioritySet( NULL, uxOurPriority + 1 );
+ {
+ configASSERT( ( uxTaskPriorityGet( NULL ) == ( uxOurPriority + 1 ) ) );
+ ( *pulCounter )++;
+ }
+ vTaskPrioritySet( NULL, uxOurPriority );
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ configASSERT( ( uxTaskPriorityGet( NULL ) == uxOurPriority ) );
+ }
}
/*-----------------------------------------------------------*/
@@ -240,200 +241,200 @@ UBaseType_t uxOurPriority;
*/
static portTASK_FUNCTION( vCounterControlTask, pvParameters )
{
-uint32_t ulLastCounter;
-short sLoops;
-short sError = pdFALSE;
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Start with the counter at zero. */
- ulCounter = ( uint32_t ) 0;
-
- /* First section : */
-
- /* Check the continuous count task is running. */
- for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
- {
- /* Suspend the continuous count task so we can take a mirror of the
- shared variable without risk of corruption. This is not really
- needed as the other task raises its priority above this task's
- priority. */
- vTaskSuspend( xContinuousIncrementHandle );
- {
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- ulLastCounter = ulCounter;
- }
- vTaskResume( xContinuousIncrementHandle );
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eReady );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* Now delay to ensure the other task has processor time. */
- vTaskDelay( priSLEEP_TIME );
-
- /* Check the shared variable again. This time to ensure mutual
- exclusion the whole scheduler will be locked. This is just for
- demo purposes! */
- vTaskSuspendAll();
- {
- if( ulLastCounter == ulCounter )
- {
- /* The shared variable has not changed. There is a problem
- with the continuous count task so flag an error. */
- sError = pdTRUE;
- }
- }
- xTaskResumeAll();
- }
-
- /* Second section: */
-
- /* Suspend the continuous counter task so it stops accessing the shared
- variable. */
- vTaskSuspend( xContinuousIncrementHandle );
-
- /* Reset the variable. */
- ulCounter = ( uint32_t ) 0;
-
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* Resume the limited count task which has a higher priority than us.
- We should therefore not return from this call until the limited count
- task has suspended itself with a known value in the counter variable. */
- vTaskResume( xLimitedIncrementHandle );
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- /* This task should not run again until xLimitedIncrementHandle has
- suspended itself. */
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* Does the counter variable have the expected value? */
- if( ulCounter != priMAX_COUNT )
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If no errors have occurred then increment the check variable. */
- portENTER_CRITICAL();
- usCheckVariable++;
- portEXIT_CRITICAL();
- }
-
- /* Resume the continuous count task and do it all again. */
- vTaskResume( xContinuousIncrementHandle );
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
- }
+ uint32_t ulLastCounter;
+ short sLoops;
+ short sError = pdFALSE;
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Start with the counter at zero. */
+ ulCounter = ( uint32_t ) 0;
+
+ /* First section : */
+
+ /* Check the continuous count task is running. */
+ for( sLoops = 0; sLoops < priLOOPS; sLoops++ )
+ {
+ /* Suspend the continuous count task so we can take a mirror of the
+ * shared variable without risk of corruption. This is not really
+ * needed as the other task raises its priority above this task's
+ * priority. */
+ vTaskSuspend( xContinuousIncrementHandle );
+ {
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ ulLastCounter = ulCounter;
+ }
+ vTaskResume( xContinuousIncrementHandle );
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xContinuousIncrementHandle ) == eReady );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* Now delay to ensure the other task has processor time. */
+ vTaskDelay( priSLEEP_TIME );
+
+ /* Check the shared variable again. This time to ensure mutual
+ * exclusion the whole scheduler will be locked. This is just for
+ * demo purposes! */
+ vTaskSuspendAll();
+ {
+ if( ulLastCounter == ulCounter )
+ {
+ /* The shared variable has not changed. There is a problem
+ * with the continuous count task so flag an error. */
+ sError = pdTRUE;
+ }
+ }
+ xTaskResumeAll();
+ }
+
+ /* Second section: */
+
+ /* Suspend the continuous counter task so it stops accessing the shared
+ * variable. */
+ vTaskSuspend( xContinuousIncrementHandle );
+
+ /* Reset the variable. */
+ ulCounter = ( uint32_t ) 0;
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* Resume the limited count task which has a higher priority than us.
+ * We should therefore not return from this call until the limited count
+ * task has suspended itself with a known value in the counter variable. */
+ vTaskResume( xLimitedIncrementHandle );
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ /* This task should not run again until xLimitedIncrementHandle has
+ * suspended itself. */
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xLimitedIncrementHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* Does the counter variable have the expected value? */
+ if( ulCounter != priMAX_COUNT )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If no errors have occurred then increment the check variable. */
+ portENTER_CRITICAL();
+ usCheckVariable++;
+ portEXIT_CRITICAL();
+ }
+
+ /* Resume the continuous count task and do it all again. */
+ vTaskResume( xContinuousIncrementHandle );
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters )
{
-static uint32_t ulValueToSend = ( uint32_t ) 0;
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- vTaskSuspendAll();
- {
- /* We must not block while the scheduler is suspended! */
- if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
- {
- xSuspendedQueueSendError = pdTRUE;
- }
- }
- xTaskResumeAll();
-
- vTaskDelay( priSLEEP_TIME );
-
- ++ulValueToSend;
- }
+ static uint32_t ulValueToSend = ( uint32_t ) 0;
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ vTaskSuspendAll();
+ {
+ /* We must not block while the scheduler is suspended! */
+ if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )
+ {
+ xSuspendedQueueSendError = pdTRUE;
+ }
+ }
+ xTaskResumeAll();
+
+ vTaskDelay( priSLEEP_TIME );
+
+ ++ulValueToSend;
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters )
{
-uint32_t ulReceivedValue;
-BaseType_t xGotValue;
-
- /* Just to stop warning messages. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- do
- {
- /* Suspending the scheduler here is fairly pointless and
- undesirable for a normal application. It is done here purely
- to test the scheduler. The inner xTaskResumeAll() should
- never return pdTRUE as the scheduler is still locked by the
- outer call. */
- vTaskSuspendAll();
- {
- vTaskSuspendAll();
- {
- xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
- }
- if( xTaskResumeAll() != pdFALSE )
- {
- xSuspendedQueueReceiveError = pdTRUE;
- }
- }
- xTaskResumeAll();
-
- #if configUSE_PREEMPTION == 0
- {
- taskYIELD();
- }
- #endif
-
- } while( xGotValue == pdFALSE );
-
- if( ulReceivedValue != ulExpectedValue )
- {
- xSuspendedQueueReceiveError = pdTRUE;
- }
-
- if( xSuspendedQueueReceiveError != pdTRUE )
- {
- /* Only increment the variable if an error has not occurred. This
- allows xAreDynamicPriorityTasksStillRunning() to check for stalled
- tasks as well as explicit errors. */
- ++ulExpectedValue;
- }
- }
+ uint32_t ulReceivedValue;
+ BaseType_t xGotValue;
+
+ /* Just to stop warning messages. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ do
+ {
+ /* Suspending the scheduler here is fairly pointless and
+ * undesirable for a normal application. It is done here purely
+ * to test the scheduler. The inner xTaskResumeAll() should
+ * never return pdTRUE as the scheduler is still locked by the
+ * outer call. */
+ vTaskSuspendAll();
+ {
+ vTaskSuspendAll();
+ {
+ xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );
+ }
+
+ if( xTaskResumeAll() != pdFALSE )
+ {
+ xSuspendedQueueReceiveError = pdTRUE;
+ }
+ }
+ xTaskResumeAll();
+
+ #if configUSE_PREEMPTION == 0
+ {
+ taskYIELD();
+ }
+ #endif
+ } while( xGotValue == pdFALSE );
+
+ if( ulReceivedValue != ulExpectedValue )
+ {
+ xSuspendedQueueReceiveError = pdTRUE;
+ }
+
+ if( xSuspendedQueueReceiveError != pdTRUE )
+ {
+ /* Only increment the variable if an error has not occurred. This
+ * allows xAreDynamicPriorityTasksStillRunning() to check for stalled
+ * tasks as well as explicit errors. */
+ ++ulExpectedValue;
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -441,39 +442,39 @@ BaseType_t xGotValue;
BaseType_t xAreDynamicPriorityTasksStillRunning( void )
{
/* Keep a history of the check variables so we know if it has been incremented
-since the last call. */
-static uint16_t usLastTaskCheck = ( uint16_t ) 0;
-static uint32_t ulLastExpectedValue = ( uint32_t ) 0U;
-BaseType_t xReturn = pdTRUE;
-
- /* Check the tasks are still running by ensuring the check variable
- is still incrementing. */
-
- if( usCheckVariable == usLastTaskCheck )
- {
- /* The check has not incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- if( ulExpectedValue == ulLastExpectedValue )
- {
- /* The value being received by the queue receive task has not
- incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- if( xSuspendedQueueSendError == pdTRUE )
- {
- xReturn = pdFALSE;
- }
-
- if( xSuspendedQueueReceiveError == pdTRUE )
- {
- xReturn = pdFALSE;
- }
-
- usLastTaskCheck = usCheckVariable;
- ulLastExpectedValue = ulExpectedValue;
-
- return xReturn;
+ * since the last call. */
+ static uint16_t usLastTaskCheck = ( uint16_t ) 0;
+ static uint32_t ulLastExpectedValue = ( uint32_t ) 0U;
+ BaseType_t xReturn = pdTRUE;
+
+ /* Check the tasks are still running by ensuring the check variable
+ * is still incrementing. */
+
+ if( usCheckVariable == usLastTaskCheck )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ if( ulExpectedValue == ulLastExpectedValue )
+ {
+ /* The value being received by the queue receive task has not
+ * incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ if( xSuspendedQueueSendError == pdTRUE )
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( xSuspendedQueueReceiveError == pdTRUE )
+ {
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck = usCheckVariable;
+ ulLastExpectedValue = ulExpectedValue;
+
+ return xReturn;
}
diff --git a/Demo/Common/Minimal/flash.c b/Demo/Common/Minimal/flash.c
index bae054b8a..bed3a68dd 100644
--- a/Demo/Common/Minimal/flash.c
+++ b/Demo/Common/Minimal/flash.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -49,12 +49,12 @@
#include "partest.h"
#include "flash.h"
-#define ledSTACK_SIZE configMINIMAL_STACK_SIZE
-#define ledNUMBER_OF_LEDS ( 3 )
-#define ledFLASH_RATE_BASE ( ( TickType_t ) 333 )
+#define ledSTACK_SIZE configMINIMAL_STACK_SIZE
+#define ledNUMBER_OF_LEDS ( 3 )
+#define ledFLASH_RATE_BASE ( ( TickType_t ) 333 )
/* Variable used by the created tasks to calculate the LED number to use, and
-the rate at which they should flash the LED. */
+ * the rate at which they should flash the LED. */
static volatile UBaseType_t uxFlashTaskNumber = 0;
/* The task that is created three times. */
@@ -64,56 +64,55 @@ static portTASK_FUNCTION_PROTO( vLEDFlashTask, pvParameters );
void vStartLEDFlashTasks( UBaseType_t uxPriority )
{
-BaseType_t xLEDTask;
-
- /* Create the three tasks. */
- for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask )
- {
- /* Spawn the task. */
- xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
- }
+ BaseType_t xLEDTask;
+
+ /* Create the three tasks. */
+ for( xLEDTask = 0; xLEDTask < ledNUMBER_OF_LEDS; ++xLEDTask )
+ {
+ /* Spawn the task. */
+ xTaskCreate( vLEDFlashTask, "LEDx", ledSTACK_SIZE, NULL, uxPriority, ( TaskHandle_t * ) NULL );
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vLEDFlashTask, pvParameters )
{
-TickType_t xFlashRate, xLastFlashTime;
-UBaseType_t uxLED;
-
- /* The parameters are not used. */
- ( void ) pvParameters;
-
- /* Calculate the LED and flash rate. */
- portENTER_CRITICAL();
- {
- /* See which of the eight LED's we should use. */
- uxLED = uxFlashTaskNumber;
-
- /* Update so the next task uses the next LED. */
- uxFlashTaskNumber++;
- }
- portEXIT_CRITICAL();
-
- xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( TickType_t ) uxLED );
- xFlashRate /= portTICK_PERIOD_MS;
-
- /* We will turn the LED on and off again in the delay period, so each
- delay is only half the total period. */
- xFlashRate /= ( TickType_t ) 2;
-
- /* We need to initialise xLastFlashTime prior to the first call to
- vTaskDelayUntil(). */
- xLastFlashTime = xTaskGetTickCount();
-
- for(;;)
- {
- /* Delay for half the flash period then turn the LED on. */
- vTaskDelayUntil( &xLastFlashTime, xFlashRate );
- vParTestToggleLED( uxLED );
-
- /* Delay for half the flash period then turn the LED off. */
- vTaskDelayUntil( &xLastFlashTime, xFlashRate );
- vParTestToggleLED( uxLED );
- }
+ TickType_t xFlashRate, xLastFlashTime;
+ UBaseType_t uxLED;
+
+ /* The parameters are not used. */
+ ( void ) pvParameters;
+
+ /* Calculate the LED and flash rate. */
+ portENTER_CRITICAL();
+ {
+ /* See which of the eight LED's we should use. */
+ uxLED = uxFlashTaskNumber;
+
+ /* Update so the next task uses the next LED. */
+ uxFlashTaskNumber++;
+ }
+ portEXIT_CRITICAL();
+
+ xFlashRate = ledFLASH_RATE_BASE + ( ledFLASH_RATE_BASE * ( TickType_t ) uxLED );
+ xFlashRate /= portTICK_PERIOD_MS;
+
+ /* We will turn the LED on and off again in the delay period, so each
+ * delay is only half the total period. */
+ xFlashRate /= ( TickType_t ) 2;
+
+ /* We need to initialise xLastFlashTime prior to the first call to
+ * vTaskDelayUntil(). */
+ xLastFlashTime = xTaskGetTickCount();
+
+ for( ; ; )
+ {
+ /* Delay for half the flash period then turn the LED on. */
+ vTaskDelayUntil( &xLastFlashTime, xFlashRate );
+ vParTestToggleLED( uxLED );
+
+ /* Delay for half the flash period then turn the LED off. */
+ vTaskDelayUntil( &xLastFlashTime, xFlashRate );
+ vParTestToggleLED( uxLED );
+ }
} /*lint !e715 !e818 !e830 Function definition must be standard for task creation. */
-
diff --git a/Demo/Common/Minimal/flash_timer.c b/Demo/Common/Minimal/flash_timer.c
index 7cb15efdc..190a109b6 100644
--- a/Demo/Common/Minimal/flash_timer.c
+++ b/Demo/Common/Minimal/flash_timer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -39,10 +39,10 @@
#include "flash_timer.h"
/* The toggle rates are all a multple of ledFLASH_RATE_BASE. */
-#define ledFLASH_RATE_BASE ( ( ( TickType_t ) 333 ) / portTICK_PERIOD_MS )
+#define ledFLASH_RATE_BASE ( ( ( TickType_t ) 333 ) / portTICK_PERIOD_MS )
/* A block time of zero simple means "don't block". */
-#define ledDONT_BLOCK ( ( TickType_t ) 0 )
+#define ledDONT_BLOCK ( ( TickType_t ) 0 )
/*-----------------------------------------------------------*/
@@ -57,42 +57,40 @@ static void prvLEDTimerCallback( TimerHandle_t xTimer );
void vStartLEDFlashTimers( UBaseType_t uxNumberOfLEDs )
{
-UBaseType_t uxLEDTimer;
-TimerHandle_t xTimer;
+ UBaseType_t uxLEDTimer;
+ TimerHandle_t xTimer;
- /* Create and start the requested number of timers. */
- for( uxLEDTimer = 0; uxLEDTimer < uxNumberOfLEDs; ++uxLEDTimer )
- {
- /* Create the timer. */
- xTimer = xTimerCreate( "Flasher", /* A text name, purely to help debugging. */
- ledFLASH_RATE_BASE * ( uxLEDTimer + 1 ),/* The timer period, which is a multiple of ledFLASH_RATE_BASE. */
- pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
- ( void * ) uxLEDTimer, /* The ID is used to identify the timer within the timer callback function, as each timer uses the same callback. */
- prvLEDTimerCallback /* Each timer uses the same callback. */
- );
+ /* Create and start the requested number of timers. */
+ for( uxLEDTimer = 0; uxLEDTimer < uxNumberOfLEDs; ++uxLEDTimer )
+ {
+ /* Create the timer. */
+ xTimer = xTimerCreate( "Flasher", /* A text name, purely to help debugging. */
+ ledFLASH_RATE_BASE * ( uxLEDTimer + 1 ), /* The timer period, which is a multiple of ledFLASH_RATE_BASE. */
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+ ( void * ) uxLEDTimer, /* The ID is used to identify the timer within the timer callback function, as each timer uses the same callback. */
+ prvLEDTimerCallback /* Each timer uses the same callback. */
+ );
- /* If the timer was created successfully, attempt to start it. If the
- scheduler has not yet been started then the timer command queue must
- be long enough to hold each command sent to it until such time that the
- scheduler is started. The timer command queue length is set by
- configTIMER_QUEUE_LENGTH in FreeRTOSConfig.h. */
- if( xTimer != NULL )
- {
- xTimerStart( xTimer, ledDONT_BLOCK );
- }
- }
+ /* If the timer was created successfully, attempt to start it. If the
+ * scheduler has not yet been started then the timer command queue must
+ * be long enough to hold each command sent to it until such time that the
+ * scheduler is started. The timer command queue length is set by
+ * configTIMER_QUEUE_LENGTH in FreeRTOSConfig.h. */
+ if( xTimer != NULL )
+ {
+ xTimerStart( xTimer, ledDONT_BLOCK );
+ }
+ }
}
/*-----------------------------------------------------------*/
static void prvLEDTimerCallback( TimerHandle_t xTimer )
{
-BaseType_t xTimerID;
+ BaseType_t xTimerID;
- /* The timer ID is used to identify the timer that has actually expired as
- each timer uses the same callback. The ID is then also used as the number
- of the LED that is to be toggled. */
- xTimerID = ( BaseType_t ) pvTimerGetTimerID( xTimer );
- vParTestToggleLED( xTimerID );
+ /* The timer ID is used to identify the timer that has actually expired as
+ * each timer uses the same callback. The ID is then also used as the number
+ * of the LED that is to be toggled. */
+ xTimerID = ( BaseType_t ) pvTimerGetTimerID( xTimer );
+ vParTestToggleLED( xTimerID );
}
-
-
diff --git a/Demo/Common/Minimal/flop.c b/Demo/Common/Minimal/flop.c
index 3f9393eb8..6b973e223 100644
--- a/Demo/Common/Minimal/flop.c
+++ b/Demo/Common/Minimal/flop.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -50,300 +50,298 @@
#include "flop.h"
#ifndef mathSTACK_SIZE
- #define mathSTACK_SIZE configMINIMAL_STACK_SIZE
+ #define mathSTACK_SIZE configMINIMAL_STACK_SIZE
#endif
-#define mathNUMBER_OF_TASKS ( 4 )
+#define mathNUMBER_OF_TASKS ( 4 )
/* Four tasks, each of which performs a different floating point calculation.
-Each of the four is created twice. */
+ * Each of the four is created twice. */
static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
/* These variables are used to check that all the tasks are still running. If a
-task gets a calculation wrong it will stop setting its check variable. */
+ * task gets a calculation wrong it will stop setting its check variable. */
static uint16_t usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
/*-----------------------------------------------------------*/
void vStartMathTasks( UBaseType_t uxPriority )
{
- xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
{
-volatile portDOUBLE d1, d2, d3, d4;
-volatile uint16_t *pusTaskCheckVariable;
-volatile portDOUBLE dAnswer;
-short sError = pdFALSE;
-
- /* Some ports require that tasks that use a hardware floating point unit
- tell the kernel that they require a floating point context before any
- floating point instructions are executed. */
- portTASK_USES_FLOATING_POINT();
-
- d1 = 123.4567;
- d2 = 2345.6789;
- d3 = -918.222;
-
- dAnswer = ( d1 + d2 ) * d3;
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for(;;)
- {
- d1 = 123.4567;
- d2 = 2345.6789;
- d3 = -918.222;
-
- d4 = ( d1 + d2 ) * d3;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( fabs( d4 - dAnswer ) > 0.001 )
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct then set set the check
- variable. The check variable will get set to pdFALSE each time
- xAreMathsTaskStillRunning() is executed. */
- ( *pusTaskCheckVariable ) = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- }
+ volatile portDOUBLE d1, d2, d3, d4;
+ volatile uint16_t * pusTaskCheckVariable;
+ volatile portDOUBLE dAnswer;
+ short sError = pdFALSE;
+
+ /* Some ports require that tasks that use a hardware floating point unit
+ * tell the kernel that they require a floating point context before any
+ * floating point instructions are executed. */
+ portTASK_USES_FLOATING_POINT();
+
+ d1 = 123.4567;
+ d2 = 2345.6789;
+ d3 = -918.222;
+
+ dAnswer = ( d1 + d2 ) * d3;
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ d1 = 123.4567;
+ d2 = 2345.6789;
+ d3 = -918.222;
+
+ d4 = ( d1 + d2 ) * d3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( fabs( d4 - dAnswer ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct then set set the check
+ * variable. The check variable will get set to pdFALSE each time
+ * xAreMathsTaskStillRunning() is executed. */
+ ( *pusTaskCheckVariable ) = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
{
-volatile portDOUBLE d1, d2, d3, d4;
-volatile uint16_t *pusTaskCheckVariable;
-volatile portDOUBLE dAnswer;
-short sError = pdFALSE;
-
- /* Some ports require that tasks that use a hardware floating point unit
- tell the kernel that they require a floating point context before any
- floating point instructions are executed. */
- portTASK_USES_FLOATING_POINT();
-
- d1 = -389.38;
- d2 = 32498.2;
- d3 = -2.0001;
-
- dAnswer = ( d1 / d2 ) * d3;
-
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for( ;; )
- {
- d1 = -389.38;
- d2 = 32498.2;
- d3 = -2.0001;
-
- d4 = ( d1 / d2 ) * d3;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( fabs( d4 - dAnswer ) > 0.001 )
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct then set set the check
- variable. The check variable will get set to pdFALSE each time
- xAreMathsTaskStillRunning() is executed. */
- ( *pusTaskCheckVariable ) = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
- }
+ volatile portDOUBLE d1, d2, d3, d4;
+ volatile uint16_t * pusTaskCheckVariable;
+ volatile portDOUBLE dAnswer;
+ short sError = pdFALSE;
+
+ /* Some ports require that tasks that use a hardware floating point unit
+ * tell the kernel that they require a floating point context before any
+ * floating point instructions are executed. */
+ portTASK_USES_FLOATING_POINT();
+
+ d1 = -389.38;
+ d2 = 32498.2;
+ d3 = -2.0001;
+
+ dAnswer = ( d1 / d2 ) * d3;
+
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ d1 = -389.38;
+ d2 = 32498.2;
+ d3 = -2.0001;
+
+ d4 = ( d1 / d2 ) * d3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( fabs( d4 - dAnswer ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct then set set the check
+ * variable. The check variable will get set to pdFALSE each time
+ * xAreMathsTaskStillRunning() is executed. */
+ ( *pusTaskCheckVariable ) = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
{
-volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
-volatile uint16_t *pusTaskCheckVariable;
-const size_t xArraySize = 10;
-size_t xPosition;
-short sError = pdFALSE;
-
- /* Some ports require that tasks that use a hardware floating point unit
- tell the kernel that they require a floating point context before any
- floating point instructions are executed. */
- portTASK_USES_FLOATING_POINT();
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
-
- pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
-
- /* Keep filling an array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- dTotal1 = 0.0;
- dTotal2 = 0.0;
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5;
- dTotal1 += ( portDOUBLE ) xPosition + 5.5;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- dTotal2 += pdArray[ xPosition ];
- }
-
- dDifference = dTotal1 - dTotal2;
- if( fabs( dDifference ) > 0.001 )
- {
- sError = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct then set set the check
- variable. The check variable will get set to pdFALSE each time
- xAreMathsTaskStillRunning() is executed. */
- ( *pusTaskCheckVariable ) = pdTRUE;
- }
- }
+ volatile portDOUBLE * pdArray, dTotal1, dTotal2, dDifference;
+ volatile uint16_t * pusTaskCheckVariable;
+ const size_t xArraySize = 10;
+ size_t xPosition;
+ short sError = pdFALSE;
+
+ /* Some ports require that tasks that use a hardware floating point unit
+ * tell the kernel that they require a floating point context before any
+ * floating point instructions are executed. */
+ portTASK_USES_FLOATING_POINT();
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+ pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ dTotal1 = 0.0;
+ dTotal2 = 0.0;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5;
+ dTotal1 += ( portDOUBLE ) xPosition + 5.5;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ dTotal2 += pdArray[ xPosition ];
+ }
+
+ dDifference = dTotal1 - dTotal2;
+
+ if( fabs( dDifference ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct then set set the check
+ * variable. The check variable will get set to pdFALSE each time
+ * xAreMathsTaskStillRunning() is executed. */
+ ( *pusTaskCheckVariable ) = pdTRUE;
+ }
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
{
-volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
-volatile uint16_t *pusTaskCheckVariable;
-const size_t xArraySize = 10;
-size_t xPosition;
-short sError = pdFALSE;
-
- /* Some ports require that tasks that use a hardware floating point unit
- tell the kernel that they require a floating point context before any
- floating point instructions are executed. */
- portTASK_USES_FLOATING_POINT();
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
-
- pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
-
- /* Keep filling an array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- dTotal1 = 0.0;
- dTotal2 = 0.0;
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123;
- dTotal1 += ( portDOUBLE ) xPosition * 12.123;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- dTotal2 += pdArray[ xPosition ];
- }
-
- dDifference = dTotal1 - dTotal2;
- if( fabs( dDifference ) > 0.001 )
- {
- sError = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct then set set the check
- variable. The check variable will get set to pdFALSE each time
- xAreMathsTaskStillRunning() is executed. */
- ( *pusTaskCheckVariable ) = pdTRUE;
- }
- }
+ volatile portDOUBLE * pdArray, dTotal1, dTotal2, dDifference;
+ volatile uint16_t * pusTaskCheckVariable;
+ const size_t xArraySize = 10;
+ size_t xPosition;
+ short sError = pdFALSE;
+
+ /* Some ports require that tasks that use a hardware floating point unit
+ * tell the kernel that they require a floating point context before any
+ * floating point instructions are executed. */
+ portTASK_USES_FLOATING_POINT();
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( volatile uint16_t * ) pvParameters;
+
+ pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ dTotal1 = 0.0;
+ dTotal2 = 0.0;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123;
+ dTotal1 += ( portDOUBLE ) xPosition * 12.123;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ dTotal2 += pdArray[ xPosition ];
+ }
+
+ dDifference = dTotal1 - dTotal2;
+
+ if( fabs( dDifference ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct then set set the check
+ * variable. The check variable will get set to pdFALSE each time
+ * xAreMathsTaskStillRunning() is executed. */
+ ( *pusTaskCheckVariable ) = pdTRUE;
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreMathsTaskStillRunning( void )
{
-BaseType_t xReturn = pdPASS, xTask;
-
- /* Check the maths tasks are still running by ensuring their check variables
- have been set to pdPASS. */
- for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
- {
- if( usTaskCheck[ xTask ] != pdTRUE )
- {
- /* The check has not been set so the associated task has either
- stalled or detected an error. */
- xReturn = pdFAIL;
- }
- else
- {
- /* Reset the variable so it can be checked again the next time this
- function is executed. */
- usTaskCheck[ xTask ] = pdFALSE;
- }
- }
-
- return xReturn;
+ BaseType_t xReturn = pdPASS, xTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ * have been set to pdPASS. */
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+ {
+ if( usTaskCheck[ xTask ] != pdTRUE )
+ {
+ /* The check has not been set so the associated task has either
+ * stalled or detected an error. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ /* Reset the variable so it can be checked again the next time this
+ * function is executed. */
+ usTaskCheck[ xTask ] = pdFALSE;
+ }
+ }
+
+ return xReturn;
}
-
-
-
diff --git a/Demo/Common/Minimal/integer.c b/Demo/Common/Minimal/integer.c
index fb169925a..fc785b6c0 100644
--- a/Demo/Common/Minimal/integer.c
+++ b/Demo/Common/Minimal/integer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -42,122 +42,121 @@
#include "integer.h"
/* The constants used in the calculation. */
-#define intgCONST1 ( ( long ) 123 )
-#define intgCONST2 ( ( long ) 234567 )
-#define intgCONST3 ( ( long ) -3 )
-#define intgCONST4 ( ( long ) 7 )
-#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
+#define intgCONST1 ( ( long ) 123 )
+#define intgCONST2 ( ( long ) 234567 )
+#define intgCONST3 ( ( long ) -3 )
+#define intgCONST4 ( ( long ) 7 )
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )
-#define intgSTACK_SIZE configMINIMAL_STACK_SIZE
+#define intgSTACK_SIZE configMINIMAL_STACK_SIZE
/* As this is the minimal version, we will only create one task. */
-#define intgNUMBER_OF_TASKS ( 1 )
+#define intgNUMBER_OF_TASKS ( 1 )
/* The task function. Repeatedly performs a 32 bit calculation, checking the
-result against the expected result. If the result is incorrect then the
-context switch must have caused some corruption. */
+ * result against the expected result. If the result is incorrect then the
+ * context switch must have caused some corruption. */
static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters );
/* Variables that are set to true within the calculation task to indicate
-that the task is still executing. The check task sets the variable back to
-false, flagging an error if the variable is still false the next time it
-is called. */
+ * that the task is still executing. The check task sets the variable back to
+ * false, flagging an error if the variable is still false the next time it
+ * is called. */
static BaseType_t xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( BaseType_t ) pdFALSE };
/*-----------------------------------------------------------*/
void vStartIntegerMathTasks( UBaseType_t uxPriority )
{
-short sTask;
+ short sTask;
- for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
- {
- xTaskCreate( vCompeteingIntMathTask, "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( TaskHandle_t * ) NULL );
- }
+ for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
+ {
+ xTaskCreate( vCompeteingIntMathTask, "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( TaskHandle_t * ) NULL );
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters )
{
/* These variables are all effectively set to constants so they are volatile to
-ensure the compiler does not just get rid of them. */
-volatile long lValue;
-short sError = pdFALSE;
-volatile BaseType_t *pxTaskHasExecuted;
-
- /* Set a pointer to the variable we are going to set to true each
- iteration. This is also a good test of the parameter passing mechanism
- within each port. */
- pxTaskHasExecuted = ( volatile BaseType_t * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for( ;; )
- {
- /* Perform the calculation. This will store partial value in
- registers, resulting in a good test of the context switch mechanism. */
- lValue = intgCONST1;
- lValue += intgCONST2;
-
- /* Yield in case cooperative scheduling is being used. */
- #if configUSE_PREEMPTION == 0
- {
- taskYIELD();
- }
- #endif
-
- /* Finish off the calculation. */
- lValue *= intgCONST3;
- lValue /= intgCONST4;
-
- /* If the calculation is found to be incorrect we stop setting the
- TaskHasExecuted variable so the check task can see an error has
- occurred. */
- if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* We have not encountered any errors, so set the flag that show
- we are still executing. This will be periodically cleared by
- the check task. */
- portENTER_CRITICAL();
- *pxTaskHasExecuted = pdTRUE;
- portEXIT_CRITICAL();
- }
-
- /* Yield in case cooperative scheduling is being used. */
- #if configUSE_PREEMPTION == 0
- {
- taskYIELD();
- }
- #endif
- }
+ * ensure the compiler does not just get rid of them. */
+ volatile long lValue;
+ short sError = pdFALSE;
+ volatile BaseType_t * pxTaskHasExecuted;
+
+ /* Set a pointer to the variable we are going to set to true each
+ * iteration. This is also a good test of the parameter passing mechanism
+ * within each port. */
+ pxTaskHasExecuted = ( volatile BaseType_t * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ /* Perform the calculation. This will store partial value in
+ * registers, resulting in a good test of the context switch mechanism. */
+ lValue = intgCONST1;
+ lValue += intgCONST2;
+
+ /* Yield in case cooperative scheduling is being used. */
+ #if configUSE_PREEMPTION == 0
+ {
+ taskYIELD();
+ }
+ #endif
+
+ /* Finish off the calculation. */
+ lValue *= intgCONST3;
+ lValue /= intgCONST4;
+
+ /* If the calculation is found to be incorrect we stop setting the
+ * TaskHasExecuted variable so the check task can see an error has
+ * occurred. */
+ if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* We have not encountered any errors, so set the flag that show
+ * we are still executing. This will be periodically cleared by
+ * the check task. */
+ portENTER_CRITICAL();
+ *pxTaskHasExecuted = pdTRUE;
+ portEXIT_CRITICAL();
+ }
+
+ /* Yield in case cooperative scheduling is being used. */
+ #if configUSE_PREEMPTION == 0
+ {
+ taskYIELD();
+ }
+ #endif
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreIntegerMathsTaskStillRunning( void )
{
-BaseType_t xReturn = pdTRUE;
-short sTask;
-
- /* Check the maths tasks are still running by ensuring their check variables
- are still being set to true. */
- for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
- {
- if( xTaskCheck[ sTask ] == pdFALSE )
- {
- /* The check has not incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- /* Reset the check variable so we can tell if it has been set by
- the next time around. */
- xTaskCheck[ sTask ] = pdFALSE;
- }
-
- return xReturn;
+ BaseType_t xReturn = pdTRUE;
+ short sTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ * are still being set to true. */
+ for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )
+ {
+ if( xTaskCheck[ sTask ] == pdFALSE )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ /* Reset the check variable so we can tell if it has been set by
+ * the next time around. */
+ xTaskCheck[ sTask ] = pdFALSE;
+ }
+
+ return xReturn;
}
-
diff --git a/Demo/Common/Minimal/recmutex.c b/Demo/Common/Minimal/recmutex.c
index bc0b284d2..48ca8bb07 100644
--- a/Demo/Common/Minimal/recmutex.c
+++ b/Demo/Common/Minimal/recmutex.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,40 +26,40 @@
*/
/*
- The tasks defined on this page demonstrate the use of recursive mutexes.
-
- For recursive mutex functionality the created mutex should be created using
- xSemaphoreCreateRecursiveMutex(), then be manipulated
- using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API
- functions.
-
- This demo creates three tasks all of which access the same recursive mutex:
-
- prvRecursiveMutexControllingTask() has the highest priority so executes
- first and grabs the mutex. It then performs some recursive accesses -
- between each of which it sleeps for a short period to let the lower
- priority tasks execute. When it has completed its demo functionality
- it gives the mutex back before suspending itself.
-
- prvRecursiveMutexBlockingTask() attempts to access the mutex by performing
- a blocking 'take'. The blocking task has a lower priority than the
- controlling task so by the time it executes the mutex has already been
- taken by the controlling task, causing the blocking task to block. It
- does not unblock until the controlling task has given the mutex back,
- and it does not actually run until the controlling task has suspended
- itself (due to the relative priorities). When it eventually does obtain
- the mutex all it does is give the mutex back prior to also suspending
- itself. At this point both the controlling task and the blocking task are
- suspended.
-
- prvRecursiveMutexPollingTask() runs at the idle priority. It spins round
- a tight loop attempting to obtain the mutex with a non-blocking call. As
- the lowest priority task it will not successfully obtain the mutex until
- both the controlling and blocking tasks are suspended. Once it eventually
- does obtain the mutex it first unsuspends both the controlling task and
- blocking task prior to giving the mutex back - resulting in the polling
- task temporarily inheriting the controlling tasks priority.
-*/
+ * The tasks defined on this page demonstrate the use of recursive mutexes.
+ *
+ * For recursive mutex functionality the created mutex should be created using
+ * xSemaphoreCreateRecursiveMutex(), then be manipulated
+ * using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API
+ * functions.
+ *
+ * This demo creates three tasks all of which access the same recursive mutex:
+ *
+ * prvRecursiveMutexControllingTask() has the highest priority so executes
+ * first and grabs the mutex. It then performs some recursive accesses -
+ * between each of which it sleeps for a short period to let the lower
+ * priority tasks execute. When it has completed its demo functionality
+ * it gives the mutex back before suspending itself.
+ *
+ * prvRecursiveMutexBlockingTask() attempts to access the mutex by performing
+ * a blocking 'take'. The blocking task has a lower priority than the
+ * controlling task so by the time it executes the mutex has already been
+ * taken by the controlling task, causing the blocking task to block. It
+ * does not unblock until the controlling task has given the mutex back,
+ * and it does not actually run until the controlling task has suspended
+ * itself (due to the relative priorities). When it eventually does obtain
+ * the mutex all it does is give the mutex back prior to also suspending
+ * itself. At this point both the controlling task and the blocking task are
+ * suspended.
+ *
+ * prvRecursiveMutexPollingTask() runs at the idle priority. It spins round
+ * a tight loop attempting to obtain the mutex with a non-blocking call. As
+ * the lowest priority task it will not successfully obtain the mutex until
+ * both the controlling and blocking tasks are suspended. Once it eventually
+ * does obtain the mutex it first unsuspends both the controlling task and
+ * blocking task prior to giving the mutex back - resulting in the polling
+ * task temporarily inheriting the controlling tasks priority.
+ */
/* Scheduler include files. */
#include "FreeRTOS.h"
@@ -70,29 +70,29 @@
#include "recmutex.h"
/* Priorities assigned to the three tasks. recmuCONTROLLING_TASK_PRIORITY can
-be overridden by a definition in FreeRTOSConfig.h. */
+ * be overridden by a definition in FreeRTOSConfig.h. */
#ifndef recmuCONTROLLING_TASK_PRIORITY
- #define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+ #define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#endif
-#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 )
+#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 )
/* The recursive call depth. */
-#define recmuMAX_COUNT ( 10 )
+#define recmuMAX_COUNT ( 10 )
/* Misc. */
-#define recmuSHORT_DELAY ( pdMS_TO_TICKS( 20 ) )
-#define recmuNO_DELAY ( ( TickType_t ) 0 )
-#define recmu15ms_DELAY ( pdMS_TO_TICKS( 15 ) )
+#define recmuSHORT_DELAY ( pdMS_TO_TICKS( 20 ) )
+#define recmuNO_DELAY ( ( TickType_t ) 0 )
+#define recmu15ms_DELAY ( pdMS_TO_TICKS( 15 ) )
#ifndef recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE
- #define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
+ #define recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE configMINIMAL_STACK_SIZE
#endif
/* The three tasks as described at the top of this file. */
-static void prvRecursiveMutexControllingTask( void *pvParameters );
-static void prvRecursiveMutexBlockingTask( void *pvParameters );
-static void prvRecursiveMutexPollingTask( void *pvParameters );
+static void prvRecursiveMutexControllingTask( void * pvParameters );
+static void prvRecursiveMutexBlockingTask( void * pvParameters );
+static void prvRecursiveMutexPollingTask( void * pvParameters );
/* The mutex used by the demo. */
static SemaphoreHandle_t xMutex;
@@ -102,315 +102,311 @@ static volatile BaseType_t xErrorOccurred = pdFALSE, xControllingIsSuspended = p
static volatile UBaseType_t uxControllingCycles = 0, uxBlockingCycles = 0, uxPollingCycles = 0;
/* Handles of the two higher priority tasks, required so they can be resumed
-(unsuspended). */
+ * (unsuspended). */
static TaskHandle_t xControllingTaskHandle, xBlockingTaskHandle;
/*-----------------------------------------------------------*/
void vStartRecursiveMutexTasks( void )
{
- /* Just creates the mutex and the three tasks. */
-
- xMutex = xSemaphoreCreateRecursiveMutex();
-
- if( xMutex != NULL )
- {
- /* vQueueAddToRegistry() adds the mutex to the registry, if one is
- in use. The registry is provided as a means for kernel aware
- debuggers to locate mutex and has no purpose if a kernel aware debugger
- is not being used. The call to vQueueAddToRegistry() will be removed
- by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
- defined to be less than 1. */
- vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Recursive_Mutex" );
-
- xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle );
- xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle );
- xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL );
- }
+ /* Just creates the mutex and the three tasks. */
+
+ xMutex = xSemaphoreCreateRecursiveMutex();
+
+ if( xMutex != NULL )
+ {
+ /* vQueueAddToRegistry() adds the mutex to the registry, if one is
+ * in use. The registry is provided as a means for kernel aware
+ * debuggers to locate mutex and has no purpose if a kernel aware debugger
+ * is not being used. The call to vQueueAddToRegistry() will be removed
+ * by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is
+ * defined to be less than 1. */
+ vQueueAddToRegistry( ( QueueHandle_t ) xMutex, "Recursive_Mutex" );
+
+ xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle );
+ xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle );
+ xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", recmuRECURSIVE_MUTEX_TEST_TASK_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL );
+ }
}
/*-----------------------------------------------------------*/
-static void prvRecursiveMutexControllingTask( void *pvParameters )
+static void prvRecursiveMutexControllingTask( void * pvParameters )
{
-UBaseType_t ux;
-
- /* Just to remove compiler warning. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Should not be able to 'give' the mutex, as we have not yet 'taken'
- it. The first time through, the mutex will not have been used yet,
- subsequent times through, at this point the mutex will be held by the
- polling task. */
- if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- for( ux = 0; ux < recmuMAX_COUNT; ux++ )
- {
- /* We should now be able to take the mutex as many times as
- we like.
-
- The first time through the mutex will be immediately available, on
- subsequent times through the mutex will be held by the polling task
- at this point and this Take will cause the polling task to inherit
- the priority of this task. In this case the block time must be
- long enough to ensure the polling task will execute again before the
- block time expires. If the block time does expire then the error
- flag will be set here. */
- if( xSemaphoreTakeRecursive( xMutex, recmu15ms_DELAY ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Ensure the other task attempting to access the mutex (and the
- other demo tasks) are able to execute to ensure they either block
- (where a block time is specified) or return an error (where no
- block time is specified) as the mutex is held by this task. */
- vTaskDelay( recmuSHORT_DELAY );
- }
-
- /* For each time we took the mutex, give it back. */
- for( ux = 0; ux < recmuMAX_COUNT; ux++ )
- {
- /* Ensure the other task attempting to access the mutex (and the
- other demo tasks) are able to execute. */
- vTaskDelay( recmuSHORT_DELAY );
-
- /* We should now be able to give the mutex as many times as we
- took it. When the mutex is available again the Blocking task
- should be unblocked but not run because it has a lower priority
- than this task. The polling task should also not run at this point
- as it too has a lower priority than this task. */
- if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
- }
-
- /* Having given it back the same number of times as it was taken, we
- should no longer be the mutex owner, so the next give should fail. */
- if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Keep count of the number of cycles this task has performed so a
- stall can be detected. */
- uxControllingCycles++;
-
- /* Suspend ourselves so the blocking task can execute. */
- xControllingIsSuspended = pdTRUE;
- vTaskSuspend( NULL );
- xControllingIsSuspended = pdFALSE;
- }
+ UBaseType_t ux;
+
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Should not be able to 'give' the mutex, as we have not yet 'taken'
+ * it. The first time through, the mutex will not have been used yet,
+ * subsequent times through, at this point the mutex will be held by the
+ * polling task. */
+ if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ for( ux = 0; ux < recmuMAX_COUNT; ux++ )
+ {
+ /* We should now be able to take the mutex as many times as
+ * we like.
+ *
+ * The first time through the mutex will be immediately available, on
+ * subsequent times through the mutex will be held by the polling task
+ * at this point and this Take will cause the polling task to inherit
+ * the priority of this task. In this case the block time must be
+ * long enough to ensure the polling task will execute again before the
+ * block time expires. If the block time does expire then the error
+ * flag will be set here. */
+ if( xSemaphoreTakeRecursive( xMutex, recmu15ms_DELAY ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Ensure the other task attempting to access the mutex (and the
+ * other demo tasks) are able to execute to ensure they either block
+ * (where a block time is specified) or return an error (where no
+ * block time is specified) as the mutex is held by this task. */
+ vTaskDelay( recmuSHORT_DELAY );
+ }
+
+ /* For each time we took the mutex, give it back. */
+ for( ux = 0; ux < recmuMAX_COUNT; ux++ )
+ {
+ /* Ensure the other task attempting to access the mutex (and the
+ * other demo tasks) are able to execute. */
+ vTaskDelay( recmuSHORT_DELAY );
+
+ /* We should now be able to give the mutex as many times as we
+ * took it. When the mutex is available again the Blocking task
+ * should be unblocked but not run because it has a lower priority
+ * than this task. The polling task should also not run at this point
+ * as it too has a lower priority than this task. */
+ if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+ }
+
+ /* Having given it back the same number of times as it was taken, we
+ * should no longer be the mutex owner, so the next give should fail. */
+ if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Keep count of the number of cycles this task has performed so a
+ * stall can be detected. */
+ uxControllingCycles++;
+
+ /* Suspend ourselves so the blocking task can execute. */
+ xControllingIsSuspended = pdTRUE;
+ vTaskSuspend( NULL );
+ xControllingIsSuspended = pdFALSE;
+ }
}
/*-----------------------------------------------------------*/
-static void prvRecursiveMutexBlockingTask( void *pvParameters )
+static void prvRecursiveMutexBlockingTask( void * pvParameters )
{
- /* Just to remove compiler warning. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* This task will run while the controlling task is blocked, and the
- controlling task will block only once it has the mutex - therefore
- this call should block until the controlling task has given up the
- mutex, and not actually execute past this call until the controlling
- task is suspended. portMAX_DELAY - 1 is used instead of portMAX_DELAY
- to ensure the task's state is reported as Blocked and not Suspended in
- a later call to configASSERT() (within the polling task). */
- if( xSemaphoreTakeRecursive( xMutex, ( portMAX_DELAY - 1 ) ) == pdPASS )
- {
- if( xControllingIsSuspended != pdTRUE )
- {
- /* Did not expect to execute until the controlling task was
- suspended. */
- xErrorOccurred = pdTRUE;
- }
- else
- {
- /* Give the mutex back before suspending ourselves to allow
- the polling task to obtain the mutex. */
- if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- xBlockingIsSuspended = pdTRUE;
- vTaskSuspend( NULL );
- xBlockingIsSuspended = pdFALSE;
- }
- }
- else
- {
- /* We should not leave the xSemaphoreTakeRecursive() function
- until the mutex was obtained. */
- xErrorOccurred = pdTRUE;
- }
-
- /* The controlling and blocking tasks should be in lock step. */
- if( uxControllingCycles != (UBaseType_t) ( uxBlockingCycles + 1 ) )
- {
- xErrorOccurred = pdTRUE;
- }
-
- /* Keep count of the number of cycles this task has performed so a
- stall can be detected. */
- uxBlockingCycles++;
- }
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* This task will run while the controlling task is blocked, and the
+ * controlling task will block only once it has the mutex - therefore
+ * this call should block until the controlling task has given up the
+ * mutex, and not actually execute past this call until the controlling
+ * task is suspended. portMAX_DELAY - 1 is used instead of portMAX_DELAY
+ * to ensure the task's state is reported as Blocked and not Suspended in
+ * a later call to configASSERT() (within the polling task). */
+ if( xSemaphoreTakeRecursive( xMutex, ( portMAX_DELAY - 1 ) ) == pdPASS )
+ {
+ if( xControllingIsSuspended != pdTRUE )
+ {
+ /* Did not expect to execute until the controlling task was
+ * suspended. */
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ /* Give the mutex back before suspending ourselves to allow
+ * the polling task to obtain the mutex. */
+ if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ xBlockingIsSuspended = pdTRUE;
+ vTaskSuspend( NULL );
+ xBlockingIsSuspended = pdFALSE;
+ }
+ }
+ else
+ {
+ /* We should not leave the xSemaphoreTakeRecursive() function
+ * until the mutex was obtained. */
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* The controlling and blocking tasks should be in lock step. */
+ if( uxControllingCycles != ( UBaseType_t ) ( uxBlockingCycles + 1 ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ /* Keep count of the number of cycles this task has performed so a
+ * stall can be detected. */
+ uxBlockingCycles++;
+ }
}
/*-----------------------------------------------------------*/
-static void prvRecursiveMutexPollingTask( void *pvParameters )
+static void prvRecursiveMutexPollingTask( void * pvParameters )
{
- /* Just to remove compiler warning. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Keep attempting to obtain the mutex. It should only be obtained when
- the blocking task has suspended itself, which in turn should only
- happen when the controlling task is also suspended. */
- if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS )
- {
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xControllingTaskHandle ) == eSuspended );
- configASSERT( eTaskGetState( xBlockingTaskHandle ) == eSuspended );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* Is the blocking task suspended? */
- if( ( xBlockingIsSuspended != pdTRUE ) || ( xControllingIsSuspended != pdTRUE ) )
- {
- xErrorOccurred = pdTRUE;
- }
- else
- {
- /* Keep count of the number of cycles this task has performed
- so a stall can be detected. */
- uxPollingCycles++;
-
- /* We can resume the other tasks here even though they have a
- higher priority than the polling task. When they execute they
- will attempt to obtain the mutex but fail because the polling
- task is still the mutex holder. The polling task (this task)
- will then inherit the higher priority. The Blocking task will
- block indefinitely when it attempts to obtain the mutex, the
- Controlling task will only block for a fixed period and an
- error will be latched if the polling task has not returned the
- mutex by the time this fixed period has expired. */
- vTaskResume( xBlockingTaskHandle );
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- vTaskResume( xControllingTaskHandle );
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
-
- /* The other two tasks should now have executed and no longer
- be suspended. */
- if( ( xBlockingIsSuspended == pdTRUE ) || ( xControllingIsSuspended == pdTRUE ) )
- {
- xErrorOccurred = pdTRUE;
- }
-
- #if( INCLUDE_uxTaskPriorityGet == 1 )
- {
- /* Check priority inherited. */
- configASSERT( uxTaskPriorityGet( NULL ) == recmuCONTROLLING_TASK_PRIORITY );
- }
- #endif /* INCLUDE_uxTaskPriorityGet */
-
- #if( INCLUDE_eTaskGetState == 1 )
- {
- configASSERT( eTaskGetState( xControllingTaskHandle ) == eBlocked );
- configASSERT( eTaskGetState( xBlockingTaskHandle ) == eBlocked );
- }
- #endif /* INCLUDE_eTaskGetState */
-
- /* Release the mutex, disinheriting the higher priority again. */
- if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
- {
- xErrorOccurred = pdTRUE;
- }
-
- #if( INCLUDE_uxTaskPriorityGet == 1 )
- {
- /* Check priority disinherited. */
- configASSERT( uxTaskPriorityGet( NULL ) == recmuPOLLING_TASK_PRIORITY );
- }
- #endif /* INCLUDE_uxTaskPriorityGet */
- }
- }
-
- #if configUSE_PREEMPTION == 0
- {
- taskYIELD();
- }
- #endif
- }
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Keep attempting to obtain the mutex. It should only be obtained when
+ * the blocking task has suspended itself, which in turn should only
+ * happen when the controlling task is also suspended. */
+ if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS )
+ {
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xControllingTaskHandle ) == eSuspended );
+ configASSERT( eTaskGetState( xBlockingTaskHandle ) == eSuspended );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* Is the blocking task suspended? */
+ if( ( xBlockingIsSuspended != pdTRUE ) || ( xControllingIsSuspended != pdTRUE ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ /* Keep count of the number of cycles this task has performed
+ * so a stall can be detected. */
+ uxPollingCycles++;
+
+ /* We can resume the other tasks here even though they have a
+ * higher priority than the polling task. When they execute they
+ * will attempt to obtain the mutex but fail because the polling
+ * task is still the mutex holder. The polling task (this task)
+ * will then inherit the higher priority. The Blocking task will
+ * block indefinitely when it attempts to obtain the mutex, the
+ * Controlling task will only block for a fixed period and an
+ * error will be latched if the polling task has not returned the
+ * mutex by the time this fixed period has expired. */
+ vTaskResume( xBlockingTaskHandle );
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ vTaskResume( xControllingTaskHandle );
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+
+ /* The other two tasks should now have executed and no longer
+ * be suspended. */
+ if( ( xBlockingIsSuspended == pdTRUE ) || ( xControllingIsSuspended == pdTRUE ) )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ #if ( INCLUDE_uxTaskPriorityGet == 1 )
+ {
+ /* Check priority inherited. */
+ configASSERT( uxTaskPriorityGet( NULL ) == recmuCONTROLLING_TASK_PRIORITY );
+ }
+ #endif /* INCLUDE_uxTaskPriorityGet */
+
+ #if ( INCLUDE_eTaskGetState == 1 )
+ {
+ configASSERT( eTaskGetState( xControllingTaskHandle ) == eBlocked );
+ configASSERT( eTaskGetState( xBlockingTaskHandle ) == eBlocked );
+ }
+ #endif /* INCLUDE_eTaskGetState */
+
+ /* Release the mutex, disinheriting the higher priority again. */
+ if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+
+ #if ( INCLUDE_uxTaskPriorityGet == 1 )
+ {
+ /* Check priority disinherited. */
+ configASSERT( uxTaskPriorityGet( NULL ) == recmuPOLLING_TASK_PRIORITY );
+ }
+ #endif /* INCLUDE_uxTaskPriorityGet */
+ }
+ }
+
+ #if configUSE_PREEMPTION == 0
+ {
+ taskYIELD();
+ }
+ #endif
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreRecursiveMutexTasksStillRunning( void )
{
-BaseType_t xReturn;
-static UBaseType_t uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0;
-
- /* Is the controlling task still cycling? */
- if( uxLastControllingCycles == uxControllingCycles )
- {
- xErrorOccurred = pdTRUE;
- }
- else
- {
- uxLastControllingCycles = uxControllingCycles;
- }
-
- /* Is the blocking task still cycling? */
- if( uxLastBlockingCycles == uxBlockingCycles )
- {
- xErrorOccurred = pdTRUE;
- }
- else
- {
- uxLastBlockingCycles = uxBlockingCycles;
- }
-
- /* Is the polling task still cycling? */
- if( uxLastPollingCycles == uxPollingCycles )
- {
- xErrorOccurred = pdTRUE;
- }
- else
- {
- uxLastPollingCycles = uxPollingCycles;
- }
-
- if( xErrorOccurred == pdTRUE )
- {
- xReturn = pdFAIL;
- }
- else
- {
- xReturn = pdPASS;
- }
-
- return xReturn;
+ BaseType_t xReturn;
+ static UBaseType_t uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0;
+
+ /* Is the controlling task still cycling? */
+ if( uxLastControllingCycles == uxControllingCycles )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ uxLastControllingCycles = uxControllingCycles;
+ }
+
+ /* Is the blocking task still cycling? */
+ if( uxLastBlockingCycles == uxBlockingCycles )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ uxLastBlockingCycles = uxBlockingCycles;
+ }
+
+ /* Is the polling task still cycling? */
+ if( uxLastPollingCycles == uxPollingCycles )
+ {
+ xErrorOccurred = pdTRUE;
+ }
+ else
+ {
+ uxLastPollingCycles = uxPollingCycles;
+ }
+
+ if( xErrorOccurred == pdTRUE )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
}
-
-
-
-
diff --git a/Demo/Common/Minimal/semtest.c b/Demo/Common/Minimal/semtest.c
index 20ca28b10..6d557c70f 100644
--- a/Demo/Common/Minimal/semtest.c
+++ b/Demo/Common/Minimal/semtest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -60,14 +60,14 @@
#include "semtest.h"
/* The value to which the shared variables are counted. */
-#define semtstBLOCKING_EXPECTED_VALUE ( ( uint32_t ) 0xfff )
-#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( uint32_t ) 0xff )
+#define semtstBLOCKING_EXPECTED_VALUE ( ( uint32_t ) 0xfff )
+#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( uint32_t ) 0xff )
-#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE
+#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE
-#define semtstNUM_TASKS ( 4 )
+#define semtstNUM_TASKS ( 4 )
-#define semtstDELAY_FACTOR ( ( TickType_t ) 10 )
+#define semtstDELAY_FACTOR ( ( TickType_t ) 10 )
/* The task function as described at the top of the file. */
static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters );
@@ -75,9 +75,9 @@ static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters );
/* Structure used to pass parameters to each task. */
typedef struct SEMAPHORE_PARAMETERS
{
- SemaphoreHandle_t xSemaphore;
- volatile uint32_t *pulSharedVariable;
- TickType_t xBlockTime;
+ SemaphoreHandle_t xSemaphore;
+ volatile uint32_t * pulSharedVariable;
+ TickType_t xBlockTime;
} xSemaphoreParameters;
/* Variables used to check that all the tasks are still running without errors. */
@@ -88,182 +88,185 @@ static volatile short sNextCheckVariable = 0;
void vStartSemaphoreTasks( UBaseType_t uxPriority )
{
-xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;
-const TickType_t xBlockTime = ( TickType_t ) 100;
-
- /* Create the structure used to pass parameters to the first two tasks. */
- pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
-
- if( pxFirstSemaphoreParameters != NULL )
- {
- /* Create the semaphore used by the first two tasks. */
- pxFirstSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary();
-
- if( pxFirstSemaphoreParameters->xSemaphore != NULL )
- {
- xSemaphoreGive( pxFirstSemaphoreParameters->xSemaphore );
-
- /* Create the variable which is to be shared by the first two tasks. */
- pxFirstSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) );
-
- /* Initialise the share variable to the value the tasks expect. */
- *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
-
- /* The first two tasks do not block on semaphore calls. */
- pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0;
-
- /* Spawn the first two tasks. As they poll they operate at the idle priority. */
- xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
- xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
-
- /* vQueueAddToRegistry() adds the semaphore to the registry, if one
- is in use. The registry is provided as a means for kernel aware
- debuggers to locate semaphores and has no purpose if a kernel aware
- debugger is not being used. The call to vQueueAddToRegistry() will
- be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
- defined or is defined to be less than 1. */
- vQueueAddToRegistry( ( QueueHandle_t ) pxFirstSemaphoreParameters->xSemaphore, "Counting_Sem_1" );
- }
- }
-
- /* Do exactly the same to create the second set of tasks, only this time
- provide a block time for the semaphore calls. */
- pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
- if( pxSecondSemaphoreParameters != NULL )
- {
- pxSecondSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary();
-
- if( pxSecondSemaphoreParameters->xSemaphore != NULL )
- {
- xSemaphoreGive( pxSecondSemaphoreParameters->xSemaphore );
-
- pxSecondSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) );
- *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
- pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS;
-
- xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
- xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
-
- /* vQueueAddToRegistry() adds the semaphore to the registry, if one
- is in use. The registry is provided as a means for kernel aware
- debuggers to locate semaphores and has no purpose if a kernel aware
- debugger is not being used. The call to vQueueAddToRegistry() will
- be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
- defined or is defined to be less than 1. */
- vQueueAddToRegistry( ( QueueHandle_t ) pxSecondSemaphoreParameters->xSemaphore, "Counting_Sem_2" );
- }
- }
+ xSemaphoreParameters * pxFirstSemaphoreParameters, * pxSecondSemaphoreParameters;
+ const TickType_t xBlockTime = ( TickType_t ) 100;
+
+ /* Create the structure used to pass parameters to the first two tasks. */
+ pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+
+ if( pxFirstSemaphoreParameters != NULL )
+ {
+ /* Create the semaphore used by the first two tasks. */
+ pxFirstSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary();
+
+ if( pxFirstSemaphoreParameters->xSemaphore != NULL )
+ {
+ xSemaphoreGive( pxFirstSemaphoreParameters->xSemaphore );
+
+ /* Create the variable which is to be shared by the first two tasks. */
+ pxFirstSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) );
+
+ /* Initialise the share variable to the value the tasks expect. */
+ *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;
+
+ /* The first two tasks do not block on semaphore calls. */
+ pxFirstSemaphoreParameters->xBlockTime = ( TickType_t ) 0;
+
+ /* Spawn the first two tasks. As they poll they operate at the idle priority. */
+ xTaskCreate( prvSemaphoreTest, "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+ xTaskCreate( prvSemaphoreTest, "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( TaskHandle_t * ) NULL );
+
+ /* vQueueAddToRegistry() adds the semaphore to the registry, if one
+ * is in use. The registry is provided as a means for kernel aware
+ * debuggers to locate semaphores and has no purpose if a kernel aware
+ * debugger is not being used. The call to vQueueAddToRegistry() will
+ * be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+ * defined or is defined to be less than 1. */
+ vQueueAddToRegistry( ( QueueHandle_t ) pxFirstSemaphoreParameters->xSemaphore, "Counting_Sem_1" );
+ }
+ }
+
+ /* Do exactly the same to create the second set of tasks, only this time
+ * provide a block time for the semaphore calls. */
+ pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );
+
+ if( pxSecondSemaphoreParameters != NULL )
+ {
+ pxSecondSemaphoreParameters->xSemaphore = xSemaphoreCreateBinary();
+
+ if( pxSecondSemaphoreParameters->xSemaphore != NULL )
+ {
+ xSemaphoreGive( pxSecondSemaphoreParameters->xSemaphore );
+
+ pxSecondSemaphoreParameters->pulSharedVariable = ( uint32_t * ) pvPortMalloc( sizeof( uint32_t ) );
+ *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;
+ pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_PERIOD_MS;
+
+ xTaskCreate( prvSemaphoreTest, "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+ xTaskCreate( prvSemaphoreTest, "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( TaskHandle_t * ) NULL );
+
+ /* vQueueAddToRegistry() adds the semaphore to the registry, if one
+ * is in use. The registry is provided as a means for kernel aware
+ * debuggers to locate semaphores and has no purpose if a kernel aware
+ * debugger is not being used. The call to vQueueAddToRegistry() will
+ * be removed by the pre-processor if configQUEUE_REGISTRY_SIZE is not
+ * defined or is defined to be less than 1. */
+ vQueueAddToRegistry( ( QueueHandle_t ) pxSecondSemaphoreParameters->xSemaphore, "Counting_Sem_2" );
+ }
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( prvSemaphoreTest, pvParameters )
{
-xSemaphoreParameters *pxParameters;
-volatile uint32_t *pulSharedVariable, ulExpectedValue;
-uint32_t ulCounter;
-short sError = pdFALSE, sCheckVariableToUse;
-
- /* See which check variable to use. sNextCheckVariable is not semaphore
- protected! */
- portENTER_CRITICAL();
- sCheckVariableToUse = sNextCheckVariable;
- sNextCheckVariable++;
- portEXIT_CRITICAL();
-
- /* A structure is passed in as the parameter. This contains the shared
- variable being guarded. */
- pxParameters = ( xSemaphoreParameters * ) pvParameters;
- pulSharedVariable = pxParameters->pulSharedVariable;
-
- /* If we are blocking we use a much higher count to ensure loads of context
- switches occur during the count. */
- if( pxParameters->xBlockTime > ( TickType_t ) 0 )
- {
- ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
- }
- else
- {
- ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
- }
-
- for( ;; )
- {
- /* Try to obtain the semaphore. */
- if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
- {
- /* We have the semaphore and so expect any other tasks using the
- shared variable to have left it in the state we expect to find
- it. */
- if( *pulSharedVariable != ulExpectedValue )
- {
- sError = pdTRUE;
- }
-
- /* Clear the variable, then count it back up to the expected value
- before releasing the semaphore. Would expect a context switch or
- two during this time. */
- for( ulCounter = ( uint32_t ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
- {
- *pulSharedVariable = ulCounter;
- if( *pulSharedVariable != ulCounter )
- {
- sError = pdTRUE;
- }
- }
-
- /* Release the semaphore, and if no errors have occurred increment the check
- variable. */
- if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- if( sCheckVariableToUse < semtstNUM_TASKS )
- {
- ( sCheckVariables[ sCheckVariableToUse ] )++;
- }
- }
-
- /* If we have a block time then we are running at a priority higher
- than the idle priority. This task takes a long time to complete
- a cycle (deliberately so to test the guarding) so will be starving
- out lower priority tasks. Block for some time to allow give lower
- priority tasks some processor time. */
- vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
- }
- else
- {
- if( pxParameters->xBlockTime == ( TickType_t ) 0 )
- {
- /* We have not got the semaphore yet, so no point using the
- processor. We are not blocking when attempting to obtain the
- semaphore. */
- taskYIELD();
- }
- }
- }
+ xSemaphoreParameters * pxParameters;
+ volatile uint32_t * pulSharedVariable, ulExpectedValue;
+ uint32_t ulCounter;
+ short sError = pdFALSE, sCheckVariableToUse;
+
+ /* See which check variable to use. sNextCheckVariable is not semaphore
+ * protected! */
+ portENTER_CRITICAL();
+ sCheckVariableToUse = sNextCheckVariable;
+ sNextCheckVariable++;
+ portEXIT_CRITICAL();
+
+ /* A structure is passed in as the parameter. This contains the shared
+ * variable being guarded. */
+ pxParameters = ( xSemaphoreParameters * ) pvParameters;
+ pulSharedVariable = pxParameters->pulSharedVariable;
+
+ /* If we are blocking we use a much higher count to ensure loads of context
+ * switches occur during the count. */
+ if( pxParameters->xBlockTime > ( TickType_t ) 0 )
+ {
+ ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;
+ }
+ else
+ {
+ ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;
+ }
+
+ for( ; ; )
+ {
+ /* Try to obtain the semaphore. */
+ if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )
+ {
+ /* We have the semaphore and so expect any other tasks using the
+ * shared variable to have left it in the state we expect to find
+ * it. */
+ if( *pulSharedVariable != ulExpectedValue )
+ {
+ sError = pdTRUE;
+ }
+
+ /* Clear the variable, then count it back up to the expected value
+ * before releasing the semaphore. Would expect a context switch or
+ * two during this time. */
+ for( ulCounter = ( uint32_t ) 0; ulCounter <= ulExpectedValue; ulCounter++ )
+ {
+ *pulSharedVariable = ulCounter;
+
+ if( *pulSharedVariable != ulCounter )
+ {
+ sError = pdTRUE;
+ }
+ }
+
+ /* Release the semaphore, and if no errors have occurred increment the check
+ * variable. */
+ if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ if( sCheckVariableToUse < semtstNUM_TASKS )
+ {
+ ( sCheckVariables[ sCheckVariableToUse ] )++;
+ }
+ }
+
+ /* If we have a block time then we are running at a priority higher
+ * than the idle priority. This task takes a long time to complete
+ * a cycle (deliberately so to test the guarding) so will be starving
+ * out lower priority tasks. Block for some time to allow give lower
+ * priority tasks some processor time. */
+ if( pxParameters->xBlockTime != ( TickType_t ) 0 )
+ {
+ vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );
+ }
+ }
+ else
+ {
+ if( pxParameters->xBlockTime == ( TickType_t ) 0 )
+ {
+ /* We have not got the semaphore yet, so no point using the
+ * processor. We are not blocking when attempting to obtain the
+ * semaphore. */
+ taskYIELD();
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
/* This is called to check that all the created tasks are still running. */
BaseType_t xAreSemaphoreTasksStillRunning( void )
{
-static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
-BaseType_t xTask, xReturn = pdTRUE;
+ static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };
+ BaseType_t xTask, xReturn = pdTRUE;
- for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
- {
- if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
- {
- xReturn = pdFALSE;
- }
+ for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )
+ {
+ if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )
+ {
+ xReturn = pdFALSE;
+ }
- sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
- }
+ sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];
+ }
- return xReturn;
+ return xReturn;
}
-
-
diff --git a/Demo/Common/Minimal/sp_flop.c b/Demo/Common/Minimal/sp_flop.c
index ade5a2544..32261bcca 100644
--- a/Demo/Common/Minimal/sp_flop.c
+++ b/Demo/Common/Minimal/sp_flop.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -48,254 +48,255 @@
/* Demo program include files. */
#include "flop.h"
-#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
-#define mathNUMBER_OF_TASKS ( 8 )
+#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
+#define mathNUMBER_OF_TASKS ( 8 )
/* Four tasks, each of which performs a different floating point calculation.
-Each of the four is created twice. */
+ * Each of the four is created twice. */
static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
/* These variables are used to check that all the tasks are still running. If a
-task gets a calculation wrong it will
-stop incrementing its check variable. */
+ * task gets a calculation wrong it will
+ * stop incrementing its check variable. */
static volatile uint16_t usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
/*-----------------------------------------------------------*/
void vStartMathTasks( UBaseType_t uxPriority )
{
- xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
- xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask1, "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask1, "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
{
-volatile float f1, f2, f3, f4;
-volatile uint16_t *pusTaskCheckVariable;
-volatile float fAnswer;
-short sError = pdFALSE;
-
- f1 = 123.4567F;
- f2 = 2345.6789F;
- f3 = -918.222F;
-
- fAnswer = ( f1 + f2 ) * f3;
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( uint16_t * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for(;;)
- {
- f1 = 123.4567F;
- f2 = 2345.6789F;
- f3 = -918.222F;
-
- f4 = ( f1 + f2 ) * f3;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( fabs( f4 - fAnswer ) > 0.001F )
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- }
+ volatile float f1, f2, f3, f4;
+ volatile uint16_t * pusTaskCheckVariable;
+ volatile float fAnswer;
+ short sError = pdFALSE;
+
+ f1 = 123.4567F;
+ f2 = 2345.6789F;
+ f3 = -918.222F;
+
+ fAnswer = ( f1 + f2 ) * f3;
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ f1 = 123.4567F;
+ f2 = 2345.6789F;
+ f3 = -918.222F;
+
+ f4 = ( f1 + f2 ) * f3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( fabs( f4 - fAnswer ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
{
-volatile float f1, f2, f3, f4;
-volatile uint16_t *pusTaskCheckVariable;
-volatile float fAnswer;
-short sError = pdFALSE;
-
- f1 = -389.38F;
- f2 = 32498.2F;
- f3 = -2.0001F;
-
- fAnswer = ( f1 / f2 ) * f3;
-
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( uint16_t * ) pvParameters;
-
- /* Keep performing a calculation and checking the result against a constant. */
- for( ;; )
- {
- f1 = -389.38F;
- f2 = 32498.2F;
- f3 = -2.0001F;
-
- f4 = ( f1 / f2 ) * f3;
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- /* If the calculation does not match the expected constant, stop the
- increment of the check variable. */
- if( fabs( f4 - fAnswer ) > 0.001F )
- {
- sError = pdTRUE;
- }
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know
- this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
- }
+ volatile float f1, f2, f3, f4;
+ volatile uint16_t * pusTaskCheckVariable;
+ volatile float fAnswer;
+ short sError = pdFALSE;
+
+ f1 = -389.38F;
+ f2 = 32498.2F;
+ f3 = -2.0001F;
+
+ fAnswer = ( f1 / f2 ) * f3;
+
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ; ; )
+ {
+ f1 = -389.38F;
+ f2 = 32498.2F;
+ f3 = -2.0001F;
+
+ f4 = ( f1 / f2 ) * f3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ * increment of the check variable. */
+ if( fabs( f4 - fAnswer ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know
+ * this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
{
-volatile float *pfArray, fTotal1, fTotal2, fDifference, fPosition;
-volatile uint16_t *pusTaskCheckVariable;
-const size_t xArraySize = 10;
-size_t xPosition;
-short sError = pdFALSE;
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( uint16_t * ) pvParameters;
-
- pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) );
-
- /* Keep filling an array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- fTotal1 = 0.0F;
- fTotal2 = 0.0F;
- fPosition = 0.0F;
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- pfArray[ xPosition ] = fPosition + 5.5F;
- fTotal1 += fPosition + 5.5F;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- fTotal2 += pfArray[ xPosition ];
- }
-
- fDifference = fTotal1 - fTotal2;
- if( fabs( fDifference ) > 0.001F )
- {
- sError = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ volatile float * pfArray, fTotal1, fTotal2, fDifference, fPosition;
+ volatile uint16_t * pusTaskCheckVariable;
+ const size_t xArraySize = 10;
+ size_t xPosition;
+ short sError = pdFALSE;
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+ pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ fTotal1 = 0.0F;
+ fTotal2 = 0.0F;
+ fPosition = 0.0F;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pfArray[ xPosition ] = fPosition + 5.5F;
+ fTotal1 += fPosition + 5.5F;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ fTotal2 += pfArray[ xPosition ];
+ }
+
+ fDifference = fTotal1 - fTotal2;
+
+ if( fabs( fDifference ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
{
-volatile float *pfArray, fTotal1, fTotal2, fDifference, fPosition;
-volatile uint16_t *pusTaskCheckVariable;
-const size_t xArraySize = 10;
-size_t xPosition;
-short sError = pdFALSE;
-
- /* The variable this task increments to show it is still running is passed in
- as the parameter. */
- pusTaskCheckVariable = ( uint16_t * ) pvParameters;
-
- pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) );
-
- /* Keep filling an array, keeping a running total of the values placed in the
- array. Then run through the array adding up all the values. If the two totals
- do not match, stop the check variable from incrementing. */
- for( ;; )
- {
- fTotal1 = 0.0F;
- fTotal2 = 0.0F;
- fPosition = 0.0F;
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- pfArray[ xPosition ] = fPosition * 12.123F;
- fTotal1 += fPosition * 12.123F;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- for( xPosition = 0; xPosition < xArraySize; xPosition++ )
- {
- fTotal2 += pfArray[ xPosition ];
- }
-
- fDifference = fTotal1 - fTotal2;
- if( fabs( fDifference ) > 0.001F )
- {
- sError = pdTRUE;
- }
-
- #if configUSE_PREEMPTION == 0
- taskYIELD();
- #endif
-
- if( sError == pdFALSE )
- {
- /* If the calculation has always been correct, increment the check
- variable so we know this task is still running okay. */
- ( *pusTaskCheckVariable )++;
- }
- }
+ volatile float * pfArray, fTotal1, fTotal2, fDifference, fPosition;
+ volatile uint16_t * pusTaskCheckVariable;
+ const size_t xArraySize = 10;
+ size_t xPosition;
+ short sError = pdFALSE;
+
+ /* The variable this task increments to show it is still running is passed in
+ * as the parameter. */
+ pusTaskCheckVariable = ( uint16_t * ) pvParameters;
+
+ pfArray = ( float * ) pvPortMalloc( xArraySize * sizeof( float ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ * array. Then run through the array adding up all the values. If the two totals
+ * do not match, stop the check variable from incrementing. */
+ for( ; ; )
+ {
+ fTotal1 = 0.0F;
+ fTotal2 = 0.0F;
+ fPosition = 0.0F;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pfArray[ xPosition ] = fPosition * 12.123F;
+ fTotal1 += fPosition * 12.123F;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ fTotal2 += pfArray[ xPosition ];
+ }
+
+ fDifference = fTotal1 - fTotal2;
+
+ if( fabs( fDifference ) > 0.001F )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ * variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
}
/*-----------------------------------------------------------*/
@@ -303,25 +304,22 @@ short sError = pdFALSE;
BaseType_t xAreMathsTaskStillRunning( void )
{
/* Keep a history of the check variables so we know if they have been incremented
-since the last call. */
-static uint16_t usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
-BaseType_t xReturn = pdTRUE, xTask;
-
- /* Check the maths tasks are still running by ensuring their check variables
- are still incrementing. */
- for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
- {
- if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
- {
- /* The check has not incremented so an error exists. */
- xReturn = pdFALSE;
- }
-
- usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
- }
-
- return xReturn;
+ * since the last call. */
+ static uint16_t usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( uint16_t ) 0 };
+ BaseType_t xReturn = pdTRUE, xTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ * are still incrementing. */
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+ {
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+ }
+
+ return xReturn;
}
-
-
-
diff --git a/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c b/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c
index bc23cd82f..3aed7a9ea 100644
--- a/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c
+++ b/Demo/Common/ethernet/lwip-1.4.0/ports/MicroBlaze-Ethernet-Lite/ethernetif.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/* FreeRTOS includes. */
@@ -182,7 +181,7 @@ unsigned portBASE_TYPE uxOriginalPriority;
*
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
* strange results. You might consider waiting for space in the DMA queue
- * to become availale since the stack doesn't retry to send a packet
+ * to become available since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
diff --git a/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c b/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c
index b5231a757..37da99e61 100644
--- a/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c
+++ b/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/arch.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h b/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h
index 7ab8abc00..4dc1bfe55 100644
--- a/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h
+++ b/Demo/Common/ethernet/lwip-1.4.0/ports/win32/WinPCap/netif.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c b/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c
index 4224af2d2..5be0e88d3 100644
--- a/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c
+++ b/Demo/Common/ethernet/lwip-1.4.0/ports/win32/ethernetif.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/* WinPCap includes. */
@@ -171,7 +170,7 @@ pcap_if_t *pxAllNetworkInterfaces;
*
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
* strange results. You might consider waiting for space in the DMA queue
- * to become availale since the stack doesn't retry to send a packet
+ * to become available since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
diff --git a/Demo/Common/include/AbortDelay.h b/Demo/Common/include/AbortDelay.h
index ce8e9a11b..6e9fb19b8 100644
--- a/Demo/Common/include/AbortDelay.h
+++ b/Demo/Common/include/AbortDelay.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vCreateAbortDelayTasks( void );
BaseType_t xAreAbortDelayTestTasksStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/BlockQ.h b/Demo/Common/include/BlockQ.h
index d2905b97a..52df7ca3c 100644
--- a/Demo/Common/include/BlockQ.h
+++ b/Demo/Common/include/BlockQ.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vStartBlockingQueueTasks( UBaseType_t uxPriority );
BaseType_t xAreBlockingQueuesStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/EventGroupsDemo.h b/Demo/Common/include/EventGroupsDemo.h
index 3e46575d4..186f3e816 100644
--- a/Demo/Common/include/EventGroupsDemo.h
+++ b/Demo/Common/include/EventGroupsDemo.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -41,4 +41,3 @@ BaseType_t xAreEventGroupTasksStillRunning( void );
void vPeriodicEventGroupsProcessing( void );
#endif /* EVENT_GROUPS_DEMO_H */
-
diff --git a/Demo/Common/include/GenQTest.h b/Demo/Common/include/GenQTest.h
index 1c2a7231c..0ddf246f9 100644
--- a/Demo/Common/include/GenQTest.h
+++ b/Demo/Common/include/GenQTest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -33,6 +33,3 @@ BaseType_t xAreGenericQueueTasksStillRunning( void );
void vMutexISRInteractionTest( void );
#endif /* GEN_Q_TEST_H */
-
-
-
diff --git a/Demo/Common/include/IntQueue.h b/Demo/Common/include/IntQueue.h
index 1ca270ed9..b2c4ce99f 100644
--- a/Demo/Common/include/IntQueue.h
+++ b/Demo/Common/include/IntQueue.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -34,9 +34,3 @@ BaseType_t xFirstTimerHandler( void );
BaseType_t xSecondTimerHandler( void );
#endif /* QUEUE_ACCESS_TEST */
-
-
-
-
-
-
diff --git a/Demo/Common/include/IntSemTest.h b/Demo/Common/include/IntSemTest.h
index 622732dfb..33cc147f0 100644
--- a/Demo/Common/include/IntSemTest.h
+++ b/Demo/Common/include/IntSemTest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -33,6 +33,3 @@ BaseType_t xAreInterruptSemaphoreTasksStillRunning( void );
void vInterruptSemaphorePeriodicTest( void );
#endif /* INT_SEM_TEST_H */
-
-
-
diff --git a/Demo/Common/include/MessageBufferAMP.h b/Demo/Common/include/MessageBufferAMP.h
index a385154fa..f37cd30b6 100644
--- a/Demo/Common/include/MessageBufferAMP.h
+++ b/Demo/Common/include/MessageBufferAMP.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Common/include/MessageBufferDemo.h b/Demo/Common/include/MessageBufferDemo.h
index d8ca83a27..e0cad845b 100644
--- a/Demo/Common/include/MessageBufferDemo.h
+++ b/Demo/Common/include/MessageBufferDemo.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,10 +28,7 @@
#ifndef MESSAGE_BUFFER_TEST_H
#define MESSAGE_BUFFER_TEST_H
-void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize );
+void vStartMessageBufferTasks( configSTACK_DEPTH_TYPE xStackSize );
BaseType_t xAreMessageBufferTasksStillRunning( void );
#endif /* MESSAGE_BUFFER_TEST_H */
-
-
-
diff --git a/Demo/Common/include/PollQ.h b/Demo/Common/include/PollQ.h
index 009519529..b7c53381b 100644
--- a/Demo/Common/include/PollQ.h
+++ b/Demo/Common/include/PollQ.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vStartPolledQueueTasks( UBaseType_t uxPriority );
BaseType_t xArePollingQueuesStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/QPeek.h b/Demo/Common/include/QPeek.h
index d0733cb6b..e5bb38a4b 100644
--- a/Demo/Common/include/QPeek.h
+++ b/Demo/Common/include/QPeek.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,6 +32,3 @@ void vStartQueuePeekTasks( void );
BaseType_t xAreQueuePeekTasksStillRunning( void );
#endif /* Q_PEEK_TEST_H */
-
-
-
diff --git a/Demo/Common/include/QueueOverwrite.h b/Demo/Common/include/QueueOverwrite.h
index 9465d6786..18d1a394a 100644
--- a/Demo/Common/include/QueueOverwrite.h
+++ b/Demo/Common/include/QueueOverwrite.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -33,5 +33,3 @@ BaseType_t xIsQueueOverwriteTaskStillRunning( void );
void vQueueOverwritePeriodicISRDemo( void );
#endif /* QUEUE_OVERWRITE_H */
-
-
diff --git a/Demo/Common/include/QueueSet.h b/Demo/Common/include/QueueSet.h
index 03ceaea71..a326c7691 100644
--- a/Demo/Common/include/QueueSet.h
+++ b/Demo/Common/include/QueueSet.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -33,5 +33,3 @@ BaseType_t xAreQueueSetTasksStillRunning( void );
void vQueueSetAccessQueueSetFromISR( void );
#endif /* QUEUE_WAIT_MULTIPLE_H */
-
-
diff --git a/Demo/Common/include/QueueSetPolling.h b/Demo/Common/include/QueueSetPolling.h
index c86a53d5f..ed815bd1e 100644
--- a/Demo/Common/include/QueueSetPolling.h
+++ b/Demo/Common/include/QueueSetPolling.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -33,5 +33,3 @@ BaseType_t xAreQueueSetPollTasksStillRunning( void );
void vQueueSetPollingInterruptAccess( void );
#endif /* QUEUE_SET_POLLING_H */
-
-
diff --git a/Demo/Common/include/StaticAllocation.h b/Demo/Common/include/StaticAllocation.h
index ec2b1d1f2..92c9d5294 100644
--- a/Demo/Common/include/StaticAllocation.h
+++ b/Demo/Common/include/StaticAllocation.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,10 +28,7 @@
#ifndef STATIC_ALLOCATION_H
#define STATIC_ALLOCATION_H
-void vStartStaticallyAllocatedTasks( void );
+void vStartStaticallyAllocatedTasks( void );
BaseType_t xAreStaticAllocationTasksStillRunning( void );
#endif /* STATIC_ALLOCATION_H */
-
-
-
diff --git a/Demo/Common/include/StreamBufferDemo.h b/Demo/Common/include/StreamBufferDemo.h
index cddcc91b9..c96b57f74 100644
--- a/Demo/Common/include/StreamBufferDemo.h
+++ b/Demo/Common/include/StreamBufferDemo.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -33,6 +33,3 @@ BaseType_t xAreStreamBufferTasksStillRunning( void );
void vPeriodicStreamBufferProcessing( void );
#endif /* STREAM_BUFFER_TEST_H */
-
-
-
diff --git a/Demo/Common/include/StreamBufferInterrupt.h b/Demo/Common/include/StreamBufferInterrupt.h
index cf8c75075..3cb368ab8 100644
--- a/Demo/Common/include/StreamBufferInterrupt.h
+++ b/Demo/Common/include/StreamBufferInterrupt.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Common/include/TaskNotify.h b/Demo/Common/include/TaskNotify.h
index a7588b6b0..5e8738c62 100644
--- a/Demo/Common/include/TaskNotify.h
+++ b/Demo/Common/include/TaskNotify.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,11 +28,8 @@
#ifndef TASK_NOTIFY_H
#define TASK_NOTIFY_H
-void vStartTaskNotifyTask( void );
+void vStartTaskNotifyTask( void );
BaseType_t xAreTaskNotificationTasksStillRunning( void );
void xNotifyTaskFromISR( void );
#endif /* TASK_NOTIFY_H */
-
-
-
diff --git a/Demo/Common/include/TaskNotifyArray.h b/Demo/Common/include/TaskNotifyArray.h
index c4aefe5cc..d941e8eda 100644
--- a/Demo/Common/include/TaskNotifyArray.h
+++ b/Demo/Common/include/TaskNotifyArray.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,11 +28,8 @@
#ifndef TASK_NOTIFY_ARRAY_H
#define TASK_NOTIFY_ARRAY_H
-void vStartTaskNotifyArrayTask( void );
+void vStartTaskNotifyArrayTask( void );
BaseType_t xAreTaskNotificationArrayTasksStillRunning( void );
void xNotifyArrayTaskFromISR( void );
#endif /* TASK_NOTIFY_ARRAY_H */
-
-
-
diff --git a/Demo/Common/include/TimerDemo.h b/Demo/Common/include/TimerDemo.h
index 4b2a3550f..437ff72c4 100644
--- a/Demo/Common/include/TimerDemo.h
+++ b/Demo/Common/include/TimerDemo.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
#ifndef TIMER_DEMO_H
@@ -31,8 +30,6 @@
void vStartTimerDemoTask( TickType_t xBaseFrequencyIn );
BaseType_t xAreTimerDemoTasksStillRunning( TickType_t xCycleFrequency );
void vTimerPeriodicISRTests( void );
+void vTimerDemoIncludeBacklogTests( BaseType_t includeBacklogTests );
#endif /* TIMER_DEMO_H */
-
-
-
diff --git a/Demo/Common/include/blocktim.h b/Demo/Common/include/blocktim.h
index 0310e7efd..29bc8a03c 100644
--- a/Demo/Common/include/blocktim.h
+++ b/Demo/Common/include/blocktim.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vCreateBlockTimeTasks( void );
BaseType_t xAreBlockTimeTestTasksStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/comtest.h b/Demo/Common/include/comtest.h
index 278b2b84e..b1a2a6c4a 100644
--- a/Demo/Common/include/comtest.h
+++ b/Demo/Common/include/comtest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,10 +28,13 @@
#ifndef COMTEST_H
#define COMTEST_H
-void vAltStartComTestTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED );
-void vStartComTestTasks( UBaseType_t uxPriority, eCOMPort ePort, eBaud eBaudRate );
+void vAltStartComTestTasks( UBaseType_t uxPriority,
+ uint32_t ulBaudRate,
+ UBaseType_t uxLED );
+void vStartComTestTasks( UBaseType_t uxPriority,
+ eCOMPort ePort,
+ eBaud eBaudRate );
BaseType_t xAreComTestTasksStillRunning( void );
void vComTestUnsuspendTask( void );
-#endif
-
+#endif /* ifndef COMTEST_H */
diff --git a/Demo/Common/include/comtest2.h b/Demo/Common/include/comtest2.h
index 6db9146a5..6a52ee878 100644
--- a/Demo/Common/include/comtest2.h
+++ b/Demo/Common/include/comtest2.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,8 +28,9 @@
#ifndef COMTEST_H
#define COMTEST_H
-void vAltStartComTestTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED );
+void vAltStartComTestTasks( UBaseType_t uxPriority,
+ uint32_t ulBaudRate,
+ UBaseType_t uxLED );
BaseType_t xAreComTestTasksStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/comtest_strings.h b/Demo/Common/include/comtest_strings.h
index b3b4480c7..18b138900 100644
--- a/Demo/Common/include/comtest_strings.h
+++ b/Demo/Common/include/comtest_strings.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,8 +28,9 @@
#ifndef COMTEST_STRINGS_H
#define COMTEST_STRINGS_H
-void vStartComTestStringsTasks( UBaseType_t uxPriority, uint32_t ulBaudRate, UBaseType_t uxLED );
+void vStartComTestStringsTasks( UBaseType_t uxPriority,
+ uint32_t ulBaudRate,
+ UBaseType_t uxLED );
BaseType_t xAreComTestTasksStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/countsem.h b/Demo/Common/include/countsem.h
index f9f7f48e6..48cbc6422 100644
--- a/Demo/Common/include/countsem.h
+++ b/Demo/Common/include/countsem.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,4 +32,3 @@ void vStartCountingSemaphoreTasks( void );
BaseType_t xAreCountingSemaphoreTasksStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/crflash.h b/Demo/Common/include/crflash.h
index 78dbbf9cd..ded8863b5 100644
--- a/Demo/Common/include/crflash.h
+++ b/Demo/Common/include/crflash.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -44,4 +44,3 @@ void vStartFlashCoRoutines( UBaseType_t uxPriority );
BaseType_t xAreFlashCoRoutinesStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/crhook.h b/Demo/Common/include/crhook.h
index 1fcd10422..3b45603d8 100644
--- a/Demo/Common/include/crhook.h
+++ b/Demo/Common/include/crhook.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -40,4 +40,3 @@ void vStartHookCoRoutines( void );
BaseType_t xAreHookCoRoutinesStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/death.h b/Demo/Common/include/death.h
index c1062e2f3..20ad76361 100644
--- a/Demo/Common/include/death.h
+++ b/Demo/Common/include/death.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vCreateSuicidalTasks( UBaseType_t uxPriority );
BaseType_t xIsCreateTaskStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/dynamic.h b/Demo/Common/include/dynamic.h
index ff84fe0d1..2abf9c3cd 100644
--- a/Demo/Common/include/dynamic.h
+++ b/Demo/Common/include/dynamic.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vStartDynamicPriorityTasks( void );
BaseType_t xAreDynamicPriorityTasksStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/fileIO.h b/Demo/Common/include/fileIO.h
index ab0e9baaf..1f0d79292 100644
--- a/Demo/Common/include/fileIO.h
+++ b/Demo/Common/include/fileIO.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -30,7 +30,7 @@
void vDisplayMessage( const char * const pcMessageToPrint );
void vWriteMessageToDisk( const char * const pcMessage );
-void vWriteBufferToDisk( const char * const pcBuffer, uint32_t ulBufferLength );
+void vWriteBufferToDisk( const char * const pcBuffer,
+ uint32_t ulBufferLength );
#endif
-
diff --git a/Demo/Common/include/flash.h b/Demo/Common/include/flash.h
index 1422d6e96..ed36fbdb6 100644
--- a/Demo/Common/include/flash.h
+++ b/Demo/Common/include/flash.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -31,4 +31,3 @@
void vStartLEDFlashTasks( UBaseType_t uxPriority );
#endif
-
diff --git a/Demo/Common/include/flash_timer.h b/Demo/Common/include/flash_timer.h
index 3b02592de..06767495d 100644
--- a/Demo/Common/include/flash_timer.h
+++ b/Demo/Common/include/flash_timer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -30,7 +30,7 @@
/*
* Creates the LED flashing timers. xNumberOfLEDs specifies how many timers to
- * create, with each timer toggling a different LED. The first LED to be
+ * create, with each timer toggling a different LED. The first LED to be
* toggled is LED 0, with subsequent LEDs following on in numerical order. Each
* timer uses the exact same callback function, with the timer ID being used
* within the callback function to determine which timer has actually expired
diff --git a/Demo/Common/include/flop.h b/Demo/Common/include/flop.h
index 51f6d2492..c745b6cf3 100644
--- a/Demo/Common/include/flop.h
+++ b/Demo/Common/include/flop.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vStartMathTasks( UBaseType_t uxPriority );
BaseType_t xAreMathsTaskStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/integer.h b/Demo/Common/include/integer.h
index c4ad5ac25..8f0b9223f 100644
--- a/Demo/Common/include/integer.h
+++ b/Demo/Common/include/integer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vStartIntegerMathTasks( UBaseType_t uxPriority );
BaseType_t xAreIntegerMathsTaskStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/mevents.h b/Demo/Common/include/mevents.h
index c14cdd098..b53aa5bc1 100644
--- a/Demo/Common/include/mevents.h
+++ b/Demo/Common/include/mevents.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,5 +32,3 @@ void vStartMultiEventTasks( void );
BaseType_t xAreMultiEventTasksStillRunning( void );
#endif
-
-
diff --git a/Demo/Common/include/partest.h b/Demo/Common/include/partest.h
index a3b9cc5c0..e4b7ef1ec 100644
--- a/Demo/Common/include/partest.h
+++ b/Demo/Common/include/partest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -28,11 +28,11 @@
#ifndef PARTEST_H
#define PARTEST_H
-#define partstDEFAULT_PORT_ADDRESS ( ( uint16_t ) 0x378 )
+#define partstDEFAULT_PORT_ADDRESS ( ( uint16_t ) 0x378 )
void vParTestInitialise( void );
-void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue );
+void vParTestSetLED( UBaseType_t uxLED,
+ BaseType_t xValue );
void vParTestToggleLED( UBaseType_t uxLED );
#endif
-
diff --git a/Demo/Common/include/print.h b/Demo/Common/include/print.h
index 5e9bab00a..ce1d15423 100644
--- a/Demo/Common/include/print.h
+++ b/Demo/Common/include/print.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -30,8 +30,6 @@
void vPrintInitialise( void );
void vPrintDisplayMessage( const char * const * pcMessageToSend );
-const char *pcPrintGetNextMessage( TickType_t xPrintRate );
+const char * pcPrintGetNextMessage( TickType_t xPrintRate );
#endif
-
-
diff --git a/Demo/Common/include/recmutex.h b/Demo/Common/include/recmutex.h
index cfa87031e..08f2ce8b3 100644
--- a/Demo/Common/include/recmutex.h
+++ b/Demo/Common/include/recmutex.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,4 +32,3 @@ void vStartRecursiveMutexTasks( void );
BaseType_t xAreRecursiveMutexTasksStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/semtest.h b/Demo/Common/include/semtest.h
index a2084e037..101e3251f 100644
--- a/Demo/Common/include/semtest.h
+++ b/Demo/Common/include/semtest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -32,4 +32,3 @@ void vStartSemaphoreTasks( UBaseType_t uxPriority );
BaseType_t xAreSemaphoreTasksStillRunning( void );
#endif
-
diff --git a/Demo/Common/include/serial.h b/Demo/Common/include/serial.h
index 6ba10abce..187af834d 100644
--- a/Demo/Common/include/serial.h
+++ b/Demo/Common/include/serial.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -31,68 +31,79 @@
typedef void * xComPortHandle;
typedef enum
-{
- serCOM1,
- serCOM2,
- serCOM3,
- serCOM4,
- serCOM5,
- serCOM6,
- serCOM7,
- serCOM8
+{
+ serCOM1,
+ serCOM2,
+ serCOM3,
+ serCOM4,
+ serCOM5,
+ serCOM6,
+ serCOM7,
+ serCOM8
} eCOMPort;
-typedef enum
-{
- serNO_PARITY,
- serODD_PARITY,
- serEVEN_PARITY,
- serMARK_PARITY,
- serSPACE_PARITY
+typedef enum
+{
+ serNO_PARITY,
+ serODD_PARITY,
+ serEVEN_PARITY,
+ serMARK_PARITY,
+ serSPACE_PARITY
} eParity;
-typedef enum
-{
- serSTOP_1,
- serSTOP_2
+typedef enum
+{
+ serSTOP_1,
+ serSTOP_2
} eStopBits;
-typedef enum
-{
- serBITS_5,
- serBITS_6,
- serBITS_7,
- serBITS_8
+typedef enum
+{
+ serBITS_5,
+ serBITS_6,
+ serBITS_7,
+ serBITS_8
} eDataBits;
-typedef enum
-{
- ser50,
- ser75,
- ser110,
- ser134,
- ser150,
- ser200,
- ser300,
- ser600,
- ser1200,
- ser1800,
- ser2400,
- ser4800,
- ser9600,
- ser19200,
- ser38400,
- ser57600,
- ser115200
+typedef enum
+{
+ ser50,
+ ser75,
+ ser110,
+ ser134,
+ ser150,
+ ser200,
+ ser300,
+ ser600,
+ ser1200,
+ ser1800,
+ ser2400,
+ ser4800,
+ ser9600,
+ ser19200,
+ ser38400,
+ ser57600,
+ ser115200
} eBaud;
-xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength );
-xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );
-void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength );
-signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime );
-signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime );
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud,
+ unsigned portBASE_TYPE uxQueueLength );
+xComPortHandle xSerialPortInit( eCOMPort ePort,
+ eBaud eWantedBaud,
+ eParity eWantedParity,
+ eDataBits eWantedDataBits,
+ eStopBits eWantedStopBits,
+ unsigned portBASE_TYPE uxBufferLength );
+void vSerialPutString( xComPortHandle pxPort,
+ const signed char * const pcString,
+ unsigned short usStringLength );
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort,
+ signed char * pcRxedChar,
+ TickType_t xBlockTime );
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort,
+ signed char cOutChar,
+ TickType_t xBlockTime );
portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );
void vSerialClose( xComPortHandle xPort );
-#endif
-
+#endif /* ifndef SERIAL_COMMS_H */
diff --git a/Demo/Cygnal/FreeRTOSConfig.h b/Demo/Cygnal/FreeRTOSConfig.h
index 5ca61b5aa..d1a87de26 100644
--- a/Demo/Cygnal/FreeRTOSConfig.h
+++ b/Demo/Cygnal/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Cygnal/Makefile b/Demo/Cygnal/Makefile
index 4e6d72f8a..ba0a583bf 100644
--- a/Demo/Cygnal/Makefile
+++ b/Demo/Cygnal/Makefile
@@ -1,5 +1,5 @@
#/*
-# * FreeRTOS V202104.00
+# * FreeRTOS V202111.00
# * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
# *
# * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Cygnal/ParTest/ParTest.c b/Demo/Cygnal/ParTest/ParTest.c
index e5d596392..41eee7e41 100644
--- a/Demo/Cygnal/ParTest/ParTest.c
+++ b/Demo/Cygnal/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Cygnal/main.c b/Demo/Cygnal/main.c
index 4b99beaa8..0f320d2c4 100644
--- a/Demo/Cygnal/main.c
+++ b/Demo/Cygnal/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Cygnal/serial/serial.c b/Demo/Cygnal/serial/serial.c
index 241d3216e..dc9361650 100644
--- a/Demo/Cygnal/serial/serial.c
+++ b/Demo/Cygnal/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Flshlite/FRConfig.h b/Demo/Flshlite/FRConfig.h
index b9d71e697..d704ff502 100644
--- a/Demo/Flshlite/FRConfig.h
+++ b/Demo/Flshlite/FRConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Flshlite/FileIO/fileIO.c b/Demo/Flshlite/FileIO/fileIO.c
index c55386b5b..c9cea65d5 100644
--- a/Demo/Flshlite/FileIO/fileIO.c
+++ b/Demo/Flshlite/FileIO/fileIO.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Flshlite/FreeRTOSConfig.h b/Demo/Flshlite/FreeRTOSConfig.h
index 013a18ffc..44775d59a 100644
--- a/Demo/Flshlite/FreeRTOSConfig.h
+++ b/Demo/Flshlite/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Flshlite/ParTest/ParTest.c b/Demo/Flshlite/ParTest/ParTest.c
index d74267ac6..cd60db602 100644
--- a/Demo/Flshlite/ParTest/ParTest.c
+++ b/Demo/Flshlite/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Flshlite/main.c b/Demo/Flshlite/main.c
index c246236c5..6343243be 100644
--- a/Demo/Flshlite/main.c
+++ b/Demo/Flshlite/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Flshlite/serial/serial.c b/Demo/Flshlite/serial/serial.c
index 37715d3fd..b12a61a76 100644
--- a/Demo/Flshlite/serial/serial.c
+++ b/Demo/Flshlite/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h
index c56a39459..fd92679bf 100644
--- a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h
+++ b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/H8S/RTOSDemo/ParTest/ParTest.c b/Demo/H8S/RTOSDemo/ParTest/ParTest.c
index 40a36e176..224d48f2f 100644
--- a/Demo/H8S/RTOSDemo/ParTest/ParTest.c
+++ b/Demo/H8S/RTOSDemo/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/H8S/RTOSDemo/main.c b/Demo/H8S/RTOSDemo/main.c
index 1044484fc..2c3b7aabc 100644
--- a/Demo/H8S/RTOSDemo/main.c
+++ b/Demo/H8S/RTOSDemo/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/H8S/RTOSDemo/serial/serial.c b/Demo/H8S/RTOSDemo/serial/serial.c
index 64c29f5a6..a208db6ca 100644
--- a/Demo/H8S/RTOSDemo/serial/serial.c
+++ b/Demo/H8S/RTOSDemo/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h
index 7f16b2df8..22990785a 100644
--- a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h
+++ b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c
index 5a46dc822..2de50d573 100644
--- a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c
+++ b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_banked/main.c b/Demo/HCS12_CodeWarrior_banked/main.c
index 72a83fd83..d3dd558f5 100644
--- a/Demo/HCS12_CodeWarrior_banked/main.c
+++ b/Demo/HCS12_CodeWarrior_banked/main.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_banked/serial/serial.c b/Demo/HCS12_CodeWarrior_banked/serial/serial.c
index 0a089c765..ba8642cb3 100644
--- a/Demo/HCS12_CodeWarrior_banked/serial/serial.c
+++ b/Demo/HCS12_CodeWarrior_banked/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h
index 7428b1f35..e00ed089e 100644
--- a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h
+++ b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c
index 5a46dc822..2de50d573 100644
--- a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c
+++ b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_small/main.c b/Demo/HCS12_CodeWarrior_small/main.c
index d7091a5e6..1d5fcfb5c 100644
--- a/Demo/HCS12_CodeWarrior_small/main.c
+++ b/Demo/HCS12_CodeWarrior_small/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_CodeWarrior_small/serial/serial.c b/Demo/HCS12_CodeWarrior_small/serial/serial.c
index ea7380434..853561e00 100644
--- a/Demo/HCS12_CodeWarrior_small/serial/serial.c
+++ b/Demo/HCS12_CodeWarrior_small/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h
index b7999fc50..52555397a 100644
--- a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h
+++ b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_GCC_banked/ParTest.c b/Demo/HCS12_GCC_banked/ParTest.c
index 8326eb79e..3f7881e59 100644
--- a/Demo/HCS12_GCC_banked/ParTest.c
+++ b/Demo/HCS12_GCC_banked/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_GCC_banked/main.c b/Demo/HCS12_GCC_banked/main.c
index 70e5e1b9b..27b0b6101 100644
--- a/Demo/HCS12_GCC_banked/main.c
+++ b/Demo/HCS12_GCC_banked/main.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/HCS12_GCC_banked/startup.c b/Demo/HCS12_GCC_banked/startup.c
index db35475dc..d82dc6d41 100644
--- a/Demo/HCS12_GCC_banked/startup.c
+++ b/Demo/HCS12_GCC_banked/startup.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Blinky_Demo/main_blinky.c b/Demo/IA32_flat_GCC_Galileo_Gen_2/Blinky_Demo/main_blinky.c
index 3aaee7456..21f8d732d 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Blinky_Demo/main_blinky.c
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Blinky_Demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/FreeRTOSConfig.h b/Demo/IA32_flat_GCC_Galileo_Gen_2/FreeRTOSConfig.h
index ce2ee1171..197fc4536 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/FreeRTOSConfig.h
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.c b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.c
index 536092a20..feeea49d4 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.c
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.h b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.h
index 9a9c40b16..b3e86d6e2 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.h
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/IntQueueTimer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/RegTest.S b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/RegTest.S
index 96da041a0..f6c2498e5 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/RegTest.S
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/RegTest.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/main_full.c b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/main_full.c
index dfd3618ad..423df3750 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/main_full.c
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Full_Demo/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/freestanding_functions.c b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/freestanding_functions.c
index f9a7ab9a4..5ef70353e 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/freestanding_functions.c
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/freestanding_functions.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/math.h b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/math.h
index 3905f485b..b57ecb30a 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/math.h
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/math.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/startup.S b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/startup.S
index fb984057d..30e5cb61f 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/startup.S
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/startup.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/stdint.h b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/stdint.h
index cd8274e98..6739148fc 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/stdint.h
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/Support_Files/stdint.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/IA32_flat_GCC_Galileo_Gen_2/main.c b/Demo/IA32_flat_GCC_Galileo_Gen_2/main.c
index 5692e3b9f..7758900be 100644
--- a/Demo/IA32_flat_GCC_Galileo_Gen_2/main.c
+++ b/Demo/IA32_flat_GCC_Galileo_Gen_2/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h b/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
index 72d1639fa..99f5e678f 100644
--- a/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
+++ b/Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB91460_Softune/SRC/crflash_modified.c b/Demo/MB91460_Softune/SRC/crflash_modified.c
index e4cf2df55..56893f598 100644
--- a/Demo/MB91460_Softune/SRC/crflash_modified.c
+++ b/Demo/MB91460_Softune/SRC/crflash_modified.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB91460_Softune/SRC/main.c b/Demo/MB91460_Softune/SRC/main.c
index ba346ed48..29c497d9b 100644
--- a/Demo/MB91460_Softune/SRC/main.c
+++ b/Demo/MB91460_Softune/SRC/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB91460_Softune/SRC/partest/partest.c b/Demo/MB91460_Softune/SRC/partest/partest.c
index e93deef4f..a818f100d 100644
--- a/Demo/MB91460_Softune/SRC/partest/partest.c
+++ b/Demo/MB91460_Softune/SRC/partest/partest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB91460_Softune/SRC/serial/serial.c b/Demo/MB91460_Softune/SRC/serial/serial.c
index bc2319106..cc0489de8 100644
--- a/Demo/MB91460_Softune/SRC/serial/serial.c
+++ b/Demo/MB91460_Softune/SRC/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/FreeRTOSConfig.h b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/FreeRTOSConfig.h
index 8f7632580..16e8e8206 100644
--- a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/FreeRTOSConfig.h
+++ b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c
index e4cf2df55..56893f598 100644
--- a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c
+++ b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/crflash_sk16fx100mpc.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c
index 50bc2669b..eb406439d 100644
--- a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c
+++ b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/partest/partest.c b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/partest/partest.c
index b7dc97408..1cb22f2bf 100644
--- a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/partest/partest.c
+++ b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/partest/partest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c
index 91c14513c..a73864e04 100644
--- a/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c
+++ b/Demo/MB96340_Softune/FreeRTOS_96348hs_SK16FX100PMC/Src/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96350_Softune_Dice_Kit/DiceTask.c b/Demo/MB96350_Softune_Dice_Kit/DiceTask.c
index 55d9a9391..4d33f2857 100644
--- a/Demo/MB96350_Softune_Dice_Kit/DiceTask.c
+++ b/Demo/MB96350_Softune_Dice_Kit/DiceTask.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96350_Softune_Dice_Kit/DiceTask.h b/Demo/MB96350_Softune_Dice_Kit/DiceTask.h
index 4dc3993a4..411b6443f 100644
--- a/Demo/MB96350_Softune_Dice_Kit/DiceTask.h
+++ b/Demo/MB96350_Softune_Dice_Kit/DiceTask.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96350_Softune_Dice_Kit/FreeRTOSConfig.h b/Demo/MB96350_Softune_Dice_Kit/FreeRTOSConfig.h
index b8b81d93a..9f22268cd 100644
--- a/Demo/MB96350_Softune_Dice_Kit/FreeRTOSConfig.h
+++ b/Demo/MB96350_Softune_Dice_Kit/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96350_Softune_Dice_Kit/ParTest/ParTest.c b/Demo/MB96350_Softune_Dice_Kit/ParTest/ParTest.c
index 851bc1274..0a40f66f4 100644
--- a/Demo/MB96350_Softune_Dice_Kit/ParTest/ParTest.c
+++ b/Demo/MB96350_Softune_Dice_Kit/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96350_Softune_Dice_Kit/SegmentToggleTasks.c b/Demo/MB96350_Softune_Dice_Kit/SegmentToggleTasks.c
index f224254ba..facaaf0e0 100644
--- a/Demo/MB96350_Softune_Dice_Kit/SegmentToggleTasks.c
+++ b/Demo/MB96350_Softune_Dice_Kit/SegmentToggleTasks.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MB96350_Softune_Dice_Kit/main.c b/Demo/MB96350_Softune_Dice_Kit/main.c
index 455496a7c..de5ca642b 100644
--- a/Demo/MB96350_Softune_Dice_Kit/main.c
+++ b/Demo/MB96350_Softune_Dice_Kit/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MCF5235_GCC/Changelog.txt b/Demo/MCF5235_GCC/Changelog.txt
deleted file mode 100644
index 0290fbae0..000000000
--- a/Demo/MCF5235_GCC/Changelog.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-
-2006-08-31 (REL_1_2) Christian Walter :
- Notes: Recreated from lwIP port.
-
diff --git a/Demo/MCF5235_GCC/FreeRTOSConfig.h b/Demo/MCF5235_GCC/FreeRTOSConfig.h
deleted file mode 100644
index c9f2a1615..000000000
--- a/Demo/MCF5235_GCC/FreeRTOSConfig.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- FreeRTOS V202104.00
- MCF5235 Port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION 1
-#define configUSE_IDLE_HOOK 0
-#define configUSE_TICK_HOOK 0
-#define configCPU_CLOCK_HZ ( ( unsigned long ) 25000000 )
-#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
-#define configMAX_PRIORITIES ( 7 )
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 )
-#define configMAX_TASK_NAME_LEN ( 16 )
-#define configUSE_TRACE_FACILITY 1
-#define configUSE_16_BIT_TICKS 0
-#define configIDLE_SHOULD_YIELD 1
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 0
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_vTaskDelayUntil 1
-#define INCLUDE_vTaskDelay 1
-#define INCLUDE_xTaskGetCurrentTaskHandle 1
-
-#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT b/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT
deleted file mode 100644
index 7e58b1174..000000000
--- a/Demo/MCF5235_GCC/LICENSE_FREESCALE.TXT
+++ /dev/null
@@ -1,35 +0,0 @@
-MCF523x example code
-
-IMPORTANT. Read the following Freescale Semiconductor Software License Agreement (“Agreementâ€) completely. By selecting the "I Accept" button at the end of this page, you indicate that you accept the terms of this Agreement. You may then download the file.
-
-FREESCALE SEMICONDUCTOR SOFTWARE LICENSE AGREEMENT
-
-This is a legal agreement between you (either as an individual or as an authorized representative of your employer) and Freescale Semiconductor, Inc. ("Freescale"). It concerns your rights to use this file and any accompanying written materials (the "Software"). In consideration for Freescale allowing you to access the Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download the Software. If you change your mind later, stop using the Software and delete all copies of the Software in your possession or control. Any copies of the Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement.
-
-LICENSE GRANT. Freescale grants to you, free of charge, the non-exclusive, non-transferable right (1) to use the Software, (2) to reproduce the Software, (3) to prepare derivative works of the Software, (4) to distribute the Software and derivative works thereof in source (human-readable) form and object (machine–readable) form, and (5) to sublicense to others the right to use the distributed Software. If you violate any of the terms or restrictions of this Agreement, Freescale may immediately terminate this Agreement, and require that you stop using and delete all copies of the Software in your possession or control.
-
-COPYRIGHT. The Software is licensed to you, not sold. Freescale owns the Software, and United States copyright laws and international treaty provisions protect the Software. Therefore, you must treat the Software like any other copyrighted material (e.g. a book or musical recording). You may not use or copy the Software for any other purpose than what is described in this Agreement. Except as expressly provided herein, Freescale does not grant to you any express or implied rights under any Freescale or third-party patents, copyrights, trademarks, or trade secrets. Additionally, you must reproduce and apply any copyright or other proprietary rights notices included on or embedded in the Software to any copies or derivative works made thereof, in whole or in part, if any.
-
-SUPPORT. Freescale is NOT obligated to provide any support, upgrades or new releases of the Software. If you wish, you may contact Freescale and report problems and provide suggestions regarding the Software. Freescale has no obligation whatsoever to respond in any way to such a problem report or suggestion. Freescale may make changes to the Software at any time, without any obligation to notify or provide updated versions of the Software to you.
-
-NO WARRANTY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, FREESCALE EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE. THE SOFTWARE IS PROVIDED “AS ISâ€, WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. YOU ASSUME THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING THE SOFTWARE (IF ANY). NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A WARRANTY OR REPRESENTATION BY FREESCALE THAT THE SOFTWARE OR ANY DERIVATIVE WORK DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.
-
-INDEMNITY. You agree to fully defend and indemnify Freescale from any and all claims, liabilities, and costs (including reasonable attorney’s fees) related to (1) your use (including your sublicensee’s use, if permitted) of the Software or (2) your violation of the terms and conditions of this Agreement.
-
-LIMITATION OF LIABILITY. IN NO EVENT WILL FREESCALE BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.
-
-COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS. This software may be subject to the U.S. Export Regulations and/or the regulatory authority of the country in which the download takes place. By downloading this software you understand and agree to comply with all applicable export control regulations when further transferring or exporting the software either as downloaded or as integrated into other software or commodities.
-
-GOVERNMENT USE. Use of the Software and any corresponding documentation, if any, is provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Manufacturer is Freescale Semiconductor, Inc., 6501 William Cannon Drive West, Austin, TX, 78735.
-
-HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault tolerant and is not designed, manufactured or intended by Freescale for incorporation into products intended for use or resale in on-line control equipment in hazardous, dangerous to life or potentially life-threatening environments requiring fail-safe performance, such as in the operation of nuclear facilities, aircraft navigation or communication systems, air traffic control, direct life support machines or weapons systems, in which the failure of products could lead directly to death, personal injury or severe physical or environmental damage (“High Risk Activitiesâ€). You specifically represent and warrant that you will not use the Software or any derivative work of the Software for High Risk Activities.
-
-CHOICE OF LAW; VENUE; LIMITATIONS. You agree that the statutes and laws of the United States and the State of Texas, USA, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the state or federal courts in Texas, USA. You agree that regardless of any statute or law to the contrary, any claim or cause of action arising out of or related to this Agreement or the Software must be filed within one (1) year after such claim or cause of action arose or be forever barred.
-
-PRODUCT LABELING. You are not authorized to use any Freescale trademarks, brand names, or logos.
-
-ENTIRE AGREEMENT. This Agreement constitutes the entire agreement between you and Freescale regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, executed by you and Freescale.
-
-SEVERABILITY. If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or Freescale of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision.
-
-NO WAIVER. The waiver by Freescale of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.
diff --git a/Demo/MCF5235_GCC/Makefile b/Demo/MCF5235_GCC/Makefile
deleted file mode 100644
index 7a2da52f6..000000000
--- a/Demo/MCF5235_GCC/Makefile
+++ /dev/null
@@ -1,87 +0,0 @@
-#
-# FreeRTOS 4.1.0 - MCF5235 Coldfire Port
-#
-# Copyright (c) 2006 Christian Walter, Vienna 2006.
-#
-# $Id: Makefile,v 1.1 2006/08/31 22:45:48 wolti Exp $
-#
-# ---------------------------------------------------------------------------
-BASE = /opt/gcc-m68k/bin
-CC = $(BASE)/m68k-elf-gcc
-CXX = $(BASE)/m68k-elf-g++
-OBJCOPY = $(BASE)/m68k-elf-objcopy
-SIZE = $(BASE)/m68k-elf-size
-INSIGHT = $(BASE)/m68k-bdm-elf-insight
-BDMFLASH = $(BASE)/bdmflash
-
-#CFLAGS = -MD -O2 -m528x -Wall
-CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall \
- -D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \
- -D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \
- -I. -Iinclude -Iinclude/arch -Ifec \
- -I../../Source/include -I../Common/include
-
-ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \
- -Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000
-LDSCRIPT = m5235-ram.ld
-LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT)
-
-TGT = demo
-OTHER_CSRC =
-OTHER_ASRC = $(addprefix system/, crt0.S vector.S)
-CSRC = demo.c \
- $(addprefix system/, init.c newlib.c serial.c) \
- $(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \
- $(addprefix ../../Source/, tasks.c queue.c list.c) \
- $(addprefix ../../Source/portable/MemMang/, heap_3.c) \
- $(addprefix ../../Source/portable/GCC/MCF5235/, port.c)
-
-ASRC = $(addprefix system/, mcf5xxx.S )
-OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o)
-NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o)
-DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d)
-BIN = $(TGT).elf
-
-.PHONY: clean all
-
-all: $(BIN)
-
-flash-programm: $(TGT).elf
- $(OBJCOPY) -O binary $(TGT).elf $(TGT).bin
- @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
- echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \
- $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0
-
-flash-verify:
- @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
- echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \
- $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE
-
-flash-erase:
- $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase
-
-debug:
- $(INSIGHT) --command=m5235.gdb --se=$(TGT).elf
-
-$(BIN): $(OBJS) $(NOLINK_OBJS)
- $(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@
-
-clean:
- rm -f $(DEPS)
- rm -f $(OBJS) $(NOLINK_OBJS)
- rm -f $(BIN) $(TGT).map
-
-# ---------------------------------------------------------------------------
-# rules for code generation
-# ---------------------------------------------------------------------------
-%.o: %.c
- $(CC) $(CFLAGS) -o $@ -c $<
-
-%.o: %.S
- $(CC) $(ASFLAGS) -o $@ -c $<
-
-# ---------------------------------------------------------------------------
-# # compiler generated dependencies
-# ---------------------------------------------------------------------------
--include $(DEPS)
-
diff --git a/Demo/MCF5235_GCC/demo.c b/Demo/MCF5235_GCC/demo.c
deleted file mode 100644
index b98e33e66..000000000
--- a/Demo/MCF5235_GCC/demo.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- FreeRTOS V202104.00
- MCF5235 Port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-/* ------------------------ System includes ------------------------------- */
-#include
-#include
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* ------------------------ Demo application includes --------------------- */
-#include "partest.h"
-#include "flash.h"
-#include "integer.h"
-#include "PollQ.h"
-#include "comtest2.h"
-#include "semtest.h"
-#include "flop.h"
-#include "dynamic.h"
-#include "BlockQ.h"
-#include "serial.h"
-
-/* ------------------------ Defines --------------------------------------- */
-/* Constants for the ComTest tasks. */
-#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 38400 )
-#define mainCOM_TEST_LED ( -1 )
-
-/* Priorities for the demo application tasks. */
-#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
-#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
-
-/* Interval in which tasks are checked. */
-#define mainCHECK_PERIOD ( ( TickType_t ) 2000 / portTICK_PERIOD_MS )
-
-/* Constants used by the vMemCheckTask() task. */
-#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 )
-#define mainNO_TASK ( 0 )
-
-/* The size of the memory blocks allocated by the vMemCheckTask() task. */
-#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
-#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
-#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
-
-/* ------------------------ Static variables ------------------------------ */
-xComPortHandle xSTDComPort = NULL;
-
-/* ------------------------ Static functions ------------------------------ */
-static portTASK_FUNCTION( vErrorChecks, pvParameters );
-static long prvCheckOtherTasksAreStillRunning( unsigned long
- ulMemCheckTaskCount );
-static portTASK_FUNCTION( vMemCheckTask, pvParameters );
-
-/* ------------------------ Implementation -------------------------------- */
-int
-main( int argc, char *argv[] )
-{
- asm volatile ( "move.w #0x2000, %sr\n\t" );
-
- xSTDComPort = xSerialPortInitMinimal( 38400, 8 );
-
- /* Start the demo/test application tasks. */
- vStartIntegerMathTasks( tskIDLE_PRIORITY );
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
- vStartMathTasks( tskIDLE_PRIORITY );
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
- vStartDynamicPriorityTasks( );
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
-
- /* Start the check task - which is defined in this file. */
- xTaskCreate( vErrorChecks, "Check", 512, NULL,
- mainCHECK_TASK_PRIORITY, NULL );
-
- /* Now all the tasks have been started - start the scheduler. */
- vTaskStartScheduler( );
-
- /* Should never get here! */
- return 0;
-}
-
-
-
-static
-portTASK_FUNCTION( vErrorChecks, pvParameters )
-{
- unsigned long ulMemCheckTaskRunningCount;
- TaskHandle_t xCreatedTask;
-
- /* The parameters are not used in this function. */
- ( void )pvParameters;
-
- xSerialPortInitMinimal( mainCOM_TEST_BAUD_RATE, 8 );
-
- for( ;; )
- {
- ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
- xCreatedTask = mainNO_TASK;
-
- if( xTaskCreate
- ( vMemCheckTask, "MEM_CHECK",
- configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount,
- tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
- {
- xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
- }
-
- /* Delay until it is time to execute again. */
- vTaskDelay( mainCHECK_PERIOD );
-
- /* Delete the dynamically created task. */
- if( xCreatedTask != mainNO_TASK )
- {
- vTaskDelete( xCreatedTask );
- }
-
- if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) !=
- pdPASS )
- {
- xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
- }
- else
- {
- xSerialPutChar( xSTDComPort, '.', portMAX_DELAY );
- }
- }
-}
-
-static long
-prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount )
-{
- long lReturn = ( long ) pdPASS;
-
- /* Check all the demo tasks (other than the flash tasks) to ensure
- * that they are all still running, and that none of them have detected
- * an error.
- */
-
- if( xAreIntegerMathsTaskStillRunning( ) != pdTRUE )
- {
- lReturn = ( long ) pdFAIL;
- }
-
- if( xArePollingQueuesStillRunning( ) != pdTRUE )
- {
- lReturn = ( long ) pdFAIL;
- }
-
- if( xAreMathsTaskStillRunning( ) != pdTRUE )
- {
- lReturn = ( long ) pdFAIL;
- }
-
- if( xAreSemaphoreTasksStillRunning( ) != pdTRUE )
- {
- lReturn = ( long ) pdFAIL;
- }
-
- if( xAreDynamicPriorityTasksStillRunning( ) != pdTRUE )
- {
- lReturn = ( long ) pdFAIL;
- }
-
- if( xAreBlockingQueuesStillRunning( ) != pdTRUE )
- {
- lReturn = ( long ) pdFAIL;
- }
- if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
- {
- // The vMemCheckTask did not increment the counter - it must
- // have failed.
- lReturn = ( long ) pdFAIL;
- }
- return lReturn;
-}
-
-static void
-vMemCheckTask( void *pvParameters )
-{
- unsigned long *pulMemCheckTaskRunningCounter;
- void *pvMem1, *pvMem2, *pvMem3;
- static long lErrorOccurred = pdFALSE;
-
- /* This task is dynamically created then deleted during each cycle of the
- vErrorChecks task to check the operation of the memory allocator. Each time
- the task is created memory is allocated for the stack and TCB. Each time
- the task is deleted this memory is returned to the heap. This task itself
- exercises the allocator by allocating and freeing blocks.
-
- The task executes at the idle priority so does not require a delay.
-
- pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
- vErrorChecks() task that this task is still executing without error. */
-
- pulMemCheckTaskRunningCounter = ( unsigned long * )pvParameters;
-
- for( ;; )
- {
- if( lErrorOccurred == pdFALSE )
- {
- /* We have never seen an error so increment the counter. */
- ( *pulMemCheckTaskRunningCounter )++;
- }
-
- /* Allocate some memory - just to give the allocator some extra
- exercise. This has to be in a critical section to ensure the
- task does not get deleted while it has memory allocated. */
- vTaskSuspendAll( );
- {
- pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
- if( pvMem1 == NULL )
- {
- lErrorOccurred = pdTRUE;
- }
- else
- {
- memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
- vPortFree( pvMem1 );
- }
- }
- xTaskResumeAll( );
-
- /* Again - with a different size block. */
- vTaskSuspendAll( );
- {
- pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
- if( pvMem2 == NULL )
- {
- lErrorOccurred = pdTRUE;
- }
- else
- {
- memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
- vPortFree( pvMem2 );
- }
- }
- xTaskResumeAll( );
-
- /* Again - with a different size block. */
- vTaskSuspendAll( );
- {
- pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
- if( pvMem3 == NULL )
- {
- lErrorOccurred = pdTRUE;
- }
- else
- {
- memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
- vPortFree( pvMem3 );
- }
- }
- xTaskResumeAll( );
- }
-}
-
-void
-vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
-{
-}
-
-void
-vParTestToggleLED( unsigned portBASE_TYPE uxLED )
-{
-}
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x.h b/Demo/MCF5235_GCC/include/arch/mcf523x.h
deleted file mode 100644
index 4b7761fd5..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_H__
-#define __MCF523X_H__
-
-/*********************************************************************/
-
-#include "mcf523x/mcf523x_fec.h"
-#include "mcf523x/mcf523x_rng.h"
-#include "mcf523x/mcf523x_fmpll.h"
-#include "mcf523x/mcf523x_cs.h"
-#include "mcf523x/mcf523x_intc0.h"
-#include "mcf523x/mcf523x_intc1.h"
-#include "mcf523x/mcf523x_sdramc.h"
-#include "mcf523x/mcf523x_sram.h"
-#include "mcf523x/mcf523x_uart.h"
-#include "mcf523x/mcf523x_timer.h"
-#include "mcf523x/mcf523x_qspi.h"
-#include "mcf523x/mcf523x_eport.h"
-#include "mcf523x/mcf523x_i2c.h"
-#include "mcf523x/mcf523x_scm.h"
-#include "mcf523x/mcf523x_pit.h"
-#include "mcf523x/mcf523x_can.h"
-#include "mcf523x/mcf523x_wtm.h"
-#include "mcf523x/mcf523x_gpio.h"
-#include "mcf523x/mcf523x_mdha.h"
-#include "mcf523x/mcf523x_ccm.h"
-#include "mcf523x/mcf523x_rcm.h"
-#include "mcf523x/mcf523x_etpu.h"
-
-
-/********************************************************************/
-
-#endif /* __MCF523X_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h
deleted file mode 100644
index 7aaa34496..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_can.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_can.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_CAN_H__
-#define __MCF523X_CAN_H__
-
-/*********************************************************************
-*
-* FlexCAN Module (CAN)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
-#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
-#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
-#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
-#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
-#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
-#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
-#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
-#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
-#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
-#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
-#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
-#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
-#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
-#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
-#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
-#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
-#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
-#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
-#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
-#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
-#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
-#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
-#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
-#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
-#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
-#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
-#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
-#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
-#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
-
-#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
-#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
-#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
-#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
-#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
-#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
-#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
-#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
-#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
-#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
-#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
-#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
-#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
-#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
-
-
-#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
-#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
-#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
-#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
-
-
-/* Bit definitions and macros for MCF_CAN_CANMCR */
-#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
-#define MCF_CAN_CANMCR_SUPV (0x00800000)
-#define MCF_CAN_CANMCR_FRZACK (0x01000000)
-#define MCF_CAN_CANMCR_SOFTRST (0x02000000)
-#define MCF_CAN_CANMCR_HALT (0x10000000)
-#define MCF_CAN_CANMCR_FRZ (0x40000000)
-#define MCF_CAN_CANMCR_MDIS (0x80000000)
-
-/* Bit definitions and macros for MCF_CAN_CANCTRL */
-#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
-#define MCF_CAN_CANCTRL_LOM (0x00000008)
-#define MCF_CAN_CANCTRL_LBUF (0x00000010)
-#define MCF_CAN_CANCTRL_TSYNC (0x00000020)
-#define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
-#define MCF_CAN_CANCTRL_SAMP (0x00000080)
-#define MCF_CAN_CANCTRL_LPB (0x00001000)
-#define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
-#define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
-#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
-#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
-#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
-#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
-#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_CAN_TIMER */
-#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_RXGMASK */
-#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_RX14MASK */
-#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_RX15MASK */
-#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_CAN_ERRCNT */
-#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
-#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
-
-/* Bit definitions and macros for MCF_CAN_ERRSTAT */
-#define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
-#define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
-#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
-#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
-#define MCF_CAN_ERRSTAT_TXRX (0x00000040)
-#define MCF_CAN_ERRSTAT_IDLE (0x00000080)
-#define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
-#define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
-#define MCF_CAN_ERRSTAT_STFERR (0x00000400)
-#define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
-#define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
-#define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
-#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
-#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
-#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
-#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
-
-/* Bit definitions and macros for MCF_CAN_IMASK */
-#define MCF_CAN_IMASK_BUF0M (0x0001)
-#define MCF_CAN_IMASK_BUF1M (0x0002)
-#define MCF_CAN_IMASK_BUF2M (0x0004)
-#define MCF_CAN_IMASK_BUF3M (0x0008)
-#define MCF_CAN_IMASK_BUF4M (0x0010)
-#define MCF_CAN_IMASK_BUF5M (0x0020)
-#define MCF_CAN_IMASK_BUF6M (0x0040)
-#define MCF_CAN_IMASK_BUF7M (0x0080)
-#define MCF_CAN_IMASK_BUF8M (0x0100)
-#define MCF_CAN_IMASK_BUF9M (0x0200)
-#define MCF_CAN_IMASK_BUF10M (0x0400)
-#define MCF_CAN_IMASK_BUF11M (0x0800)
-#define MCF_CAN_IMASK_BUF12M (0x1000)
-#define MCF_CAN_IMASK_BUF13M (0x2000)
-#define MCF_CAN_IMASK_BUF14M (0x4000)
-#define MCF_CAN_IMASK_BUF15M (0x8000)
-
-/* Bit definitions and macros for MCF_CAN_IFLAG */
-#define MCF_CAN_IFLAG_BUF0I (0x0001)
-#define MCF_CAN_IFLAG_BUF1I (0x0002)
-#define MCF_CAN_IFLAG_BUF2I (0x0004)
-#define MCF_CAN_IFLAG_BUF3I (0x0008)
-#define MCF_CAN_IFLAG_BUF4I (0x0010)
-#define MCF_CAN_IFLAG_BUF5I (0x0020)
-#define MCF_CAN_IFLAG_BUF6I (0x0040)
-#define MCF_CAN_IFLAG_BUF7I (0x0080)
-#define MCF_CAN_IFLAG_BUF8I (0x0100)
-#define MCF_CAN_IFLAG_BUF9I (0x0200)
-#define MCF_CAN_IFLAG_BUF10I (0x0400)
-#define MCF_CAN_IFLAG_BUF11I (0x0800)
-#define MCF_CAN_IFLAG_BUF12I (0x1000)
-#define MCF_CAN_IFLAG_BUF13I (0x2000)
-#define MCF_CAN_IFLAG_BUF14I (0x4000)
-#define MCF_CAN_IFLAG_BUF15I (0x8000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_CAN_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h
deleted file mode 100644
index da9bdb79e..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_ccm.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_ccm.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_CCM_H__
-#define __MCF523X_CCM_H__
-
-/*********************************************************************
-*
-* Chip Configuration Module (CCM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
-#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
-#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
-#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
-
-/* Bit definitions and macros for MCF_CCM_CCR */
-#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0)
-#define MCF_CCM_CCR_BME (0x0008)
-#define MCF_CCM_CCR_SZEN (0x0040)
-#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8)
-
-/* Bit definitions and macros for MCF_CCM_LPCR */
-#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3)
-#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6)
-#define MCF_CCM_LPCR_LPMD_STOP (0xC0)
-#define MCF_CCM_LPCR_LPMD_WAIT (0x80)
-#define MCF_CCM_LPCR_LPMD_DOZE (0x40)
-#define MCF_CCM_LPCR_LPMD_RUN (0x00)
-
-/* Bit definitions and macros for MCF_CCM_CIR */
-#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
-#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
-
-/* Bit definitions and macros for MCF_CCM_RCON */
-#define MCF_CCM_RCON_MODE (0x0001)
-#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
-#define MCF_CCM_RCON_RLOAD (0x0020)
-#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
-
-/********************************************************************/
-
-#endif /* __MCF523X_CCM_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h
deleted file mode 100644
index 27251c80a..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_cs.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_cs.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_CS_H__
-#define __MCF523X_CS_H__
-
-/*********************************************************************
-*
-* Chip Selects (CS)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
-#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
-#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
-#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
-#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
-#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
-#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
-#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
-#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
-#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
-#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
-#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
-#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
-#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
-#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
-#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
-#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
-#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
-#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
-#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
-#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
-#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
-#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
-#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
-#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
-#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
-#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
-
-/* Bit definitions and macros for MCF_CS_CSAR */
-#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16))
-
-/* Bit definitions and macros for MCF_CS_CSMR */
-#define MCF_CS_CSMR_V (0x00000001)
-#define MCF_CS_CSMR_UD (0x00000002)
-#define MCF_CS_CSMR_UC (0x00000004)
-#define MCF_CS_CSMR_SD (0x00000008)
-#define MCF_CS_CSMR_SC (0x00000010)
-#define MCF_CS_CSMR_CI (0x00000020)
-#define MCF_CS_CSMR_AM (0x00000040)
-#define MCF_CS_CSMR_WP (0x00000100)
-#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
-#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)
-#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)
-#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)
-#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)
-#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)
-#define MCF_CS_CSMR_BAM_256M (0x0FFF0000)
-#define MCF_CS_CSMR_BAM_128M (0x07FF0000)
-#define MCF_CS_CSMR_BAM_64M (0x03FF0000)
-#define MCF_CS_CSMR_BAM_32M (0x01FF0000)
-#define MCF_CS_CSMR_BAM_16M (0x00FF0000)
-#define MCF_CS_CSMR_BAM_8M (0x007F0000)
-#define MCF_CS_CSMR_BAM_4M (0x003F0000)
-#define MCF_CS_CSMR_BAM_2M (0x001F0000)
-#define MCF_CS_CSMR_BAM_1M (0x000F0000)
-#define MCF_CS_CSMR_BAM_1024K (0x000F0000)
-#define MCF_CS_CSMR_BAM_512K (0x00070000)
-#define MCF_CS_CSMR_BAM_256K (0x00030000)
-#define MCF_CS_CSMR_BAM_128K (0x00010000)
-#define MCF_CS_CSMR_BAM_64K (0x00000000)
-
-/* Bit definitions and macros for MCF_CS_CSCR */
-#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0)
-#define MCF_CS_CSCR_BSTW (0x0008)
-#define MCF_CS_CSCR_BSTR (0x0010)
-#define MCF_CS_CSCR_BEM (0x0020)
-#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6)
-#define MCF_CS_CSCR_AA (0x0100)
-#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10)
-#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14)
-#define MCF_CS_CSCR_PS_8 (0x0040)
-#define MCF_CS_CSCR_PS_16 (0x0080)
-#define MCF_CS_CSCR_PS_32 (0x0000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_CS_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h
deleted file mode 100644
index 5629ebfa4..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_eport.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_eport.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_EPORT_H__
-#define __MCF523X_EPORT_H__
-
-/*********************************************************************
-*
-* Edge Port Module (EPORT)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
-#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
-#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
-#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
-#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
-#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
-
-/* Bit definitions and macros for MCF_EPORT_EPPAR */
-#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
-#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
-#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
-#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
-#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
-#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
-#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
-#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0)
-#define MCF_EPORT_EPPAR_EPPAx_RISING (1)
-#define MCF_EPORT_EPPAR_EPPAx_FALLING (2)
-#define MCF_EPORT_EPPAR_EPPAx_BOTH (3)
-
-/* Bit definitions and macros for MCF_EPORT_EPDDR */
-#define MCF_EPORT_EPDDR_EPDD1 (0x02)
-#define MCF_EPORT_EPDDR_EPDD2 (0x04)
-#define MCF_EPORT_EPDDR_EPDD3 (0x08)
-#define MCF_EPORT_EPDDR_EPDD4 (0x10)
-#define MCF_EPORT_EPDDR_EPDD5 (0x20)
-#define MCF_EPORT_EPDDR_EPDD6 (0x40)
-#define MCF_EPORT_EPDDR_EPDD7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPIER */
-#define MCF_EPORT_EPIER_EPIE1 (0x02)
-#define MCF_EPORT_EPIER_EPIE2 (0x04)
-#define MCF_EPORT_EPIER_EPIE3 (0x08)
-#define MCF_EPORT_EPIER_EPIE4 (0x10)
-#define MCF_EPORT_EPIER_EPIE5 (0x20)
-#define MCF_EPORT_EPIER_EPIE6 (0x40)
-#define MCF_EPORT_EPIER_EPIE7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPDR */
-#define MCF_EPORT_EPDR_EPD1 (0x02)
-#define MCF_EPORT_EPDR_EPD2 (0x04)
-#define MCF_EPORT_EPDR_EPD3 (0x08)
-#define MCF_EPORT_EPDR_EPD4 (0x10)
-#define MCF_EPORT_EPDR_EPD5 (0x20)
-#define MCF_EPORT_EPDR_EPD6 (0x40)
-#define MCF_EPORT_EPDR_EPD7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPPDR */
-#define MCF_EPORT_EPPDR_EPPD1 (0x02)
-#define MCF_EPORT_EPPDR_EPPD2 (0x04)
-#define MCF_EPORT_EPPDR_EPPD3 (0x08)
-#define MCF_EPORT_EPPDR_EPPD4 (0x10)
-#define MCF_EPORT_EPPDR_EPPD5 (0x20)
-#define MCF_EPORT_EPPDR_EPPD6 (0x40)
-#define MCF_EPORT_EPPDR_EPPD7 (0x80)
-
-/* Bit definitions and macros for MCF_EPORT_EPFR */
-#define MCF_EPORT_EPFR_EPF1 (0x02)
-#define MCF_EPORT_EPFR_EPF2 (0x04)
-#define MCF_EPORT_EPFR_EPF3 (0x08)
-#define MCF_EPORT_EPFR_EPF4 (0x10)
-#define MCF_EPORT_EPFR_EPF5 (0x20)
-#define MCF_EPORT_EPFR_EPF6 (0x40)
-#define MCF_EPORT_EPFR_EPF7 (0x80)
-
-/********************************************************************/
-
-#endif /* __MCF523X_EPORT_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h
deleted file mode 100644
index 91075acf8..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_etpu.h
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_etpu.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_ETPU_H__
-#define __MCF523X_ETPU_H__
-
-/*********************************************************************
-*
-* enhanced Time Processor Unit (ETPU)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
-#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
-#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
-#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
-#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
-#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
-#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
-#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
-#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
-#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
-#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
-#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
-#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
-#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
-#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
-#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
-#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
-#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
-#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
-#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
-#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
-#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
-#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
-#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
-#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
-#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
-#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
-#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
-#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
-#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
-#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
-#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
-#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
-#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
-#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
-#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
-#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
-#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
-#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
-#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
-#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
-#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
-#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
-#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
-#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
-#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
-#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
-#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
-#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
-#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
-#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
-#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
-#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
-#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
-#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
-#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
-#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
-#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
-#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
-#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
-#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
-#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
-#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
-#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
-#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
-#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
-#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
-#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
-#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
-#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
-#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
-#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
-#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
-#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
-#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
-#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
-#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
-#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
-#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
-#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
-#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
-#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
-#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
-#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
-#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
-#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
-#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
-#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
-#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
-#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
-#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
-#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
-#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
-#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
-#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
-#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
-#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
-#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
-#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
-#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
-#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
-#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
-#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
-#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
-#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
-#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
-#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
-#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
-#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
-#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
-#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
-#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
-#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
-#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
-#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
-#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
-
-/* Bit definitions and macros for MCF_ETPU_EMCR */
-#define MCF_ETPU_EMCR_GTBE (0x00000001)
-#define MCF_ETPU_EMCR_VIS (0x00000040)
-#define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
-#define MCF_ETPU_EMCR_SCMMISF (0x00000400)
-#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
-#define MCF_ETPU_EMCR_ILF2 (0x01000000)
-#define MCF_ETPU_EMCR_ILF1 (0x02000000)
-#define MCF_ETPU_EMCR_MGE2 (0x04000000)
-#define MCF_ETPU_EMCR_MGE1 (0x08000000)
-#define MCF_ETPU_EMCR_GEC (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDCR */
-#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
-#define MCF_ETPU_ECDCR_WR (0x00000080)
-#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
-#define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
-#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
-#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
-#define MCF_ETPU_ECDCR_STS (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_EECR */
-#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
-#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
-#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
-#define MCF_ETPU_EECR_HLTF (0x00800000)
-#define MCF_ETPU_EECR_STF (0x10000000)
-#define MCF_ETPU_EECR_MDIS (0x40000000)
-#define MCF_ETPU_EECR_FEND (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ETBCR */
-#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
-#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
-#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
-#define MCF_ETPU_ETBCR_AM (0x02000000)
-#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
-#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
-
-/* Bit definitions and macros for MCF_ETPU_ETB1R */
-#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_ETPU_ETB2R */
-#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
-
-/* Bit definitions and macros for MCF_ETPU_EREDCR */
-#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
-#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
-#define MCF_ETPU_EREDCR_RSC2 (0x00004000)
-#define MCF_ETPU_EREDCR_REN2 (0x00008000)
-#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
-#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
-#define MCF_ETPU_EREDCR_RSC1 (0x40000000)
-#define MCF_ETPU_EREDCR_REN1 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECISR */
-#define MCF_ETPU_ECISR_CIS0 (0x00000001)
-#define MCF_ETPU_ECISR_CIS1 (0x00000002)
-#define MCF_ETPU_ECISR_CIS2 (0x00000004)
-#define MCF_ETPU_ECISR_CIS3 (0x00000008)
-#define MCF_ETPU_ECISR_CIS4 (0x00000010)
-#define MCF_ETPU_ECISR_CIS5 (0x00000020)
-#define MCF_ETPU_ECISR_CIS6 (0x00000040)
-#define MCF_ETPU_ECISR_CIS7 (0x00000080)
-#define MCF_ETPU_ECISR_CIS8 (0x00000100)
-#define MCF_ETPU_ECISR_CIS9 (0x00000200)
-#define MCF_ETPU_ECISR_CIS10 (0x00000400)
-#define MCF_ETPU_ECISR_CIS11 (0x00000800)
-#define MCF_ETPU_ECISR_CIS12 (0x00001000)
-#define MCF_ETPU_ECISR_CIS13 (0x00002000)
-#define MCF_ETPU_ECISR_CIS14 (0x00004000)
-#define MCF_ETPU_ECISR_CIS15 (0x00008000)
-#define MCF_ETPU_ECISR_CIS16 (0x00010000)
-#define MCF_ETPU_ECISR_CIS17 (0x00020000)
-#define MCF_ETPU_ECISR_CIS18 (0x00040000)
-#define MCF_ETPU_ECISR_CIS19 (0x00080000)
-#define MCF_ETPU_ECISR_CIS20 (0x00100000)
-#define MCF_ETPU_ECISR_CIS21 (0x00200000)
-#define MCF_ETPU_ECISR_CIS22 (0x00400000)
-#define MCF_ETPU_ECISR_CIS23 (0x00800000)
-#define MCF_ETPU_ECISR_CIS24 (0x01000000)
-#define MCF_ETPU_ECISR_CIS25 (0x02000000)
-#define MCF_ETPU_ECISR_CIS26 (0x04000000)
-#define MCF_ETPU_ECISR_CIS27 (0x08000000)
-#define MCF_ETPU_ECISR_CIS28 (0x10000000)
-#define MCF_ETPU_ECISR_CIS29 (0x20000000)
-#define MCF_ETPU_ECISR_CIS30 (0x40000000)
-#define MCF_ETPU_ECISR_CIS31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
-#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
-#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
-#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
-#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
-#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
-#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
-#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
-#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
-#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
-#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
-#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
-#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
-#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
-#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
-#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
-#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
-#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
-#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
-#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
-#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
-#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
-#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
-#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
-#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
-#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
-#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
-#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
-#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
-#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
-#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
-#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
-#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECIOSR */
-#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
-#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
-#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
-#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
-#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
-#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
-#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
-#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
-#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
-#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
-#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
-#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
-#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
-#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
-#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
-#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
-#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
-#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
-#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
-#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
-#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
-#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
-#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
-#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
-#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
-#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
-#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
-#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
-#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
-#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
-#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
-#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
-#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
-#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
-#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
-#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
-#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
-#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
-#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
-#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
-#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
-#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
-#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
-#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
-#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
-#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
-#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
-#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
-#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
-#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
-#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
-#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
-#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
-#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
-#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
-#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
-#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
-#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
-#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
-#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
-#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
-#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
-#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
-#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECIER */
-#define MCF_ETPU_ECIER_CIE0 (0x00000001)
-#define MCF_ETPU_ECIER_CIE1 (0x00000002)
-#define MCF_ETPU_ECIER_CIE2 (0x00000004)
-#define MCF_ETPU_ECIER_CIE3 (0x00000008)
-#define MCF_ETPU_ECIER_CIE4 (0x00000010)
-#define MCF_ETPU_ECIER_CIE5 (0x00000020)
-#define MCF_ETPU_ECIER_CIE6 (0x00000040)
-#define MCF_ETPU_ECIER_CIE7 (0x00000080)
-#define MCF_ETPU_ECIER_CIE8 (0x00000100)
-#define MCF_ETPU_ECIER_CIE9 (0x00000200)
-#define MCF_ETPU_ECIER_CIE10 (0x00000400)
-#define MCF_ETPU_ECIER_CIE11 (0x00000800)
-#define MCF_ETPU_ECIER_CIE12 (0x00001000)
-#define MCF_ETPU_ECIER_CIE13 (0x00002000)
-#define MCF_ETPU_ECIER_CIE14 (0x00004000)
-#define MCF_ETPU_ECIER_CIE15 (0x00008000)
-#define MCF_ETPU_ECIER_CIE16 (0x00010000)
-#define MCF_ETPU_ECIER_CIE17 (0x00020000)
-#define MCF_ETPU_ECIER_CIE18 (0x00040000)
-#define MCF_ETPU_ECIER_CIE19 (0x00080000)
-#define MCF_ETPU_ECIER_CIE20 (0x00100000)
-#define MCF_ETPU_ECIER_CIE21 (0x00200000)
-#define MCF_ETPU_ECIER_CIE22 (0x00400000)
-#define MCF_ETPU_ECIER_CIE23 (0x00800000)
-#define MCF_ETPU_ECIER_CIE24 (0x01000000)
-#define MCF_ETPU_ECIER_CIE25 (0x02000000)
-#define MCF_ETPU_ECIER_CIE26 (0x04000000)
-#define MCF_ETPU_ECIER_CIE27 (0x08000000)
-#define MCF_ETPU_ECIER_CIE28 (0x10000000)
-#define MCF_ETPU_ECIER_CIE29 (0x20000000)
-#define MCF_ETPU_ECIER_CIE30 (0x40000000)
-#define MCF_ETPU_ECIER_CIE31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECDTRER */
-#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
-#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
-#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
-#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
-#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
-#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
-#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
-#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
-#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
-#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
-#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
-#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
-#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
-#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
-#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
-#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
-#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
-#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
-#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
-#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
-#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
-#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
-#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
-#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
-#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
-#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
-#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
-#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
-#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
-#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
-#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
-#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECPSSR */
-#define MCF_ETPU_ECPSSR_SR0 (0x00000001)
-#define MCF_ETPU_ECPSSR_SR1 (0x00000002)
-#define MCF_ETPU_ECPSSR_SR2 (0x00000004)
-#define MCF_ETPU_ECPSSR_SR3 (0x00000008)
-#define MCF_ETPU_ECPSSR_SR4 (0x00000010)
-#define MCF_ETPU_ECPSSR_SR5 (0x00000020)
-#define MCF_ETPU_ECPSSR_SR6 (0x00000040)
-#define MCF_ETPU_ECPSSR_SR7 (0x00000080)
-#define MCF_ETPU_ECPSSR_SR8 (0x00000100)
-#define MCF_ETPU_ECPSSR_SR9 (0x00000200)
-#define MCF_ETPU_ECPSSR_SR10 (0x00000400)
-#define MCF_ETPU_ECPSSR_SR11 (0x00000800)
-#define MCF_ETPU_ECPSSR_SR12 (0x00001000)
-#define MCF_ETPU_ECPSSR_SR13 (0x00002000)
-#define MCF_ETPU_ECPSSR_SR14 (0x00004000)
-#define MCF_ETPU_ECPSSR_SR15 (0x00008000)
-#define MCF_ETPU_ECPSSR_SR16 (0x00010000)
-#define MCF_ETPU_ECPSSR_SR17 (0x00020000)
-#define MCF_ETPU_ECPSSR_SR18 (0x00040000)
-#define MCF_ETPU_ECPSSR_SR19 (0x00080000)
-#define MCF_ETPU_ECPSSR_SR20 (0x00100000)
-#define MCF_ETPU_ECPSSR_SR21 (0x00200000)
-#define MCF_ETPU_ECPSSR_SR22 (0x00400000)
-#define MCF_ETPU_ECPSSR_SR23 (0x00800000)
-#define MCF_ETPU_ECPSSR_SR24 (0x01000000)
-#define MCF_ETPU_ECPSSR_SR25 (0x02000000)
-#define MCF_ETPU_ECPSSR_SR26 (0x04000000)
-#define MCF_ETPU_ECPSSR_SR27 (0x08000000)
-#define MCF_ETPU_ECPSSR_SR28 (0x10000000)
-#define MCF_ETPU_ECPSSR_SR29 (0x20000000)
-#define MCF_ETPU_ECPSSR_SR30 (0x40000000)
-#define MCF_ETPU_ECPSSR_SR31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECSSR */
-#define MCF_ETPU_ECSSR_SS0 (0x00000001)
-#define MCF_ETPU_ECSSR_SS1 (0x00000002)
-#define MCF_ETPU_ECSSR_SS2 (0x00000004)
-#define MCF_ETPU_ECSSR_SS3 (0x00000008)
-#define MCF_ETPU_ECSSR_SS4 (0x00000010)
-#define MCF_ETPU_ECSSR_SS5 (0x00000020)
-#define MCF_ETPU_ECSSR_SS6 (0x00000040)
-#define MCF_ETPU_ECSSR_SS7 (0x00000080)
-#define MCF_ETPU_ECSSR_SS8 (0x00000100)
-#define MCF_ETPU_ECSSR_SS9 (0x00000200)
-#define MCF_ETPU_ECSSR_SS10 (0x00000400)
-#define MCF_ETPU_ECSSR_SS11 (0x00000800)
-#define MCF_ETPU_ECSSR_SS12 (0x00001000)
-#define MCF_ETPU_ECSSR_SS13 (0x00002000)
-#define MCF_ETPU_ECSSR_SS14 (0x00004000)
-#define MCF_ETPU_ECSSR_SS15 (0x00008000)
-#define MCF_ETPU_ECSSR_SS16 (0x00010000)
-#define MCF_ETPU_ECSSR_SS17 (0x00020000)
-#define MCF_ETPU_ECSSR_SS18 (0x00040000)
-#define MCF_ETPU_ECSSR_SS19 (0x00080000)
-#define MCF_ETPU_ECSSR_SS20 (0x00100000)
-#define MCF_ETPU_ECSSR_SS21 (0x00200000)
-#define MCF_ETPU_ECSSR_SS22 (0x00400000)
-#define MCF_ETPU_ECSSR_SS23 (0x00800000)
-#define MCF_ETPU_ECSSR_SS24 (0x01000000)
-#define MCF_ETPU_ECSSR_SS25 (0x02000000)
-#define MCF_ETPU_ECSSR_SS26 (0x04000000)
-#define MCF_ETPU_ECSSR_SS27 (0x08000000)
-#define MCF_ETPU_ECSSR_SS28 (0x10000000)
-#define MCF_ETPU_ECSSR_SS29 (0x20000000)
-#define MCF_ETPU_ECSSR_SS30 (0x40000000)
-#define MCF_ETPU_ECSSR_SS31 (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECnSCR */
-#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
-#define MCF_ETPU_ECnSCR_OBE (0x00002000)
-#define MCF_ETPU_ECnSCR_OPS (0x00004000)
-#define MCF_ETPU_ECnSCR_IPS (0x00008000)
-#define MCF_ETPU_ECnSCR_DTROS (0x00400000)
-#define MCF_ETPU_ECnSCR_DTRS (0x00800000)
-#define MCF_ETPU_ECnSCR_CIOS (0x40000000)
-#define MCF_ETPU_ECnSCR_CIS (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECnCR */
-#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
-#define MCF_ETPU_ECnCR_OPOL (0x00004000)
-#define MCF_ETPU_ECnCR_ODIS (0x00008000)
-#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
-#define MCF_ETPU_ECnCR_ETCS (0x01000000)
-#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
-#define MCF_ETPU_ECnCR_DTRE (0x40000000)
-#define MCF_ETPU_ECnCR_CIE (0x80000000)
-
-/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
-#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_ETPU_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h
deleted file mode 100644
index 2b20a153f..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fec.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_fec.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_FEC_H__
-#define __MCF523X_FEC_H__
-
-/*********************************************************************
-*
-* Fast Ethernet Controller (FEC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
-#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
-#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
-#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
-#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
-#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
-#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
-#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
-#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
-#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
-#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
-#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
-#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
-#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
-#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
-#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
-#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
-#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
-#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
-#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
-#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
-#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
-#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
-#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
-#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
-#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
-#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
-#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
-#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
-#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
-#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
-#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
-#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
-#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
-#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
-#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
-#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
-#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
-#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
-#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
-#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
-#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
-#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
-#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
-#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
-#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
-#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
-#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
-#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
-#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
-#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
-#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
-#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
-#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
-#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
-#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
-#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
-#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
-#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
-#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
-#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
-#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
-#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
-#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
-#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
-#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
-#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
-#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
-#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
-#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
-#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
-#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
-#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
-#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
-#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
-#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
-#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
-
-/* Bit definitions and macros for MCF_FEC_EIR */
-#define MCF_FEC_EIR_UN (0x00080000)
-#define MCF_FEC_EIR_RL (0x00100000)
-#define MCF_FEC_EIR_LC (0x00200000)
-#define MCF_FEC_EIR_EBERR (0x00400000)
-#define MCF_FEC_EIR_MII (0x00800000)
-#define MCF_FEC_EIR_RXB (0x01000000)
-#define MCF_FEC_EIR_RXF (0x02000000)
-#define MCF_FEC_EIR_TXB (0x04000000)
-#define MCF_FEC_EIR_TXF (0x08000000)
-#define MCF_FEC_EIR_GRA (0x10000000)
-#define MCF_FEC_EIR_BABT (0x20000000)
-#define MCF_FEC_EIR_BABR (0x40000000)
-#define MCF_FEC_EIR_HBERR (0x80000000)
-
-/* Bit definitions and macros for MCF_FEC_EIMR */
-#define MCF_FEC_EIMR_UN (0x00080000)
-#define MCF_FEC_EIMR_RL (0x00100000)
-#define MCF_FEC_EIMR_LC (0x00200000)
-#define MCF_FEC_EIMR_EBERR (0x00400000)
-#define MCF_FEC_EIMR_MII (0x00800000)
-#define MCF_FEC_EIMR_RXB (0x01000000)
-#define MCF_FEC_EIMR_RXF (0x02000000)
-#define MCF_FEC_EIMR_TXB (0x04000000)
-#define MCF_FEC_EIMR_TXF (0x08000000)
-#define MCF_FEC_EIMR_GRA (0x10000000)
-#define MCF_FEC_EIMR_BABT (0x20000000)
-#define MCF_FEC_EIMR_BABR (0x40000000)
-#define MCF_FEC_EIMR_HBERR (0x80000000)
-
-/* Bit definitions and macros for MCF_FEC_RDAR */
-#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
-
-/* Bit definitions and macros for MCF_FEC_TDAR */
-#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
-
-/* Bit definitions and macros for MCF_FEC_ECR */
-#define MCF_FEC_ECR_RESET (0x00000001)
-#define MCF_FEC_ECR_ETHER_EN (0x00000002)
-
-/* Bit definitions and macros for MCF_FEC_MMFR */
-#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
-#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
-#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
-#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
-#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
-#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
-#define MCF_FEC_MMFR_ST_01 (0x40000000)
-#define MCF_FEC_MMFR_OP_READ (0x20000000)
-#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
-#define MCF_FEC_MMFR_TA_10 (0x00020000)
-
-
-/* Bit definitions and macros for MCF_FEC_MSCR */
-#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
-#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
-
-/* Bit definitions and macros for MCF_FEC_MIBC */
-#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
-#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
-
-/* Bit definitions and macros for MCF_FEC_RCR */
-#define MCF_FEC_RCR_LOOP (0x00000001)
-#define MCF_FEC_RCR_DRT (0x00000002)
-#define MCF_FEC_RCR_MII_MODE (0x00000004)
-#define MCF_FEC_RCR_PROM (0x00000008)
-#define MCF_FEC_RCR_BC_REJ (0x00000010)
-#define MCF_FEC_RCR_FCE (0x00000020)
-#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
-
-/* Bit definitions and macros for MCF_FEC_TCR */
-#define MCF_FEC_TCR_GTS (0x00000001)
-#define MCF_FEC_TCR_HBC (0x00000002)
-#define MCF_FEC_TCR_FDEN (0x00000004)
-#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
-#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
-
-/* Bit definitions and macros for MCF_FEC_PAUR */
-#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
-#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for MCF_FEC_OPD */
-#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
-#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for MCF_FEC_TFWR */
-#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
-
-/* Bit definitions and macros for MCF_FEC_FRBR */
-#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_FRSR */
-#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_ERDSR */
-#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_ETDSR */
-#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
-
-/* Bit definitions and macros for MCF_FEC_EMRBR */
-#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
-
-/********************************************************************/
-
-#endif /* __MCF523X_FEC_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h
deleted file mode 100644
index d9dc941d4..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_fmpll.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_fmpll.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_FMPLL_H__
-#define __MCF523X_FMPLL_H__
-
-/*********************************************************************
-*
-* Frequency Modulated Phase Locked Loop (FMPLL)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
-#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
-
-/* Bit definitions and macros for MCF_FMPLL_SYNCR */
-#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0)
-#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10)
-#define MCF_FMPLL_SYNCR_RATE (0x00001000)
-#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000)
-#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000)
-#define MCF_FMPLL_SYNCR_DISCLK (0x00008000)
-#define MCF_FMPLL_SYNCR_LOCRE (0x00010000)
-#define MCF_FMPLL_SYNCR_LOLRE (0x00020000)
-#define MCF_FMPLL_SYNCR_LOCEN (0x00040000)
-#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19)
-#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24)
-
-/* Bit definitions and macros for MCF_FMPLL_SYNSR */
-#define MCF_FMPLL_SYNSR_CALPASS (0x00000001)
-#define MCF_FMPLL_SYNSR_CALDONE (0x00000002)
-#define MCF_FMPLL_SYNSR_LOCF (0x00000004)
-#define MCF_FMPLL_SYNSR_LOCK (0x00000008)
-#define MCF_FMPLL_SYNSR_LOCKS (0x00000010)
-#define MCF_FMPLL_SYNSR_PLLREF (0x00000020)
-#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040)
-#define MCF_FMPLL_SYNSR_MODE (0x00000080)
-#define MCF_FMPLL_SYNSR_LOC (0x00000100)
-#define MCF_FMPLL_SYNSR_LOLF (0x00000200)
-
-/********************************************************************/
-
-#endif /* __MCF523X_FMPLL_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h
deleted file mode 100644
index 455ac850d..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_gpio.h
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_gpio.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_GPIO_H__
-#define __MCF523X_GPIO_H__
-
-/*********************************************************************
-*
-* General Purpose I/O (GPIO)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000]))
-#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001]))
-#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002]))
-#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003]))
-#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004]))
-#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005]))
-#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006]))
-#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007]))
-#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008]))
-#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009]))
-#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A]))
-#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B]))
-#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C]))
-#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010]))
-#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011]))
-#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012]))
-#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013]))
-#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014]))
-#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015]))
-#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016]))
-#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017]))
-#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018]))
-#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019]))
-#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A]))
-#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B]))
-#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C]))
-#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020]))
-#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021]))
-#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022]))
-#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023]))
-#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024]))
-#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027]))
-#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025]))
-#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026]))
-#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028]))
-#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029]))
-#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A]))
-#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B]))
-#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C]))
-#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030]))
-#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031]))
-#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032]))
-#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033]))
-#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034]))
-#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035]))
-#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036]))
-#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037]))
-#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038]))
-#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039]))
-#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A]))
-#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B]))
-#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C]))
-#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040]))
-#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042]))
-#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044]))
-#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045]))
-#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046]))
-#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047]))
-#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048]))
-#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A]))
-#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C]))
-#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E]))
-#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050]))
-#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051]))
-#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052]))
-#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053]))
-#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054]))
-#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055]))
-
-/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */
-#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20)
-#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40)
-#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40)
-#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40)
-#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40)
-#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_BS */
-#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01)
-#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02)
-#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04)
-#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_CS */
-#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
-#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
-#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
-#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
-#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
-#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40)
-#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10)
-#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */
-#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01)
-#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40)
-#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
-#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40)
-#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */
-#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01)
-#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02)
-#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */
-#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20)
-#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40)
-#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40)
-#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40)
-#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40)
-#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_BS */
-#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01)
-#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
-#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
-#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
-#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
-#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
-#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
-#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40)
-#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10)
-#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */
-#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01)
-#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40)
-#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
-#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40)
-#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */
-#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01)
-#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02)
-#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */
-#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20)
-#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40)
-#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40)
-#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40)
-#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40)
-#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01)
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02)
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04)
-#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40)
-#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40)
-#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */
-#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01)
-#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40)
-#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
-#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40)
-#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */
-#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01)
-#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02)
-#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */
-#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20)
-#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40)
-#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40)
-#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40)
-#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40)
-#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01)
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02)
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04)
-#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40)
-#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10)
-#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */
-#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01)
-#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40)
-#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
-#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40)
-#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */
-#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01)
-#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02)
-#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_AD */
-#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01)
-#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20)
-#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40)
-#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040)
-#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002)
-#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_BS */
-#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01)
-#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02)
-#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04)
-#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_CS */
-#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
-#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
-#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
-#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
-#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
-#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40)
-#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */
-#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01)
-#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02)
-#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04)
-#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08)
-#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10)
-#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20)
-#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20)
-#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08)
-#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02)
-#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_UART */
-#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001)
-#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002)
-#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004)
-#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000)
-#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000)
-#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000)
-#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800)
-#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200)
-#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080)
-#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020)
-#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
-#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0)
-#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80)
-#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10)
-#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C)
-#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00)
-#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02)
-#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800)
-#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200)
-#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080)
-#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020)
-#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008)
-#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C)
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000)
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002)
-#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003)
-
-/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */
-#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01)
-#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02)
-#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */
-#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01)
-#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01)
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04)
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10)
-#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */
-#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01)
-#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
-#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01)
-#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04)
-#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10)
-#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
-#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)
-
-/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
-#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01)
-
-/********************************************************************/
-
-#endif /* __MCF523X_GPIO_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h
deleted file mode 100644
index ee4665507..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_i2c.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_i2c.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_I2C_H__
-#define __MCF523X_I2C_H__
-
-/*********************************************************************
-*
-* I2C Module (I2C)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
-#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
-#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
-#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
-#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
-#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
-
-/* Bit definitions and macros for MCF_I2C_I2AR */
-#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for MCF_I2C_I2FDR */
-#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
-
-/* Bit definitions and macros for MCF_I2C_I2CR */
-#define MCF_I2C_I2CR_RSTA (0x04)
-#define MCF_I2C_I2CR_TXAK (0x08)
-#define MCF_I2C_I2CR_MTX (0x10)
-#define MCF_I2C_I2CR_MSTA (0x20)
-#define MCF_I2C_I2CR_IIEN (0x40)
-#define MCF_I2C_I2CR_IEN (0x80)
-
-/* Bit definitions and macros for MCF_I2C_I2SR */
-#define MCF_I2C_I2SR_RXAK (0x01)
-#define MCF_I2C_I2SR_IIF (0x02)
-#define MCF_I2C_I2SR_SRW (0x04)
-#define MCF_I2C_I2SR_IAL (0x10)
-#define MCF_I2C_I2SR_IBB (0x20)
-#define MCF_I2C_I2SR_IAAS (0x40)
-#define MCF_I2C_I2SR_ICF (0x80)
-
-/* Bit definitions and macros for MCF_I2C_I2ICR */
-#define MCF_I2C_I2ICR_IE (0x01)
-#define MCF_I2C_I2ICR_RE (0x02)
-#define MCF_I2C_I2ICR_TE (0x04)
-#define MCF_I2C_I2ICR_BNBE (0x08)
-
-/********************************************************************/
-
-#endif /* __MCF523X_I2C_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h
deleted file mode 100644
index 7d19e9863..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc0.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_intc0.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_INTC0_H__
-#define __MCF523X_INTC0_H__
-
-/*********************************************************************
-*
-* Interrupt Controller 0 (INTC0)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
-#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
-#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
-#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
-#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
-#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
-#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
-#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
-#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
-#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
-#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
-#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
-#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
-#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
-#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
-#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
-#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
-#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
-#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
-#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
-#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
-#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
-#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
-#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
-#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
-#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
-#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
-#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
-#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
-#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
-#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
-#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
-#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
-#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
-#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
-#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
-#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
-#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
-#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
-#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
-#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
-#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
-#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
-#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
-#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
-#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
-#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
-#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
-#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
-#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
-#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
-#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
-#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
-#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
-#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
-#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
-#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
-#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
-#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
-#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
-#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
-#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
-#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
-#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
-#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
-#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
-#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
-#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
-#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
-#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
-#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
-#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
-#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
-#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
-#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
-#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
-#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
-#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
-#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
-#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
-#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
-#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
-
-/* Bit definitions and macros for MCF_INTC0_IPRH */
-#define MCF_INTC0_IPRH_INT32 (0x00000001)
-#define MCF_INTC0_IPRH_INT33 (0x00000002)
-#define MCF_INTC0_IPRH_INT34 (0x00000004)
-#define MCF_INTC0_IPRH_INT35 (0x00000008)
-#define MCF_INTC0_IPRH_INT36 (0x00000010)
-#define MCF_INTC0_IPRH_INT37 (0x00000020)
-#define MCF_INTC0_IPRH_INT38 (0x00000040)
-#define MCF_INTC0_IPRH_INT39 (0x00000080)
-#define MCF_INTC0_IPRH_INT40 (0x00000100)
-#define MCF_INTC0_IPRH_INT41 (0x00000200)
-#define MCF_INTC0_IPRH_INT42 (0x00000400)
-#define MCF_INTC0_IPRH_INT43 (0x00000800)
-#define MCF_INTC0_IPRH_INT44 (0x00001000)
-#define MCF_INTC0_IPRH_INT45 (0x00002000)
-#define MCF_INTC0_IPRH_INT46 (0x00004000)
-#define MCF_INTC0_IPRH_INT47 (0x00008000)
-#define MCF_INTC0_IPRH_INT48 (0x00010000)
-#define MCF_INTC0_IPRH_INT49 (0x00020000)
-#define MCF_INTC0_IPRH_INT50 (0x00040000)
-#define MCF_INTC0_IPRH_INT51 (0x00080000)
-#define MCF_INTC0_IPRH_INT52 (0x00100000)
-#define MCF_INTC0_IPRH_INT53 (0x00200000)
-#define MCF_INTC0_IPRH_INT54 (0x00400000)
-#define MCF_INTC0_IPRH_INT55 (0x00800000)
-#define MCF_INTC0_IPRH_INT56 (0x01000000)
-#define MCF_INTC0_IPRH_INT57 (0x02000000)
-#define MCF_INTC0_IPRH_INT58 (0x04000000)
-#define MCF_INTC0_IPRH_INT59 (0x08000000)
-#define MCF_INTC0_IPRH_INT60 (0x10000000)
-#define MCF_INTC0_IPRH_INT61 (0x20000000)
-#define MCF_INTC0_IPRH_INT62 (0x40000000)
-#define MCF_INTC0_IPRH_INT63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IPRL */
-#define MCF_INTC0_IPRL_INT1 (0x00000002)
-#define MCF_INTC0_IPRL_INT2 (0x00000004)
-#define MCF_INTC0_IPRL_INT3 (0x00000008)
-#define MCF_INTC0_IPRL_INT4 (0x00000010)
-#define MCF_INTC0_IPRL_INT5 (0x00000020)
-#define MCF_INTC0_IPRL_INT6 (0x00000040)
-#define MCF_INTC0_IPRL_INT7 (0x00000080)
-#define MCF_INTC0_IPRL_INT8 (0x00000100)
-#define MCF_INTC0_IPRL_INT9 (0x00000200)
-#define MCF_INTC0_IPRL_INT10 (0x00000400)
-#define MCF_INTC0_IPRL_INT11 (0x00000800)
-#define MCF_INTC0_IPRL_INT12 (0x00001000)
-#define MCF_INTC0_IPRL_INT13 (0x00002000)
-#define MCF_INTC0_IPRL_INT14 (0x00004000)
-#define MCF_INTC0_IPRL_INT15 (0x00008000)
-#define MCF_INTC0_IPRL_INT16 (0x00010000)
-#define MCF_INTC0_IPRL_INT17 (0x00020000)
-#define MCF_INTC0_IPRL_INT18 (0x00040000)
-#define MCF_INTC0_IPRL_INT19 (0x00080000)
-#define MCF_INTC0_IPRL_INT20 (0x00100000)
-#define MCF_INTC0_IPRL_INT21 (0x00200000)
-#define MCF_INTC0_IPRL_INT22 (0x00400000)
-#define MCF_INTC0_IPRL_INT23 (0x00800000)
-#define MCF_INTC0_IPRL_INT24 (0x01000000)
-#define MCF_INTC0_IPRL_INT25 (0x02000000)
-#define MCF_INTC0_IPRL_INT26 (0x04000000)
-#define MCF_INTC0_IPRL_INT27 (0x08000000)
-#define MCF_INTC0_IPRL_INT28 (0x10000000)
-#define MCF_INTC0_IPRL_INT29 (0x20000000)
-#define MCF_INTC0_IPRL_INT30 (0x40000000)
-#define MCF_INTC0_IPRL_INT31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IMRH */
-#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001)
-#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002)
-#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004)
-#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008)
-#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010)
-#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020)
-#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040)
-#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080)
-#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100)
-#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200)
-#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400)
-#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800)
-#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000)
-#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000)
-#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000)
-#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000)
-#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000)
-#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000)
-#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000)
-#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000)
-#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000)
-#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000)
-#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000)
-#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000)
-#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000)
-#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000)
-#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000)
-#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000)
-#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000)
-#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000)
-#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000)
-#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IMRL */
-#define MCF_INTC0_IMRL_MASKALL (0x00000001)
-#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002)
-#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004)
-#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008)
-#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010)
-#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020)
-#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040)
-#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080)
-#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100)
-#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200)
-#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400)
-#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800)
-#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000)
-#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000)
-#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000)
-#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000)
-#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000)
-#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000)
-#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000)
-#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000)
-#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000)
-#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000)
-#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000)
-#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000)
-#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000)
-#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000)
-#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000)
-#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000)
-#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000)
-#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000)
-#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000)
-#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_INTFRCH */
-#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001)
-#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002)
-#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004)
-#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008)
-#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010)
-#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020)
-#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040)
-#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080)
-#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100)
-#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200)
-#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400)
-#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800)
-#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000)
-#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000)
-#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000)
-#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000)
-#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000)
-#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000)
-#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000)
-#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000)
-#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000)
-#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000)
-#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000)
-#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000)
-#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000)
-#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000)
-#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000)
-#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000)
-#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000)
-#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000)
-#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000)
-#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_INTFRCL */
-#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002)
-#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004)
-#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008)
-#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010)
-#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020)
-#define MCF_INTC0_INTFRCL_INT6 (0x00000040)
-#define MCF_INTC0_INTFRCL_INT7 (0x00000080)
-#define MCF_INTC0_INTFRCL_INT8 (0x00000100)
-#define MCF_INTC0_INTFRCL_INT9 (0x00000200)
-#define MCF_INTC0_INTFRCL_INT10 (0x00000400)
-#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800)
-#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000)
-#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000)
-#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000)
-#define MCF_INTC0_INTFRCL_INT15 (0x00008000)
-#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000)
-#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000)
-#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000)
-#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000)
-#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000)
-#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000)
-#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000)
-#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000)
-#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000)
-#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000)
-#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000)
-#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000)
-#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000)
-#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000)
-#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000)
-#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC0_IRLR */
-#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for MCF_INTC0_IACKLPR */
-#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0)
-#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
-
-/* Bit definitions and macros for MCF_INTC0_ICRn */
-#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0)
-#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3)
-
-/********************************************************************/
-
-#endif /* __MCF523X_INTC0_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h
deleted file mode 100644
index 45613eaaf..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_intc1.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_intc1.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_INTC1_H__
-#define __MCF523X_INTC1_H__
-
-/*********************************************************************
-*
-* Interrupt Controller 1 (INTC1)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
-#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
-#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
-#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
-#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
-#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
-#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
-#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
-#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
-#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
-#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
-#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
-#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
-#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
-#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
-#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
-#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
-#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
-#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
-#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
-#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
-#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
-#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
-#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
-#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
-#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
-#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
-#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
-#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
-#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
-#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
-#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
-#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
-#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
-#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
-#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
-#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
-#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
-#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
-#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
-#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
-#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
-#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
-#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
-#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
-#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
-#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
-#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
-#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
-#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
-#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
-#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
-#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
-#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
-#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
-#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
-#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
-#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
-#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
-#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
-#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
-#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
-#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
-#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
-#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
-#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
-#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
-#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
-#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
-#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
-#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
-#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
-#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
-#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
-#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
-#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
-#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
-#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
-#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
-#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
-#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
-#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
-
-/* Bit definitions and macros for MCF_INTC1_IPRH */
-#define MCF_INTC1_IPRH_INT32 (0x00000001)
-#define MCF_INTC1_IPRH_INT33 (0x00000002)
-#define MCF_INTC1_IPRH_INT34 (0x00000004)
-#define MCF_INTC1_IPRH_INT35 (0x00000008)
-#define MCF_INTC1_IPRH_INT36 (0x00000010)
-#define MCF_INTC1_IPRH_INT37 (0x00000020)
-#define MCF_INTC1_IPRH_INT38 (0x00000040)
-#define MCF_INTC1_IPRH_INT39 (0x00000080)
-#define MCF_INTC1_IPRH_INT40 (0x00000100)
-#define MCF_INTC1_IPRH_INT41 (0x00000200)
-#define MCF_INTC1_IPRH_INT42 (0x00000400)
-#define MCF_INTC1_IPRH_INT43 (0x00000800)
-#define MCF_INTC1_IPRH_INT44 (0x00001000)
-#define MCF_INTC1_IPRH_INT45 (0x00002000)
-#define MCF_INTC1_IPRH_INT46 (0x00004000)
-#define MCF_INTC1_IPRH_INT47 (0x00008000)
-#define MCF_INTC1_IPRH_INT48 (0x00010000)
-#define MCF_INTC1_IPRH_INT49 (0x00020000)
-#define MCF_INTC1_IPRH_INT50 (0x00040000)
-#define MCF_INTC1_IPRH_INT51 (0x00080000)
-#define MCF_INTC1_IPRH_INT52 (0x00100000)
-#define MCF_INTC1_IPRH_INT53 (0x00200000)
-#define MCF_INTC1_IPRH_INT54 (0x00400000)
-#define MCF_INTC1_IPRH_INT55 (0x00800000)
-#define MCF_INTC1_IPRH_INT56 (0x01000000)
-#define MCF_INTC1_IPRH_INT57 (0x02000000)
-#define MCF_INTC1_IPRH_INT58 (0x04000000)
-#define MCF_INTC1_IPRH_INT59 (0x08000000)
-#define MCF_INTC1_IPRH_INT60 (0x10000000)
-#define MCF_INTC1_IPRH_INT61 (0x20000000)
-#define MCF_INTC1_IPRH_INT62 (0x40000000)
-#define MCF_INTC1_IPRH_INT63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IPRL */
-#define MCF_INTC1_IPRL_INT1 (0x00000002)
-#define MCF_INTC1_IPRL_INT2 (0x00000004)
-#define MCF_INTC1_IPRL_INT3 (0x00000008)
-#define MCF_INTC1_IPRL_INT4 (0x00000010)
-#define MCF_INTC1_IPRL_INT5 (0x00000020)
-#define MCF_INTC1_IPRL_INT6 (0x00000040)
-#define MCF_INTC1_IPRL_INT7 (0x00000080)
-#define MCF_INTC1_IPRL_INT8 (0x00000100)
-#define MCF_INTC1_IPRL_INT9 (0x00000200)
-#define MCF_INTC1_IPRL_INT10 (0x00000400)
-#define MCF_INTC1_IPRL_INT11 (0x00000800)
-#define MCF_INTC1_IPRL_INT12 (0x00001000)
-#define MCF_INTC1_IPRL_INT13 (0x00002000)
-#define MCF_INTC1_IPRL_INT14 (0x00004000)
-#define MCF_INTC1_IPRL_INT15 (0x00008000)
-#define MCF_INTC1_IPRL_INT16 (0x00010000)
-#define MCF_INTC1_IPRL_INT17 (0x00020000)
-#define MCF_INTC1_IPRL_INT18 (0x00040000)
-#define MCF_INTC1_IPRL_INT19 (0x00080000)
-#define MCF_INTC1_IPRL_INT20 (0x00100000)
-#define MCF_INTC1_IPRL_INT21 (0x00200000)
-#define MCF_INTC1_IPRL_INT22 (0x00400000)
-#define MCF_INTC1_IPRL_INT23 (0x00800000)
-#define MCF_INTC1_IPRL_INT24 (0x01000000)
-#define MCF_INTC1_IPRL_INT25 (0x02000000)
-#define MCF_INTC1_IPRL_INT26 (0x04000000)
-#define MCF_INTC1_IPRL_INT27 (0x08000000)
-#define MCF_INTC1_IPRL_INT28 (0x10000000)
-#define MCF_INTC1_IPRL_INT29 (0x20000000)
-#define MCF_INTC1_IPRL_INT30 (0x40000000)
-#define MCF_INTC1_IPRL_INT31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IMRH */
-#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001)
-#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002)
-#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004)
-#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008)
-#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010)
-#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020)
-#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040)
-#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080)
-#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100)
-#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200)
-#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400)
-#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800)
-#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000)
-#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000)
-#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000)
-#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000)
-#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000)
-#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000)
-#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000)
-#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000)
-#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000)
-#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000)
-#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000)
-#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000)
-#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000)
-#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000)
-#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000)
-#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000)
-#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000)
-#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000)
-#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000)
-#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IMRL */
-#define MCF_INTC1_IMRL_MASKALL (0x00000001)
-#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002)
-#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004)
-#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008)
-#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010)
-#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020)
-#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040)
-#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080)
-#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100)
-#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200)
-#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400)
-#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800)
-#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000)
-#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000)
-#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000)
-#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000)
-#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000)
-#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000)
-#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000)
-#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000)
-#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000)
-#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000)
-#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000)
-#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000)
-#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000)
-#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000)
-#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000)
-#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000)
-#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000)
-#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000)
-#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000)
-#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_INTFRCH */
-#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001)
-#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002)
-#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004)
-#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008)
-#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010)
-#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020)
-#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040)
-#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080)
-#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100)
-#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200)
-#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400)
-#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800)
-#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000)
-#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000)
-#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000)
-#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000)
-#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000)
-#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000)
-#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000)
-#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000)
-#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000)
-#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000)
-#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000)
-#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000)
-#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000)
-#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000)
-#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000)
-#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000)
-#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000)
-#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000)
-#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000)
-#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_INTFRCL */
-#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002)
-#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004)
-#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008)
-#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010)
-#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020)
-#define MCF_INTC1_INTFRCL_INT6 (0x00000040)
-#define MCF_INTC1_INTFRCL_INT7 (0x00000080)
-#define MCF_INTC1_INTFRCL_INT8 (0x00000100)
-#define MCF_INTC1_INTFRCL_INT9 (0x00000200)
-#define MCF_INTC1_INTFRCL_INT10 (0x00000400)
-#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800)
-#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000)
-#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000)
-#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000)
-#define MCF_INTC1_INTFRCL_INT15 (0x00008000)
-#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000)
-#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000)
-#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000)
-#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000)
-#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000)
-#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000)
-#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000)
-#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000)
-#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000)
-#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000)
-#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000)
-#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000)
-#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000)
-#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000)
-#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000)
-#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000)
-
-/* Bit definitions and macros for MCF_INTC1_IRLR */
-#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
-
-/* Bit definitions and macros for MCF_INTC1_IACKLPR */
-#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
-#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
-
-/* Bit definitions and macros for MCF_INTC1_ICRn */
-#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0)
-#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3)
-
-/********************************************************************/
-
-#endif /* __MCF523X_INTC1_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h
deleted file mode 100644
index adc714f6d..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_mdha.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_mdha.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_MDHA_H__
-#define __MCF523X_MDHA_H__
-
-/*********************************************************************
-*
-* Message Digest Hardware Accelerator (MDHA)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
-#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
-#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
-#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
-#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
-#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
-#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
-#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
-#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
-#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
-#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
-#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
-#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
-#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
-#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
-#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
-#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
-#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
-#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
-
-/* Bit definitions and macros for MCF_MDHA_MDMR */
-#define MCF_MDHA_MDMR_ALG (0x00000001)
-#define MCF_MDHA_MDMR_PDATA (0x00000004)
-#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3)
-#define MCF_MDHA_MDMR_INIT (0x00000020)
-#define MCF_MDHA_MDMR_IPAD (0x00000040)
-#define MCF_MDHA_MDMR_OPAD (0x00000080)
-#define MCF_MDHA_MDMR_SWAP (0x00000100)
-#define MCF_MDHA_MDMR_MACFULL (0x00000200)
-#define MCF_MDHA_MDMR_SSL (0x00000400)
-
-/* Bit definitions and macros for MCF_MDHA_MDCR */
-#define MCF_MDHA_MDCR_IE (0x00000001)
-
-/* Bit definitions and macros for MCF_MDHA_MDCMR */
-#define MCF_MDHA_MDCMR_SWR (0x00000001)
-#define MCF_MDHA_MDCMR_RI (0x00000002)
-#define MCF_MDHA_MDCMR_CI (0x00000004)
-#define MCF_MDHA_MDCMR_GO (0x00000008)
-
-/* Bit definitions and macros for MCF_MDHA_MDSR */
-#define MCF_MDHA_MDSR_INT (0x00000001)
-#define MCF_MDHA_MDSR_DONE (0x00000002)
-#define MCF_MDHA_MDSR_ERR (0x00000004)
-#define MCF_MDHA_MDSR_RD (0x00000008)
-#define MCF_MDHA_MDSR_BUSY (0x00000010)
-#define MCF_MDHA_MDSR_END (0x00000020)
-#define MCF_MDHA_MDSR_HSH (0x00000040)
-#define MCF_MDHA_MDSR_GNW (0x00000080)
-#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8)
-#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13)
-#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16)
-
-/* Bit definitions and macros for MCF_MDHA_MDIR */
-#define MCF_MDHA_MDIR_IFO (0x00000001)
-#define MCF_MDHA_MDIR_NON (0x00000004)
-#define MCF_MDHA_MDIR_IME (0x00000010)
-#define MCF_MDHA_MDIR_IDS (0x00000020)
-#define MCF_MDHA_MDIR_RMDP (0x00000080)
-#define MCF_MDHA_MDIR_ERE (0x00000100)
-#define MCF_MDHA_MDIR_GTDS (0x00000200)
-
-/* Bit definitions and macros for MCF_MDHA_MDIMR */
-#define MCF_MDHA_MDIMR_IFO (0x00000001)
-#define MCF_MDHA_MDIMR_NON (0x00000004)
-#define MCF_MDHA_MDIMR_IME (0x00000010)
-#define MCF_MDHA_MDIMR_IDS (0x00000020)
-#define MCF_MDHA_MDIMR_RMDP (0x00000080)
-#define MCF_MDHA_MDIMR_ERE (0x00000100)
-#define MCF_MDHA_MDIMR_GTDS (0x00000200)
-
-/* Bit definitions and macros for MCF_MDHA_MDDSR */
-#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_MDHA_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h
deleted file mode 100644
index 0763d20f2..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_pit.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_pit.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_PIT_H__
-#define __MCF523X_PIT_H__
-
-/*********************************************************************
-*
-* Programmable Interrupt Timer Modules (PIT)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
-#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
-#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
-#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
-#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
-#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
-#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
-#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
-#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
-#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
-#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
-#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
-#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
-#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
-#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
-
-/* Bit definitions and macros for MCF_PIT_PCSR */
-#define MCF_PIT_PCSR_EN (0x0001)
-#define MCF_PIT_PCSR_RLD (0x0002)
-#define MCF_PIT_PCSR_PIF (0x0004)
-#define MCF_PIT_PCSR_PIE (0x0008)
-#define MCF_PIT_PCSR_OVW (0x0010)
-#define MCF_PIT_PCSR_HALTED (0x0020)
-#define MCF_PIT_PCSR_DOZE (0x0040)
-#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
-
-/* Bit definitions and macros for MCF_PIT_PMR */
-#define MCF_PIT_PMR_PM0 (0x0001)
-#define MCF_PIT_PMR_PM1 (0x0002)
-#define MCF_PIT_PMR_PM2 (0x0004)
-#define MCF_PIT_PMR_PM3 (0x0008)
-#define MCF_PIT_PMR_PM4 (0x0010)
-#define MCF_PIT_PMR_PM5 (0x0020)
-#define MCF_PIT_PMR_PM6 (0x0040)
-#define MCF_PIT_PMR_PM7 (0x0080)
-#define MCF_PIT_PMR_PM8 (0x0100)
-#define MCF_PIT_PMR_PM9 (0x0200)
-#define MCF_PIT_PMR_PM10 (0x0400)
-#define MCF_PIT_PMR_PM11 (0x0800)
-#define MCF_PIT_PMR_PM12 (0x1000)
-#define MCF_PIT_PMR_PM13 (0x2000)
-#define MCF_PIT_PMR_PM14 (0x4000)
-#define MCF_PIT_PMR_PM15 (0x8000)
-
-/* Bit definitions and macros for MCF_PIT_PCNTR */
-#define MCF_PIT_PCNTR_PC0 (0x0001)
-#define MCF_PIT_PCNTR_PC1 (0x0002)
-#define MCF_PIT_PCNTR_PC2 (0x0004)
-#define MCF_PIT_PCNTR_PC3 (0x0008)
-#define MCF_PIT_PCNTR_PC4 (0x0010)
-#define MCF_PIT_PCNTR_PC5 (0x0020)
-#define MCF_PIT_PCNTR_PC6 (0x0040)
-#define MCF_PIT_PCNTR_PC7 (0x0080)
-#define MCF_PIT_PCNTR_PC8 (0x0100)
-#define MCF_PIT_PCNTR_PC9 (0x0200)
-#define MCF_PIT_PCNTR_PC10 (0x0400)
-#define MCF_PIT_PCNTR_PC11 (0x0800)
-#define MCF_PIT_PCNTR_PC12 (0x1000)
-#define MCF_PIT_PCNTR_PC13 (0x2000)
-#define MCF_PIT_PCNTR_PC14 (0x4000)
-#define MCF_PIT_PCNTR_PC15 (0x8000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_PIT_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
deleted file mode 100644
index ed32d6d40..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_qspi.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_qspi.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_QSPI_H__
-#define __MCF523X_QSPI_H__
-
-/*********************************************************************
-*
-* Queued Serial Peripheral Interface (QSPI)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
-#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
-#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
-#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
-#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
-#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
-
-/* Bit definitions and macros for MCF_QSPI_QMR */
-#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
-#define MCF_QSPI_QMR_CPHA (0x0100)
-#define MCF_QSPI_QMR_CPOL (0x0200)
-#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
-#define MCF_QSPI_QMR_DOHIE (0x4000)
-#define MCF_QSPI_QMR_MSTR (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QDLYR */
-#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
-#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
-#define MCF_QSPI_QDLYR_SPE (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QWR */
-#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
-#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
-#define MCF_QSPI_QWR_CSIV (0x1000)
-#define MCF_QSPI_QWR_WRTO (0x2000)
-#define MCF_QSPI_QWR_WREN (0x4000)
-#define MCF_QSPI_QWR_HALT (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QIR */
-#define MCF_QSPI_QIR_SPIF (0x0001)
-#define MCF_QSPI_QIR_ABRT (0x0004)
-#define MCF_QSPI_QIR_WCEF (0x0008)
-#define MCF_QSPI_QIR_SPIFE (0x0100)
-#define MCF_QSPI_QIR_ABRTE (0x0400)
-#define MCF_QSPI_QIR_WCEFE (0x0800)
-#define MCF_QSPI_QIR_ABRTL (0x1000)
-#define MCF_QSPI_QIR_ABRTB (0x4000)
-#define MCF_QSPI_QIR_WCEFB (0x8000)
-
-/* Bit definitions and macros for MCF_QSPI_QAR */
-#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_QSPI_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h
deleted file mode 100644
index 784d0fab0..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rcm.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_rcm.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_RCM_H__
-#define __MCF523X_RCM_H__
-
-/*********************************************************************
-*
-* Reset Configuration Module (RCM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
-#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
-
-/* Bit definitions and macros for MCF_RCM_RCR */
-#define MCF_RCM_RCR_FRCRSTOUT (0x40)
-#define MCF_RCM_RCR_SOFTRST (0x80)
-
-/* Bit definitions and macros for MCF_RCM_RSR */
-#define MCF_RCM_RSR_LOL (0x01)
-#define MCF_RCM_RSR_LOC (0x02)
-#define MCF_RCM_RSR_EXT (0x04)
-#define MCF_RCM_RSR_POR (0x08)
-#define MCF_RCM_RSR_WDR (0x10)
-#define MCF_RCM_RSR_SOFT (0x20)
-
-/********************************************************************/
-
-#endif /* __MCF523X_RCM_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h
deleted file mode 100644
index 744bd0ae3..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_rng.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_rng.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_RNG_H__
-#define __MCF523X_RNG_H__
-
-/*********************************************************************
-*
-* Random Number Generator (RNG)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
-#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
-#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
-#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
-
-/* Bit definitions and macros for MCF_RNG_RNGCR */
-#define MCF_RNG_RNGCR_GO (0x00000001)
-#define MCF_RNG_RNGCR_HA (0x00000002)
-#define MCF_RNG_RNGCR_IM (0x00000004)
-#define MCF_RNG_RNGCR_CI (0x00000008)
-
-/* Bit definitions and macros for MCF_RNG_RNGSR */
-#define MCF_RNG_RNGSR_SV (0x00000001)
-#define MCF_RNG_RNGSR_LRS (0x00000002)
-#define MCF_RNG_RNGSR_FUF (0x00000004)
-#define MCF_RNG_RNGSR_EI (0x00000008)
-#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
-#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
-
-/********************************************************************/
-
-#endif /* __MCF523X_RNG_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h
deleted file mode 100644
index d9ef0f0eb..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_scm.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_scm.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_SCM_H__
-#define __MCF523X_SCM_H__
-
-/*********************************************************************
-*
-* System Control Module (SCM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
-#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
-#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
-#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
-#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
-#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
-#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
-#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
-#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
-#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
-#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
-#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
-#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
-#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
-#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
-#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
-#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
-#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
-#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
-
-/* Bit definitions and macros for MCF_SCM_IPSBAR */
-#define MCF_SCM_IPSBAR_V (0x00000001)
-#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30)
-
-/* Bit definitions and macros for MCF_SCM_RAMBAR */
-#define MCF_SCM_RAMBAR_BDE (0x00000200)
-#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
-
-/* Bit definitions and macros for MCF_SCM_CRSR */
-#define MCF_SCM_CRSR_CWDR (0x20)
-#define MCF_SCM_CRSR_EXT (0x80)
-
-/* Bit definitions and macros for MCF_SCM_CWCR */
-#define MCF_SCM_CWCR_CWTIC (0x01)
-#define MCF_SCM_CWCR_CWTAVAL (0x02)
-#define MCF_SCM_CWCR_CWTA (0x04)
-#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
-#define MCF_SCM_CWCR_CWRI (0x40)
-#define MCF_SCM_CWCR_CWE (0x80)
-
-/* Bit definitions and macros for MCF_SCM_LPICR */
-#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
-#define MCF_SCM_LPICR_ENBSTOP (0x80)
-
-/* Bit definitions and macros for MCF_SCM_DMAREQC */
-#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0)
-#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4)
-#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8)
-#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12)
-
-/* Bit definitions and macros for MCF_SCM_MPARK */
-#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8)
-#define MCF_SCM_MPARK_PRKLAST (0x00001000)
-#define MCF_SCM_MPARK_TIMEOUT (0x00002000)
-#define MCF_SCM_MPARK_FIXED (0x00004000)
-#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16)
-#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18)
-#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20)
-#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22)
-#define MCF_SCM_MPARK_BCR24BIT (0x01000000)
-#define MCF_SCM_MPARK_M2_P_EN (0x02000000)
-
-/* Bit definitions and macros for MCF_SCM_MPR */
-#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0)
-
-/* Bit definitions and macros for MCF_SCM_PACR0 */
-#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR0_LOCK0 (0x08)
-#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR0_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR1 */
-#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR1_LOCK0 (0x08)
-#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR1_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR2 */
-#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR2_LOCK0 (0x08)
-#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR2_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR3 */
-#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR3_LOCK0 (0x08)
-#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR3_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR4 */
-#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR4_LOCK0 (0x08)
-#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR4_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR5 */
-#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR5_LOCK0 (0x08)
-#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR5_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR6 */
-#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR6_LOCK0 (0x08)
-#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR6_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR7 */
-#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR7_LOCK0 (0x08)
-#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR7_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_PACR8 */
-#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0)
-#define MCF_SCM_PACR8_LOCK0 (0x08)
-#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4)
-#define MCF_SCM_PACR8_LOCK1 (0x80)
-
-/* Bit definitions and macros for MCF_SCM_GPACR0 */
-#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0)
-#define MCF_SCM_GPACR0_LOCK (0x80)
-
-/********************************************************************/
-
-#endif /* __MCF523X_SCM_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h
deleted file mode 100644
index dbf38f8b6..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sdramc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_sdramc.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_SDRAMC_H__
-#define __MCF523X_SDRAMC_H__
-
-/*********************************************************************
-*
-* SDRAM Controller (SDRAMC)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
-#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
-#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
-#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
-#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
-
-/* Bit definitions and macros for MCF_SDRAMC_DCR */
-#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
-#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
-#define MCF_SDRAMC_DCR_IS (0x0800)
-#define MCF_SDRAMC_DCR_COC (0x1000)
-#define MCF_SDRAMC_DCR_NAM (0x2000)
-
-/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
-#define MCF_SDRAMC_DACR0_IP (0x00000008)
-#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
-#define MCF_SDRAMC_DACR0_MRS (0x00000040)
-#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
-#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
-#define MCF_SDRAMC_DACR0_RE (0x00008000)
-#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
-
-/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
-#define MCF_SDRAMC_DMR0_V (0x00000001)
-#define MCF_SDRAMC_DMR0_WP (0x00000100)
-#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
-
-/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
-#define MCF_SDRAMC_DACR1_IP (0x00000008)
-#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
-#define MCF_SDRAMC_DACR1_MRS (0x00000040)
-#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
-#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
-#define MCF_SDRAMC_DACR1_RE (0x00008000)
-#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
-
-/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
-#define MCF_SDRAMC_DMR1_V (0x00000001)
-#define MCF_SDRAMC_DMR1_WP (0x00000100)
-#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
-
-/********************************************************************/
-
-#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
-#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
-#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
-#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
-#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
-#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000)
-#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000)
-#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000)
-#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000)
-#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000)
-#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000)
-#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000)
-#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000)
-#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000)
-#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000)
-#define MCF_SDRAMC_DMR_BAM_512K (0x00040000)
-#define MCF_SDRAMC_DMR_BAM_256K (0x00000000)
-#define MCF_SDRAMC_DMR_WP (0x00000100)
-#define MCF_SDRAMC_DMR_CI (0x00000040)
-#define MCF_SDRAMC_DMR_AM (0x00000020)
-#define MCF_SDRAMC_DMR_SC (0x00000010)
-#define MCF_SDRAMC_DMR_SD (0x00000008)
-#define MCF_SDRAMC_DMR_UC (0x00000004)
-#define MCF_SDRAMC_DMR_UD (0x00000002)
-#define MCF_SDRAMC_DMR_V (0x00000001)
-
-#endif /* __MCF523X_SDRAMC_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h
deleted file mode 100644
index e03d2e05c..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_skha.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_skha.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_SKHA_H__
-#define __MCF523X_SKHA_H__
-
-/*********************************************************************
-*
-* Symmetric Key Hardware Accelerator (SKHA)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
-#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
-#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
-#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
-#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
-#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
-#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
-#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
-#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
-#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
-#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
-#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
-#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
-#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
-#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
-#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
-#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
-#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
-#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
-#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
-#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
-#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
-#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
-#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
-#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
-#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
-#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
-#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
-#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
-#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
-
-/* Bit definitions and macros for MCF_SKHA_SKMR */
-#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0)
-#define MCF_SKHA_SKMR_DIR (0x00000004)
-#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3)
-#define MCF_SKHA_SKMR_DKP (0x00000100)
-#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9)
-#define MCF_SKHA_SKMR_CM_ECB (0x00000000)
-#define MCF_SKHA_SKMR_CM_CBC (0x00000008)
-#define MCF_SKHA_SKMR_CM_CTR (0x00000018)
-#define MCF_SKHA_SKMR_DIR_DEC (0x00000000)
-#define MCF_SKHA_SKMR_DIR_ENC (0x00000004)
-#define MCF_SKHA_SKMR_ALG_AES (0x00000000)
-#define MCF_SKHA_SKMR_ALG_DES (0x00000001)
-#define MCF_SKHA_SKMR_ALG_TDES (0x00000002)
-
-/* Bit definitions and macros for MCF_SKHA_SKCR */
-#define MCF_SKHA_SKCR_IE (0x00000001)
-
-/* Bit definitions and macros for MCF_SKHA_SKCMR */
-#define MCF_SKHA_SKCMR_SWR (0x00000001)
-#define MCF_SKHA_SKCMR_RI (0x00000002)
-#define MCF_SKHA_SKCMR_CI (0x00000004)
-#define MCF_SKHA_SKCMR_GO (0x00000008)
-
-/* Bit definitions and macros for MCF_SKHA_SKSR */
-#define MCF_SKHA_SKSR_INT (0x00000001)
-#define MCF_SKHA_SKSR_DONE (0x00000002)
-#define MCF_SKHA_SKSR_ERR (0x00000004)
-#define MCF_SKHA_SKSR_RD (0x00000008)
-#define MCF_SKHA_SKSR_BUSY (0x00000010)
-#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16)
-#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24)
-
-/* Bit definitions and macros for MCF_SKHA_SKIR */
-#define MCF_SKHA_SKIR_IFO (0x00000001)
-#define MCF_SKHA_SKIR_OFU (0x00000002)
-#define MCF_SKHA_SKIR_NEIF (0x00000004)
-#define MCF_SKHA_SKIR_NEOF (0x00000008)
-#define MCF_SKHA_SKIR_IME (0x00000010)
-#define MCF_SKHA_SKIR_DSE (0x00000020)
-#define MCF_SKHA_SKIR_KSE (0x00000040)
-#define MCF_SKHA_SKIR_RMDP (0x00000080)
-#define MCF_SKHA_SKIR_ERE (0x00000100)
-#define MCF_SKHA_SKIR_KPE (0x00000200)
-#define MCF_SKHA_SKIR_KRE (0x00000400)
-
-/* Bit definitions and macros for MCF_SKHA_SKIMR */
-#define MCF_SKHA_SKIMR_IFO (0x00000001)
-#define MCF_SKHA_SKIMR_OFU (0x00000002)
-#define MCF_SKHA_SKIMR_NEIF (0x00000004)
-#define MCF_SKHA_SKIMR_NEOF (0x00000008)
-#define MCF_SKHA_SKIMR_IME (0x00000010)
-#define MCF_SKHA_SKIMR_DSE (0x00000020)
-#define MCF_SKHA_SKIMR_KSE (0x00000040)
-#define MCF_SKHA_SKIMR_RMDP (0x00000080)
-#define MCF_SKHA_SKIMR_ERE (0x00000100)
-#define MCF_SKHA_SKIMR_KPE (0x00000200)
-#define MCF_SKHA_SKIMR_KRE (0x00000400)
-
-/* Bit definitions and macros for MCF_SKHA_SKKSR */
-#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0)
-
-/********************************************************************/
-
-#endif /* __MCF523X_SKHA_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h
deleted file mode 100644
index b40dda0e6..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_sram.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_sram.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_SRAM_H__
-#define __MCF523X_SRAM_H__
-
-/*********************************************************************
-*
-* 64KByte System SRAM (SRAM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
-
-/* Bit definitions and macros for MCF_SRAM_RAMBAR */
-#define MCF_SRAM_RAMBAR_V (0x00000001)
-#define MCF_SRAM_RAMBAR_UD (0x00000002)
-#define MCF_SRAM_RAMBAR_UC (0x00000004)
-#define MCF_SRAM_RAMBAR_SD (0x00000008)
-#define MCF_SRAM_RAMBAR_SC (0x00000010)
-#define MCF_SRAM_RAMBAR_CI (0x00000020)
-#define MCF_SRAM_RAMBAR_WP (0x00000100)
-#define MCF_SRAM_RAMBAR_SPV (0x00000200)
-#define MCF_SRAM_RAMBAR_PRI2 (0x00000400)
-#define MCF_SRAM_RAMBAR_PRI1 (0x00000800)
-#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
-
-/********************************************************************/
-
-#endif /* __MCF523X_SRAM_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h
deleted file mode 100644
index e9db74c27..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_timer.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_timer.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_TIMER_H__
-#define __MCF523X_TIMER_H__
-
-/*********************************************************************
-*
-* DMA Timers (TIMER)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
-#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
-#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
-#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
-#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
-#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
-#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
-#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
-#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
-#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
-#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
-#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
-#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
-#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
-#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
-#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
-#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
-#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
-#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
-#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
-#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
-#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
-#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
-#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
-#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
-#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
-#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
-#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
-#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
-#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
-
-/* Bit definitions and macros for MCF_TIMER_DTMR */
-#define MCF_TIMER_DTMR_RST (0x0001)
-#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1)
-#define MCF_TIMER_DTMR_FRR (0x0008)
-#define MCF_TIMER_DTMR_ORRI (0x0010)
-#define MCF_TIMER_DTMR_OM (0x0020)
-#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6)
-#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8)
-#define MCF_TIMER_DTMR_CE_ANY (0x00C0)
-#define MCF_TIMER_DTMR_CE_FALL (0x0080)
-#define MCF_TIMER_DTMR_CE_RISE (0x0040)
-#define MCF_TIMER_DTMR_CE_NONE (0x0000)
-#define MCF_TIMER_DTMR_CLK_DTIN (0x0006)
-#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004)
-#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002)
-#define MCF_TIMER_DTMR_CLK_STOP (0x0000)
-
-/* Bit definitions and macros for MCF_TIMER_DTXMR */
-#define MCF_TIMER_DTXMR_MODE16 (0x01)
-#define MCF_TIMER_DTXMR_DMAEN (0x80)
-
-/* Bit definitions and macros for MCF_TIMER_DTER */
-#define MCF_TIMER_DTER_CAP (0x01)
-#define MCF_TIMER_DTER_REF (0x02)
-
-/********************************************************************/
-
-#endif /* __MCF523X_TIMER_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h
deleted file mode 100644
index 43a44a67f..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_uart.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_uart.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_UART_H__
-#define __MCF523X_UART_H__
-
-/*********************************************************************
-*
-* Universal Asynchronous Receiver Transmitter (UART)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
-#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
-#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
-#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
-#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
-#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
-#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
-#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
-#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
-#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
-#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
-#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
-#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
-#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
-#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
-#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
-#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
-#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
-#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
-#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
-#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
-#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
-#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
-#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
-#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
-#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
-#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
-#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
-#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
-#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
-#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
-#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
-#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
-#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
-#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
-#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
-#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
-#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
-#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
-#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
-#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
-#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
-#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
-#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
-#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
-#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
-#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
-#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
-#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
-#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
-#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
-#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
-#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
-#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
-#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
-#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
-#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
-#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
-#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
-#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
-
-/* Bit definitions and macros for MCF_UART_UMR */
-#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
-#define MCF_UART_UMR_PT (0x04)
-#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
-#define MCF_UART_UMR_ERR (0x20)
-#define MCF_UART_UMR_RXIRQ (0x40)
-#define MCF_UART_UMR_RXRTS (0x80)
-#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
-#define MCF_UART_UMR_TXCTS (0x10)
-#define MCF_UART_UMR_TXRTS (0x20)
-#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
-#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
-#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
-#define MCF_UART_UMR_PM_NONE (0x10)
-#define MCF_UART_UMR_PM_FORCE_HI (0x0C)
-#define MCF_UART_UMR_PM_FORCE_LO (0x08)
-#define MCF_UART_UMR_PM_ODD (0x04)
-#define MCF_UART_UMR_PM_EVEN (0x00)
-#define MCF_UART_UMR_BC_5 (0x00)
-#define MCF_UART_UMR_BC_6 (0x01)
-#define MCF_UART_UMR_BC_7 (0x02)
-#define MCF_UART_UMR_BC_8 (0x03)
-#define MCF_UART_UMR_CM_NORMAL (0x00)
-#define MCF_UART_UMR_CM_ECHO (0x40)
-#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
-#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
-#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
-#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
-#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
-
-/* Bit definitions and macros for MCF_UART_USR */
-#define MCF_UART_USR_RXRDY (0x01)
-#define MCF_UART_USR_FFULL (0x02)
-#define MCF_UART_USR_TXRDY (0x04)
-#define MCF_UART_USR_TXEMP (0x08)
-#define MCF_UART_USR_OE (0x10)
-#define MCF_UART_USR_PE (0x20)
-#define MCF_UART_USR_FE (0x40)
-#define MCF_UART_USR_RB (0x80)
-
-/* Bit definitions and macros for MCF_UART_UCSR */
-#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
-#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
-#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
-#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
-#define MCF_UART_UCSR_RCS_CTM (0xF0)
-#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
-#define MCF_UART_UCSR_TCS_CTM16 (0x0E)
-#define MCF_UART_UCSR_TCS_CTM (0x0F)
-
-/* Bit definitions and macros for MCF_UART_UCR */
-#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
-#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
-#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
-#define MCF_UART_UCR_NONE (0x00)
-#define MCF_UART_UCR_STOP_BREAK (0x70)
-#define MCF_UART_UCR_START_BREAK (0x60)
-#define MCF_UART_UCR_BKCHGINT (0x50)
-#define MCF_UART_UCR_RESET_ERROR (0x40)
-#define MCF_UART_UCR_RESET_TX (0x30)
-#define MCF_UART_UCR_RESET_RX (0x20)
-#define MCF_UART_UCR_RESET_MR (0x10)
-#define MCF_UART_UCR_TX_DISABLED (0x08)
-#define MCF_UART_UCR_TX_ENABLED (0x04)
-#define MCF_UART_UCR_RX_DISABLED (0x02)
-#define MCF_UART_UCR_RX_ENABLED (0x01)
-
-/* Bit definitions and macros for MCF_UART_UIPCR */
-#define MCF_UART_UIPCR_CTS (0x01)
-#define MCF_UART_UIPCR_COS (0x10)
-
-/* Bit definitions and macros for MCF_UART_UACR */
-#define MCF_UART_UACR_IEC (0x01)
-
-/* Bit definitions and macros for MCF_UART_UISR */
-#define MCF_UART_UISR_TXRDY (0x01)
-#define MCF_UART_UISR_RXRDY_FU (0x02)
-#define MCF_UART_UISR_DB (0x04)
-#define MCF_UART_UISR_RXFTO (0x08)
-#define MCF_UART_UISR_TXFIFO (0x10)
-#define MCF_UART_UISR_RXFIFO (0x20)
-#define MCF_UART_UISR_COS (0x80)
-
-/* Bit definitions and macros for MCF_UART_UIMR */
-#define MCF_UART_UIMR_TXRDY (0x01)
-#define MCF_UART_UIMR_RXRDY_FU (0x02)
-#define MCF_UART_UIMR_DB (0x04)
-#define MCF_UART_UIMR_COS (0x80)
-
-/* Bit definitions and macros for MCF_UART_UIP */
-#define MCF_UART_UIP_CTS (0x01)
-
-/* Bit definitions and macros for MCF_UART_UOP1 */
-#define MCF_UART_UOP1_RTS (0x01)
-
-/* Bit definitions and macros for MCF_UART_UOP0 */
-#define MCF_UART_UOP0_RTS (0x01)
-
-/********************************************************************/
-
-#endif /* __MCF523X_UART_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h b/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h
deleted file mode 100644
index 489486791..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf523x/mcf523x_wtm.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf523x_wtm.h
- * Purpose: Register and bit definitions for the MCF523X
- *
- * Notes:
- *
- */
-
-#ifndef __MCF523X_WTM_H__
-#define __MCF523X_WTM_H__
-
-/*********************************************************************
-*
-* Watchdog Timer Modules (WTM)
-*
-*********************************************************************/
-
-/* Register read/write macros */
-#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
-#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
-#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
-#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
-
-/* Bit definitions and macros for MCF_WTM_WCR */
-#define MCF_WTM_WCR_EN (0x0001)
-#define MCF_WTM_WCR_HALTED (0x0002)
-#define MCF_WTM_WCR_DOZE (0x0004)
-#define MCF_WTM_WCR_WAIT (0x0008)
-
-/* Bit definitions and macros for MCF_WTM_WMR */
-#define MCF_WTM_WMR_WM0 (0x0001)
-#define MCF_WTM_WMR_WM1 (0x0002)
-#define MCF_WTM_WMR_WM2 (0x0004)
-#define MCF_WTM_WMR_WM3 (0x0008)
-#define MCF_WTM_WMR_WM4 (0x0010)
-#define MCF_WTM_WMR_WM5 (0x0020)
-#define MCF_WTM_WMR_WM6 (0x0040)
-#define MCF_WTM_WMR_WM7 (0x0080)
-#define MCF_WTM_WMR_WM8 (0x0100)
-#define MCF_WTM_WMR_WM9 (0x0200)
-#define MCF_WTM_WMR_WM10 (0x0400)
-#define MCF_WTM_WMR_WM11 (0x0800)
-#define MCF_WTM_WMR_WM12 (0x1000)
-#define MCF_WTM_WMR_WM13 (0x2000)
-#define MCF_WTM_WMR_WM14 (0x4000)
-#define MCF_WTM_WMR_WM15 (0x8000)
-
-/* Bit definitions and macros for MCF_WTM_WCNTR */
-#define MCF_WTM_WCNTR_WC0 (0x0001)
-#define MCF_WTM_WCNTR_WC1 (0x0002)
-#define MCF_WTM_WCNTR_WC2 (0x0004)
-#define MCF_WTM_WCNTR_WC3 (0x0008)
-#define MCF_WTM_WCNTR_WC4 (0x0010)
-#define MCF_WTM_WCNTR_WC5 (0x0020)
-#define MCF_WTM_WCNTR_WC6 (0x0040)
-#define MCF_WTM_WCNTR_WC7 (0x0080)
-#define MCF_WTM_WCNTR_WC8 (0x0100)
-#define MCF_WTM_WCNTR_WC9 (0x0200)
-#define MCF_WTM_WCNTR_WC10 (0x0400)
-#define MCF_WTM_WCNTR_WC11 (0x0800)
-#define MCF_WTM_WCNTR_WC12 (0x1000)
-#define MCF_WTM_WCNTR_WC13 (0x2000)
-#define MCF_WTM_WCNTR_WC14 (0x4000)
-#define MCF_WTM_WCNTR_WC15 (0x8000)
-
-/* Bit definitions and macros for MCF_WTM_WSR */
-#define MCF_WTM_WSR_WS0 (0x0001)
-#define MCF_WTM_WSR_WS1 (0x0002)
-#define MCF_WTM_WSR_WS2 (0x0004)
-#define MCF_WTM_WSR_WS3 (0x0008)
-#define MCF_WTM_WSR_WS4 (0x0010)
-#define MCF_WTM_WSR_WS5 (0x0020)
-#define MCF_WTM_WSR_WS6 (0x0040)
-#define MCF_WTM_WSR_WS7 (0x0080)
-#define MCF_WTM_WSR_WS8 (0x0100)
-#define MCF_WTM_WSR_WS9 (0x0200)
-#define MCF_WTM_WSR_WS10 (0x0400)
-#define MCF_WTM_WSR_WS11 (0x0800)
-#define MCF_WTM_WSR_WS12 (0x1000)
-#define MCF_WTM_WSR_WS13 (0x2000)
-#define MCF_WTM_WSR_WS14 (0x4000)
-#define MCF_WTM_WSR_WS15 (0x8000)
-
-/********************************************************************/
-
-#endif /* __MCF523X_WTM_H__ */
diff --git a/Demo/MCF5235_GCC/include/arch/mcf5xxx.h b/Demo/MCF5235_GCC/include/arch/mcf5xxx.h
deleted file mode 100644
index 692d690e1..000000000
--- a/Demo/MCF5235_GCC/include/arch/mcf5xxx.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * These files are taken from the MCF523X source code example package
- * which is available on the Freescale website. Freescale explicitly
- * grants the redistribution and modification of these source files.
- * The complete licensing information is available in the file
- * LICENSE_FREESCALE.TXT.
- *
- * File: mcf5xxx.h
- * Purpose: Definitions common to all ColdFire processors
- *
- * Notes:
- */
-
-#ifndef _CPU_MCF5XXX_H
-#define _CPU_MCF5XXX_H
-
-/***********************************************************************/
-/*
- * Misc. Defines
- */
-
-#ifdef FALSE
-#undef FALSE
-#endif
-#define FALSE (0)
-
-#ifdef TRUE
-#undef TRUE
-#endif
-#define TRUE (1)
-
-#ifdef NULL
-#undef NULL
-#endif
-#define NULL (0)
-
-/***********************************************************************/
-/*
- * The basic data types
- */
-
-typedef unsigned char uint8; /* 8 bits */
-typedef unsigned short int uint16; /* 16 bits */
-typedef unsigned long int uint32; /* 32 bits */
-
-typedef signed char int8; /* 8 bits */
-typedef signed short int int16; /* 16 bits */
-typedef signed long int int32; /* 32 bits */
-
-typedef volatile uint8 vuint8; /* 8 bits */
-typedef volatile uint16 vuint16; /* 16 bits */
-typedef volatile uint32 vuint32; /* 32 bits */
-
-/***********************************************************************/
-/*
- * Common M68K & ColdFire definitions
- */
-
-#define ADDRESS uint32
-#define INSTRUCTION uint16
-#define ILLEGAL 0x4AFC
-#define CPU_WORD_SIZE 16
-
-#define MCF5XXX_SR_T (0x8000)
-#define MCF5XXX_SR_S (0x2000)
-#define MCF5XXX_SR_M (0x1000)
-#define MCF5XXX_SR_IPL (0x0700)
-#define MCF5XXX_SR_IPL_0 (0x0000)
-#define MCF5XXX_SR_IPL_1 (0x0100)
-#define MCF5XXX_SR_IPL_2 (0x0200)
-#define MCF5XXX_SR_IPL_3 (0x0300)
-#define MCF5XXX_SR_IPL_4 (0x0400)
-#define MCF5XXX_SR_IPL_5 (0x0500)
-#define MCF5XXX_SR_IPL_6 (0x0600)
-#define MCF5XXX_SR_IPL_7 (0x0700)
-#define MCF5XXX_SR_X (0x0010)
-#define MCF5XXX_SR_N (0x0008)
-#define MCF5XXX_SR_Z (0x0004)
-#define MCF5XXX_SR_V (0x0002)
-#define MCF5XXX_SR_C (0x0001)
-
-#define MCF5XXX_CACR_CENB (0x80000000)
-#define MCF5XXX_CACR_CPDI (0x10000000)
-#define MCF5XXX_CACR_CPD (0x10000000)
-#define MCF5XXX_CACR_CFRZ (0x08000000)
-#define MCF5XXX_CACR_CINV (0x01000000)
-#define MCF5XXX_CACR_DIDI (0x00800000)
-#define MCF5XXX_CACR_DISD (0x00400000)
-#define MCF5XXX_CACR_INVI (0x00200000)
-#define MCF5XXX_CACR_INVD (0x00100000)
-#define MCF5XXX_CACR_CEIB (0x00000400)
-#define MCF5XXX_CACR_DCM_WR (0x00000000)
-#define MCF5XXX_CACR_DCM_CB (0x00000100)
-#define MCF5XXX_CACR_DCM_IP (0x00000200)
-#define MCF5XXX_CACR_DCM (0x00000200)
-#define MCF5XXX_CACR_DCM_II (0x00000300)
-#define MCF5XXX_CACR_DBWE (0x00000100)
-#define MCF5XXX_CACR_DWP (0x00000020)
-#define MCF5XXX_CACR_EUST (0x00000010)
-#define MCF5XXX_CACR_CLNF_00 (0x00000000)
-#define MCF5XXX_CACR_CLNF_01 (0x00000002)
-#define MCF5XXX_CACR_CLNF_10 (0x00000004)
-#define MCF5XXX_CACR_CLNF_11 (0x00000006)
-
-#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
-#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
-#define MCF5XXX_ACR_EN (0x00008000)
-#define MCF5XXX_ACR_SM_USER (0x00000000)
-#define MCF5XXX_ACR_SM_SUPER (0x00002000)
-#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
-#define MCF5XXX_ACR_ENIB (0x00000080)
-#define MCF5XXX_ACR_CM (0x00000040)
-#define MCF5XXX_ACR_DCM_WR (0x00000000)
-#define MCF5XXX_ACR_DCM_CB (0x00000020)
-#define MCF5XXX_ACR_DCM_IP (0x00000040)
-#define MCF5XXX_ACR_DCM_II (0x00000060)
-#define MCF5XXX_ACR_CM (0x00000040)
-#define MCF5XXX_ACR_BWE (0x00000020)
-#define MCF5XXX_ACR_WP (0x00000004)
-
-#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
-#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
-#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
-#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
-#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
-#define MCF5XXX_RAMBAR_WP (0x00000100)
-#define MCF5XXX_RAMBAR_CI (0x00000020)
-#define MCF5XXX_RAMBAR_SC (0x00000010)
-#define MCF5XXX_RAMBAR_SD (0x00000008)
-#define MCF5XXX_RAMBAR_UC (0x00000004)
-#define MCF5XXX_RAMBAR_UD (0x00000002)
-#define MCF5XXX_RAMBAR_V (0x00000001)
-
-/***********************************************************************/
-/*
- * The ColdFire family of processors has a simplified exception stack
- * frame that looks like the following:
- *
- * 3322222222221111 111111
- * 1098765432109876 5432109876543210
- * 8 +----------------+----------------+
- * | Program Counter |
- * 4 +----------------+----------------+
- * |FS/Fmt/Vector/FS| SR |
- * SP --> 0 +----------------+----------------+
- *
- * The stack self-aligns to a 4-byte boundary at an exception, with
- * the FS/Fmt/Vector/FS field indicating the size of the adjustment
- * (SP += 0,1,2,3 bytes).
- */
-
-#define MCF5XXX_RD_SF_FORMAT(PTR) \
- ((*((uint16 *)(PTR)) >> 12) & 0x00FF)
-
-#define MCF5XXX_RD_SF_VECTOR(PTR) \
- ((*((uint16 *)(PTR)) >> 2) & 0x00FF)
-
-#define MCF5XXX_RD_SF_FS(PTR) \
- ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
-
-#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
-#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
-
-/********************************************************************/
-/*
- * Functions provided by mcf5xxx.s
- */
-
-int asm_set_ipl (uint32);
-void mcf5xxx_wr_cacr (uint32);
-void mcf5xxx_wr_acr0 (uint32);
-void mcf5xxx_wr_acr1 (uint32);
-void mcf5xxx_wr_acr2 (uint32);
-void mcf5xxx_wr_acr3 (uint32);
-void mcf5xxx_wr_other_a7 (uint32);
-void mcf5xxx_wr_other_sp (uint32);
-void mcf5xxx_wr_vbr (uint32);
-void mcf5xxx_wr_macsr (uint32);
-void mcf5xxx_wr_mask (uint32);
-void mcf5xxx_wr_acc0 (uint32);
-void mcf5xxx_wr_accext01 (uint32);
-void mcf5xxx_wr_accext23 (uint32);
-void mcf5xxx_wr_acc1 (uint32);
-void mcf5xxx_wr_acc2 (uint32);
-void mcf5xxx_wr_acc3 (uint32);
-void mcf5xxx_wr_sr (uint32);
-void mcf5xxx_wr_rambar0 (uint32);
-void mcf5xxx_wr_rambar1 (uint32);
-void mcf5xxx_wr_mbar (uint32);
-void mcf5xxx_wr_mbar0 (uint32);
-void mcf5xxx_wr_mbar1 (uint32);
-
-/********************************************************************/
-
-#endif /* _CPU_MCF5XXX_H */
-
diff --git a/Demo/MCF5235_GCC/m5235-ram.ld b/Demo/MCF5235_GCC/m5235-ram.ld
deleted file mode 100644
index b26a1dbd9..000000000
--- a/Demo/MCF5235_GCC/m5235-ram.ld
+++ /dev/null
@@ -1,119 +0,0 @@
-STARTUP(system/crt0.o)
-INPUT(system/vector.o)
-OUTPUT_ARCH(m68k)
-SEARCH_DIR(.)
-GROUP(-lc -lgcc)
-
-__DYNAMIC = 0;
-
-MEMORY
-{
- sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
- sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
- ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
- flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
-}
-
-PROVIDE (__stack = 0x2000FFFC);
-
-SECTIONS
-{
- .sdram : {} > sdram
- .ipsbar : {} > ipsbar
- .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
- .flash : {} > flash
-
- .text :
- {
- __text_start = . ;
- *(.vector_rom)
- . = ALIGN (0x100);
- *(.text)
- . = ALIGN (16);
-
- *(.eh_frame)
- . = ALIGN (16);
-
- *(.gnu.linkonce.t.*)
-
- . = ALIGN(0x4);
- __CTOR_LIST__ = .;
- ___CTOR_LIST__ = .;
- LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
- *(.ctors)
- LONG(0)
- __CTOR_END__ = .;
- __DTOR_LIST__ = .;
- ___DTOR_LIST__ = .;
- LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
- *(.dtors)
- LONG(0)
- __DTOR_END__ = .;
- *(.rodata)
- *(.rodata.*)
- *(.gcc_except_table)
-
- . = ALIGN(0x2);
- __INIT_SECTION__ = . ;
- LONG (0x4e560000) /* linkw %fp,#0 */
- *(.init)
- SHORT (0x4e5e) /* unlk %fp */
- SHORT (0x4e75) /* rts */
-
- __FINI_SECTION__ = . ;
- LONG (0x4e560000) /* linkw %fp,#0 */
- *(.fini)
- SHORT (0x4e5e) /* unlk %fp */
- SHORT (0x4e75) /* rts */
-
- *(.lit)
- . = ALIGN(16);
- _etext = .;
- etext = .;
- } > sdram
-
- .data :
- {
- copy_start = .;
- *(.shdata)
- *(.data)
- *(.gnu.linkonce.d.*)
- . = ALIGN (16);
- _edata = .;
- copy_end = .;
- } > sdram
- __data_load_start = LOADADDR(.data);
- __data_load_end = __data_load_start + SIZEOF(.data);
-
- .bss :
- {
- . = ALIGN(0x4);
- __bss_start = . ;
- *(.shbss)
- *(.bss)
- *(COMMON)
- _end = ALIGN (0x8);
- __end = _end;
- } > sdram
-
- .stab 0 (NOLOAD) :
- {
- *(.stab)
- }
-
- .stabstr 0 (NOLOAD) :
- {
- *(.stabstr)
- }
-}
-
-__IPSBAR = ADDR(.ipsbar);
-
-__SDRAM = ADDR(.sdram);
-__SDRAM_SIZE = SIZEOF(.sdram);
-
-__SRAM = ADDR(.sram);
-__SRAM_SIZE = SIZEOF(.sram);
-
-__FLASH = ADDR(.flash);
-__FLASH_SIZE = SIZEOF(.flash);
diff --git a/Demo/MCF5235_GCC/m5235-rom.ld b/Demo/MCF5235_GCC/m5235-rom.ld
deleted file mode 100644
index b26a1dbd9..000000000
--- a/Demo/MCF5235_GCC/m5235-rom.ld
+++ /dev/null
@@ -1,119 +0,0 @@
-STARTUP(system/crt0.o)
-INPUT(system/vector.o)
-OUTPUT_ARCH(m68k)
-SEARCH_DIR(.)
-GROUP(-lc -lgcc)
-
-__DYNAMIC = 0;
-
-MEMORY
-{
- sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
- sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
- ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
- flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
-}
-
-PROVIDE (__stack = 0x2000FFFC);
-
-SECTIONS
-{
- .sdram : {} > sdram
- .ipsbar : {} > ipsbar
- .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
- .flash : {} > flash
-
- .text :
- {
- __text_start = . ;
- *(.vector_rom)
- . = ALIGN (0x100);
- *(.text)
- . = ALIGN (16);
-
- *(.eh_frame)
- . = ALIGN (16);
-
- *(.gnu.linkonce.t.*)
-
- . = ALIGN(0x4);
- __CTOR_LIST__ = .;
- ___CTOR_LIST__ = .;
- LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
- *(.ctors)
- LONG(0)
- __CTOR_END__ = .;
- __DTOR_LIST__ = .;
- ___DTOR_LIST__ = .;
- LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
- *(.dtors)
- LONG(0)
- __DTOR_END__ = .;
- *(.rodata)
- *(.rodata.*)
- *(.gcc_except_table)
-
- . = ALIGN(0x2);
- __INIT_SECTION__ = . ;
- LONG (0x4e560000) /* linkw %fp,#0 */
- *(.init)
- SHORT (0x4e5e) /* unlk %fp */
- SHORT (0x4e75) /* rts */
-
- __FINI_SECTION__ = . ;
- LONG (0x4e560000) /* linkw %fp,#0 */
- *(.fini)
- SHORT (0x4e5e) /* unlk %fp */
- SHORT (0x4e75) /* rts */
-
- *(.lit)
- . = ALIGN(16);
- _etext = .;
- etext = .;
- } > sdram
-
- .data :
- {
- copy_start = .;
- *(.shdata)
- *(.data)
- *(.gnu.linkonce.d.*)
- . = ALIGN (16);
- _edata = .;
- copy_end = .;
- } > sdram
- __data_load_start = LOADADDR(.data);
- __data_load_end = __data_load_start + SIZEOF(.data);
-
- .bss :
- {
- . = ALIGN(0x4);
- __bss_start = . ;
- *(.shbss)
- *(.bss)
- *(COMMON)
- _end = ALIGN (0x8);
- __end = _end;
- } > sdram
-
- .stab 0 (NOLOAD) :
- {
- *(.stab)
- }
-
- .stabstr 0 (NOLOAD) :
- {
- *(.stabstr)
- }
-}
-
-__IPSBAR = ADDR(.ipsbar);
-
-__SDRAM = ADDR(.sdram);
-__SDRAM_SIZE = SIZEOF(.sdram);
-
-__SRAM = ADDR(.sram);
-__SRAM_SIZE = SIZEOF(.sram);
-
-__FLASH = ADDR(.flash);
-__FLASH_SIZE = SIZEOF(.flash);
diff --git a/Demo/MCF5235_GCC/m5235.gdb b/Demo/MCF5235_GCC/m5235.gdb
deleted file mode 100644
index 545fbea31..000000000
--- a/Demo/MCF5235_GCC/m5235.gdb
+++ /dev/null
@@ -1,134 +0,0 @@
-set $IPSBAR = 0x40000000
-
-set $DCR = $IPSBAR + 0x000040
-set $DACR0 = $IPSBAR + 0x000048
-set $DMR0 = $IPSBAR + 0x00004C
-
-set $CSAR0 = $IPSBAR + 0x000080
-set $CSMR0 = $IPSBAR + 0x000084
-set $CSCR0 = $IPSBAR + 0x00008A
-
-set $PAR_SDRAM = $IPSBAR + 0x100046
-set $PAR_AD = $IPSBAR + 0x100040
-
-set $WCR = $IPSBAR + 0x140000
-
-define delay
- set $delay = 0
- while ($delay < 20000)
- set $delay += 1
- end
-end
-
-define delay_memsync
- set $delay = 0
- while ($delay < 10000)
- set $delay += 1
- end
-end
-
-define setup-cs
- # 2MB FLASH on CS0 at 0x80000000
- set *(unsigned short *)$CSAR0 = 0x00008000
- set *(unsigned long *)$CSMR0 = 0x001F0101
- set *(unsigned short *)$CSCR0 = 0x00001980
-end
-
-define setup-sdram
- # Set PAR_SDRAM to allow SDRAM signals to be enable
- set *(unsigned char *)$PAR_SDRAM = 0x3F
- # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit
- set *(unsigned char *)$PAR_AD = 0xE1
-
- # SDRAM
- set *(unsigned short *)$DCR = 0x0446
- set *(unsigned long *)$DACR0 = 0x00001300
- set *(unsigned long *)$DMR0 = 0x00FC0001
-
- # Set IP in DACR and init precharge.
- set *(unsigned long *)$DACR0 |= 0x00000008
- set *(0x00000000) = 0xAA55AA55
- delay
-
- # Set RE in DACR
- set *(unsigned long *)$DACR0 |= 0x00008000
- # Issue IMRS
- set *(unsigned long *)$DACR0 |= 0x00000040
- set *(0x00000400) = 0xAA55AA55
- delay
-end
-
-define setup-other
- # Turn Off WCR
- set *(unsigned char *)$WCR = 0x00
-end
-
-define setup-and-load
- bdm-reset
-
- # Set VBR to the vector table.
- set $vbr = 0x00000000
- # Set internal SRAM to start at 0x20000000
- set $rambar = 0x20000001
-
- setup-other
- setup-cs
- setup-sdram
-end
-
-define debug-sramtest
- set $srambase = 0x20000000
- set $sramsize = 0x00010000
- set $j = 0
- printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize)
- set $i = $srambase
- while $i < ($srambase + $sramsize)
- set *(unsigned long *)($i) = 0xAA55AA55
- delay_memsync
- if 0xAA55AA55 != *(unsigned long *)$i
- printf " 0x%08X = FAIL\n", $i
- else
- printf " 0x%08X = OK", $i
- if $j % 4 == 3
- printf "\n"
- end
- set $j = $j + 1
- end
- set $i = $i + 0x400
- end
-en
-
-define debug-ramtest
- set $sdrambase = 0x00000000
- set $sdramsize = 0x01000000
- set $j = 0
- printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize)
- set $i = $sdrambase
- while $i < ($sdrambase + $sdramsize)
- set *(unsigned long *)($i) = 0xAA55AA55
- delay_memsync
- if 0xAA55AA55 != *(unsigned long *)$i
- printf " 0x%08X = FAIL\n", $i
- else
- printf " 0x%08X = OK", $i
- if $j % 4 == 3
- printf "\n"
- end
- set $j = $j + 1
- end
- set $i = $i + 0x10000
- end
- printf "\n"
-end
-
-define execute
- set $pc = *(long *)0x00000004
- tbreak main
- tk gdbtk_update
-end
-
-define debug-printexception
- printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F
- printf "old pc: 0x%08x", *(unsigned long *)($sp + 4)
- printf "old sr: 0x%02x", *(unsigned short *)($sp + 2)
-end
diff --git a/Demo/MCF5235_GCC/readme.md b/Demo/MCF5235_GCC/readme.md
new file mode 100644
index 000000000..b0c6b32ea
--- /dev/null
+++ b/Demo/MCF5235_GCC/readme.md
@@ -0,0 +1,2 @@
+The MCF5235 is deprecated in FreeRTOS Kernel V10.4.4.
+The last version of FreeRTOS that includes MCF5235 is 202104.
diff --git a/Demo/MCF5235_GCC/system/crt0.S b/Demo/MCF5235_GCC/system/crt0.S
deleted file mode 100644
index 6fc8a72a0..000000000
--- a/Demo/MCF5235_GCC/system/crt0.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
- .title "crt0.S"
-
- .extern main
- .extern __stack
- .extern __bss_start
- .extern __text_start
- .extern init_main
-
- .equ MCF5XXX_RAMBAR_SPV, 0x00000200
- .equ MCF5XXX_RAMBAR_V, 0x00000001
- .global start
-
- .align 4
-debug:
- .word 0x2C80 /* write to CSR */
- .word 0x0010
- .word 0x0400
- .word 0x0000
-
-start:
- /* disable all interrupts on startup. */
- move.w #0x2700, sr
-
- /* prepare internal SRAM. */
- move.l #__SRAM, d0
- ori.l #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0
- movec d0, rambar
-
- /* prepare stack and frame pointer. */
- move.l #__stack, sp
- link a6, #-8
-
- /* initialize hardware. */
- jsr init_main
-
- /* zero out the bss section. */
- move.l #__bss_start, d1
- move.l #_end, d0
- cmp.l d0, d1
- jbeq 3f
- move.l d1, a0
- sub.l d1, d0
- subq.l #1, d0
-2:
- clr.b (a0)+
- subq.l #1, d0
- jbpl 2b
-3:
-
- /* Relocate the data section. */
- move.l #__data_load_start, %a0 /* .data in ROM */
- move.l #copy_start, %a1 /* .data in RAM */
-
- /* Test if the two sections overlap. This is the case when we are working
- * with the debugger and the debugger loads the .data section.
- */
- cmpa.l %a0, %a1
- beq 2f
-1:
- /* Have we already copied everything. */
- cmpa.l #__data_load_end, %a0
- beq 2f
- move.b (%a0)+, (%a1)+
- bra 1b
-
-2:
-
- /* C library */
- move.l #__FINI_SECTION__, -(%sp)
- jsr atexit
- jsr __INIT_SECTION__
-
- /* call main(int argc, char *argv[] */
- move.l #0, -(sp)
- move.l #0, -(sp)
- move.l #0, -(sp)
- jsr main
- lea (sp, 12), %sp
-
- /* stop on exit from main. */
-1:
- halt
-
diff --git a/Demo/MCF5235_GCC/system/init.c b/Demo/MCF5235_GCC/system/init.c
deleted file mode 100644
index 382de360d..000000000
--- a/Demo/MCF5235_GCC/system/init.c
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-
-/* Function prototypes */
-void init_main( void );
-static void disable_interrupts( void );
-static void disable_watchdog_timer( void );
-static void disable_cache( void );
-static void init_ipsbar( void );
-static void init_basics( void );
-static void init_clock_config( void );
-static void init_chip_selects( void );
-static void init_bus_config( void );
-static void init_cache( void );
-static void init_eport( void );
-static void init_flexcan( void );
-static void init_power_management( void );
-static void init_dma_timers( void );
-static void init_interrupt_timers( void );
-static void init_watchdog_timers( void );
-static void init_pin_assignments( void );
-static void init_sdram_controller( void );
-static void init_interrupt_controller( void );
-
-
-/*********************************************************************
-* init_main - Main entry point for initialisation code *
-**********************************************************************/
-void
-init_main( void )
-{
-
- /* Initialise base address of peripherals, VBR, etc */
- init_ipsbar( );
- init_basics( );
- init_clock_config( );
-
- /* Disable interrupts, watchdog timer, cache */
- disable_interrupts( );
- disable_watchdog_timer( );
- disable_cache( );
-
- /* Initialise individual modules */
- init_chip_selects( );
- init_bus_config( );
- init_cache( );
- init_eport( );
- init_flexcan( );
- init_power_management( );
- init_dma_timers( );
- init_interrupt_timers( );
- init_watchdog_timers( );
- init_pin_assignments( );
- init_sdram_controller( );
-
- /* Initialise interrupt controller */
- init_interrupt_controller( );
-}
-
-/*********************************************************************
-* disable_interrupts - Disable all interrupt sources *
-**********************************************************************/
-static void
-disable_interrupts( void )
-{
- vuint8 *p;
- int i;
-
-
- /* Set ICR008-ICR063 to 0x0 */
- p = ( vuint8 * ) & MCF_INTC0_ICR8;
- for( i = 8; i <= 63; i++ )
- *p++ = 0x0;
-
- /* Set ICR108-ICR163 to 0x0 */
- p = ( vuint8 * ) & MCF_INTC1_ICR8;
- for( i = 108; i <= 163; i++ )
- *p++ = 0x0;
-}
-
-
-/*********************************************************************
-* disable_watchdog_timer - Disable system watchdog timer *
-**********************************************************************/
-static void
-disable_watchdog_timer( void )
-{
-
- /* Disable Core Watchdog Timer */
- MCF_SCM_CWCR = 0;
-}
-
-/*********************************************************************
-* disable_cache - Disable and invalidate cache *
-**********************************************************************/
-static void
-disable_cache( void )
-{
- asm ( "move.l #0x01000000, %d0" );
- asm ( "movec %d0, %CACR" );
-}
-
-/*********************************************************************
-* init_basics - Configuration Information & VBR *
-**********************************************************************/
-static void
-init_basics( void )
-{
- int i;
- extern uint32 __RAMVEC[];
- extern uint32 __ROMVEC[];
-
- /* Transfer size not driven on SIZ[1:0] pins during external cycles
- Processor Status (PST) and Debug Data (DDATA) functions disabled
- Bus monitor disabled
- Output pads configured for full strength
- */
- MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
-
- /* Set up RAM vectors */
- for( i = 0; i < 256; i++ )
-
- {
- __RAMVEC[i] = __ROMVEC[i];
- }
- asm( "move.l %0,%%d0": :"i"( __RAMVEC ) );
- asm( "movec %d0,%vbr" );
-}
-
-
-/*********************************************************************
-* init_clock_config - Clock Module *
-**********************************************************************/
-static void
-init_clock_config( void )
-{
- /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
- MFD = 0, RFD = 1
- Bus clock frequency = 25.00 MHz
- Processor clock frequency = 2 x bus clock = 50.00 MHz
- Frequency Modulation disabled
- Loss of clock detection disabled
- Reset/Interrupt on loss of lock disabled
- */
- MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */
- while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
- ;
- MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */
- while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
- ;
-}
-
-
-/*********************************************************************
-* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) *
-**********************************************************************/
-static void
-init_ipsbar( void )
-{
- extern int __SRAM;
-
- /* Base address of internal peripherals (IPSBAR) = 0x40000000
-
- Note: Processor powers up with IPS base address = 0x40000000
- Write to IPS base + 0x00000000 to set new value
- */
- *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
-
- /* Configure RAMBAR in SCM module and allow dual-ported access. */
- MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
-}
-
-/*********************************************************************
-* init_chip_selects - Chip Select Module *
-**********************************************************************/
-static void
-init_chip_selects( void )
-{
- extern void __FLASH;
- uint32 FLASH_ADDR = (uint32)&__FLASH;
-
- /* Chip Select 0 - External Flash */
- MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
- MCF_CS_CSCR0 = ( 0
- | MCF_CS_CSCR_IWS( 6 )
- | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
- MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
-
- /* Chip Select 1 disabled (CSMR1[V] = 0) */
- MCF_CS_CSAR1 = 0;
- MCF_CS_CSMR1 = 0;
- MCF_CS_CSCR1 = 0;
-
- /* Chip Select 2 disabled (CSMR2[V] = 0) */
- MCF_CS_CSAR2 = 0;
- MCF_CS_CSMR2 = 0;
- MCF_CS_CSCR2 = 0;
-
- /* Chip Select 3 disabled (CSMR3[V] = 0) */
- MCF_CS_CSAR3 = 0;
- MCF_CS_CSMR3 = 0;
- MCF_CS_CSCR3 = 0;
-
- /* Chip Select 4 disabled (CSMR4[V] = 0) */
- MCF_CS_CSAR4 = 0;
- MCF_CS_CSMR4 = 0;
- MCF_CS_CSCR4 = 0;
-
- /* Chip Select 5 disabled (CSMR5[V] = 0) */
- MCF_CS_CSAR5 = 0;
- MCF_CS_CSMR5 = 0;
- MCF_CS_CSCR5 = 0;
-
- /* Chip Select 6 disabled (CSMR6[V] = 0) */
- MCF_CS_CSAR6 = 0;
- MCF_CS_CSMR6 = 0;
- MCF_CS_CSCR6 = 0;
-
- /* Chip Select 7 disabled (CSMR7[V] = 0) */
- MCF_CS_CSAR7 = 0;
- MCF_CS_CSMR7 = 0;
- MCF_CS_CSCR7 = 0;
-}
-
-/*********************************************************************
-* init_bus_config - Internal Bus Arbitration *
-**********************************************************************/
-static void
-init_bus_config( void )
-{
-
- /* Use round robin arbitration scheme
- Assigned priorities (highest first):
- Ethernet
- DMA Controller
- ColdFire Core
- DMA bandwidth control disabled
- Park on last active bus master
- */
- MCF_SCM_MPARK =
- MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
- MCF_SCM_MPARK_M1_PRTY( 0x1 );
-}
-
-/*********************************************************************
-* init_cache - Instruction/Data Cache *
-**********************************************************************/
-static void
-init_cache( void )
-{
- /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
- ACR0: Don't cache accesses to 16 MB memory region at address $20000000
- ACR1: Don't cache accesses to 1 GB memory region at address $40000000
- CACR: Cache accesses to the rest of memory
- */
- asm("move.l #0x80000000,%d0");
- asm("movec %d0,%CACR");
- asm("move.l #0x2000c040,%d0");
- asm("movec %d0,%ACR0");
- asm("move.l #0x403fc040,%d0");
- asm("movec %d0,%ACR1");
-
- /* Instruction/Data cache disabled. */
- //asm( "move.l #0x00000000, %d0" );
- //asm( "movec %d0,%cacr" );
-}
-
-/*********************************************************************
-* init_eport - Edge Port Module (EPORT) *
-**********************************************************************/
-static void
-init_eport( void )
-{
-
- /* Pins 1-7 configured as GPIO inputs */
- MCF_EPORT_EPPAR = 0;
- MCF_EPORT_EPDDR = 0;
- MCF_EPORT_EPIER = 0;
-}
-
-/*********************************************************************
-* init_flexcan - FlexCAN Module *
-**********************************************************************/
-static void
-init_flexcan( void )
-{
-
- /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
- MCF_CAN_IMASK0 = 0;
- MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
- MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
- MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
- MCF_CAN_CANCTRL0 = 0;
- MCF_CAN_CANMCR0 =
- MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
- MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
-
- /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
- MCF_CAN_IMASK1 = 0;
- MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
- MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
- MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
- MCF_CAN_CANCTRL1 = 0;
- MCF_CAN_CANMCR1 =
- MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
- MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
-}
-
-/*********************************************************************
-* init_power_management - Power Management *
-**********************************************************************/
-static void
-init_power_management( void )
-{
-
- /* On executing STOP instruction, processor enters RUN mode
- Mode is exited when an interrupt of level 1 or higher is received
- */
- MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
- MCF_CCM_LPCR = 0;
-}
-
-/*********************************************************************
-* init_sdram_controller - SDRAM Controller *
-**********************************************************************/
-static void
-init_sdram_controller( void )
-{
- extern void __SDRAM;
- uint32 SDRAM_ADDR = (uint32)&__SDRAM;
- int i;
-
-
- /*
- * Check to see if the SDRAM has already been initialized
- * by a run control tool
- */
- if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
- {
- /* Initialize DRAM Control Register: DCR */
- MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
- MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
-
- /* Initialize DACR0 */
- MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
- MCF_SDRAMC_DACR0_CASL( 1 ) |
- MCF_SDRAMC_DACR0_CBM( 3 ) |
- MCF_SDRAMC_DACR0_PS( 0 ) );
-
- /* Initialize DMR0 */
- MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
-
- /* Set IP (bit 3) in DACR */
- MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
-
- /* Wait 30ns to allow banks to precharge */
- for( i = 0; i < 5; i++ )
- {
- asm volatile ( " nop" );
- }
- /* Write to this block to initiate precharge */
- *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
-
- /* Set RE (bit 15) in DACR */
- MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
-
- /* Wait for at least 8 auto refresh cycles to occur */
- for( i = 0; i < 2000; i++ )
- {
- asm volatile ( "nop" );
- }
- /* Finish the configuration by issuing the IMRS. */
- MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
-
- /* Write to the SDRAM Mode Register */
- *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
- }
-}
-
-/*********************************************************************
-* init_dma_timers - DMA Timer Modules *
-**********************************************************************/
-static void
-init_dma_timers( void )
-{
-
- /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
- MCF_TIMER_DTMR0 = 0;
- MCF_TIMER_DTXMR0 = 0;
- MCF_TIMER_DTRR0 = 0xffffffff;
-
- /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
- MCF_TIMER_DTMR1 = 0;
- MCF_TIMER_DTXMR1 = 0;
- MCF_TIMER_DTRR1 = 0xffffffff;
-
- /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
- MCF_TIMER_DTMR2 = 0;
- MCF_TIMER_DTXMR2 = 0;
- MCF_TIMER_DTRR2 = 0xffffffff;
-
- /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
- MCF_TIMER_DTMR3 = 0;
- MCF_TIMER_DTXMR3 = 0;
- MCF_TIMER_DTRR3 = 0xffffffff;
-}
-
-/**********************************************************************
-* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules *
-***********************************************************************/
-static void
-init_interrupt_timers( void )
-{
-
- /* PIT0 disabled (PCSR0[EN]=0) */
- MCF_PIT_PCSR0 = 0;
-
- /* PIT1 disabled (PCSR1[EN]=0) */
- MCF_PIT_PCSR1 = 0;
-
- /* PIT2 disabled (PCSR2[EN]=0) */
- MCF_PIT_PCSR2 = 0;
-
- /* PIT3 disabled (PCSR3[EN]=0) */
- MCF_PIT_PCSR3 = 0;
-}
-
-/*********************************************************************
-* init_watchdog_timers - Watchdog Timer Modules *
-**********************************************************************/
-static void
-init_watchdog_timers( void )
-{
-
- /* Watchdog Timer disabled (WCR[EN]=0)
- NOTE: WCR and WMR cannot be written again until after the
- processor is reset.
- */
- MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
- MCF_WTM_WMR = 0xffff;
-
- /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
- MCF_SCM_CWCR = 0;
-}
-
-/*********************************************************************
-* init_interrupt_controller - Interrupt Controller *
-**********************************************************************/
-static void
-init_interrupt_controller( void )
-{
-
- /* Configured interrupt sources in order of priority...
- Level 7: External interrupt /IRQ7, (initially masked)
- Level 6: External interrupt /IRQ6, (initially masked)
- Level 5: External interrupt /IRQ5, (initially masked)
- Level 4: External interrupt /IRQ4, (initially masked)
- Level 3: External interrupt /IRQ3, (initially masked)
- Level 2: External interrupt /IRQ2, (initially masked)
- Level 1: External interrupt /IRQ1, (initially masked)
- */
- MCF_INTC0_ICR1 = 0;
- MCF_INTC0_ICR2 = 0;
- MCF_INTC0_ICR3 = 0;
- MCF_INTC0_ICR4 = 0;
- MCF_INTC0_ICR5 = 0;
- MCF_INTC0_ICR6 = 0;
- MCF_INTC0_ICR7 = 0;
- MCF_INTC0_ICR8 = 0;
- MCF_INTC0_ICR9 = 0;
- MCF_INTC0_ICR10 = 0;
- MCF_INTC0_ICR11 = 0;
- MCF_INTC0_ICR12 = 0;
- MCF_INTC0_ICR13 = 0;
- MCF_INTC0_ICR14 = 0;
- MCF_INTC0_ICR15 = 0;
- MCF_INTC0_ICR17 = 0;
- MCF_INTC0_ICR18 = 0;
- MCF_INTC0_ICR19 = 0;
- MCF_INTC0_ICR20 = 0;
- MCF_INTC0_ICR21 = 0;
- MCF_INTC0_ICR22 = 0;
- MCF_INTC0_ICR23 = 0;
- MCF_INTC0_ICR24 = 0;
- MCF_INTC0_ICR25 = 0;
- MCF_INTC0_ICR26 = 0;
- MCF_INTC0_ICR27 = 0;
- MCF_INTC0_ICR28 = 0;
- MCF_INTC0_ICR29 = 0;
- MCF_INTC0_ICR30 = 0;
- MCF_INTC0_ICR31 = 0;
- MCF_INTC0_ICR32 = 0;
- MCF_INTC0_ICR33 = 0;
- MCF_INTC0_ICR34 = 0;
- MCF_INTC0_ICR35 = 0;
- MCF_INTC0_ICR36 = 0;
- MCF_INTC0_ICR37 = 0;
- MCF_INTC0_ICR38 = 0;
- MCF_INTC0_ICR39 = 0;
- MCF_INTC0_ICR40 = 0;
- MCF_INTC0_ICR41 = 0;
- MCF_INTC0_ICR42 = 0;
- MCF_INTC0_ICR43 = 0;
- MCF_INTC0_ICR44 = 0;
- MCF_INTC0_ICR45 = 0;
- MCF_INTC0_ICR46 = 0;
- MCF_INTC0_ICR47 = 0;
- MCF_INTC0_ICR48 = 0;
- MCF_INTC0_ICR49 = 0;
- MCF_INTC0_ICR50 = 0;
- MCF_INTC0_ICR51 = 0;
- MCF_INTC0_ICR52 = 0;
- MCF_INTC0_ICR53 = 0;
- MCF_INTC0_ICR54 = 0;
- MCF_INTC0_ICR55 = 0;
- MCF_INTC0_ICR56 = 0;
- MCF_INTC0_ICR57 = 0;
- MCF_INTC0_ICR58 = 0;
- MCF_INTC0_ICR59 = 0;
- MCF_INTC0_ICR60 = 0;
- MCF_INTC1_ICR8 = 0;
- MCF_INTC1_ICR9 = 0;
- MCF_INTC1_ICR10 = 0;
- MCF_INTC1_ICR11 = 0;
- MCF_INTC1_ICR12 = 0;
- MCF_INTC1_ICR13 = 0;
- MCF_INTC1_ICR14 = 0;
- MCF_INTC1_ICR15 = 0;
- MCF_INTC1_ICR16 = 0;
- MCF_INTC1_ICR17 = 0;
- MCF_INTC1_ICR18 = 0;
- MCF_INTC1_ICR19 = 0;
- MCF_INTC1_ICR20 = 0;
- MCF_INTC1_ICR21 = 0;
- MCF_INTC1_ICR22 = 0;
- MCF_INTC1_ICR23 = 0;
- MCF_INTC1_ICR24 = 0;
- MCF_INTC1_ICR25 = 0;
- MCF_INTC1_ICR27 = 0;
- MCF_INTC1_ICR28 = 0;
- MCF_INTC1_ICR29 = 0;
- MCF_INTC1_ICR30 = 0;
- MCF_INTC1_ICR31 = 0;
- MCF_INTC1_ICR32 = 0;
- MCF_INTC1_ICR33 = 0;
- MCF_INTC1_ICR34 = 0;
- MCF_INTC1_ICR35 = 0;
- MCF_INTC1_ICR36 = 0;
- MCF_INTC1_ICR37 = 0;
- MCF_INTC1_ICR38 = 0;
- MCF_INTC1_ICR39 = 0;
- MCF_INTC1_ICR40 = 0;
- MCF_INTC1_ICR41 = 0;
- MCF_INTC1_ICR42 = 0;
- MCF_INTC1_ICR59 = 0;
- MCF_INTC0_IMRH = 0xffffffff;
- MCF_INTC0_IMRL =
- MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
- MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
- MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
- MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
- MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
- MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
- MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
- MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
- MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
- MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
- MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
- MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
- MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
- MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
- MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
- MCF_INTC0_IMRL_INT_MASK1;
- MCF_INTC1_IMRH = 0xffffffff;
- MCF_INTC1_IMRL =
- MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
- MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
- MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
- MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
- MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
- MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
- MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
- MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
- MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
- MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
- MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
- MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
- MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
- MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
- MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
- MCF_INTC1_IMRL_INT_MASK1;
-}
-
-/*********************************************************************
-* init_pin_assignments - Pin Assignment and General Purpose I/O *
-**********************************************************************/
-static void
-init_pin_assignments( void )
-{
-
- /* Pin assignments for port ADDR
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_APDDR = 0;
- MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
- | MCF_GPIO_PAR_AD_PAR_ADDR22
- | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
-
- /* Pin assignments for ports DATAH and DATAL
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_DATAH = 0;
- MCF_GPIO_PDDR_DATAL = 0;
-
- /* Pin assignments for port BUSCTL
- Pin /OE : External bus output enable, /OE
- Pin /TA : External bus transfer acknowledge, /TA
- Pin /TEA : External bus transfer error acknowledge, /TEA
- Pin R/W : External bus read/write indication, R/W
- Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
- Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
- Pin /TS : External bus transfer start, /TS
- Pin /TIP : External bus transfer in progess, /TIP
- */
- MCF_GPIO_PDDR_BUSCTL = 0;
- MCF_GPIO_PAR_BUSCTL =
- MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
- MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
- MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
- MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
- MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
-
- /* Pin assignments for port BS
- Pin /BS3 : External byte strobe /BS3
- Pin /BS2 : External byte strobe /BS2
- Pin /BS1 : External byte strobe /BS1
- Pin /BS0 : External byte strobe /BS0
- */
- MCF_GPIO_PDDR_BS = 0;
- MCF_GPIO_PAR_BS =
- MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
- MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
-
- /* Pin assignments for port CS
- Pin /CS7 : Chip select /CS7
- Pin /CS6 : Chip select /CS6
- Pin /CS5 : Chip select /CS5
- Pin /CS4 : Chip select /CS4
- Pin /CS3 : Chip select /CS3
- Pin /CS2 : Chip select /CS2
- Pin /CS1 : Chip select /CS1
- */
- MCF_GPIO_PDDR_CS = 0;
- MCF_GPIO_PAR_CS =
- MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
- MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
- MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
- MCF_GPIO_PAR_CS_PAR_CS1;
-
- /* Pin assignments for port SDRAM
- Pin /SD_WE : SDRAM controller /SD_WE
- Pin /SD_SCAS : SDRAM controller /SD_SCAS
- Pin /SD_SRAS : SDRAM controller /SD_SRAS
- Pin /SD_SCKE : SDRAM controller /SD_SCKE
- Pin /SD_CS1 : SDRAM controller /SD_CS1
- Pin /SD_CS0 : SDRAM controller /SD_CS0
- */
- MCF_GPIO_PDDR_SDRAM = 0;
- MCF_GPIO_PAR_SDRAM =
- MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
- MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
- MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
-
- /* Pin assignments for port FECI2C
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_FECI2C = 0;
- MCF_GPIO_PAR_FECI2C =
- MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
-
- /* Pin assignments for port UARTL
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_UARTL = 0;
- MCF_GPIO_PAR_UART = 0;
-
- /* Pin assignments for port UARTH
- Pin U2TXD : GPIO input
- Pin U2RXD : GPIO input
- Pin /IRQ2 : Interrupt request /IRQ2 or GPIO
- */
- MCF_GPIO_PDDR_UARTH = 0;
-
- /* Pin assignments for port QSPI
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_QSPI = 0;
- MCF_GPIO_PAR_QSPI = 0;
-
- /* Pin assignments for port TIMER
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_TIMER = 0;
- MCF_GPIO_PAR_TIMER = 0;
-
- /* Pin assignments for port ETPU
- Pins are all GPIO inputs
- */
- MCF_GPIO_PDDR_ETPU = 0;
- MCF_GPIO_PAR_ETPU = 0;
-}
diff --git a/Demo/MCF5235_GCC/system/mcf5xxx.S b/Demo/MCF5235_GCC/system/mcf5xxx.S
deleted file mode 100644
index b68c689c4..000000000
--- a/Demo/MCF5235_GCC/system/mcf5xxx.S
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Lowest level routines for all ColdFire processors. Based on the
- * MCF523x examples from Freescale.
- *
- * Freescale explicitly grants the redistribution and modification
- * of these source files. The complete licensing information is
- * available in the file LICENSE_FREESCALE.TXT.
- *
- * Modifications Copyright (c) 2006 Christian Walter
- *
- * File: $Id: mcf5xxx.S,v 1.2 2006/09/24 22:50:22 wolti Exp $
- */
-
- .global asm_set_ipl
- .global _asm_set_ipl
- .global mcf5xxx_wr_cacr
- .global _mcf5xxx_wr_cacr
- .global mcf5xxx_wr_acr0
- .global _mcf5xxx_wr_acr0
- .global mcf5xxx_wr_acr1
- .global _mcf5xxx_wr_acr1
- .global mcf5xxx_wr_acr2
- .global _mcf5xxx_wr_acr2
- .global mcf5xxx_wr_acr3
- .global _mcf5xxx_wr_acr3
- .global mcf5xxx_wr_other_sp
- .global _mcf5xxx_wr_other_sp
- .global mcf5xxx_wr_other_a7
- .global _mcf5xxx_wr_other_a7
- .global mcf5xxx_wr_vbr
- .global _mcf5xxx_wr_vbr
- .global mcf5xxx_wr_macsr
- .global _mcf5xxx_wr_macsr
- .global mcf5xxx_wr_mask
- .global _mcf5xxx_wr_mask
- .global mcf5xxx_wr_acc0
- .global _mcf5xxx_wr_acc0
- .global mcf5xxx_wr_accext01
- .global _mcf5xxx_wr_accext01
- .global mcf5xxx_wr_accext23
- .global _mcf5xxx_wr_accext23
- .global mcf5xxx_wr_acc1
- .global _mcf5xxx_wr_acc1
- .global mcf5xxx_wr_acc2
- .global _mcf5xxx_wr_acc2
- .global mcf5xxx_wr_acc3
- .global _mcf5xxx_wr_acc3
- .global mcf5xxx_wr_sr
- .global _mcf5xxx_wr_sr
- .global mcf5xxx_wr_rambar0
- .global _mcf5xxx_wr_rambar0
- .global mcf5xxx_wr_rambar1
- .global _mcf5xxx_wr_rambar1
- .global mcf5xxx_wr_mbar
- .global _mcf5xxx_wr_mbar
- .global mcf5xxx_wr_mbar0
- .global _mcf5xxx_wr_mbar0
- .global mcf5xxx_wr_mbar1
- .global _mcf5xxx_wr_mbar1
-
- .text
-
-/********************************************************************/
-/*
- * This routines changes the IPL to the value passed into the routine.
- * It also returns the old IPL value back.
- * Calling convention from C:
- * old_ipl = asm_set_ipl(new_ipl);
- * For the Diab Data C compiler, it passes return value thru D0.
- * Note that only the least significant three bits of the passed
- * value are used.
- */
-
-asm_set_ipl:
-_asm_set_ipl:
- link a6,#-8
- movem.l d6-d7,(sp)
-
- move.w sr,d7 /* current sr */
-
- move.l d7,d0 /* prepare return value */
- andi.l #0x0700,d0 /* mask out IPL */
- lsr.l #8,d0 /* IPL */
-
- move.l 8(a6),d6 /* get argument */
- andi.l #0x07,d6 /* least significant three bits */
- lsl.l #8,d6 /* move over to make mask */
-
- andi.l #0x0000F8FF,d7 /* zero out current IPL */
- or.l d6,d7 /* place new IPL in sr */
- move.w d7,sr
-
- movem.l (sp),d6-d7
- lea 8(sp),sp
- unlk a6
- rts
-
-/********************************************************************/
-/*
- * These routines write to the special purpose registers in the ColdFire
- * core. Since these registers are write-only in the supervisor model,
- * no corresponding read routines exist.
- */
-
-mcf5xxx_wr_cacr:
-_mcf5xxx_wr_cacr:
- move.l 4(sp),d0
- .long 0x4e7b0002 /* movec d0,cacr */
- nop
- rts
-
-mcf5xxx_wr_acr0:
-_mcf5xxx_wr_acr0:
- move.l 4(sp),d0
- .long 0x4e7b0004 /* movec d0,ACR0 */
- nop
- rts
-
-mcf5xxx_wr_acr1:
-_mcf5xxx_wr_acr1:
- move.l 4(sp),d0
- .long 0x4e7b0005 /* movec d0,ACR1 */
- nop
- rts
-
-mcf5xxx_wr_acr2:
-_mcf5xxx_wr_acr2:
- move.l 4(sp),d0
- .long 0x4e7b0006 /* movec d0,ACR2 */
- nop
- rts
-
-mcf5xxx_wr_acr3:
-_mcf5xxx_wr_acr3:
- move.l 4(sp),d0
- .long 0x4e7b0007 /* movec d0,ACR3 */
- nop
- rts
-
-mcf5xxx_wr_other_sp:
-_mcf5xxx_wr_other_sp:
-mcf5xxx_wr_other_a7:
-_mcf5xxx_wr_other_a7:
- move.l 4(sp),d0
- .long 0x4e7b0800 /* movec d0,OTHER_A7 */
- nop
- rts
-
-mcf5xxx_wr_vbr:
-_mcf5xxx_wr_vbr:
- move.l 4(sp),d0
- .long 0x4e7b0801 /* movec d0,VBR */
- nop
- rts
-
-mcf5xxx_wr_macsr:
-_mcf5xxx_wr_macsr:
- move.l 4(sp),d0
- .long 0x4e7b0804 /* movec d0,MACSR */
- nop
- rts
-
-mcf5xxx_wr_mask:
-_mcf5xxx_wr_mask:
- move.l 4(sp),d0
- .long 0x4e7b0805 /* movec d0,MASK */
- nop
- rts
-
-mcf5xxx_wr_acc0:
-_mcf5xxx_wr_acc0:
- move.l 4(sp),d0
- .long 0x4e7b0806 /* movec d0,ACC0 */
- nop
- rts
-
-mcf5xxx_wr_accext01:
-_mcf5xxx_wr_accext01:
- move.l 4(sp),d0
- .long 0x4e7b0807 /* movec d0,ACCEXT01 */
- nop
- rts
-
-mcf5xxx_wr_accext23:
-_mcf5xxx_wr_accext23:
- move.l 4(sp),d0
- .long 0x4e7b0808 /* movec d0,ACCEXT23 */
- nop
- rts
-
-mcf5xxx_wr_acc1:
-_mcf5xxx_wr_acc1:
- move.l 4(sp),d0
- .long 0x4e7b0809 /* movec d0,ACC1 */
- nop
- rts
-
-mcf5xxx_wr_acc2:
-_mcf5xxx_wr_acc2:
- move.l 4(sp),d0
- .long 0x4e7b080A /* movec d0,ACC2 */
- nop
- rts
-
-mcf5xxx_wr_acc3:
-_mcf5xxx_wr_acc3:
- move.l 4(sp),d0
- .long 0x4e7b080B /* movec d0,ACC3 */
- nop
- rts
-
-mcf5xxx_wr_sr:
-_mcf5xxx_wr_sr:
- move.l 4(sp),d0
- move.w d0,SR
- rts
-
-mcf5xxx_wr_rambar0:
-_mcf5xxx_wr_rambar0:
- move.l 4(sp),d0
- .long 0x4e7b0C04 /* movec d0,RAMBAR0 */
- nop
- rts
-
-mcf5xxx_wr_rambar1:
-_mcf5xxx_wr_rambar1:
- move.l 4(sp),d0
- .long 0x4e7b0C05 /* movec d0,RAMBAR1 */
- nop
- rts
-
-mcf5xxx_wr_mbar:
-_mcf5xxx_wr_mbar:
-mcf5xxx_wr_mbar0:
-_mcf5xxx_wr_mbar0:
- move.l 4(sp),d0
- .long 0x4e7b0C0F /* movec d0,MBAR0 */
- nop
- rts
-
-mcf5xxx_wr_mbar1:
-_mcf5xxx_wr_mbar1:
- move.l 4(sp),d0
- .long 0x4e7b0C0E /* movec d0,MBAR1 */
- nop
- rts
-
- .end
-/********************************************************************/
diff --git a/Demo/MCF5235_GCC/system/newlib.c b/Demo/MCF5235_GCC/system/newlib.c
deleted file mode 100644
index ff05e26e1..000000000
--- a/Demo/MCF5235_GCC/system/newlib.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-/* ------------------------ System includes ------------------------------- */
-#include
-#include
-#include
-#include
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include
-#include
-
-/* ------------------------ Prototypes ------------------------------------ */
-void vSerialPutStringNOISR( xComPortHandle pxPort,
- const signed char * const pcString,
- unsigned short usStringLength );
-
-/* ------------------------ Start implementation -------------------------- */
-void
-_exit( int status )
-{
- asm volatile ( "halt" );
-
- for( ;; );
-}
-
-pid_t
-getpid( void )
-{
- return 0;
-}
-
-int
-kill( pid_t pid, int sig )
-{
- _exit( 0 );
-}
-
-int
-close( int fd )
-{
- return 0;
-}
-
-int
-fstat( int fd, struct stat *buf )
-{
- buf->st_mode = S_IFCHR;
- buf->st_blksize = 0;
- return 0;
-}
-
-ssize_t
-write( int fd, const void *buf, size_t nbytes )
-{
- ssize_t res = nbytes;
- extern xComPortHandle xSTDComPort;
- switch ( fd )
- {
- case STDERR_FILENO:
- vSerialPutStringNOISR( xSTDComPort,
- ( const signed char * const )buf,
- ( unsigned short )nbytes );
- break;
- case STDOUT_FILENO:
- vSerialPutString( xSTDComPort,
- ( const signed char * const)buf,
- ( unsigned short )nbytes );
- break;
- default:
- errno = EIO;
- res = -1;
- break;
- }
- return res;
-}
-
-int
-read( int fd, void *buf, size_t nbytes )
-{
- switch ( fd )
- {
- default:
- errno = EIO;
- return -1;
- }
-}
-
-int
-isatty( int fd )
-{
- return 0;
-}
-
-off_t
-lseek( int fd, off_t offset, int whence )
-{
- errno = EIO;
- return ( off_t ) - 1;
-}
-
-extern char _end[];
-char *heap_ptr;
-
-void *
-sbrk( ptrdiff_t nbytes )
-{
- char *base;
-
- if( !heap_ptr )
- heap_ptr = ( char * )&_end;
- base = heap_ptr;
- heap_ptr += nbytes;
-
- return base;
-}
diff --git a/Demo/MCF5235_GCC/system/serial.c b/Demo/MCF5235_GCC/system/serial.c
deleted file mode 100644
index c9dfcebd5..000000000
--- a/Demo/MCF5235_GCC/system/serial.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
-/* ------------------------ MCF523x includes ------------------------------ */
-#include "mcf5xxx.h"
-#include "mcf523x.h"
-
-/* ------------------------ FreeRTOS includes ----------------------------- */
-#include "FreeRTOS.h"
-#include "queue.h"
-#include "task.h"
-
-#include "serial.h"
-
-/* ----------------------- Defines ----------------------------------------- */
-#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) )
-#define MCF_UART_VECTOR ( 64 + 13 )
-#define COM_NIFACE 1
-#define COM_BLOCK_RETRYTIME 10
-
-/* ------------------------ Static functions ------------------------------ */
-static void prvSerialISR( void );
-
-/* ------------------------ Static variables ------------------------------ */
-typedef struct
-{
- portBASE_TYPE xInitialized;
- QueueHandle_t xRXChars;
- QueueHandle_t xTXChars;
-} xComPortIF_t;
-
-static xComPortIF_t xComPortIF[ COM_NIFACE ];
-
-/* ------------------------ Begin implementation -------------------------- */
-xComPortHandle
-xSerialPortInitMinimal( unsigned long ulWantedBaud,
- unsigned portBASE_TYPE uxQueueLength )
-{
- extern void ( *__RAMVEC[] ) ( );
- xComPortHandle xReturn;
- portBASE_TYPE xOldIPL;
-
- /* Create the queues used to hold Rx and Tx characters. */
- xComPortIF[ 0 ].xRXChars =
- xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed char ) );
- xComPortIF[ 0 ].xTXChars =
- xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed char ) );
-
- /* If the queues were created correctly then setup the serial port hardware. */
- if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) )
- {
- xOldIPL = portSET_IPL( portIPL_MAX );
-
- /* UART 0: Reset transmitter, receiver and mode register pointer */
- MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 );
- MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 );
- MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 );
-
- /* Enable receive interrupts. */
- MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
-
- /* 8 Databits, 1 Stopbit and no parity */
- MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 );
-
- /* UART 0 Clocking */
- MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd );
- MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U;
- MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU;
-
- /* UART 0: Enable interrupts */
- __RAMVEC[MCF_UART_VECTOR] = prvSerialISR;
- MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 );
- MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13;
-
- /* UART 0 Miscellaneous */
- MCF_UART_UACR0 = 0;
-
- /* UART 0: Enable pins */
- MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD;
-
- /* Enable the UART. */
- MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 );
-
- xComPortIF[ 0 ].xInitialized = TRUE;
- xReturn = ( xComPortHandle ) &xComPortIF[ 0 ];
-
- ( void )portSET_IPL( xOldIPL );
- }
- else
- {
- xReturn = ( xComPortHandle ) 0;
- }
-
- return xReturn;
-}
-
-signed portBASE_TYPE
-xSerialGetChar( xComPortHandle pxPort, signed char * pcRxedChar,
- TickType_t xBlockTime )
-{
- int i;
- portBASE_TYPE xResult = pdFALSE;
- /* Lookup the correct interface. */
- for( i = 0; i < COM_NIFACE; i++ )
- {
- if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
- {
- break;
- }
- }
- /* This COM port is available. */
- if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
- {
- /* Get the next character from the buffer. Return false if no characters
- * are available, or arrive before xBlockTime expires.
- */
- if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) )
- {
- xResult = pdTRUE;
- }
- }
- return xResult;
-}
-
-void
-vSerialPutString( xComPortHandle pxPort, const signed char *
- const pcString, unsigned short usStringLength )
-{
- int i;
- signed char *pChNext;
-
- /* Send each character in the string, one at a time. */
- pChNext = ( signed char * )pcString;
- for( i = 0; i < usStringLength; i++ )
- {
- /* Block until character has been transmitted. */
- while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++;
- }
-}
-
-signed portBASE_TYPE
-xSerialPutChar( xComPortHandle pxPort, signed char cOutChar,
- TickType_t xBlockTime )
-{
- int i;
- portBASE_TYPE xResult = pdFALSE;
- portBASE_TYPE xOldIPL;
- /* Lookup the correct interface. */
- for( i = 0; i < COM_NIFACE; i++ )
- {
- if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
- {
- break;
- }
- }
- /* This COM port is available. */
- if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
- {
- /* Place the character in the queue of characters to be transmitted. */
- if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS )
- {
- /* Turn on the Tx interrupt so the ISR will remove the character from the
- * queue and send it. */
- MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU;
- xResult = pdTRUE;
- }
- }
- return xResult;
-}
-
-signed portBASE_TYPE
-xSerialPutCharNOISR( xComPortHandle pxPort, signed char cOutChar )
-{
- int i;
- portBASE_TYPE xResult = pdFALSE;
- portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
- /* Lookup the correct interface. */
- for( i = 0; i < COM_NIFACE; i++ )
- {
- if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
- {
- break;
- }
- }
- /* This COM port is available. Support for this only available for COM1 right now. */
- if( ( i != COM_NIFACE ) && ( i == 0 ) )
- {
- /* Wait until the transmit buffer is ready. */
- while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) );
- /* Place the character in the transmit buffer. */
- MCF_UART_UTB0 = cOutChar;
- xResult = pdTRUE;
- }
- ( void )portSET_IPL( xOldIPL );
- return xResult;
-}
-
-void
-vSerialPutStringNOISR( xComPortHandle pxPort, const signed char *
- const pcString, unsigned short usStringLength )
-{
- int i;
- signed char *pChNext;
- portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
-
- /* Send each character in the string, one at a time. */
- pChNext = ( signed char * )pcString;
- for( i = 0; i < usStringLength; i++ )
- {
- /* Block until character has been transmitted. */
- while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE );
- pChNext++;
- }
- ( void )portSET_IPL( xOldIPL );
-}
-
-void
-vSerialClose( xComPortHandle xPort )
-{
- /* Not supported as not required by the demo application. */
-}
-
-void
-prvSerialISR( void )
-{
- static signed char cChar;
- static portBASE_TYPE xHigherPriorityTaskWoken;
-
- /* We have to remvoe the effect of the GCC. Please note that the
- * __attribute__ ((interrupt_handler)) does not work here because we
- * have to do the storing of the registers ourself. Another problem
- * is the usage of a frame pointer which is unlinked on entry.
- */
-#if _GCC_USES_FP == 1
- asm volatile ( "unlk %fp\n\t" );
-#endif
- /* This ISR can cause a context switch, so the first statement must be
- * a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
- * variable declarations.
- */
- portENTER_SWITCHING_ISR();
- xHigherPriorityTaskWoken = pdFALSE;
-
- /* Ready to send a character from the buffer. */
- if( MCF_UART_USR0 & MCF_UART_USR_TXRDY )
- {
- /* Transmit buffer is ready. Test if there are characters available. */
- if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xHigherPriorityTaskWoken ) ==
- pdTRUE )
- {
- /* A character was retrieved from the queue so can be sent. */
- MCF_UART_UTB0 = cChar;
- }
- else
- {
- /* Leave only receiver enabled. */
- MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
- }
- }
- if( MCF_UART_USR0 & MCF_UART_USR_RXRDY )
- {
- cChar = MCF_UART_URB0;
- xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, &xHigherPriorityTaskWoken );
- }
- /* Exit the ISR. If a task was woken by either a character being
- * or transmitted then a context switch will occur.
- */
- portEXIT_SWITCHING_ISR( xHigherPriorityTaskWoken );
-}
diff --git a/Demo/MCF5235_GCC/system/vector.S b/Demo/MCF5235_GCC/system/vector.S
deleted file mode 100644
index ef6757f20..000000000
--- a/Demo/MCF5235_GCC/system/vector.S
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
-
- This file is part of the FreeRTOS distribution.
-
- FreeRTOS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License** as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- FreeRTOS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with FreeRTOS; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- A special exception to the GPL can be applied should you wish to distribute
- a combined work that includes FreeRTOS, without being obliged to provide
- the source code for any proprietary components. See the licensing section
- of http://www.FreeRTOS.org for full details of how and when the exception
- can be applied.
-
- ***************************************************************************
- ***************************************************************************
- * *
- * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
- * *
- * This is a concise, step by step, 'hands on' guide that describes both *
- * general multitasking concepts and FreeRTOS specifics. It presents and *
- * explains numerous examples that are written using the FreeRTOS API. *
- * Full source code for all the examples is provided in an accompanying *
- * .zip file. *
- * *
- ***************************************************************************
- ***************************************************************************
-
- Please ensure to read the configuration and relevant port sections of the
- online documentation.
-
- http://www.FreeRTOS.org - Documentation, latest information, license and
- contact details.
-
- http://www.SafeRTOS.com - A version that is certified for use in safety
- critical systems.
-
- http://www.OpenRTOS.com - Commercial support, development, porting,
- licensing and training services.
-*/
-
- .extern __stack
- .extern start
- .extern fec_handler
- .extern fec_if
- .extern decrement_timers
- .global __RAMVEC
- .global __ROMVEC
-
- .equ MCF_PIT_PCSR0, IPSBAR + 0x150000
- .equ MCF_PIT_PCSR_PIF, 0x0004
-
- .section .vector_rom, "x"
-__ROMVEC:
- .long __stack /* Reset: Initial Stack Pointer */
- .long start /* Reset: Initial Program Counter */
- .long VecDefault /* Bus Error */
- .long VecDefault /* Address Error */
- .long VecDefault /* Illegal Instruction */
- .long VecDefault /* Zero Divison */
- .space 4 /* reserved */
- .space 4 /* reserved */
- .long VecDefault /* Privilege Violation */
- .long VecDefault /* Trace */
- .long VecDefault /* Unimplemented line-a opcode */
- .long VecDefault /* Unimplemented line-b opcode */
- .long VecDefault /* Non-PC breakpoint debug interrupt */
- .long VecDefault /* PC breakpoint debug interrupt */
- .long VecDefault /* Format Error */
- .long VecDefault /* Uninitialized Interrupt */
- .org 0x60
- .long IRQSpurious /* Spurious Interrupt */
- .long IRQDefault /* Level 1 Interrupt */
- .long IRQDefault /* Level 2 Interrupt */
- .long IRQDefault /* Level 3 Interrupt */
- .long IRQDefault /* Level 4 Interrupt */
- .long IRQDefault /* Level 5 Interrupt */
- .long IRQDefault /* Level 6 Interrupt */
- .long IRQDefault /* Level 7 Interrupt */
- .org 0x80
- .long TrapDefault /* TRAP 0 */
- .long TrapDefault /* TRAP 1 */
- .long TrapDefault /* TRAP 2 */
- .long TrapDefault /* TRAP 3 */
- .long TrapDefault /* TRAP 4 */
- .long TrapDefault /* TRAP 5 */
- .long TrapDefault /* TRAP 6 */
- .long TrapDefault /* TRAP 7 */
- .long TrapDefault /* TRAP 8 */
- .long TrapDefault /* TRAP 9 */
- .long TrapDefault /* TRAP 10 */
- .long TrapDefault /* TRAP 11 */
- .long TrapDefault /* TRAP 12 */
- .long TrapDefault /* TRAP 13 */
- .long TrapDefault /* TRAP 14 */
- .long TrapDefault /* TRAP 15 */
- .org 0x100
- .long IRQDefault /* User-Defined Interrupt 0 */
- .long IRQDefault /* User-Defined Interrupt 1 */
- .long IRQDefault /* User-Defined Interrupt 2 */
- .long IRQDefault /* User-Defined Interrupt 3 */
- .long IRQDefault /* User-Defined Interrupt 4 */
- .long IRQDefault /* User-Defined Interrupt 5 */
- .long IRQDefault /* User-Defined Interrupt 6 */
- .long IRQDefault /* User-Defined Interrupt 7 */
- .long IRQDefault /* User-Defined Interrupt 8 */
- .long IRQDefault /* User-Defined Interrupt 9 */
- .long IRQDefault /* User-Defined Interrupt 10 */
- .long IRQDefault /* User-Defined Interrupt 11 */
- .long IRQDefault /* User-Defined Interrupt 12 */
- .long IRQDefault /* User-Defined Interrupt 13 */
- .long IRQDefault /* User-Defined Interrupt 14 */
- .long IRQDefault /* User-Defined Interrupt 15 */
- .long IRQDefault /* User-Defined Interrupt 16 */
- .long IRQDefault /* User-Defined Interrupt 17 */
- .long IRQDefault /* User-Defined Interrupt 18 */
- .long IRQDefault /* User-Defined Interrupt 19 */
- .long IRQDefault /* User-Defined Interrupt 20 */
- .long IRQDefault /* User-Defined Interrupt 21 */
- .long IRQDefault /* User-Defined Interrupt 22 */
- .long IRQDefault /* Transmit frame interrupt */
- .long IRQDefault /* Transmit buffer interrupt */
- .long IRQDefault /* Transmit FIFO underrun */
- .long IRQDefault /* Collision retry limit */
- .long IRQDefault /* Receive frame interrupt */
- .long IRQDefault /* Receive buffer interrupt */
- .long IRQDefault /* MII interrupt */
- .long IRQDefault /* Late collision */
- .long IRQDefault /* Heartbeat error */
- .long IRQDefault /* Graceful stop complete */
- .long IRQDefault /* Ethernet bus error */
- .long IRQDefault /* Babbling transmit error */
- .long IRQDefault /* Babbling receive error */
- .long IRQDefault /* Timer interrupt */
- .long IRQDefault /* User-Defined Interrupt 37 */
- .long IRQDefault /* User-Defined Interrupt 38 */
- .long IRQDefault /* User-Defined Interrupt 39 */
- .long IRQDefault /* User-Defined Interrupt 40 */
- .long IRQDefault /* User-Defined Interrupt 41 */
- .long IRQDefault /* User-Defined Interrupt 42 */
- .long IRQDefault /* User-Defined Interrupt 43 */
- .long IRQDefault /* User-Defined Interrupt 44 */
- .long IRQDefault /* User-Defined Interrupt 45 */
- .long IRQDefault /* User-Defined Interrupt 46 */
- .long IRQDefault /* User-Defined Interrupt 47 */
- .long IRQDefault /* User-Defined Interrupt 48 */
- .long IRQDefault /* User-Defined Interrupt 49 */
- .long IRQDefault /* User-Defined Interrupt 50 */
- .long IRQDefault /* User-Defined Interrupt 51 */
- .long IRQDefault /* User-Defined Interrupt 52 */
- .long IRQDefault /* User-Defined Interrupt 53 */
- .long IRQDefault /* User-Defined Interrupt 54 */
- .long IRQDefault /* User-Defined Interrupt 55 */
- .long IRQDefault /* User-Defined Interrupt 56 */
- .long IRQDefault /* User-Defined Interrupt 57 */
- .long IRQDefault /* User-Defined Interrupt 58 */
- .long IRQDefault /* User-Defined Interrupt 59 */
- .long IRQDefault /* User-Defined Interrupt 60 */
- .long IRQDefault /* User-Defined Interrupt 61 */
- .long IRQDefault /* User-Defined Interrupt 62 */
- .long IRQDefault /* User-Defined Interrupt 63 */
- .long IRQDefault /* User-Defined Interrupt 64 */
- .long IRQDefault /* User-Defined Interrupt 65 */
- .long IRQDefault /* User-Defined Interrupt 66 */
- .long IRQDefault /* User-Defined Interrupt 67 */
- .long IRQDefault /* User-Defined Interrupt 68 */
- .long IRQDefault /* User-Defined Interrupt 69 */
- .long IRQDefault /* User-Defined Interrupt 70 */
- .long IRQDefault /* User-Defined Interrupt 71 */
- .long IRQDefault /* User-Defined Interrupt 72 */
- .long IRQDefault /* User-Defined Interrupt 73 */
- .long IRQDefault /* User-Defined Interrupt 74 */
- .long IRQDefault /* User-Defined Interrupt 75 */
- .long IRQDefault /* User-Defined Interrupt 76 */
- .long IRQDefault /* User-Defined Interrupt 77 */
- .long IRQDefault /* User-Defined Interrupt 78 */
- .long IRQDefault /* User-Defined Interrupt 79 */
- .long IRQDefault /* User-Defined Interrupt 80 */
- .long IRQDefault /* User-Defined Interrupt 81 */
- .long IRQDefault /* User-Defined Interrupt 82 */
- .long IRQDefault /* User-Defined Interrupt 83 */
- .long IRQDefault /* User-Defined Interrupt 84 */
- .long IRQDefault /* User-Defined Interrupt 85 */
- .long IRQDefault /* User-Defined Interrupt 86 */
- .long IRQDefault /* User-Defined Interrupt 87 */
- .long IRQDefault /* User-Defined Interrupt 88 */
- .long IRQDefault /* User-Defined Interrupt 89 */
- .long IRQDefault /* User-Defined Interrupt 90 */
- .long IRQDefault /* User-Defined Interrupt 91 */
- .long IRQDefault /* User-Defined Interrupt 92 */
- .long IRQDefault /* User-Defined Interrupt 93 */
- .long IRQDefault /* User-Defined Interrupt 94 */
- .long IRQDefault /* User-Defined Interrupt 95 */
- .long IRQDefault /* User-Defined Interrupt 96 */
- .long IRQDefault /* User-Defined Interrupt 97 */
- .long IRQDefault /* User-Defined Interrupt 98 */
- .long IRQDefault /* User-Defined Interrupt 99 */
- .long IRQDefault /* User-Defined Interrupt 100 */
- .long IRQDefault /* User-Defined Interrupt 101 */
- .long IRQDefault /* User-Defined Interrupt 102 */
- .long IRQDefault /* User-Defined Interrupt 103 */
- .long IRQDefault /* User-Defined Interrupt 104 */
- .long IRQDefault /* User-Defined Interrupt 105 */
- .long IRQDefault /* User-Defined Interrupt 106 */
- .long IRQDefault /* User-Defined Interrupt 107 */
- .long IRQDefault /* User-Defined Interrupt 108 */
- .long IRQDefault /* User-Defined Interrupt 109 */
- .long IRQDefault /* User-Defined Interrupt 110 */
- .long IRQDefault /* User-Defined Interrupt 111 */
- .long IRQDefault /* User-Defined Interrupt 112 */
- .long IRQDefault /* User-Defined Interrupt 113 */
- .long IRQDefault /* User-Defined Interrupt 114 */
- .long IRQDefault /* User-Defined Interrupt 115 */
- .long IRQDefault /* User-Defined Interrupt 116 */
- .long IRQDefault /* User-Defined Interrupt 117 */
- .long IRQDefault /* User-Defined Interrupt 118 */
- .long IRQDefault /* User-Defined Interrupt 119 */
- .long IRQDefault /* User-Defined Interrupt 120 */
- .long IRQDefault /* User-Defined Interrupt 121 */
- .long IRQDefault /* User-Defined Interrupt 122 */
- .long IRQDefault /* User-Defined Interrupt 123 */
- .long IRQDefault /* User-Defined Interrupt 124 */
- .long IRQDefault /* User-Defined Interrupt 125 */
- .long IRQDefault /* User-Defined Interrupt 126 */
- .long IRQDefault /* User-Defined Interrupt 127 */
- .long IRQDefault /* User-Defined Interrupt 128 */
- .long IRQDefault /* User-Defined Interrupt 129 */
- .long IRQDefault /* User-Defined Interrupt 130 */
- .long IRQDefault /* User-Defined Interrupt 131 */
- .long IRQDefault /* User-Defined Interrupt 132 */
- .long IRQDefault /* User-Defined Interrupt 133 */
- .long IRQDefault /* User-Defined Interrupt 134 */
- .long IRQDefault /* User-Defined Interrupt 135 */
- .long IRQDefault /* User-Defined Interrupt 136 */
- .long IRQDefault /* User-Defined Interrupt 137 */
- .long IRQDefault /* User-Defined Interrupt 138 */
- .long IRQDefault /* User-Defined Interrupt 139 */
- .long IRQDefault /* User-Defined Interrupt 140 */
- .long IRQDefault /* User-Defined Interrupt 141 */
- .long IRQDefault /* User-Defined Interrupt 142 */
- .long IRQDefault /* User-Defined Interrupt 143 */
- .long IRQDefault /* User-Defined Interrupt 144 */
- .long IRQDefault /* User-Defined Interrupt 145 */
- .long IRQDefault /* User-Defined Interrupt 146 */
- .long IRQDefault /* User-Defined Interrupt 147 */
- .long IRQDefault /* User-Defined Interrupt 148 */
- .long IRQDefault /* User-Defined Interrupt 149 */
- .long IRQDefault /* User-Defined Interrupt 150 */
- .long IRQDefault /* User-Defined Interrupt 151 */
- .long IRQDefault /* User-Defined Interrupt 152 */
- .long IRQDefault /* User-Defined Interrupt 153 */
- .long IRQDefault /* User-Defined Interrupt 154 */
- .long IRQDefault /* User-Defined Interrupt 155 */
- .long IRQDefault /* User-Defined Interrupt 156 */
- .long IRQDefault /* User-Defined Interrupt 157 */
- .long IRQDefault /* User-Defined Interrupt 158 */
- .long IRQDefault /* User-Defined Interrupt 159 */
- .long IRQDefault /* User-Defined Interrupt 160 */
- .long IRQDefault /* User-Defined Interrupt 161 */
- .long IRQDefault /* User-Defined Interrupt 162 */
- .long IRQDefault /* User-Defined Interrupt 163 */
- .long IRQDefault /* User-Defined Interrupt 164 */
- .long IRQDefault /* User-Defined Interrupt 165 */
- .long IRQDefault /* User-Defined Interrupt 166 */
- .long IRQDefault /* User-Defined Interrupt 167 */
- .long IRQDefault /* User-Defined Interrupt 168 */
- .long IRQDefault /* User-Defined Interrupt 169 */
- .long IRQDefault /* User-Defined Interrupt 170 */
- .long IRQDefault /* User-Defined Interrupt 171 */
- .long IRQDefault /* User-Defined Interrupt 172 */
- .long IRQDefault /* User-Defined Interrupt 173 */
- .long IRQDefault /* User-Defined Interrupt 174 */
- .long IRQDefault /* User-Defined Interrupt 175 */
- .long IRQDefault /* User-Defined Interrupt 176 */
- .long IRQDefault /* User-Defined Interrupt 177 */
- .long IRQDefault /* User-Defined Interrupt 178 */
- .long IRQDefault /* User-Defined Interrupt 179 */
- .long IRQDefault /* User-Defined Interrupt 180 */
- .long IRQDefault /* User-Defined Interrupt 181 */
- .long IRQDefault /* User-Defined Interrupt 182 */
- .long IRQDefault /* User-Defined Interrupt 183 */
- .long IRQDefault /* User-Defined Interrupt 184 */
- .long IRQDefault /* User-Defined Interrupt 185 */
- .long IRQDefault /* User-Defined Interrupt 186 */
- .long IRQDefault /* User-Defined Interrupt 187 */
- .long IRQDefault /* User-Defined Interrupt 188 */
- .long IRQDefault /* User-Defined Interrupt 189 */
- .long IRQDefault /* User-Defined Interrupt 190 */
- .long IRQDefault /* User-Defined Interrupt 191 */
- .org 0x00000400
-
- .section .vector_ram
-__RAMVEC:
- .space 0x400
-
- .section .text
-VecDefault:
- halt
- bra VecDefault
-
-IRQDefault:
- halt
- bra IRQDefault
-
-IRQSpurious:
- halt
- bra IRQSpurious
-
-TrapDefault:
- halt
- bra TrapDefault
diff --git a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/FreeRTOSConfig.h b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/FreeRTOSConfig.h
index bf4b1760a..3c3127fa5 100644
--- a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/FreeRTOSConfig.h
+++ b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/ParTest.c b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/ParTest.c
index 3542e3dae..faad36177 100644
--- a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/ParTest.c
+++ b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RegTest.asm b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RegTest.asm
index 18a52690d..297b7f49f 100644
--- a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RegTest.asm
+++ b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RegTest.asm
@@ -1,6 +1,6 @@
;
;/*
-; * FreeRTOS V202104.00
+; * FreeRTOS V202111.00
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RunTimeStatsConfig.c b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RunTimeStatsConfig.c
index 280749a89..21bd7e3b7 100644
--- a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RunTimeStatsConfig.c
+++ b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/RunTimeStatsConfig.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/main.c b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/main.c
index 3f65a431d..223a78f83 100644
--- a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/main.c
+++ b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/serial.c b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/serial.c
index 79550232b..0bb528d47 100644
--- a/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/serial.c
+++ b/Demo/MSP430X_MSP430F5438_CCS/Demo_Source/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h b/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h
index 24028b132..ca08bdae2 100644
--- a/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h
+++ b/Demo/MSP430X_MSP430F5438_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
@@ -125,7 +124,7 @@ the timer has overflowed. */
TA1CTL &= ~TAIFG; \
} \
\
- /* Generate a 32 bit counter value by combinging the current peripheral \
+ /* Generate a 32 bit counter value by combining the current peripheral \
counter value with the number of overflows. */ \
ulCountValue = ( ulStatsOverflowCount << 16UL ); \
ulCountValue |= ( unsigned long ) TA1R; \
diff --git a/Demo/MSP430X_MSP430F5438_IAR/ParTest.c b/Demo/MSP430X_MSP430F5438_IAR/ParTest.c
index 3542e3dae..faad36177 100644
--- a/Demo/MSP430X_MSP430F5438_IAR/ParTest.c
+++ b/Demo/MSP430X_MSP430F5438_IAR/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_IAR/RegTest.s43 b/Demo/MSP430X_MSP430F5438_IAR/RegTest.s43
index 577882de9..d58837bf3 100644
--- a/Demo/MSP430X_MSP430F5438_IAR/RegTest.s43
+++ b/Demo/MSP430X_MSP430F5438_IAR/RegTest.s43
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_IAR/RunTimeStatsConfig.c b/Demo/MSP430X_MSP430F5438_IAR/RunTimeStatsConfig.c
index 51317ff31..96cdd9897 100644
--- a/Demo/MSP430X_MSP430F5438_IAR/RunTimeStatsConfig.c
+++ b/Demo/MSP430X_MSP430F5438_IAR/RunTimeStatsConfig.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_IAR/main.c b/Demo/MSP430X_MSP430F5438_IAR/main.c
index 06ab8458d..c8421999d 100644
--- a/Demo/MSP430X_MSP430F5438_IAR/main.c
+++ b/Demo/MSP430X_MSP430F5438_IAR/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430F5438_IAR/serial.c b/Demo/MSP430X_MSP430F5438_IAR/serial.c
index 71990d04d..fd9058bc9 100644
--- a/Demo/MSP430X_MSP430F5438_IAR/serial.c
+++ b/Demo/MSP430X_MSP430F5438_IAR/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Blinky_Demo/main_blinky.c b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Blinky_Demo/main_blinky.c
index 071368b1c..e39b6aedb 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Blinky_Demo/main_blinky.c
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Blinky_Demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/CCS_Only/RegTest.asm b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/CCS_Only/RegTest.asm
index 9d5db5912..b7a1ab3b7 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/CCS_Only/RegTest.asm
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/CCS_Only/RegTest.asm
@@ -1,6 +1,6 @@
;
;/*
-; * FreeRTOS V202104.00
+; * FreeRTOS V202111.00
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h
index 959dab030..ebd6b60c4 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/main_full.c b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/main_full.c
index d7da0f302..382966861 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/main_full.c
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/serial.c b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/serial.c
index 8cad18cc8..62cd6ac50 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/serial.c
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/Full_Demo/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/IAR_Only/RegTest.s43 b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/IAR_Only/RegTest.s43
index 4cccf7460..dab727551 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/IAR_Only/RegTest.s43
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/IAR_Only/RegTest.s43
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/LEDs.c b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/LEDs.c
index 2bf431e74..9e380b7a4 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/LEDs.c
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/LEDs.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/main.c b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/main.c
index a312837bc..9765658bf 100644
--- a/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/main.c
+++ b/Demo/MSP430X_MSP430FR5969_LaunchPad_IAR_CCS/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Blinky_Demo/main_blinky.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Blinky_Demo/main_blinky.c
index 1b1c82e5b..ff596e53d 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Blinky_Demo/main_blinky.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Blinky_Demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
index 1b876e785..8069de7ca 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S
index ea947cc2a..eed791f30 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/RegisterTests.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
index 19d8c5800..fbe7f754f 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/LEDs.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/LEDs.c
index 906f69caa..4f46b1f13 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/LEDs.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/LEDs.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c
index 90b05b422..09b7407f3 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c
index a4b90c71f..e95cd2959 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h
index ea1fff4eb..8b0cc079f 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/main_lwIP.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/main_lwIP.c
index 67c8cac4c..9e59e0f28 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/main_lwIP.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/lwIP_Demo/main_lwIP.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/main.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/main.c
index 1d77ae14a..360ecc597 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/main.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
index b491eb3ac..601029405 100644
--- a/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
+++ b/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_78K0R_IAR/ButtonISR.s26 b/Demo/NEC_78K0R_IAR/ButtonISR.s26
index 9f6551501..80472b846 100644
--- a/Demo/NEC_78K0R_IAR/ButtonISR.s26
+++ b/Demo/NEC_78K0R_IAR/ButtonISR.s26
@@ -1,5 +1,5 @@
;/*
-; * FreeRTOS V202104.00
+; * FreeRTOS V202111.00
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_78K0R_IAR/ButtonTask.c b/Demo/NEC_78K0R_IAR/ButtonTask.c
index e5c81a6d2..4fc3ccb7f 100644
--- a/Demo/NEC_78K0R_IAR/ButtonTask.c
+++ b/Demo/NEC_78K0R_IAR/ButtonTask.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_78K0R_IAR/FreeRTOSConfig.h b/Demo/NEC_78K0R_IAR/FreeRTOSConfig.h
index 9b70efb94..5b7da653b 100644
--- a/Demo/NEC_78K0R_IAR/FreeRTOSConfig.h
+++ b/Demo/NEC_78K0R_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_78K0R_IAR/RegTest.s26 b/Demo/NEC_78K0R_IAR/RegTest.s26
index 7b98de2c6..c86e863c4 100644
--- a/Demo/NEC_78K0R_IAR/RegTest.s26
+++ b/Demo/NEC_78K0R_IAR/RegTest.s26
@@ -1,5 +1,5 @@
;/*
-; * FreeRTOS V202104.00
+; * FreeRTOS V202111.00
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_78K0R_IAR/main.c b/Demo/NEC_78K0R_IAR/main.c
index fed9de0f6..a8c1e049e 100644
--- a/Demo/NEC_78K0R_IAR/main.c
+++ b/Demo/NEC_78K0R_IAR/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/FreeRTOSConfig.h b/Demo/NEC_V850ES_IAR/FreeRTOSConfig.h
index 816b861b8..ba9f787a5 100644
--- a/Demo/NEC_V850ES_IAR/FreeRTOSConfig.h
+++ b/Demo/NEC_V850ES_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit.c b/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit.c
index a89d54ada..bf016ae8e 100644
--- a/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit.c
+++ b/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Fx3.c b/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Fx3.c
index e530312b4..d7d922dc1 100644
--- a/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Fx3.c
+++ b/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Fx3.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Hx2.c b/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Hx2.c
index 51e568b5b..59ae49494 100644
--- a/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Hx2.c
+++ b/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit_Hx2.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/ParTest/ParTest_Fx3_App_Board.c b/Demo/NEC_V850ES_IAR/ParTest/ParTest_Fx3_App_Board.c
index ac1988052..c7098a1c2 100644
--- a/Demo/NEC_V850ES_IAR/ParTest/ParTest_Fx3_App_Board.c
+++ b/Demo/NEC_V850ES_IAR/ParTest/ParTest_Fx3_App_Board.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/ParTest/ParTest_Generic_Target_Board.c b/Demo/NEC_V850ES_IAR/ParTest/ParTest_Generic_Target_Board.c
index 109eccc41..b3f7a9a6b 100644
--- a/Demo/NEC_V850ES_IAR/ParTest/ParTest_Generic_Target_Board.c
+++ b/Demo/NEC_V850ES_IAR/ParTest/ParTest_Generic_Target_Board.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/RegTest.s85 b/Demo/NEC_V850ES_IAR/RegTest.s85
index 8ced36ddd..65635c62f 100644
--- a/Demo/NEC_V850ES_IAR/RegTest.s85
+++ b/Demo/NEC_V850ES_IAR/RegTest.s85
@@ -1,5 +1,5 @@
;/*
-; * FreeRTOS V202104.00
+; * FreeRTOS V202111.00
; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/main.c b/Demo/NEC_V850ES_IAR/main.c
index 69a963cba..a636f819d 100644
--- a/Demo/NEC_V850ES_IAR/main.c
+++ b/Demo/NEC_V850ES_IAR/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NEC_V850ES_IAR/serial/serial.c b/Demo/NEC_V850ES_IAR/serial/serial.c
index fceb3f279..f71bfb15a 100644
--- a/Demo/NEC_V850ES_IAR/serial/serial.c
+++ b/Demo/NEC_V850ES_IAR/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h
index c30848366..f82e2ef91 100644
--- a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c
index 6c8f1144c..ed146c10e 100644
--- a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c
index 237d6c0f0..dd31e8b53 100644
--- a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c
index 1dc36b3c6..9bd9404f3 100644
--- a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_MPLAB/FreeRTOSConfig.h b/Demo/PIC18_MPLAB/FreeRTOSConfig.h
index 13fd5b55a..aa9b6271f 100644
--- a/Demo/PIC18_MPLAB/FreeRTOSConfig.h
+++ b/Demo/PIC18_MPLAB/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_MPLAB/ParTest/ParTest.c b/Demo/PIC18_MPLAB/ParTest/ParTest.c
index dc921cc7b..38f8d39fc 100644
--- a/Demo/PIC18_MPLAB/ParTest/ParTest.c
+++ b/Demo/PIC18_MPLAB/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_MPLAB/main1.c b/Demo/PIC18_MPLAB/main1.c
index 95eca6151..c25f24504 100644
--- a/Demo/PIC18_MPLAB/main1.c
+++ b/Demo/PIC18_MPLAB/main1.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_MPLAB/main2.c b/Demo/PIC18_MPLAB/main2.c
index 466ffd829..fa35b6992 100644
--- a/Demo/PIC18_MPLAB/main2.c
+++ b/Demo/PIC18_MPLAB/main2.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_MPLAB/main3.c b/Demo/PIC18_MPLAB/main3.c
index 7d22fc458..36a8e9479 100644
--- a/Demo/PIC18_MPLAB/main3.c
+++ b/Demo/PIC18_MPLAB/main3.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_MPLAB/serial/serial.c b/Demo/PIC18_MPLAB/serial/serial.c
index f7a40911c..15fcdb3af 100644
--- a/Demo/PIC18_MPLAB/serial/serial.c
+++ b/Demo/PIC18_MPLAB/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h
index fe42c9f90..ae190582c 100644
--- a/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo1/WIZCmake.h b/Demo/PIC18_WizC/Demo1/WIZCmake.h
index 301653bdb..0ec451a87 100644
--- a/Demo/PIC18_WizC/Demo1/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo1/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo1/fuses.c b/Demo/PIC18_WizC/Demo1/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo1/fuses.c
+++ b/Demo/PIC18_WizC/Demo1/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo1/interrupt.c b/Demo/PIC18_WizC/Demo1/interrupt.c
index c98a3757d..3dd73ae58 100644
--- a/Demo/PIC18_WizC/Demo1/interrupt.c
+++ b/Demo/PIC18_WizC/Demo1/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo1/main.c b/Demo/PIC18_WizC/Demo1/main.c
index 406bb9eb7..549714b0e 100644
--- a/Demo/PIC18_WizC/Demo1/main.c
+++ b/Demo/PIC18_WizC/Demo1/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/*
@@ -43,7 +42,7 @@ Changes from V3.0.1
* installation. It is also included to demonstrate a minimal project-setup
* to use FreeRTOS in a wizC environment.
*
- * Eight independant tasks are created. All tasks share the same taskcode.
+ * Eight independent tasks are created. All tasks share the same taskcode.
* Each task blinks a different led on portB. The blinkrate for each task
* is different, but chosen in such a way that portB will show a binary
* counter pattern. All blinkrates are derived from a single master-rate.
diff --git a/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h
index bb20db360..95ce6d890 100644
--- a/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo2/WIZCmake.h b/Demo/PIC18_WizC/Demo2/WIZCmake.h
index 75678e88b..9a5079777 100644
--- a/Demo/PIC18_WizC/Demo2/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo2/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo2/fuses.c b/Demo/PIC18_WizC/Demo2/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo2/fuses.c
+++ b/Demo/PIC18_WizC/Demo2/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo2/interrupt.c b/Demo/PIC18_WizC/Demo2/interrupt.c
index 01db39f6a..1b4cbb94c 100644
--- a/Demo/PIC18_WizC/Demo2/interrupt.c
+++ b/Demo/PIC18_WizC/Demo2/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo2/main.c b/Demo/PIC18_WizC/Demo2/main.c
index a16a7edec..8e24fd048 100644
--- a/Demo/PIC18_WizC/Demo2/main.c
+++ b/Demo/PIC18_WizC/Demo2/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h
index 178b30d05..ee0c00193 100644
--- a/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo3/WIZCmake.h b/Demo/PIC18_WizC/Demo3/WIZCmake.h
index 75678e88b..9a5079777 100644
--- a/Demo/PIC18_WizC/Demo3/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo3/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo3/fuses.c b/Demo/PIC18_WizC/Demo3/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo3/fuses.c
+++ b/Demo/PIC18_WizC/Demo3/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo3/interrupt.c b/Demo/PIC18_WizC/Demo3/interrupt.c
index 01db39f6a..1b4cbb94c 100644
--- a/Demo/PIC18_WizC/Demo3/interrupt.c
+++ b/Demo/PIC18_WizC/Demo3/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo3/main.c b/Demo/PIC18_WizC/Demo3/main.c
index f33b1e1fe..17c922b94 100644
--- a/Demo/PIC18_WizC/Demo3/main.c
+++ b/Demo/PIC18_WizC/Demo3/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h
index 93bf11fb9..6ebb2faf7 100644
--- a/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo4/WIZCmake.h b/Demo/PIC18_WizC/Demo4/WIZCmake.h
index 75678e88b..9a5079777 100644
--- a/Demo/PIC18_WizC/Demo4/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo4/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo4/fuses.c b/Demo/PIC18_WizC/Demo4/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo4/fuses.c
+++ b/Demo/PIC18_WizC/Demo4/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo4/interrupt.c b/Demo/PIC18_WizC/Demo4/interrupt.c
index 01db39f6a..1b4cbb94c 100644
--- a/Demo/PIC18_WizC/Demo4/interrupt.c
+++ b/Demo/PIC18_WizC/Demo4/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo4/main.c b/Demo/PIC18_WizC/Demo4/main.c
index 7b6bb433c..2b80a7d75 100644
--- a/Demo/PIC18_WizC/Demo4/main.c
+++ b/Demo/PIC18_WizC/Demo4/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h
index d57cfb38d..bd22bddbe 100644
--- a/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo5/WIZCmake.h b/Demo/PIC18_WizC/Demo5/WIZCmake.h
index 75678e88b..9a5079777 100644
--- a/Demo/PIC18_WizC/Demo5/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo5/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo5/fuses.c b/Demo/PIC18_WizC/Demo5/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo5/fuses.c
+++ b/Demo/PIC18_WizC/Demo5/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo5/interrupt.c b/Demo/PIC18_WizC/Demo5/interrupt.c
index 01db39f6a..1b4cbb94c 100644
--- a/Demo/PIC18_WizC/Demo5/interrupt.c
+++ b/Demo/PIC18_WizC/Demo5/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo5/main.c b/Demo/PIC18_WizC/Demo5/main.c
index e11aaae11..57e77e69c 100644
--- a/Demo/PIC18_WizC/Demo5/main.c
+++ b/Demo/PIC18_WizC/Demo5/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h
index 9b422e89f..c71fc1661 100644
--- a/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo6/WIZCmake.h b/Demo/PIC18_WizC/Demo6/WIZCmake.h
index 75678e88b..9a5079777 100644
--- a/Demo/PIC18_WizC/Demo6/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo6/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo6/fuses.c b/Demo/PIC18_WizC/Demo6/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo6/fuses.c
+++ b/Demo/PIC18_WizC/Demo6/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo6/interrupt.c b/Demo/PIC18_WizC/Demo6/interrupt.c
index 01db39f6a..1b4cbb94c 100644
--- a/Demo/PIC18_WizC/Demo6/interrupt.c
+++ b/Demo/PIC18_WizC/Demo6/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo6/main.c b/Demo/PIC18_WizC/Demo6/main.c
index d32fbf890..d9f68aca0 100644
--- a/Demo/PIC18_WizC/Demo6/main.c
+++ b/Demo/PIC18_WizC/Demo6/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h
index 1615fa25f..431887434 100644
--- a/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo7/WIZCmake.h b/Demo/PIC18_WizC/Demo7/WIZCmake.h
index 75678e88b..9a5079777 100644
--- a/Demo/PIC18_WizC/Demo7/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo7/WIZCmake.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo7/fuses.c b/Demo/PIC18_WizC/Demo7/fuses.c
index 1bb236a14..4a9237c19 100644
--- a/Demo/PIC18_WizC/Demo7/fuses.c
+++ b/Demo/PIC18_WizC/Demo7/fuses.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo7/interrupt.c b/Demo/PIC18_WizC/Demo7/interrupt.c
index 01db39f6a..1b4cbb94c 100644
--- a/Demo/PIC18_WizC/Demo7/interrupt.c
+++ b/Demo/PIC18_WizC/Demo7/interrupt.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/Demo7/main.c b/Demo/PIC18_WizC/Demo7/main.c
index 966c73167..34774ccba 100644
--- a/Demo/PIC18_WizC/Demo7/main.c
+++ b/Demo/PIC18_WizC/Demo7/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/ParTest/ParTest.c b/Demo/PIC18_WizC/ParTest/ParTest.c
index 59770ced7..cbf8ec4e8 100644
--- a/Demo/PIC18_WizC/ParTest/ParTest.c
+++ b/Demo/PIC18_WizC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/serial/isrSerialRx.c b/Demo/PIC18_WizC/serial/isrSerialRx.c
index 3f273e0bf..88d3127cd 100644
--- a/Demo/PIC18_WizC/serial/isrSerialRx.c
+++ b/Demo/PIC18_WizC/serial/isrSerialRx.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/serial/isrSerialTx.c b/Demo/PIC18_WizC/serial/isrSerialTx.c
index 3c786608a..4b3c20ab1 100644
--- a/Demo/PIC18_WizC/serial/isrSerialTx.c
+++ b/Demo/PIC18_WizC/serial/isrSerialTx.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC18_WizC/serial/serial.c b/Demo/PIC18_WizC/serial/serial.c
index f3099e2b7..6075be79f 100644
--- a/Demo/PIC18_WizC/serial/serial.c
+++ b/Demo/PIC18_WizC/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/FreeRTOSConfig.h b/Demo/PIC24_MPLAB/FreeRTOSConfig.h
index ed0fe0c81..dabb2611a 100644
--- a/Demo/PIC24_MPLAB/FreeRTOSConfig.h
+++ b/Demo/PIC24_MPLAB/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/ParTest/ParTest.c b/Demo/PIC24_MPLAB/ParTest/ParTest.c
index 73014645e..7d27a1c4f 100644
--- a/Demo/PIC24_MPLAB/ParTest/ParTest.c
+++ b/Demo/PIC24_MPLAB/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/lcd.c b/Demo/PIC24_MPLAB/lcd.c
index dd8b622cd..da1d0b126 100644
--- a/Demo/PIC24_MPLAB/lcd.c
+++ b/Demo/PIC24_MPLAB/lcd.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/* Scheduler includes. */
@@ -170,7 +169,7 @@ static void vLCDTask( void *pvParameters )
xLCDMessage xMessage;
unsigned short usRow = 0;
- /* Remove compiler warnigns. */
+ /* Remove compiler warnings. */
( void ) pvParameters;
/* Initialise the hardware. This uses delays so must not be called prior
diff --git a/Demo/PIC24_MPLAB/lcd.h b/Demo/PIC24_MPLAB/lcd.h
index 94ed1c246..048208f15 100644
--- a/Demo/PIC24_MPLAB/lcd.h
+++ b/Demo/PIC24_MPLAB/lcd.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/main.c b/Demo/PIC24_MPLAB/main.c
index ead98b8bd..2e7f7eba5 100644
--- a/Demo/PIC24_MPLAB/main.c
+++ b/Demo/PIC24_MPLAB/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/serial/serial.c b/Demo/PIC24_MPLAB/serial/serial.c
index 3298d457d..82e9cbe5f 100644
--- a/Demo/PIC24_MPLAB/serial/serial.c
+++ b/Demo/PIC24_MPLAB/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/timertest.c b/Demo/PIC24_MPLAB/timertest.c
index 29d95449e..e43911d00 100644
--- a/Demo/PIC24_MPLAB/timertest.c
+++ b/Demo/PIC24_MPLAB/timertest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC24_MPLAB/timertest.h b/Demo/PIC24_MPLAB/timertest.h
index cc46698da..a63d5bc24 100644
--- a/Demo/PIC24_MPLAB/timertest.h
+++ b/Demo/PIC24_MPLAB/timertest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c b/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c
index 973670a90..93fb93e64 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/FreeRTOSConfig.h b/Demo/PIC32MEC14xx_MPLAB/src/FreeRTOSConfig.h
index 83aaaf369..4a71fa1e4 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/FreeRTOSConfig.h
+++ b/Demo/PIC32MEC14xx_MPLAB/src/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.c b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.c
index f9ea29dac..38214e204 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.c
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.h b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.h
index 9a9c40b16..b3e86d6e2 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.h
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S
index 94c054b01..4c9cb9870 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/RegisterTestTasks.S b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/RegisterTestTasks.S
index 2eb4233da..e0e9ca789 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/RegisterTestTasks.S
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/RegisterTestTasks.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/main_full.c b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/main_full.c
index 9a9090397..bf261dfdd 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/main_full.c
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c
index 22ef33cd3..4b322893e 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.h b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.h
index cc46698da..a63d5bc24 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.h
+++ b/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MEC14xx_MPLAB/src/main.c b/Demo/PIC32MEC14xx_MPLAB/src/main.c
index d37c3095a..5a9ce201d 100644
--- a/Demo/PIC32MEC14xx_MPLAB/src/main.c
+++ b/Demo/PIC32MEC14xx_MPLAB/src/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/ConfigPerformance.c b/Demo/PIC32MX_MPLAB/ConfigPerformance.c
index acb5cc416..bf328cc71 100644
--- a/Demo/PIC32MX_MPLAB/ConfigPerformance.c
+++ b/Demo/PIC32MX_MPLAB/ConfigPerformance.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/ConfigPerformance.h b/Demo/PIC32MX_MPLAB/ConfigPerformance.h
index f4331e6df..1206b95ab 100644
--- a/Demo/PIC32MX_MPLAB/ConfigPerformance.h
+++ b/Demo/PIC32MX_MPLAB/ConfigPerformance.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h b/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h
index 7ebd60876..570921514 100644
--- a/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h
+++ b/Demo/PIC32MX_MPLAB/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/IntQueueTimer.c b/Demo/PIC32MX_MPLAB/IntQueueTimer.c
index f12c6716b..777d30a03 100644
--- a/Demo/PIC32MX_MPLAB/IntQueueTimer.c
+++ b/Demo/PIC32MX_MPLAB/IntQueueTimer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/IntQueueTimer.h b/Demo/PIC32MX_MPLAB/IntQueueTimer.h
index 9a9c40b16..b3e86d6e2 100644
--- a/Demo/PIC32MX_MPLAB/IntQueueTimer.h
+++ b/Demo/PIC32MX_MPLAB/IntQueueTimer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/IntQueueTimer_isr.S b/Demo/PIC32MX_MPLAB/IntQueueTimer_isr.S
index ef54eb163..994871176 100644
--- a/Demo/PIC32MX_MPLAB/IntQueueTimer_isr.S
+++ b/Demo/PIC32MX_MPLAB/IntQueueTimer_isr.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/ParTest/ParTest_Explorer16.c b/Demo/PIC32MX_MPLAB/ParTest/ParTest_Explorer16.c
index 143bc9657..2e7d8876a 100644
--- a/Demo/PIC32MX_MPLAB/ParTest/ParTest_Explorer16.c
+++ b/Demo/PIC32MX_MPLAB/ParTest/ParTest_Explorer16.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/ParTest/ParTest_USBII_Starter_Kit.c b/Demo/PIC32MX_MPLAB/ParTest/ParTest_USBII_Starter_Kit.c
index 597ae798d..1a28407b8 100644
--- a/Demo/PIC32MX_MPLAB/ParTest/ParTest_USBII_Starter_Kit.c
+++ b/Demo/PIC32MX_MPLAB/ParTest/ParTest_USBII_Starter_Kit.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/RegisterTestTasks.S b/Demo/PIC32MX_MPLAB/RegisterTestTasks.S
index 08283cfbc..fb2f358ce 100644
--- a/Demo/PIC32MX_MPLAB/RegisterTestTasks.S
+++ b/Demo/PIC32MX_MPLAB/RegisterTestTasks.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/lcd.c b/Demo/PIC32MX_MPLAB/lcd.c
index 462772f7d..edfecfccd 100644
--- a/Demo/PIC32MX_MPLAB/lcd.c
+++ b/Demo/PIC32MX_MPLAB/lcd.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/lcd.h b/Demo/PIC32MX_MPLAB/lcd.h
index 94ed1c246..048208f15 100644
--- a/Demo/PIC32MX_MPLAB/lcd.h
+++ b/Demo/PIC32MX_MPLAB/lcd.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/main.c b/Demo/PIC32MX_MPLAB/main.c
index 04cf2b5a2..4baa78ba6 100644
--- a/Demo/PIC32MX_MPLAB/main.c
+++ b/Demo/PIC32MX_MPLAB/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/main_blinky.c b/Demo/PIC32MX_MPLAB/main_blinky.c
index 858b1a682..14d083c9d 100644
--- a/Demo/PIC32MX_MPLAB/main_blinky.c
+++ b/Demo/PIC32MX_MPLAB/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/main_full.c b/Demo/PIC32MX_MPLAB/main_full.c
index 33faae719..ced0716b6 100644
--- a/Demo/PIC32MX_MPLAB/main_full.c
+++ b/Demo/PIC32MX_MPLAB/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/serial/serial.c b/Demo/PIC32MX_MPLAB/serial/serial.c
index bf8322124..3499c535e 100644
--- a/Demo/PIC32MX_MPLAB/serial/serial.c
+++ b/Demo/PIC32MX_MPLAB/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/timertest.c b/Demo/PIC32MX_MPLAB/timertest.c
index 9d6ad9bb8..d8529d1a3 100644
--- a/Demo/PIC32MX_MPLAB/timertest.c
+++ b/Demo/PIC32MX_MPLAB/timertest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/timertest.h b/Demo/PIC32MX_MPLAB/timertest.h
index cc46698da..a63d5bc24 100644
--- a/Demo/PIC32MX_MPLAB/timertest.h
+++ b/Demo/PIC32MX_MPLAB/timertest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MX_MPLAB/timertest_isr.S b/Demo/PIC32MX_MPLAB/timertest_isr.S
index 8f7eed42f..a007d7f4c 100644
--- a/Demo/PIC32MX_MPLAB/timertest_isr.S
+++ b/Demo/PIC32MX_MPLAB/timertest_isr.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/ConfigPerformance.c b/Demo/PIC32MZ_MPLAB/ConfigPerformance.c
index fc445c58d..291460423 100644
--- a/Demo/PIC32MZ_MPLAB/ConfigPerformance.c
+++ b/Demo/PIC32MZ_MPLAB/ConfigPerformance.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/ConfigPerformance.h b/Demo/PIC32MZ_MPLAB/ConfigPerformance.h
index f4331e6df..1206b95ab 100644
--- a/Demo/PIC32MZ_MPLAB/ConfigPerformance.h
+++ b/Demo/PIC32MZ_MPLAB/ConfigPerformance.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/FreeRTOSConfig.h b/Demo/PIC32MZ_MPLAB/FreeRTOSConfig.h
index cbd1023aa..63bad4612 100644
--- a/Demo/PIC32MZ_MPLAB/FreeRTOSConfig.h
+++ b/Demo/PIC32MZ_MPLAB/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/ISRTriggeredTask.c b/Demo/PIC32MZ_MPLAB/ISRTriggeredTask.c
index cc351958c..95f583fcd 100644
--- a/Demo/PIC32MZ_MPLAB/ISRTriggeredTask.c
+++ b/Demo/PIC32MZ_MPLAB/ISRTriggeredTask.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/ISRTriggeredTask_isr.S b/Demo/PIC32MZ_MPLAB/ISRTriggeredTask_isr.S
index 48b874c7f..c2a598766 100644
--- a/Demo/PIC32MZ_MPLAB/ISRTriggeredTask_isr.S
+++ b/Demo/PIC32MZ_MPLAB/ISRTriggeredTask_isr.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/IntQueueTimer.c b/Demo/PIC32MZ_MPLAB/IntQueueTimer.c
index f12c6716b..777d30a03 100644
--- a/Demo/PIC32MZ_MPLAB/IntQueueTimer.c
+++ b/Demo/PIC32MZ_MPLAB/IntQueueTimer.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/IntQueueTimer.h b/Demo/PIC32MZ_MPLAB/IntQueueTimer.h
index 9a9c40b16..b3e86d6e2 100644
--- a/Demo/PIC32MZ_MPLAB/IntQueueTimer.h
+++ b/Demo/PIC32MZ_MPLAB/IntQueueTimer.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/IntQueueTimer_isr.S b/Demo/PIC32MZ_MPLAB/IntQueueTimer_isr.S
index d9ae9c1ef..a0a750cd2 100644
--- a/Demo/PIC32MZ_MPLAB/IntQueueTimer_isr.S
+++ b/Demo/PIC32MZ_MPLAB/IntQueueTimer_isr.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/ParTest/ParTest.c b/Demo/PIC32MZ_MPLAB/ParTest/ParTest.c
index a972f91e4..f87d6bf89 100644
--- a/Demo/PIC32MZ_MPLAB/ParTest/ParTest.c
+++ b/Demo/PIC32MZ_MPLAB/ParTest/ParTest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/RegisterTestTasks.S b/Demo/PIC32MZ_MPLAB/RegisterTestTasks.S
index 3afe29223..9e6eaad49 100644
--- a/Demo/PIC32MZ_MPLAB/RegisterTestTasks.S
+++ b/Demo/PIC32MZ_MPLAB/RegisterTestTasks.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/flop_mz.c b/Demo/PIC32MZ_MPLAB/flop_mz.c
index 4f23c56d5..f3076bd78 100644
--- a/Demo/PIC32MZ_MPLAB/flop_mz.c
+++ b/Demo/PIC32MZ_MPLAB/flop_mz.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/flop_mz.h b/Demo/PIC32MZ_MPLAB/flop_mz.h
index 5a894f4e9..782544ee6 100644
--- a/Demo/PIC32MZ_MPLAB/flop_mz.h
+++ b/Demo/PIC32MZ_MPLAB/flop_mz.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/main.c b/Demo/PIC32MZ_MPLAB/main.c
index 0d2f72fb8..facc66837 100644
--- a/Demo/PIC32MZ_MPLAB/main.c
+++ b/Demo/PIC32MZ_MPLAB/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/******************************************************************************
@@ -244,7 +243,7 @@ static enum {
EXCEP_Overflow, /* arithmetic overflow */
EXCEP_Trap, /* trap (possible divide by zero) */
EXCEP_FPE = 15, /* floating point exception */
- EXCEP_IS1 = 16, /* implementation specfic 1 */
+ EXCEP_IS1 = 16, /* implementation specific 1 */
EXCEP_CEU, /* CorExtend Unuseable */
EXCEP_C2E, /* coprocessor 2 */
EXCEP_DSPDis = 26 /* DSP module disabled */
diff --git a/Demo/PIC32MZ_MPLAB/main_blinky.c b/Demo/PIC32MZ_MPLAB/main_blinky.c
index 689c52895..48d0278bb 100644
--- a/Demo/PIC32MZ_MPLAB/main_blinky.c
+++ b/Demo/PIC32MZ_MPLAB/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
/******************************************************************************
@@ -179,7 +178,7 @@ static void prvQueueSendTask( void *pvParameters )
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
- /* Remove compiler warnigns in the case that configASSERT() is not dfined. */
+ /* Remove compiler warnings in the case that configASSERT() is not dfined. */
( void ) pvParameters;
/* Check the task parameter is as expected. */
diff --git a/Demo/PIC32MZ_MPLAB/main_full.c b/Demo/PIC32MZ_MPLAB/main_full.c
index d7b0f06a9..49eea5cbb 100644
--- a/Demo/PIC32MZ_MPLAB/main_full.c
+++ b/Demo/PIC32MZ_MPLAB/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/timertest.c b/Demo/PIC32MZ_MPLAB/timertest.c
index 0b0e0baf4..55ea9f3df 100644
--- a/Demo/PIC32MZ_MPLAB/timertest.c
+++ b/Demo/PIC32MZ_MPLAB/timertest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/timertest.h b/Demo/PIC32MZ_MPLAB/timertest.h
index cc46698da..a63d5bc24 100644
--- a/Demo/PIC32MZ_MPLAB/timertest.h
+++ b/Demo/PIC32MZ_MPLAB/timertest.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PIC32MZ_MPLAB/timertest_isr.S b/Demo/PIC32MZ_MPLAB/timertest_isr.S
index 4f965797a..c60f82937 100644
--- a/Demo/PIC32MZ_MPLAB/timertest_isr.S
+++ b/Demo/PIC32MZ_MPLAB/timertest_isr.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
index 432820882..126780135 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
index af2c64270..8ba152f59 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
index 8ffe66925..44d33c1fa 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
index bb8bd858e..bf682e4bf 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
index 2f0d4bf03..62c905477 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
index 778bfa544..d7784c16d 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
index 6a9113ef3..2340099a3 100644
--- a/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
+++ b/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
index 432820882..126780135 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
index e1a158caa..4c1e1d723 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
index 8ffe66925..44d33c1fa 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
index d7d0d7cec..3ebba15ff 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
index d3d4fa225..010954874 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
index 778bfa544..d7784c16d 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
index 6a9113ef3..2340099a3 100644
--- a/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
+++ b/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
index a365a20f7..b1eebd5d7 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
index e1a158caa..4c1e1d723 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
index 8ffe66925..44d33c1fa 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
index d7d0d7cec..3ebba15ff 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c
index cca7cb0a6..596fe8131 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
index b96669e64..7052e22c3 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
index 6a9113ef3..2340099a3 100644
--- a/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
+++ b/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/Posix_GCC/FreeRTOSConfig.h b/Demo/Posix_GCC/FreeRTOSConfig.h
index 05d3e754c..911b92e83 100644
--- a/Demo/Posix_GCC/FreeRTOSConfig.h
+++ b/Demo/Posix_GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -27,154 +27,158 @@
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. See
- * http://www.freertos.org/a00110.html
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION 1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configUSE_IDLE_HOOK 1
-#define configUSE_TICK_HOOK 1
-#define configUSE_DAEMON_TASK_STARTUP_HOOK 1
-#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the win32 thread. */
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) )
-#define configMAX_TASK_NAME_LEN ( 12 )
-#define configUSE_TRACE_FACILITY 1
-#define configUSE_16_BIT_TICKS 0
-#define configIDLE_SHOULD_YIELD 1
-#define configUSE_MUTEXES 1
-#define configCHECK_FOR_STACK_OVERFLOW 0
-#define configUSE_RECURSIVE_MUTEXES 1
-#define configQUEUE_REGISTRY_SIZE 20
-#define configUSE_APPLICATION_TASK_TAG 1
-#define configUSE_COUNTING_SEMAPHORES 1
-#define configUSE_ALTERNATIVE_API 0
-#define configUSE_QUEUE_SETS 1
-#define configUSE_TASK_NOTIFICATIONS 1
-#define configSUPPORT_STATIC_ALLOCATION 1
+* Application specific definitions.
+*
+* These definitions should be adjusted for your particular hardware and
+* application requirements.
+*
+* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. See
+* http://www.freertos.org/a00110.html
+*----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configUSE_DAEMON_TASK_STARTUP_HOOK 1
+#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the win32 thread. */
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 65 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 1
+#define configUSE_MUTEXES 1
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 20
+#define configUSE_APPLICATION_TASK_TAG 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+#define configUSE_QUEUE_SETS 1
+#define configUSE_TASK_NOTIFICATIONS 1
+#define configSUPPORT_STATIC_ALLOCATION 1
/* Software timer related configuration options. The maximum possible task
-priority is configMAX_PRIORITIES - 1. The priority of the timer task is
-deliberately set higher to ensure it is correctly capped back to
-configMAX_PRIORITIES - 1. */
-#define configUSE_TIMERS 1
-#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
-#define configTIMER_QUEUE_LENGTH 20
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
+ * priority is configMAX_PRIORITIES - 1. The priority of the timer task is
+ * deliberately set higher to ensure it is correctly capped back to
+ * configMAX_PRIORITIES - 1. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 20
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
-#define configMAX_PRIORITIES ( 7 )
+#define configMAX_PRIORITIES ( 7 )
/* Run time stats gathering configuration options. */
unsigned long ulGetRunTimeCounterValue( void ); /* Prototype of function that returns run time counter. */
-void vConfigureTimerForRunTimeStats( void ); /* Prototype of function that initialises the run time counter. */
-#define configGENERATE_RUN_TIME_STATS 1
+void vConfigureTimerForRunTimeStats( void ); /* Prototype of function that initialises the run time counter. */
+#define configGENERATE_RUN_TIME_STATS 1
/* Co-routine related configuration options. */
-#define configUSE_CO_ROUTINES 0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* This demo can use of one or more example stats formatting functions. These
-format the raw data provided by the uxTaskGetSystemState() function in to human
-readable ASCII form. See the notes in the implementation of vTaskList() within
-FreeRTOS/Source/tasks.c for limitations. */
-#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+ * format the raw data provided by the uxTaskGetSystemState() function in to human
+ * readable ASCII form. See the notes in the implementation of vTaskList() within
+ * FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Enables the test whereby a stack larger than the total heap size is
-requested. */
-#define configSTACK_DEPTH_TYPE uint32_t
+ * requested. */
+#define configSTACK_DEPTH_TYPE uint32_t
/* Set the following definitions to 1 to include the API function, or zero
-to exclude the API function. In most cases the linker will remove unused
-functions anyway. */
-#define INCLUDE_vTaskPrioritySet 1
-#define INCLUDE_uxTaskPriorityGet 1
-#define INCLUDE_vTaskDelete 1
-#define INCLUDE_vTaskCleanUpResources 0
-#define INCLUDE_vTaskSuspend 1
-#define INCLUDE_vTaskDelayUntil 1
-#define INCLUDE_vTaskDelay 1
-#define INCLUDE_uxTaskGetStackHighWaterMark 1
-#define INCLUDE_uxTaskGetStackHighWaterMark2 1
-#define INCLUDE_xTaskGetSchedulerState 1
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
-#define INCLUDE_xTaskGetIdleTaskHandle 1
-#define INCLUDE_xTaskGetHandle 1
-#define INCLUDE_eTaskGetState 1
-#define INCLUDE_xSemaphoreGetMutexHolder 1
-#define INCLUDE_xTimerPendFunctionCall 1
-#define INCLUDE_xTaskAbortDelay 1
-
-#define configINCLUDE_MESSAGE_BUFFER_AMP_DEMO 0
+ * to exclude the API function. In most cases the linker will remove unused
+ * functions anyway. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_uxTaskGetStackHighWaterMark2 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 1
+#define INCLUDE_xTaskGetIdleTaskHandle 1
+#define INCLUDE_xTaskGetHandle 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 1
+
+#define configINCLUDE_MESSAGE_BUFFER_AMP_DEMO 0
#if ( configINCLUDE_MESSAGE_BUFFER_AMP_DEMO == 1 )
- extern void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer );
- #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer )
+ extern void vGenerateCoreBInterrupt( void * xUpdatedMessageBuffer );
+ #define sbSEND_COMPLETED( pxStreamBuffer ) vGenerateCoreBInterrupt( pxStreamBuffer )
#endif /* configINCLUDE_MESSAGE_BUFFER_AMP_DEMO */
-extern void vAssertCalled( const char * const pcFileName, unsigned long ulLine );
+extern void vAssertCalled( const char * const pcFileName,
+ unsigned long ulLine );
/* projCOVERAGE_TEST should be defined on the command line so this file can be
-used with multiple project configurations. If it is
+ * used with multiple project configurations. If it is
*/
#ifndef projCOVERAGE_TEST
- #error projCOVERAGE_TEST should be defined to 1 or 0 on the command line.
+ #error projCOVERAGE_TEST should be defined to 1 or 0 on the command line.
#endif
-#if( projCOVERAGE_TEST == 1 )
- /* Insert NOPs in empty decision paths to ensure both true and false paths
- are being tested. */
- #define mtCOVERAGE_TEST_MARKER() __asm volatile( "NOP" )
+#if ( projCOVERAGE_TEST == 1 )
- /* Ensure the tick count overflows during the coverage test. */
- #define configINITIAL_TICK_COUNT 0xffffd800UL
+/* Insert NOPs in empty decision paths to ensure both true and false paths
+ * are being tested. */
+ #define mtCOVERAGE_TEST_MARKER() __asm volatile ( "NOP" )
- /* Allows tests of trying to allocate more than the heap has free. */
- #define configUSE_MALLOC_FAILED_HOOK 0
+/* Ensure the tick count overflows during the coverage test. */
+ #define configINITIAL_TICK_COUNT 0xffffd800UL
- /* To test builds that remove the static qualifier for debug builds. */
- #define portREMOVE_STATIC_QUALIFIER
-#else
- /* It is a good idea to define configASSERT() while developing. configASSERT()
- uses the same semantics as the standard C assert() macro. Don't define
- configASSERT() when performing code coverage tests though, as it is not
- intended to asserts() to fail, some some code is intended not to run if no
- errors are present. */
- #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ )
+/* Allows tests of trying to allocate more than the heap has free. */
+ #define configUSE_MALLOC_FAILED_HOOK 0
- #define configUSE_MALLOC_FAILED_HOOK 1
+/* To test builds that remove the static qualifier for debug builds. */
+ #define portREMOVE_STATIC_QUALIFIER
+#else /* if ( projCOVERAGE_TEST == 1 ) */
- /* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */
- #include "trcRecorder.h"
-#endif
+/* It is a good idea to define configASSERT() while developing. configASSERT()
+ * uses the same semantics as the standard C assert() macro. Don't define
+ * configASSERT() when performing code coverage tests though, as it is not
+ * intended to asserts() to fail, some some code is intended not to run if no
+ * errors are present. */
+ #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ )
+
+ #define configUSE_MALLOC_FAILED_HOOK 1
+
+/* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */
+ #include "trcRecorder.h"
+#endif /* if ( projCOVERAGE_TEST == 1 ) */
/* networking definitions */
-#define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 1 )
/* Prototype for the function used to print out. In this case it prints to the
-console before the network is connected then a UDP port after the network has
-connected. */
-extern void vLoggingPrintf( const char *pcFormatString, ... );
+ * console before the network is connected then a UDP port after the network has
+ * connected. */
+extern void vLoggingPrintf( const char * pcFormatString,
+ ... );
/* Set to 1 to print out debug messages. If ipconfigHAS_DEBUG_PRINTF is set to
-1 then FreeRTOS_debug_printf should be defined to the function used to print
-out the debugging messages. */
-#define ipconfigHAS_DEBUG_PRINTF 1
-#if( ipconfigHAS_DEBUG_PRINTF == 1 )
- #define FreeRTOS_debug_printf(X) vLoggingPrintf X
+ * 1 then FreeRTOS_debug_printf should be defined to the function used to print
+ * out the debugging messages. */
+#define ipconfigHAS_DEBUG_PRINTF 1
+#if ( ipconfigHAS_DEBUG_PRINTF == 1 )
+ #define FreeRTOS_debug_printf( X ) vLoggingPrintf X
#endif
/* Set to 1 to print out non debugging messages, for example the output of the
-FreeRTOS_netstat() command, and ping replies. If ipconfigHAS_PRINTF is set to 1
-then FreeRTOS_printf should be set to the function used to print out the
-messages. */
-#define ipconfigHAS_PRINTF 0
-#if( ipconfigHAS_PRINTF == 1 )
- #define FreeRTOS_printf(X) vLoggingPrintf X
+ * FreeRTOS_netstat() command, and ping replies. If ipconfigHAS_PRINTF is set to 1
+ * then FreeRTOS_printf should be set to the function used to print out the
+ * messages. */
+#define ipconfigHAS_PRINTF 0
+#if ( ipconfigHAS_PRINTF == 1 )
+ #define FreeRTOS_printf( X ) vLoggingPrintf X
#endif
#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/Posix_GCC/Makefile b/Demo/Posix_GCC/Makefile
index 86755f2a5..6804c6a3a 100644
--- a/Demo/Posix_GCC/Makefile
+++ b/Demo/Posix_GCC/Makefile
@@ -1,66 +1,109 @@
-CC := gcc
-BIN := posix_demo
+CC := gcc
+BIN := posix_demo
-BUILD_DIR := build
+BUILD_DIR := ./build
+BUILD_DIR_ABS := $(abspath $(BUILD_DIR))
-FREERTOS_DIR_REL := ../../../FreeRTOS
-FREERTOS_DIR := $(abspath $(FREERTOS_DIR_REL))
+FREERTOS_DIR_REL := ../../../FreeRTOS
+FREERTOS_DIR := $(abspath $(FREERTOS_DIR_REL))
FREERTOS_PLUS_DIR_REL := ../../../FreeRTOS-Plus
-FREERTOS_PLUS_DIR := $(abspath $(FREERTOS_PLUS_DIR_REL))
+FREERTOS_PLUS_DIR := $(abspath $(FREERTOS_PLUS_DIR_REL))
-INCLUDE_DIRS := -I.
-INCLUDE_DIRS += -I${FREERTOS_DIR}/Source/include
-INCLUDE_DIRS += -I${FREERTOS_DIR}/Source/portable/ThirdParty/GCC/Posix
-INCLUDE_DIRS += -I${FREERTOS_DIR}/Source/portable/ThirdParty/GCC/Posix/utils
-INCLUDE_DIRS += -I${FREERTOS_DIR}/Demo/Common/include
-INCLUDE_DIRS += -I${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/Include
+KERNEL_DIR := ${FREERTOS_DIR}/Source
-SOURCE_FILES := $(wildcard *.c)
-SOURCE_FILES += $(wildcard ${FREERTOS_DIR}/Source/*.c)
+INCLUDE_DIRS := -I.
+INCLUDE_DIRS += -I${KERNEL_DIR}/include
+INCLUDE_DIRS += -I${KERNEL_DIR}/portable/ThirdParty/GCC/Posix
+INCLUDE_DIRS += -I${KERNEL_DIR}/portable/ThirdParty/GCC/Posix/utils
+INCLUDE_DIRS += -I${FREERTOS_DIR}/Demo/Common/include
+INCLUDE_DIRS += -I${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/Include
+
+SOURCE_FILES := $(wildcard *.c)
+SOURCE_FILES += $(wildcard ${FREERTOS_DIR}/Source/*.c)
# Memory manager (use malloc() / free() )
-SOURCE_FILES += ${FREERTOS_DIR}/Source/portable/MemMang/heap_3.c
+SOURCE_FILES += ${KERNEL_DIR}/portable/MemMang/heap_3.c
# posix port
-SOURCE_FILES += ${FREERTOS_DIR}/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
-SOURCE_FILES += ${FREERTOS_DIR}/Source/portable/ThirdParty/GCC/Posix/port.c
+SOURCE_FILES += ${KERNEL_DIR}/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
+SOURCE_FILES += ${KERNEL_DIR}/portable/ThirdParty/GCC/Posix/port.c
# Demo library.
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/AbortDelay.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/BlockQ.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/blocktim.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/countsem.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/death.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/dynamic.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/EventGroupsDemo.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/flop.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/GenQTest.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/integer.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/IntSemTest.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/MessageBufferAMP.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/MessageBufferDemo.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/PollQ.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QPeek.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QueueOverwrite.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QueueSet.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QueueSetPolling.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/recmutex.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/semtest.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/StaticAllocation.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/StreamBufferDemo.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/StreamBufferInterrupt.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/TaskNotify.c
-SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/TimerDemo.c
-
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/AbortDelay.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/BlockQ.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/blocktim.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/countsem.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/death.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/dynamic.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/EventGroupsDemo.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/flop.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/GenQTest.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/integer.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/IntSemTest.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/MessageBufferAMP.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/MessageBufferDemo.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/PollQ.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QPeek.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QueueOverwrite.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QueueSet.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/QueueSetPolling.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/recmutex.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/semtest.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/StaticAllocation.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/StreamBufferDemo.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/StreamBufferInterrupt.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/TaskNotify.c
+SOURCE_FILES += ${FREERTOS_DIR}/Demo/Common/Minimal/TimerDemo.c
+
+
+
+CFLAGS := -ggdb3
+LDFLAGS := -ggdb3 -pthread
+CPPFLAGS := $(INCLUDE_DIRS) -DBUILD_DIR=\"$(BUILD_DIR_ABS)\"
+CPPFLAGS += -D_WINDOWS_
+
+ifeq ($(TRACE_ON_ENTER),1)
+ CPPFLAGS += -DTRACE_ON_ENTER=1
+else
+ CPPFLAGS += -DTRACE_ON_ENTER=0
+endif
+
+ifeq ($(COVERAGE_TEST),1)
+ CPPFLAGS += -DprojCOVERAGE_TEST=1
+else
+ CPPFLAGS += -DprojCOVERAGE_TEST=0
# Trace library.
-SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/trcKernelPort.c
-SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/trcSnapshotRecorder.c
-SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/trcStreamingRecorder.c
-SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/streamports/File/trcStreamingPort.c
+ SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/trcKernelPort.c
+ SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/trcSnapshotRecorder.c
+ SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/trcStreamingRecorder.c
+ SOURCE_FILES += ${FREERTOS_PLUS_DIR}/Source/FreeRTOS-Plus-Trace/streamports/File/trcStreamingPort.c
+endif
+
+ifdef PROFILE
+ CFLAGS += -pg -O0
+ LDFLAGS += -pg -O0
+else
+ CFLAGS += -O3
+ LDFLAGS += -O3
+endif
+
+ifdef SANITIZE_ADDRESS
+ CFLAGS += -fsanitize=address -fsanitize=alignment
+ LDFLAGS += -fsanitize=address -fsanitize=alignment
+endif
+
+ifdef SANITIZE_LEAK
+ LDFLAGS += -fsanitize=leak
+endif
+
+ifeq ($(USER_DEMO),BLINKY_DEMO)
+ CPPFLAGS += -DUSER_DEMO=0
+endif
+
+ifeq ($(USER_DEMO),FULL_DEMO)
+ CPPFLAGS += -DUSER_DEMO=1
+endif
-CFLAGS := -ggdb3 -O0 -DprojCOVERAGE_TEST=0 -D_WINDOWS_
-LDFLAGS := -ggdb3 -O0 -pthread -lpcap
-
OBJ_FILES = $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o)
DEP_FILE = $(OBJ_FILES:%.o=%.d)
@@ -69,14 +112,13 @@ ${BIN} : $(BUILD_DIR)/$(BIN)
${BUILD_DIR}/${BIN} : ${OBJ_FILES}
-mkdir -p ${@D}
- $(CC) $^ $(CFLAGS) $(INCLUDE_DIRS) ${LDFLAGS} -o $@
-
+ $(CC) $^ ${LDFLAGS} -o $@
-include ${DEP_FILE}
-${BUILD_DIR}/%.o : %.c
+${BUILD_DIR}/%.o : %.c Makefile
-mkdir -p $(@D)
- $(CC) $(CFLAGS) ${INCLUDE_DIRS} -MMD -c $< -o $@
+ $(CC) $(CPPFLAGS) $(CFLAGS) -MMD -c $< -o $@
.PHONY: clean
@@ -84,8 +126,8 @@ clean:
-rm -rf $(BUILD_DIR)
-
-
-
-
+GPROF_OPTIONS := --directory-path=$(INCLUDE_DIRS)
+profile:
+ gprof -a -p --all-lines $(GPROF_OPTIONS) $(BUILD_DIR)/$(BIN) $(BUILD_DIR)/gmon.out > $(BUILD_DIR)/prof_flat.txt
+ gprof -a --graph $(GPROF_OPTIONS) $(BUILD_DIR)/$(BIN) $(BUILD_DIR)/gmon.out > $(BUILD_DIR)/prof_call_graph.txt
diff --git a/Demo/Posix_GCC/Readme.md b/Demo/Posix_GCC/Readme.md
new file mode 100644
index 000000000..966697a1d
--- /dev/null
+++ b/Demo/Posix_GCC/Readme.md
@@ -0,0 +1,71 @@
+# Profiling your application
+
+## Introduction [(from the official gprof doc)](https://sourceware.org/binutils/docs/gprof/Introduction.html#Introduction)
+Profiling allows you to learn where your program spent its time and which
+functions called which other functions while it was executing. This information
+can show you which pieces of your program are slower than you expected, and
+might be candidates for rewriting to make your program execute faster. It can
+also tell you which functions are being called more or less often than you
+expected. This may help you spot bugs that had otherwise been unnoticed.
+
+## Requirements
+### gprof
+Version as tested: GNU gprof (GNU Binutils) 2.36
+### make
+Version as tested: GNU Make 3.82
+### gcc
+Version as tested: gcc (GCC) 11.0.0
+
+## Generating Profiles
+```
+$ make PROFILE=1
+```
+Run your application
+```
+$ ./build/posix_demo
+```
+Since FreeRTOS and its application never come to an end and typically run
+forever. The user has to kill the application with **Ctrl_C** when they feel
+satisfied that the application achieved its intented task. Killing the
+application will force the profiling file *gmon.out* to be generated
+automatically.
+In order to make sense of this file, the user has to convert the file with:
+```
+$ make profile
+```
+After running the previous command, two (2) profiling files
+*prof_call_graph.txt* and *prof_flat.txt* will be generated and placed in
+the build directory.
+* *prof_call_graph.txt*: The call graph shows which functions called which
+others, and how much time each function used when its subroutine calls are
+included.
+* *prof_flat.txt*: The flat profile shows how much time was spent
+executing directly in each function.
+In order to understand the outputs generated, the best way is to read the
+official documentation of gprof
+[here](https://sourceware.org/binutils/docs/gprof/Output.html#Output)
+
+
+# Run your application with Sanitizers
+## Introduction
+* AddressSanitizer, a fast memory error detector. Memory
+access instructions are instrumented to detect out-of-bounds and use-after-free
+bugs
+* LeakSanitizer, a memory leak detector. This option only matters for linking of
+executables and the executable is linked against a library that overrides malloc
+and other allocator functions
+
+## Requirements
+### gcc
+Version as tested: gcc (GCC) 11.0.0
+## Building and Running the Application
+```
+$ make SANITIZE_ADDRESS=1
+or
+$ make SANITIZE_LEAK=1
+```
+Then run your program normally.
+```
+$ ./build/posix_demo
+```
+If an error is detected by the sanitizer, a report showing the error will be printed to stdout.
diff --git a/Demo/Posix_GCC/code_coverage_additions.c b/Demo/Posix_GCC/code_coverage_additions.c
index defa62db9..73f54d593 100644
--- a/Demo/Posix_GCC/code_coverage_additions.c
+++ b/Demo/Posix_GCC/code_coverage_additions.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -26,7 +26,7 @@
/*
* Contains sundry tests to exercise code that is not touched by the standard
- * demo tasks (which are predominantly test tasks). Some tests are incldued
+ * demo tasks (which are predominantly test tasks). Some tests are included
* here because they can only be executed when configASSERT() is not defined.
*/
@@ -88,527 +88,557 @@ static BaseType_t prvTimerQuery( void );
static BaseType_t prvStaticAllocationsWithNullBuffers( void )
{
-uintptr_t ulReturned = 0;
-BaseType_t xReturn = pdPASS;
-UBaseType_t uxDummy = 10;
-
- /* Don't expect to create any of the objects as a NULL parameter is always
- passed in place of a required buffer. Hence if all passes then none of the
- |= will be against 0, and ulReturned will still be zero at the end of this
- function. */
- ulReturned |= ( uintptr_t ) xEventGroupCreateStatic( NULL );
-
- /* Try creating a task twice, once with puxStackBuffer NULL, and once with
- pxTaskBuffer NULL. */
- ulReturned |= ( uintptr_t ) xTaskCreateStatic( NULL, /* Task to run, not needed as the task is not created. */
- "Dummy", /* Task name. */
- configMINIMAL_STACK_SIZE,
- NULL,
- tskIDLE_PRIORITY,
- NULL,
- ( StaticTask_t * ) &xReturn ); /* Dummy value just to pass a non NULL value in - won't get used. */
-
- ulReturned |= ( uintptr_t ) xTaskCreateStatic( NULL, /* Task to run, not needed as the task is not created. */
- "Dummy", /* Task name. */
- configMINIMAL_STACK_SIZE,
- NULL,
- tskIDLE_PRIORITY,
- ( StackType_t * ) &xReturn, /* Dummy value just to pass a non NULL value in - won't get used. */
- NULL );
-
- ulReturned |= ( uintptr_t ) xQueueCreateStatic( uxDummy,
- uxDummy,
- ( uint8_t * ) &xReturn, /* Dummy value just to pass a non NULL value in - won't get used. */
- NULL );
-
- /* Try creating a stream buffer twice, once with pucStreamBufferStorageArea
- set to NULL, and once with pxStaticStreamBuffer set to NULL. */
- ulReturned |= ( uintptr_t ) xStreamBufferCreateStatic( uxDummy,
- uxDummy,
- NULL,
- ( StaticStreamBuffer_t * ) &xReturn ); /* Dummy value just to pass a non NULL value in - won't get used. */
-
- ulReturned |= ( uintptr_t ) xStreamBufferCreateStatic( uxDummy,
- uxDummy,
- ( uint8_t * ) &xReturn, /* Dummy value just to pass a non NULL value in - won't get used. */
- NULL );
-
- if( ulReturned != 0 )
- {
- /* Something returned a non-NULL value. */
- xReturn = pdFAIL;
- }
-
- return xReturn;
+ uintptr_t ulReturned = 0;
+ BaseType_t xReturn = pdPASS;
+ UBaseType_t uxDummy = 10;
+
+ /* Don't expect to create any of the objects as a NULL parameter is always
+ * passed in place of a required buffer. Hence if all passes then none of the
+ |= will be against 0, and ulReturned will still be zero at the end of this
+ * function. */
+ ulReturned |= ( uintptr_t ) xEventGroupCreateStatic( NULL );
+
+ /* Try creating a task twice, once with puxStackBuffer NULL, and once with
+ * pxTaskBuffer NULL. */
+ ulReturned |= ( uintptr_t ) xTaskCreateStatic( NULL, /* Task to run, not needed as the task is not created. */
+ "Dummy", /* Task name. */
+ configMINIMAL_STACK_SIZE,
+ NULL,
+ tskIDLE_PRIORITY,
+ NULL,
+ ( StaticTask_t * ) &xReturn ); /* Dummy value just to pass a non NULL value in - won't get used. */
+
+ ulReturned |= ( uintptr_t ) xTaskCreateStatic( NULL, /* Task to run, not needed as the task is not created. */
+ "Dummy", /* Task name. */
+ configMINIMAL_STACK_SIZE,
+ NULL,
+ tskIDLE_PRIORITY,
+ ( StackType_t * ) &xReturn, /* Dummy value just to pass a non NULL value in - won't get used. */
+ NULL );
+
+ ulReturned |= ( uintptr_t ) xQueueCreateStatic( uxDummy,
+ uxDummy,
+ ( uint8_t * ) &xReturn, /* Dummy value just to pass a non NULL value in - won't get used. */
+ NULL );
+
+ /* Try creating a stream buffer twice, once with pucStreamBufferStorageArea
+ * set to NULL, and once with pxStaticStreamBuffer set to NULL. */
+ ulReturned |= ( uintptr_t ) xStreamBufferCreateStatic( uxDummy,
+ uxDummy,
+ NULL,
+ ( StaticStreamBuffer_t * ) &xReturn ); /* Dummy value just to pass a non NULL value in - won't get used. */
+
+ ulReturned |= ( uintptr_t ) xStreamBufferCreateStatic( uxDummy,
+ uxDummy,
+ ( uint8_t * ) &xReturn, /* Dummy value just to pass a non NULL value in - won't get used. */
+ NULL );
+
+ if( ulReturned != 0 )
+ {
+ /* Something returned a non-NULL value. */
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
static BaseType_t prvTraceUtils( void )
{
-EventGroupHandle_t xEventGroup;
-QueueHandle_t xQueue;
-BaseType_t xReturn = pdPASS;
-const UBaseType_t xNumber = ( UBaseType_t ) 100, xQueueLength = ( UBaseType_t ) 1;
-UBaseType_t uxValue;
-TaskHandle_t xTaskHandle;
-StreamBufferHandle_t xStreamBuffer;
-MessageBufferHandle_t xMessageBuffer;
-
- /* Exercise the event group trace utilities. */
- xEventGroup = xEventGroupCreate();
-
- if( xEventGroup != NULL )
- {
- vEventGroupSetNumber( xEventGroup, xNumber );
- if( uxEventGroupGetNumber( NULL ) != 0 )
- {
- xReturn = pdFAIL;
- }
- if( uxEventGroupGetNumber( xEventGroup ) != xNumber )
- {
- xReturn = pdFAIL;
- }
-
- vEventGroupDelete( xEventGroup );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- /* Exercise the queue trace utilities. */
- xQueue = xQueueCreate( xQueueLength, ( UBaseType_t ) sizeof( uxValue ) );
- if( xQueue != NULL )
- {
- vQueueSetQueueNumber( xQueue, xNumber );
- if( uxQueueGetQueueNumber( xQueue ) != xNumber )
- {
- xReturn = pdFAIL;
- }
- if( ucQueueGetQueueType( xQueue ) != queueQUEUE_TYPE_BASE )
- {
- xReturn = pdFAIL;
- }
-
- vQueueDelete( xQueue );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- /* Exercise the task trace utilities. Value of 100 is arbitrary, just want
- to check the value that is set is also read back. */
- uxValue = 100;
- xTaskHandle = xTaskGetCurrentTaskHandle();
- vTaskSetTaskNumber( xTaskHandle, uxValue );
- if( uxTaskGetTaskNumber( xTaskHandle ) != uxValue )
- {
- xReturn = pdFAIL;
- }
- if( uxTaskGetTaskNumber( NULL ) != 0 )
- {
- xReturn = pdFAIL;
- }
-
- /* Timer trace util functions are exercised in prvTimerQuery(). */
-
-
- /* Exercise the stream buffer utilities. Try creating with a trigger level
- of 0, it should then get capped to 1. */
- xStreamBuffer = xStreamBufferCreate( sizeof( uint32_t ), 0 );
- if( xStreamBuffer != NULL )
- {
- vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxValue );
- if( uxStreamBufferGetStreamBufferNumber( xStreamBuffer ) != uxValue )
- {
- xReturn = pdFALSE;
- }
- if( ucStreamBufferGetStreamBufferType( xStreamBuffer ) != 0 )
- {
- /* "Is Message Buffer" flag should have been 0. */
- xReturn = pdFALSE;
- }
-
- vStreamBufferDelete( xStreamBuffer );
- }
- else
- {
- xReturn = pdFALSE;
- }
-
- xMessageBuffer = xMessageBufferCreate( sizeof( uint32_t ) );
- if( xMessageBuffer != NULL )
- {
- if( ucStreamBufferGetStreamBufferType( xMessageBuffer ) == 0 )
- {
- /* "Is Message Buffer" flag should have been 1. */
- xReturn = pdFALSE;
- }
-
- vMessageBufferDelete( xMessageBuffer );
- }
- else
- {
- xReturn = pdFALSE;
- }
-
- return xReturn;
+ EventGroupHandle_t xEventGroup;
+ QueueHandle_t xQueue;
+ BaseType_t xReturn = pdPASS;
+ const UBaseType_t xNumber = ( UBaseType_t ) 100, xQueueLength = ( UBaseType_t ) 1;
+ UBaseType_t uxValue;
+ TaskHandle_t xTaskHandle;
+ StreamBufferHandle_t xStreamBuffer;
+ MessageBufferHandle_t xMessageBuffer;
+
+ /* Exercise the event group trace utilities. */
+ xEventGroup = xEventGroupCreate();
+
+ if( xEventGroup != NULL )
+ {
+ vEventGroupSetNumber( xEventGroup, xNumber );
+
+ if( uxEventGroupGetNumber( NULL ) != 0 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( uxEventGroupGetNumber( xEventGroup ) != xNumber )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vEventGroupDelete( xEventGroup );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Exercise the queue trace utilities. */
+ xQueue = xQueueCreate( xQueueLength, ( UBaseType_t ) sizeof( uxValue ) );
+
+ if( xQueue != NULL )
+ {
+ vQueueSetQueueNumber( xQueue, xNumber );
+
+ if( uxQueueGetQueueNumber( xQueue ) != xNumber )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( ucQueueGetQueueType( xQueue ) != queueQUEUE_TYPE_BASE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vQueueDelete( xQueue );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Exercise the task trace utilities. Value of 100 is arbitrary, just want
+ * to check the value that is set is also read back. */
+ uxValue = 100;
+ xTaskHandle = xTaskGetCurrentTaskHandle();
+ vTaskSetTaskNumber( xTaskHandle, uxValue );
+
+ if( uxTaskGetTaskNumber( xTaskHandle ) != uxValue )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( uxTaskGetTaskNumber( NULL ) != 0 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Timer trace util functions are exercised in prvTimerQuery(). */
+
+
+ /* Exercise the stream buffer utilities. Try creating with a trigger level
+ * of 0, it should then get capped to 1. */
+ xStreamBuffer = xStreamBufferCreate( sizeof( uint32_t ), 0 );
+
+ if( xStreamBuffer != NULL )
+ {
+ vStreamBufferSetStreamBufferNumber( xStreamBuffer, uxValue );
+
+ if( uxStreamBufferGetStreamBufferNumber( xStreamBuffer ) != uxValue )
+ {
+ xReturn = pdFALSE;
+ }
+
+ if( ucStreamBufferGetStreamBufferType( xStreamBuffer ) != 0 )
+ {
+ /* "Is Message Buffer" flag should have been 0. */
+ xReturn = pdFALSE;
+ }
+
+ vStreamBufferDelete( xStreamBuffer );
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ xMessageBuffer = xMessageBufferCreate( sizeof( uint32_t ) );
+
+ if( xMessageBuffer != NULL )
+ {
+ if( ucStreamBufferGetStreamBufferType( xMessageBuffer ) == 0 )
+ {
+ /* "Is Message Buffer" flag should have been 1. */
+ xReturn = pdFALSE;
+ }
+
+ vMessageBufferDelete( xMessageBuffer );
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
static BaseType_t prvPeekTimeout( void )
{
-QueueHandle_t xHandle;
-const UBaseType_t xQueueLength = 1;
-BaseType_t xReturn = pdPASS;
-TickType_t xBlockTime = ( TickType_t ) 2;
-UBaseType_t uxReceived;
-
- /* Create the queue just to try peeking it while it is empty. */
- xHandle = xQueueCreate( xQueueLength, ( UBaseType_t ) sizeof( xQueueLength ) );
-
- if( xHandle != NULL )
- {
- if( uxQueueMessagesWaiting( xHandle ) != 0 )
- {
- xReturn = pdFAIL;
- }
-
- /* Ensure peeking from the queue times out as the queue is empty. */
- if( xQueuePeek( xHandle, &uxReceived, xBlockTime ) != pdFALSE )
- {
- xReturn = pdFAIL;
- }
-
- vQueueDelete( xHandle );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
+ QueueHandle_t xHandle;
+ const UBaseType_t xQueueLength = 1;
+ BaseType_t xReturn = pdPASS;
+ TickType_t xBlockTime = ( TickType_t ) 2;
+ UBaseType_t uxReceived;
+
+ /* Create the queue just to try peeking it while it is empty. */
+ xHandle = xQueueCreate( xQueueLength, ( UBaseType_t ) sizeof( xQueueLength ) );
+
+ if( xHandle != NULL )
+ {
+ if( uxQueueMessagesWaiting( xHandle ) != 0 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Ensure peeking from the queue times out as the queue is empty. */
+ if( xQueuePeek( xHandle, &uxReceived, xBlockTime ) != pdFALSE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vQueueDelete( xHandle );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
static BaseType_t prvQueueQueryFromISR( void )
{
-BaseType_t xReturn = pdPASS, xValue = 1;
-const UBaseType_t xISRQueueLength = ( UBaseType_t ) 1;
-const char *pcISRQueueName = "ISRQueue";
-QueueHandle_t xISRQueue = NULL;
-
- xISRQueue = xQueueCreate( xISRQueueLength, ( UBaseType_t ) sizeof( BaseType_t ) );
-
- if( xISRQueue != NULL )
- {
- vQueueAddToRegistry( xISRQueue, pcISRQueueName );
- if( strcmp( pcQueueGetName( xISRQueue ), pcISRQueueName ) )
- {
- xReturn = pdFAIL;
- }
-
- /* Expect the queue to be empty here. */
- if( uxQueueMessagesWaitingFromISR( xISRQueue ) != 0 )
- {
- xReturn = pdFAIL;
- }
-
- if( xQueueIsQueueEmptyFromISR( xISRQueue ) != pdTRUE )
- {
- xReturn = pdFAIL;
- }
-
- if( xQueueIsQueueFullFromISR( xISRQueue ) != pdFALSE )
- {
- xReturn = pdFAIL;
- }
-
- /* Now fill the queue - it only has one space. */
- if( xQueueSendFromISR( xISRQueue, &xValue, NULL ) != pdPASS )
- {
- xReturn = pdFAIL;
- }
-
- /* Check it now reports as full. */
- if( uxQueueMessagesWaitingFromISR( xISRQueue ) != 1 )
- {
- xReturn = pdFAIL;
- }
-
- if( xQueueIsQueueEmptyFromISR( xISRQueue ) != pdFALSE )
- {
- xReturn = pdFAIL;
- }
-
- if( xQueueIsQueueFullFromISR( xISRQueue ) != pdTRUE )
- {
- xReturn = pdFAIL;
- }
-
- vQueueDelete( xISRQueue );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
+ BaseType_t xReturn = pdPASS, xValue = 1;
+ const UBaseType_t xISRQueueLength = ( UBaseType_t ) 1;
+ const char * pcISRQueueName = "ISRQueue";
+ QueueHandle_t xISRQueue = NULL;
+
+ xISRQueue = xQueueCreate( xISRQueueLength, ( UBaseType_t ) sizeof( BaseType_t ) );
+
+ if( xISRQueue != NULL )
+ {
+ vQueueAddToRegistry( xISRQueue, pcISRQueueName );
+
+ if( strcmp( pcQueueGetName( xISRQueue ), pcISRQueueName ) )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Expect the queue to be empty here. */
+ if( uxQueueMessagesWaitingFromISR( xISRQueue ) != 0 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xQueueIsQueueEmptyFromISR( xISRQueue ) != pdTRUE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xQueueIsQueueFullFromISR( xISRQueue ) != pdFALSE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Now fill the queue - it only has one space. */
+ if( xQueueSendFromISR( xISRQueue, &xValue, NULL ) != pdPASS )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Check it now reports as full. */
+ if( uxQueueMessagesWaitingFromISR( xISRQueue ) != 1 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xQueueIsQueueEmptyFromISR( xISRQueue ) != pdFALSE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xQueueIsQueueFullFromISR( xISRQueue ) != pdTRUE )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vQueueDelete( xISRQueue );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
static BaseType_t prvTaskQueryFunctions( void )
{
-static TaskStatus_t xStatus, *pxStatusArray;
-TaskHandle_t xTimerTask, xIdleTask;
-BaseType_t xReturn = pdPASS;
-UBaseType_t uxNumberOfTasks, uxReturned, ux;
-uint32_t ulTotalRunTime1, ulTotalRunTime2;
-const uint32_t ulRunTimeTollerance = ( uint32_t ) 0xfff;
-
- /* Obtain task status with the stack high water mark and without the
- state. */
- vTaskGetInfo( NULL, &xStatus, pdTRUE, eRunning );
-
- if( uxTaskGetStackHighWaterMark( NULL ) != xStatus.usStackHighWaterMark )
- {
- xReturn = pdFAIL;
- }
-
- if( uxTaskGetStackHighWaterMark2( NULL ) != ( configSTACK_DEPTH_TYPE ) xStatus.usStackHighWaterMark )
- {
- xReturn = pdFAIL;
- }
-
- /* Now obtain a task status without the high water mark but with the state,
- which in the case of the idle task should be Read. */
- xTimerTask = xTimerGetTimerDaemonTaskHandle();
- vTaskSuspend( xTimerTask ); /* Should never suspend Timer task normally!. */
- vTaskGetInfo( xTimerTask, &xStatus, pdFALSE, eInvalid );
- if( xStatus.eCurrentState != eSuspended )
- {
- xReturn = pdFAIL;
- }
- if( xStatus.uxBasePriority != uxTaskPriorityGetFromISR( xTimerTask ) )
- {
- xReturn = pdFAIL;
- }
- if( xStatus.uxBasePriority != ( configMAX_PRIORITIES - 1 ) )
- {
- xReturn = pdFAIL;
- }
- xTaskResumeFromISR( xTimerTask );
- vTaskGetInfo( xTimerTask, &xStatus, pdTRUE, eInvalid );
- if( ( xStatus.eCurrentState != eReady ) && ( xStatus.eCurrentState != eBlocked ) )
- {
- xReturn = pdFAIL;
- }
- if( uxTaskGetStackHighWaterMark( xTimerTask ) != xStatus.usStackHighWaterMark )
- {
- xReturn = pdFAIL;
- }
- if( uxTaskGetStackHighWaterMark2( xTimerTask ) != ( configSTACK_DEPTH_TYPE ) xStatus.usStackHighWaterMark )
- {
- xReturn = pdFAIL;
- }
-
- /* Attempting to abort a delay in the idle task should be guaranteed to
- fail as the idle task should never block. */
- xIdleTask = xTaskGetIdleTaskHandle();
- if( xTaskAbortDelay( xIdleTask ) != pdFAIL )
- {
- xReturn = pdFAIL;
- }
-
- /* Create an array of task status objects large enough to hold information
- on the number of tasks at this time - note this may change at any time if
- higher priority tasks are executing and creating tasks. */
- uxNumberOfTasks = uxTaskGetNumberOfTasks();
- pxStatusArray = ( TaskStatus_t * ) pvPortMalloc( uxNumberOfTasks * sizeof( TaskStatus_t ) );
-
- if( pxStatusArray != NULL )
- {
- /* Pass part of the array into uxTaskGetSystemState() to ensure it doesn't
- try using more space than there is available. */
- uxReturned = uxTaskGetSystemState( pxStatusArray, uxNumberOfTasks / ( UBaseType_t ) 2, NULL );
- if( uxReturned != ( UBaseType_t ) 0 )
- {
- xReturn = pdFAIL;
- }
-
- /* Now do the same but passing in the complete array size, this is done
- twice to check for a difference in the total run time. */
- uxTaskGetSystemState( pxStatusArray, uxNumberOfTasks, &ulTotalRunTime1 );
- memset( ( void * ) pxStatusArray, 0xaa, uxNumberOfTasks * sizeof( TaskStatus_t ) );
- uxReturned = uxTaskGetSystemState( pxStatusArray, uxNumberOfTasks, &ulTotalRunTime2 );
- if( ( ulTotalRunTime2 - ulTotalRunTime1 ) > ulRunTimeTollerance )
- {
- xReturn = pdFAIL;
- }
-
- /* Basic santity check of array contents. */
- for( ux = 0; ux < uxReturned; ux++ )
- {
- if( pxStatusArray[ ux ].eCurrentState >= ( UBaseType_t ) eInvalid )
- {
- xReturn = pdFAIL;
- }
- if( pxStatusArray[ ux ].uxCurrentPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
- {
- xReturn = pdFAIL;
- }
- }
-
- vPortFree( pxStatusArray );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
+ static TaskStatus_t xStatus, * pxStatusArray;
+ TaskHandle_t xTimerTask, xIdleTask;
+ BaseType_t xReturn = pdPASS;
+ UBaseType_t uxNumberOfTasks, uxReturned, ux;
+ uint32_t ulTotalRunTime1, ulTotalRunTime2;
+ const uint32_t ulRunTimeTollerance = ( uint32_t ) 0xfff;
+
+ /* Obtain task status with the stack high water mark and without the
+ * state. */
+ vTaskGetInfo( NULL, &xStatus, pdTRUE, eRunning );
+
+ if( uxTaskGetStackHighWaterMark( NULL ) != xStatus.usStackHighWaterMark )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( uxTaskGetStackHighWaterMark2( NULL ) != ( configSTACK_DEPTH_TYPE ) xStatus.usStackHighWaterMark )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Now obtain a task status without the high water mark but with the state,
+ * which in the case of the idle task should be Read. */
+ xTimerTask = xTimerGetTimerDaemonTaskHandle();
+ vTaskSuspend( xTimerTask ); /* Should never suspend Timer task normally!. */
+ vTaskGetInfo( xTimerTask, &xStatus, pdFALSE, eInvalid );
+
+ if( xStatus.eCurrentState != eSuspended )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xStatus.uxBasePriority != uxTaskPriorityGetFromISR( xTimerTask ) )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xStatus.uxBasePriority != ( configMAX_PRIORITIES - 1 ) )
+ {
+ xReturn = pdFAIL;
+ }
+
+ xTaskResumeFromISR( xTimerTask );
+ vTaskGetInfo( xTimerTask, &xStatus, pdTRUE, eInvalid );
+
+ if( ( xStatus.eCurrentState != eReady ) && ( xStatus.eCurrentState != eBlocked ) )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( uxTaskGetStackHighWaterMark( xTimerTask ) != xStatus.usStackHighWaterMark )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( uxTaskGetStackHighWaterMark2( xTimerTask ) != ( configSTACK_DEPTH_TYPE ) xStatus.usStackHighWaterMark )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Attempting to abort a delay in the idle task should be guaranteed to
+ * fail as the idle task should never block. */
+ xIdleTask = xTaskGetIdleTaskHandle();
+
+ if( xTaskAbortDelay( xIdleTask ) != pdFAIL )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Create an array of task status objects large enough to hold information
+ * on the number of tasks at this time - note this may change at any time if
+ * higher priority tasks are executing and creating tasks. */
+ uxNumberOfTasks = uxTaskGetNumberOfTasks();
+ pxStatusArray = ( TaskStatus_t * ) pvPortMalloc( uxNumberOfTasks * sizeof( TaskStatus_t ) );
+
+ if( pxStatusArray != NULL )
+ {
+ /* Pass part of the array into uxTaskGetSystemState() to ensure it doesn't
+ * try using more space than there is available. */
+ uxReturned = uxTaskGetSystemState( pxStatusArray, uxNumberOfTasks / ( UBaseType_t ) 2, NULL );
+
+ if( uxReturned != ( UBaseType_t ) 0 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Now do the same but passing in the complete array size, this is done
+ * twice to check for a difference in the total run time. */
+ uxTaskGetSystemState( pxStatusArray, uxNumberOfTasks, &ulTotalRunTime1 );
+ memset( ( void * ) pxStatusArray, 0xaa, uxNumberOfTasks * sizeof( TaskStatus_t ) );
+ uxReturned = uxTaskGetSystemState( pxStatusArray, uxNumberOfTasks, &ulTotalRunTime2 );
+
+ if( ( ulTotalRunTime2 - ulTotalRunTime1 ) > ulRunTimeTollerance )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Basic santity check of array contents. */
+ for( ux = 0; ux < uxReturned; ux++ )
+ {
+ if( pxStatusArray[ ux ].eCurrentState >= ( UBaseType_t ) eInvalid )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( pxStatusArray[ ux ].uxCurrentPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ {
+ xReturn = pdFAIL;
+ }
+ }
+
+ vPortFree( pxStatusArray );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
-static BaseType_t prvDummyTagFunction( void *pvParameter )
+static BaseType_t prvDummyTagFunction( void * pvParameter )
{
- return ( BaseType_t ) pvParameter;
+ return ( BaseType_t ) pvParameter;
}
/*-----------------------------------------------------------*/
static BaseType_t prvTaskTags( void )
{
-BaseType_t xReturn = pdPASS, xParameter = ( BaseType_t ) 0xDEADBEEF;
-TaskHandle_t xTask;
-
- /* First try with the handle of a different task. Use the timer task for
- convenience. */
- xTask = xTimerGetTimerDaemonTaskHandle();
-
- vTaskSetApplicationTaskTag( xTask, prvDummyTagFunction );
- if( xTaskGetApplicationTaskTag( xTask ) != prvDummyTagFunction )
- {
- xReturn = pdFAIL;
- }
- else
- {
- if( xTaskCallApplicationTaskHook( xTask, ( void * ) xParameter ) != xParameter )
- {
- xReturn = pdFAIL;
- }
- if( xTaskCallApplicationTaskHook( xTask, ( void * ) NULL ) != pdFAIL )
- {
- xReturn = pdFAIL;
- }
- }
-
- /* Try FromISR version too. */
- if( xTaskGetApplicationTaskTagFromISR( xTask ) != prvDummyTagFunction )
- {
- xReturn = pdFAIL;
- }
-
- /* Now try with a NULL handle, so using this task. */
- vTaskSetApplicationTaskTag( NULL, NULL );
- if( xTaskGetApplicationTaskTag( NULL ) != NULL )
- {
- xReturn = pdFAIL;
- }
- if( xTaskGetApplicationTaskTagFromISR( NULL ) != NULL )
- {
- xReturn = pdFAIL;
- }
-
- vTaskSetApplicationTaskTag( NULL, prvDummyTagFunction );
- if( xTaskGetApplicationTaskTag( NULL ) != prvDummyTagFunction )
- {
- xReturn = pdFAIL;
- }
- else
- {
- if( xTaskCallApplicationTaskHook( NULL, ( void * ) xParameter ) != xParameter )
- {
- xReturn = pdFAIL;
- }
- if( xTaskCallApplicationTaskHook( NULL, ( void * ) NULL ) != pdFAIL )
- {
- xReturn = pdFAIL;
- }
- }
-
- /* Try FromISR version too. */
- if( xTaskGetApplicationTaskTagFromISR( NULL ) != prvDummyTagFunction )
- {
- xReturn = pdFAIL;
- }
-
- vTaskSetApplicationTaskTag( NULL, NULL );
- if( xTaskGetApplicationTaskTag( NULL ) != NULL )
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
+ BaseType_t xReturn = pdPASS, xParameter = ( BaseType_t ) 0xDEADBEEF;
+ TaskHandle_t xTask;
+
+ /* First try with the handle of a different task. Use the timer task for
+ * convenience. */
+ xTask = xTimerGetTimerDaemonTaskHandle();
+
+ vTaskSetApplicationTaskTag( xTask, prvDummyTagFunction );
+
+ if( xTaskGetApplicationTaskTag( xTask ) != prvDummyTagFunction )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ if( xTaskCallApplicationTaskHook( xTask, ( void * ) xParameter ) != xParameter )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xTaskCallApplicationTaskHook( xTask, ( void * ) NULL ) != pdFAIL )
+ {
+ xReturn = pdFAIL;
+ }
+ }
+
+ /* Try FromISR version too. */
+ if( xTaskGetApplicationTaskTagFromISR( xTask ) != prvDummyTagFunction )
+ {
+ xReturn = pdFAIL;
+ }
+
+ /* Now try with a NULL handle, so using this task. */
+ vTaskSetApplicationTaskTag( NULL, NULL );
+
+ if( xTaskGetApplicationTaskTag( NULL ) != NULL )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xTaskGetApplicationTaskTagFromISR( NULL ) != NULL )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vTaskSetApplicationTaskTag( NULL, prvDummyTagFunction );
+
+ if( xTaskGetApplicationTaskTag( NULL ) != prvDummyTagFunction )
+ {
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ if( xTaskCallApplicationTaskHook( NULL, ( void * ) xParameter ) != xParameter )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( xTaskCallApplicationTaskHook( NULL, ( void * ) NULL ) != pdFAIL )
+ {
+ xReturn = pdFAIL;
+ }
+ }
+
+ /* Try FromISR version too. */
+ if( xTaskGetApplicationTaskTagFromISR( NULL ) != prvDummyTagFunction )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vTaskSetApplicationTaskTag( NULL, NULL );
+
+ if( xTaskGetApplicationTaskTag( NULL ) != NULL )
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
static BaseType_t prvTimerQuery( void )
{
-TimerHandle_t xTimer;
-BaseType_t xReturn = pdPASS;
-const char *pcTimerName = "TestTimer";
-const TickType_t xTimerPeriod = ( TickType_t ) 100;
-const UBaseType_t uxTimerNumber = ( UBaseType_t ) 55;
-
- xTimer = xTimerCreate( pcTimerName,
- xTimerPeriod,
- pdFALSE,
- ( void * ) xTimerPeriod,
- NULL ); /* Not actually going to start timer so NULL callback is ok. */
-
- if( xTimer != NULL )
- {
- if( xTimerGetPeriod( xTimer ) != xTimerPeriod )
- {
- xReturn = pdFAIL;
- }
-
- if( strcmp( pcTimerGetName( xTimer ), pcTimerName ) != 0 )
- {
- xReturn = pdFAIL;
- }
-
- vTimerSetTimerNumber( xTimer, uxTimerNumber );
- if( uxTimerGetTimerNumber( xTimer ) != uxTimerNumber )
- {
- xReturn = pdFAIL;
- }
-
- xTimerDelete( xTimer, portMAX_DELAY );
- }
- else
- {
- xReturn = pdFAIL;
- }
-
- return xReturn;
+ TimerHandle_t xTimer;
+ BaseType_t xReturn = pdPASS;
+ const char * pcTimerName = "TestTimer";
+ const TickType_t xTimerPeriod = ( TickType_t ) 100;
+ const UBaseType_t uxTimerNumber = ( UBaseType_t ) 55;
+
+ xTimer = xTimerCreate( pcTimerName,
+ xTimerPeriod,
+ pdFALSE,
+ ( void * ) xTimerPeriod,
+ NULL ); /* Not actually going to start timer so NULL callback is ok. */
+
+ if( xTimer != NULL )
+ {
+ if( xTimerGetPeriod( xTimer ) != xTimerPeriod )
+ {
+ xReturn = pdFAIL;
+ }
+
+ if( strcmp( pcTimerGetName( xTimer ), pcTimerName ) != 0 )
+ {
+ xReturn = pdFAIL;
+ }
+
+ vTimerSetTimerNumber( xTimer, uxTimerNumber );
+
+ if( uxTimerGetTimerNumber( xTimer ) != uxTimerNumber )
+ {
+ xReturn = pdFAIL;
+ }
+
+ xTimerDelete( xTimer, portMAX_DELAY );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
}
/*-----------------------------------------------------------*/
BaseType_t xRunCodeCoverageTestAdditions( void )
{
-BaseType_t xReturn = pdPASS;
+ BaseType_t xReturn = pdPASS;
- xReturn &= prvStaticAllocationsWithNullBuffers();
- xReturn &= prvTraceUtils();
- xReturn &= prvPeekTimeout();
- xReturn &= prvQueueQueryFromISR();
- xReturn &= prvTaskQueryFunctions();
- xReturn &= prvTaskTags();
- xReturn &= prvTimerQuery();
+ xReturn &= prvStaticAllocationsWithNullBuffers();
+ xReturn &= prvTraceUtils();
+ xReturn &= prvPeekTimeout();
+ xReturn &= prvQueueQueryFromISR();
+ xReturn &= prvTaskQueryFunctions();
+ xReturn &= prvTaskTags();
+ xReturn &= prvTimerQuery();
- return xReturn;
+ return xReturn;
}
/*-----------------------------------------------------------*/
-
diff --git a/Demo/Posix_GCC/console.c b/Demo/Posix_GCC/console.c
index abd0618ae..18d259a34 100644
--- a/Demo/Posix_GCC/console.c
+++ b/Demo/Posix_GCC/console.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -25,8 +25,8 @@
*/
/*-----------------------------------------------------------
- * Example console I/O wrappers.
- *----------------------------------------------------------*/
+* Example console I/O wrappers.
+*----------------------------------------------------------*/
#include
#include
@@ -37,22 +37,23 @@
SemaphoreHandle_t xStdioMutex;
StaticSemaphore_t xStdioMutexBuffer;
-void console_init(void)
+void console_init( void )
{
- xStdioMutex = xSemaphoreCreateMutexStatic(&xStdioMutexBuffer);
+ xStdioMutex = xSemaphoreCreateMutexStatic( &xStdioMutexBuffer );
}
-void console_print(const char *fmt, ...)
+void console_print( const char * fmt,
+ ... )
{
va_list vargs;
- va_start(vargs, fmt);
-
- xSemaphoreTake(xStdioMutex, portMAX_DELAY);
+ va_start( vargs, fmt );
- vprintf(fmt, vargs);
+ xSemaphoreTake( xStdioMutex, portMAX_DELAY );
- xSemaphoreGive(xStdioMutex);
+ vprintf( fmt, vargs );
- va_end(vargs);
+ xSemaphoreGive( xStdioMutex );
+
+ va_end( vargs );
}
diff --git a/Demo/Posix_GCC/console.h b/Demo/Posix_GCC/console.h
index 99fb56ed5..4a0c3cdf9 100644
--- a/Demo/Posix_GCC/console.h
+++ b/Demo/Posix_GCC/console.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -25,21 +25,22 @@
*/
#ifndef CONSOLE_H
-#define CONSOLE_H
+ #define CONSOLE_H
-#ifdef __cplusplus
-extern "C" {
-#endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
/*-----------------------------------------------------------
- * Example console I/O wrappers.
- *----------------------------------------------------------*/
+* Example console I/O wrappers.
+*----------------------------------------------------------*/
-void console_init(void);
-void console_print(const char *fmt, ...);
+ void console_init( void );
+ void console_print( const char * fmt,
+ ... );
-#ifdef __cplusplus
-}
-#endif
+ #ifdef __cplusplus
+ }
+ #endif
#endif /* CONSOLE_H */
diff --git a/Demo/Posix_GCC/main.c b/Demo/Posix_GCC/main.c
index f5196d24d..33229ce95 100644
--- a/Demo/Posix_GCC/main.c
+++ b/Demo/Posix_GCC/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -25,8 +25,8 @@
*/
/******************************************************************************
- * This project provides three demo applications. A simple blinky style project,
- * a more comprehensive test and demo application, and a TCP echo demo.
+ * This project provides two demo applications. A simple blinky style project,
+ * a more comprehensive test and demo application.
* The mainSELECTED_APPLICATION setting is used to select between
* the three
*
@@ -55,6 +55,9 @@
#include
#include
#include
+#include
+#include
+#include
/* FreeRTOS kernel includes. */
#include "FreeRTOS.h"
@@ -63,18 +66,29 @@
/* Local includes. */
#include "console.h"
-#define BLINKY_DEMO 0
-#define FULL_DEMO 1
+#define BLINKY_DEMO 0
+#define FULL_DEMO 1
-#define mainSELECTED_APPLICATION BLINKY_DEMO
+#ifdef BUILD_DIR
+ #define BUILD BUILD_DIR
+#else
+ #define BUILD "./"
+#endif
+
+/* Demo type is passed as an argument */
+#ifdef USER_DEMO
+ #define mainSELECTED_APPLICATION USER_DEMO
+#else /* Default Setting */
+ #define mainSELECTED_APPLICATION BLINKY_DEMO
+#endif
/* This demo uses heap_3.c (the libc provided malloc() and free()). */
/*-----------------------------------------------------------*/
extern void main_blinky( void );
extern void main_full( void );
-extern void main_tcp_echo_client_tasks( void );
static void traceOnEnter( void );
+
/*
* Only the comprehensive demo uses application hook (callback) functions. See
* http://www.freertos.org/a00016.html for more information.
@@ -89,14 +103,14 @@ void vFullDemoIdleFunction( void );
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask,
- char *pcTaskName );
+ char * pcTaskName );
void vApplicationTickHook( void );
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
- StackType_t **ppxIdleTaskStackBuffer,
- uint32_t *pulIdleTaskStackSize );
-void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
- StackType_t **ppxTimerTaskStackBuffer,
- uint32_t *pulTimerTaskStackSize );
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+ StackType_t ** ppxIdleTaskStackBuffer,
+ uint32_t * pulIdleTaskStackSize );
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+ StackType_t ** ppxTimerTaskStackBuffer,
+ uint32_t * pulTimerTaskStackSize );
/*
* Writes trace data to a disk file when the trace recording is stopped.
@@ -104,52 +118,68 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
*/
static void prvSaveTraceFile( void );
+/*
+ * Signal handler for Ctrl_C to cause the program to exit, and generate the
+ * profiling info.
+ */
+static void handle_sigint( int signal );
+
/*-----------------------------------------------------------*/
/* When configSUPPORT_STATIC_ALLOCATION is set to 1 the application writer can
-use a callback function to optionally provide the memory required by the idle
-and timer tasks. This is the stack that will be used by the timer task. It is
-declared here, as a global, so it can be checked by a test that is implemented
-in a different file. */
+ * use a callback function to optionally provide the memory required by the idle
+ * and timer tasks. This is the stack that will be used by the timer task. It is
+ * declared here, as a global, so it can be checked by a test that is implemented
+ * in a different file. */
StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
/* Notes if the trace is running or not. */
-static BaseType_t xTraceRunning = pdTRUE;
+#if ( projCOVERAGE_TEST == 1 )
+ static BaseType_t xTraceRunning = pdFALSE;
+#else
+ static BaseType_t xTraceRunning = pdTRUE;
+#endif
/*-----------------------------------------------------------*/
int main( void )
{
+ /* SIGINT is not blocked by the posix port */
+ signal( SIGINT, handle_sigint );
+
/* Do not include trace code when performing a code coverage analysis. */
#if ( projCOVERAGE_TEST != 1 )
- {
- /* Initialise the trace recorder. Use of the trace recorder is optional.
- See http://www.FreeRTOS.org/trace for more information. */
- vTraceEnable( TRC_START );
-
- /* Start the trace recording - the recording is written to a file if
- configASSERT() is called. */
- printf( "\r\nTrace started.\r\nThe trace will be dumped to disk if a call to configASSERT() fails.\r\n" );
- printf( "\r\nThe trace will be dumped to disk if Enter is hit.\r\n" );
- uiTraceStart();
- }
- #endif
+ {
+ /* Initialise the trace recorder. Use of the trace recorder is optional.
+ * See http://www.FreeRTOS.org/trace for more information. */
+ vTraceEnable( TRC_START );
+
+ /* Start the trace recording - the recording is written to a file if
+ * configASSERT() is called. */
+ printf( "\r\nTrace started.\r\nThe trace will be dumped to disk if a call to configASSERT() fails.\r\n" );
+
+ #if ( TRACE_ON_ENTER == 1 )
+ printf( "\r\nThe trace will be dumped to disk if Enter is hit.\r\n" );
+ #endif
+ uiTraceStart();
+ }
+ #endif /* if ( projCOVERAGE_TEST != 1 ) */
console_init();
#if ( mainSELECTED_APPLICATION == BLINKY_DEMO )
- {
- console_print("Starting echo blinky demo\n");
- main_blinky();
- }
- #elif ( mainSELECTED_APPLICATION == FULL_DEMO)
- {
- console_print("Starting full demo\n");
- main_full();
- }
+ {
+ console_print( "Starting echo blinky demo\n" );
+ main_blinky();
+ }
+ #elif ( mainSELECTED_APPLICATION == FULL_DEMO )
+ {
+ console_print( "Starting full demo\n" );
+ main_full();
+ }
#else
- {
- #error "The selected demo is not valid"
- }
+ {
+ #error "The selected demo is not valid"
+ }
#endif /* if ( mainSELECTED_APPLICATION ) */
return 0;
@@ -159,17 +189,17 @@ int main( void )
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
- configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
- function that will get called if a call to pvPortMalloc() fails.
- pvPortMalloc() is called internally by the kernel whenever a task, queue,
- timer or semaphore is created. It is also called by various parts of the
- demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the
- size of the heap available to pvPortMalloc() is defined by
- configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize()
- API function can be used to query the size of free heap space that remains
- (although it does not provide information on how the remaining heap might be
- fragmented). See http://www.freertos.org/a00111.html for more
- information. */
+ * configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ * function that will get called if a call to pvPortMalloc() fails.
+ * pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ * timer or semaphore is created. It is also called by various parts of the
+ * demo application. If heap_1.c, heap_2.c or heap_4.c is being used, then the
+ * size of the heap available to pvPortMalloc() is defined by
+ * configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize()
+ * API function can be used to query the size of free heap space that remains
+ * (although it does not provide information on how the remaining heap might be
+ * fragmented). See http://www.freertos.org/a00111.html for more
+ * information. */
vAssertCalled( __FILE__, __LINE__ );
}
/*-----------------------------------------------------------*/
@@ -177,40 +207,40 @@ void vApplicationMallocFailedHook( void )
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
- to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
- task. It is essential that code added to this hook function never attempts
- to block in any way (for example, call xQueueReceive() with a block time
- specified, or call vTaskDelay()). If application tasks make use of the
- vTaskDelete() API function to delete themselves then it is also important
- that vApplicationIdleHook() is permitted to return to its calling function,
- because it is the responsibility of the idle task to clean up memory
- allocated by the kernel to any task that has since deleted itself. */
+ * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ * task. It is essential that code added to this hook function never attempts
+ * to block in any way (for example, call xQueueReceive() with a block time
+ * specified, or call vTaskDelay()). If application tasks make use of the
+ * vTaskDelete() API function to delete themselves then it is also important
+ * that vApplicationIdleHook() is permitted to return to its calling function,
+ * because it is the responsibility of the idle task to clean up memory
+ * allocated by the kernel to any task that has since deleted itself. */
- usleep(15000);
+ usleep( 15000 );
traceOnEnter();
#if ( mainSELECTED_APPLICATION == FULL_DEMO )
- {
- /* Call the idle task processing used by the full demo. The simple
- blinky demo does not use the idle task hook. */
- vFullDemoIdleFunction();
- }
+ {
+ /* Call the idle task processing used by the full demo. The simple
+ * blinky demo does not use the idle task hook. */
+ vFullDemoIdleFunction();
+ }
#endif
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask,
- char *pcTaskName )
+ char * pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
- function is called if a stack overflow is detected. This function is
- provided as an example only as stack overflow checking does not function
- when running the FreeRTOS POSIX port. */
+ * configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ * function is called if a stack overflow is detected. This function is
+ * provided as an example only as stack overflow checking does not function
+ * when running the FreeRTOS POSIX port. */
vAssertCalled( __FILE__, __LINE__ );
}
/*-----------------------------------------------------------*/
@@ -218,42 +248,48 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask,
void vApplicationTickHook( void )
{
/* This function will be called by each tick interrupt if
- configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
- added here, but the tick hook is called from an interrupt context, so
- code must not attempt to block, and only the interrupt safe FreeRTOS API
- functions can be used (those that end in FromISR()). */
+ * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
+ * added here, but the tick hook is called from an interrupt context, so
+ * code must not attempt to block, and only the interrupt safe FreeRTOS API
+ * functions can be used (those that end in FromISR()). */
- #if (mainSELECTED_APPLICATION == FULL_DEMO )
- {
- vFullDemoTickHookFunction();
- }
+ #if ( mainSELECTED_APPLICATION == FULL_DEMO )
+ {
+ vFullDemoTickHookFunction();
+ }
#endif /* mainSELECTED_APPLICATION */
}
void traceOnEnter()
{
- int ret;
- struct timeval tv = { 0L, 0L };
- fd_set fds;
- FD_ZERO(&fds);
- FD_SET(0, &fds);
- ret = select(1, &fds, NULL, NULL, &tv);
- if ( ret > 0 )
- {
- if( xTraceRunning == pdTRUE )
- {
- prvSaveTraceFile();
- }
- /* clear the buffer */
- char buffer[200];
- read(1, &buffer, 200);
- }
+ #if ( TRACE_ON_ENTER == 1 )
+ int xReturn;
+ struct timeval tv = { 0L, 0L };
+ fd_set fds;
+
+ FD_ZERO( &fds );
+ FD_SET( STDIN_FILENO, &fds );
+
+ xReturn = select( STDIN_FILENO + 1, &fds, NULL, NULL, &tv );
+
+ if( xReturn > 0 )
+ {
+ if( xTraceRunning == pdTRUE )
+ {
+ prvSaveTraceFile();
+ }
+
+ /* clear the buffer */
+ char buffer[ 0 ];
+ read( STDIN_FILENO, &buffer, 1 );
+ }
+ #endif /* if ( TRACE_ON_ENTER == 1 ) */
}
-void vLoggingPrintf( const char *pcFormat,
+void vLoggingPrintf( const char * pcFormat,
... )
{
-va_list arg;
+ va_list arg;
va_start( arg, pcFormat );
vprintf( pcFormat, arg );
@@ -264,20 +300,20 @@ va_list arg;
void vApplicationDaemonTaskStartupHook( void )
{
/* This function will be called once only, when the daemon task starts to
- execute (sometimes called the timer task). This is useful if the
- application includes initialisation code that would benefit from executing
- after the scheduler has been started. */
+ * execute (sometimes called the timer task). This is useful if the
+ * application includes initialisation code that would benefit from executing
+ * after the scheduler has been started. */
}
/*-----------------------------------------------------------*/
void vAssertCalled( const char * const pcFileName,
unsigned long ulLine )
{
-static BaseType_t xPrinted = pdFALSE;
-volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0;
+ static BaseType_t xPrinted = pdFALSE;
+ volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0;
/* Called if an assertion passed to configASSERT() fails. See
- http://www.freertos.org/a00110.html#configASSERT for more information. */
+ * http://www.freertos.org/a00110.html#configASSERT for more information. */
/* Parameters are not used. */
( void ) ulLine;
@@ -298,8 +334,8 @@ volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0;
}
/* You can step out of this function to debug the assertion by using
- the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero
- value. */
+ * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero
+ * value. */
while( ulSetToNonZeroInDebuggerToContinue == 0 )
{
__asm volatile ( "NOP" );
@@ -314,76 +350,90 @@ static void prvSaveTraceFile( void )
{
/* Tracing is not used when code coverage analysis is being performed. */
#if ( projCOVERAGE_TEST != 1 )
- {
- FILE * pxOutputFile;
+ {
+ FILE * pxOutputFile;
- vTraceStop();
+ vTraceStop();
- pxOutputFile = fopen( "Trace.dump", "wb" );
+ pxOutputFile = fopen( "Trace.dump", "wb" );
- if( pxOutputFile != NULL )
- {
- fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile );
- fclose( pxOutputFile );
- printf( "\r\nTrace output saved to Trace.dump\r\n" );
- }
- else
- {
- printf( "\r\nFailed to create trace dump file\r\n" );
+ if( pxOutputFile != NULL )
+ {
+ fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile );
+ fclose( pxOutputFile );
+ printf( "\r\nTrace output saved to Trace.dump\r\n" );
+ }
+ else
+ {
+ printf( "\r\nFailed to create trace dump file\r\n" );
+ }
}
- }
#endif /* if ( projCOVERAGE_TEST != 1 ) */
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
-implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
-used by the Idle task. */
-void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
- StackType_t **ppxIdleTaskStackBuffer,
- uint32_t *pulIdleTaskStackSize )
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+ StackType_t ** ppxIdleTaskStackBuffer,
+ uint32_t * pulIdleTaskStackSize )
{
/* If the buffers to be provided to the Idle task are declared inside this
-function then they must be declared static - otherwise they will be allocated on
-the stack and so not exists after this function exits. */
+ * function then they must be declared static - otherwise they will be allocated on
+ * the stack and so not exists after this function exits. */
static StaticTask_t xIdleTaskTCB;
static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
/* Pass out a pointer to the StaticTask_t structure in which the Idle task's
- state will be stored. */
+ * state will be stored. */
*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
/* Pass out the array that will be used as the Idle task's stack. */
*ppxIdleTaskStackBuffer = uxIdleTaskStack;
/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
- Note that, as the array is necessarily of type StackType_t,
- configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ * Note that, as the array is necessarily of type StackType_t,
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
}
/*-----------------------------------------------------------*/
/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
-application must provide an implementation of vApplicationGetTimerTaskMemory()
-to provide the memory that is used by the Timer service task. */
-void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer,
- StackType_t **ppxTimerTaskStackBuffer,
- uint32_t *pulTimerTaskStackSize )
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+ StackType_t ** ppxTimerTaskStackBuffer,
+ uint32_t * pulTimerTaskStackSize )
{
/* If the buffers to be provided to the Timer task are declared inside this
-function then they must be declared static - otherwise they will be allocated on
-the stack and so not exists after this function exits. */
+ * function then they must be declared static - otherwise they will be allocated on
+ * the stack and so not exists after this function exits. */
static StaticTask_t xTimerTaskTCB;
/* Pass out a pointer to the StaticTask_t structure in which the Timer
- task's state will be stored. */
+ * task's state will be stored. */
*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
/* Pass out the array that will be used as the Timer task's stack. */
*ppxTimerTaskStackBuffer = uxTimerTaskStack;
/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
- Note that, as the array is necessarily of type StackType_t,
- configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+ * Note that, as the array is necessarily of type StackType_t,
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
}
+
+void handle_sigint( int signal )
+{
+ int xReturn;
+
+ xReturn = chdir( BUILD ); /* changing dir to place gmon.out inside build */
+
+ if( xReturn == -1 )
+ {
+ printf( "chdir into %s error is %d\n", BUILD, errno );
+ }
+
+ exit( 2 );
+}
diff --git a/Demo/Posix_GCC/main_blinky.c b/Demo/Posix_GCC/main_blinky.c
index 493dc9f44..b52ee1139 100644
--- a/Demo/Posix_GCC/main_blinky.c
+++ b/Demo/Posix_GCC/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -93,29 +93,29 @@
#include "console.h"
/* Priorities at which the tasks are created. */
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The times are converted from
-milliseconds to ticks using the pdMS_TO_TICKS() macro. */
-#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL )
-#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL )
+ * milliseconds to ticks using the pdMS_TO_TICKS() macro. */
+#define mainTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL )
+#define mainTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL )
/* The number of items the queue can hold at once. */
-#define mainQUEUE_LENGTH ( 2 )
+#define mainQUEUE_LENGTH ( 2 )
/* The values sent to the queue receive task from the queue send task and the
-queue send software timer respectively. */
-#define mainVALUE_SENT_FROM_TASK ( 100UL )
-#define mainVALUE_SENT_FROM_TIMER ( 200UL )
+ * queue send software timer respectively. */
+#define mainVALUE_SENT_FROM_TASK ( 100UL )
+#define mainVALUE_SENT_FROM_TIMER ( 200UL )
/*-----------------------------------------------------------*/
/*
* The tasks as described in the comments at the top of this file.
*/
-static void prvQueueReceiveTask( void *pvParameters );
-static void prvQueueSendTask( void *pvParameters );
+static void prvQueueReceiveTask( void * pvParameters );
+static void prvQueueSendTask( void * pvParameters );
/*
* The callback function executed when the software timer expires.
@@ -135,130 +135,132 @@ static TimerHandle_t xTimer = NULL;
/*** SEE THE COMMENTS AT THE TOP OF THIS FILE ***/
void main_blinky( void )
{
-const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS;
-
- /* Create the queue. */
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
-
- if( xQueue != NULL )
- {
- /* Start the two tasks as described in the comments at the top of this
- file. */
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
- "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
- NULL, /* The parameter passed to the task - not used in this simple case. */
- mainQUEUE_RECEIVE_TASK_PRIORITY,/* The priority assigned to the task. */
- NULL ); /* The task handle is not required, so NULL is passed. */
-
- xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
-
- /* Create the software timer, but don't start it yet. */
- xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */
- xTimerPeriod, /* The period of the software timer in ticks. */
- pdTRUE, /* xAutoReload is set to pdTRUE. */
- NULL, /* The timer's ID is not used. */
- prvQueueSendTimerCallback );/* The function executed when the timer expires. */
-
- if( xTimer != NULL )
- {
- xTimerStart( xTimer, 0 );
- }
-
- /* Start the tasks and timer running. */
- vTaskStartScheduler();
- }
-
- /* If all is well, the scheduler will now be running, and the following
- line will never be reached. If the following line does execute, then
- there was insufficient FreeRTOS heap memory available for the idle and/or
- timer tasks to be created. See the memory management section on the
- FreeRTOS web site for more details. */
- for( ;; );
+ const TickType_t xTimerPeriod = mainTIMER_SEND_FREQUENCY_MS;
+
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xQueue != NULL )
+ {
+ /* Start the two tasks as described in the comments at the top of this
+ * file. */
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
+ "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
+ NULL, /* The parameter passed to the task - not used in this simple case. */
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
+ NULL ); /* The task handle is not required, so NULL is passed. */
+
+ xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* Create the software timer, but don't start it yet. */
+ xTimer = xTimerCreate( "Timer", /* The text name assigned to the software timer - for debug only as it is not used by the kernel. */
+ xTimerPeriod, /* The period of the software timer in ticks. */
+ pdTRUE, /* xAutoReload is set to pdTRUE. */
+ NULL, /* The timer's ID is not used. */
+ prvQueueSendTimerCallback ); /* The function executed when the timer expires. */
+
+ if( xTimer != NULL )
+ {
+ xTimerStart( xTimer, 0 );
+ }
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+ }
+
+ /* If all is well, the scheduler will now be running, and the following
+ * line will never be reached. If the following line does execute, then
+ * there was insufficient FreeRTOS heap memory available for the idle and/or
+ * timer tasks to be created. See the memory management section on the
+ * FreeRTOS web site for more details. */
+ for( ; ; )
+ {
+ }
}
/*-----------------------------------------------------------*/
-static void prvQueueSendTask( void *pvParameters )
+static void prvQueueSendTask( void * pvParameters )
{
-TickType_t xNextWakeTime;
-const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS;
-const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK;
-
- /* Prevent the compiler warning about the unused parameter. */
- ( void ) pvParameters;
-
- /* Initialise xNextWakeTime - this only needs to be done once. */
- xNextWakeTime = xTaskGetTickCount();
-
- for( ;; )
- {
- /* Place this task in the blocked state until it is time to run again.
- The block time is specified in ticks, pdMS_TO_TICKS() was used to
- convert a time specified in milliseconds into a time specified in ticks.
- While in the Blocked state this task will not consume any CPU time. */
- vTaskDelayUntil( &xNextWakeTime, xBlockTime );
-
- /* Send to the queue - causing the queue receive task to unblock and
- write to the console. 0 is used as the block time so the send operation
- will not block - it shouldn't need to block as the queue should always
- have at least one space at this point in the code. */
- xQueueSend( xQueue, &ulValueToSend, 0U );
- }
+ TickType_t xNextWakeTime;
+ const TickType_t xBlockTime = mainTASK_SEND_FREQUENCY_MS;
+ const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TASK;
+
+ /* Prevent the compiler warning about the unused parameter. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ; ; )
+ {
+ /* Place this task in the blocked state until it is time to run again.
+ * The block time is specified in ticks, pdMS_TO_TICKS() was used to
+ * convert a time specified in milliseconds into a time specified in ticks.
+ * While in the Blocked state this task will not consume any CPU time. */
+ vTaskDelayUntil( &xNextWakeTime, xBlockTime );
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ * write to the console. 0 is used as the block time so the send operation
+ * will not block - it shouldn't need to block as the queue should always
+ * have at least one space at this point in the code. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
+ }
}
/*-----------------------------------------------------------*/
static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle )
{
-const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER;
+ const uint32_t ulValueToSend = mainVALUE_SENT_FROM_TIMER;
- /* This is the software timer callback function. The software timer has a
- period of two seconds and is reset each time a key is pressed. This
- callback function will execute if the timer expires, which will only happen
- if a key is not pressed for two seconds. */
+ /* This is the software timer callback function. The software timer has a
+ * period of two seconds and is reset each time a key is pressed. This
+ * callback function will execute if the timer expires, which will only happen
+ * if a key is not pressed for two seconds. */
- /* Avoid compiler warnings resulting from the unused parameter. */
- ( void ) xTimerHandle;
+ /* Avoid compiler warnings resulting from the unused parameter. */
+ ( void ) xTimerHandle;
- /* Send to the queue - causing the queue receive task to unblock and
- write out a message. This function is called from the timer/daemon task, so
- must not block. Hence the block time is set to 0. */
- xQueueSend( xQueue, &ulValueToSend, 0U );
+ /* Send to the queue - causing the queue receive task to unblock and
+ * write out a message. This function is called from the timer/daemon task, so
+ * must not block. Hence the block time is set to 0. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
}
/*-----------------------------------------------------------*/
-static void prvQueueReceiveTask( void *pvParameters )
+static void prvQueueReceiveTask( void * pvParameters )
{
-uint32_t ulReceivedValue;
-
- /* Prevent the compiler warning about the unused parameter. */
- ( void ) pvParameters;
-
- for( ;; )
- {
- /* Wait until something arrives in the queue - this task will block
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
- FreeRTOSConfig.h. It will not use any CPU time while it is in the
- Blocked state. */
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
-
- /* To get here something must have been received from the queue, but
- is it an expected value? Normally calling printf() from a task is not
- a good idea. Here there is lots of stack space and only one task is
- using console IO so it is ok. However, note the comments at the top of
- this file about the risks of making Linux system calls (such as
- console output) from a FreeRTOS task. */
- if( ulReceivedValue == mainVALUE_SENT_FROM_TASK )
- {
- console_print( "Message received from task\n" );
- }
- else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER )
- {
- console_print( "Message received from software timer\n" );
- }
- else
- {
- console_print( "Unexpected message\n" );
- }
- }
+ uint32_t ulReceivedValue;
+
+ /* Prevent the compiler warning about the unused parameter. */
+ ( void ) pvParameters;
+
+ for( ; ; )
+ {
+ /* Wait until something arrives in the queue - this task will block
+ * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ * FreeRTOSConfig.h. It will not use any CPU time while it is in the
+ * Blocked state. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ * is it an expected value? Normally calling printf() from a task is not
+ * a good idea. Here there is lots of stack space and only one task is
+ * using console IO so it is ok. However, note the comments at the top of
+ * this file about the risks of making Linux system calls (such as
+ * console output) from a FreeRTOS task. */
+ if( ulReceivedValue == mainVALUE_SENT_FROM_TASK )
+ {
+ console_print( "Message received from task\n" );
+ }
+ else if( ulReceivedValue == mainVALUE_SENT_FROM_TIMER )
+ {
+ console_print( "Message received from software timer\n" );
+ }
+ else
+ {
+ console_print( "Unexpected message\n" );
+ }
+ }
}
/*-----------------------------------------------------------*/
diff --git a/Demo/Posix_GCC/main_full.c b/Demo/Posix_GCC/main_full.c
index bebed4fd8..36c7a3159 100644
--- a/Demo/Posix_GCC/main_full.c
+++ b/Demo/Posix_GCC/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -35,7 +35,7 @@
* the timing information in the FreeRTOS+Trace logs have no meaningful units.
* See the documentation page for the Linux simulator for an explanation of
* the slow timing:
- * https://freertos-wordpress.corp.amazon.com/FreeRTOS-simulator-for-Linux.html
+ * https://www.freertos.org/FreeRTOS-simulator-for-Linux.html
* - READ THE WEB DOCUMENTATION FOR THIS PORT FOR MORE INFORMATION ON USING IT -
*
* NOTE 2: This project provides two demo applications. A simple blinky style
@@ -109,18 +109,18 @@
#include "console.h"
/* Priorities at which the tasks are created. */
-#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
-#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
-#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
-#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
-#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )
-#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
-#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
-#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
-
-#define mainTIMER_TEST_PERIOD ( 50 )
+#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
+
+#define mainTIMER_TEST_PERIOD ( 50 )
/*
* Exercises code that is not otherwise covered by the standard demo/test
@@ -129,11 +129,11 @@
extern BaseType_t xRunCodeCoverageTestAdditions( void );
/* Task function prototypes. */
-static void prvCheckTask( void *pvParameters );
+static void prvCheckTask( void * pvParameters );
/* A task that is created from the idle task to test the functionality of
-eTaskStateGet(). */
-static void prvTestTask( void *pvParameters );
+ * eTaskStateGet(). */
+static void prvTestTask( void * pvParameters );
/*
* Called from the idle task hook function to demonstrate a few utility
@@ -151,7 +151,8 @@ static void prvDemonstratePendingFunctionCall( void );
/*
* The function that is pended by prvDemonstratePendingFunctionCall().
*/
-static void prvPendedFunction( void *pvParameter1, uint32_t ulParameter2 );
+static void prvPendedFunction( void * pvParameter1,
+ uint32_t ulParameter2 );
/*
* prvDemonstrateTimerQueryFunctions() is called from the idle task hook
@@ -165,747 +166,799 @@ static void prvTestTimerCallback( TimerHandle_t xTimer );
/*
* A task to demonstrate the use of the xQueueSpacesAvailable() function.
*/
-static void prvDemoQueueSpaceFunctions( void *pvParameters );
+static void prvDemoQueueSpaceFunctions( void * pvParameters );
/*
* Tasks that ensure indefinite delays are truly indefinite.
*/
-static void prvPermanentlyBlockingSemaphoreTask( void *pvParameters );
-static void prvPermanentlyBlockingNotificationTask( void *pvParameters );
+static void prvPermanentlyBlockingSemaphoreTask( void * pvParameters );
+static void prvPermanentlyBlockingNotificationTask( void * pvParameters );
/*
* The test function and callback function used when exercising the timer AP
* function that changes the timer's auto-reload mode.
*/
-static void prvDemonstrateChangingTimerReloadMode( void *pvParameters );
+static void prvDemonstrateChangingTimerReloadMode( void * pvParameters );
static void prvReloadModeTestTimerCallback( TimerHandle_t xTimer );
/*-----------------------------------------------------------*/
/* The variable into which error messages are latched. */
-static char *pcStatusMessage = "OK: No errors";
+static char * pcStatusMessage = "OK: No errors";
+int xErrorCount = 0;
/* This semaphore is created purely to test using the vSemaphoreDelete() and
-semaphore tracing API functions. It has no other purpose. */
+ * semaphore tracing API functions. It has no other purpose. */
static SemaphoreHandle_t xMutexToDelete = NULL;
/*-----------------------------------------------------------*/
int main_full( void )
{
- /* Start the check task as described at the top of this file. */
- xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
-
- /* Create the standard demo tasks. */
- vStartTaskNotifyTask();
- // vStartTaskNotifyArrayTask();
- vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
- vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
- vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );
- vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
- vStartQueuePeekTasks();
- vStartMathTasks( mainFLOP_TASK_PRIORITY );
- vStartRecursiveMutexTasks();
- vStartCountingSemaphoreTasks();
- vStartDynamicPriorityTasks();
- vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );
- vStartEventGroupTasks();
- vStartInterruptSemaphoreTasks();
- vCreateBlockTimeTasks();
- vCreateAbortDelayTasks();
- xTaskCreate( prvDemoQueueSpaceFunctions, "QSpace", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( prvPermanentlyBlockingSemaphoreTask, "BlockSem", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- xTaskCreate( prvPermanentlyBlockingNotificationTask, "BlockNoti", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
- vStartMessageBufferTasks( configMINIMAL_STACK_SIZE );
- vStartStreamBufferTasks();
- vStartStreamBufferInterruptDemo();
- vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE );
-
- #if( configUSE_QUEUE_SETS == 1 )
- {
- vStartQueueSetTasks();
- vStartQueueSetPollingTask();
- }
- #endif
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- vStartStaticallyAllocatedTasks();
- }
- #endif
-
- #if( configUSE_PREEMPTION != 0 )
- {
- /* Don't expect these tasks to pass when preemption is not used. */
- vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
- }
- #endif
-
- /* The suicide tasks must be created last as they need to know how many
- tasks were running prior to their creation. This then allows them to
- ascertain whether or not the correct/expected number of tasks are running at
- any given time. */
- vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
-
- /* Create the semaphore that will be deleted in the idle task hook. This
- is done purely to test the use of vSemaphoreDelete(). */
- xMutexToDelete = xSemaphoreCreateMutex();
-
- /* Start the scheduler itself. */
- vTaskStartScheduler();
-
- /* Should never get here unless there was not enough heap space to create
- the idle and other system tasks. */
- return 0;
+ /* Start the check task as described at the top of this file. */
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+ /* Create the standard demo tasks. */
+ vStartTaskNotifyTask();
+ /* vStartTaskNotifyArrayTask(); */
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+ vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
+ vStartQueuePeekTasks();
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );
+ vStartRecursiveMutexTasks();
+ vStartCountingSemaphoreTasks();
+ vStartDynamicPriorityTasks();
+ vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );
+ vStartEventGroupTasks();
+ vStartInterruptSemaphoreTasks();
+ vCreateBlockTimeTasks();
+ vCreateAbortDelayTasks();
+ xTaskCreate( prvDemoQueueSpaceFunctions, "QSpace", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvPermanentlyBlockingSemaphoreTask, "BlockSem", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( prvPermanentlyBlockingNotificationTask, "BlockNoti", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+ vStartMessageBufferTasks( configMINIMAL_STACK_SIZE );
+ vStartStreamBufferTasks();
+ vStartStreamBufferInterruptDemo();
+ vStartMessageBufferAMPTasks( configMINIMAL_STACK_SIZE );
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ vStartQueueSetTasks();
+ vStartQueueSetPollingTask();
+ }
+ #endif
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ vStartStaticallyAllocatedTasks();
+ }
+ #endif
+
+ #if ( configUSE_PREEMPTION != 0 )
+ {
+ /* Don't expect these tasks to pass when preemption is not used. */
+ vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
+ }
+ #endif
+
+ /* The suicide tasks must be created last as they need to know how many
+ * tasks were running prior to their creation. This then allows them to
+ * ascertain whether or not the correct/expected number of tasks are running at
+ * any given time. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Create the semaphore that will be deleted in the idle task hook. This
+ * is done purely to test the use of vSemaphoreDelete(). */
+ xMutexToDelete = xSemaphoreCreateMutex();
+
+ /* Start the scheduler itself. */
+ vTaskStartScheduler();
+
+ /* Should never get here unless there was not enough heap space to create
+ * the idle and other system tasks. */
+ return 0;
}
/*-----------------------------------------------------------*/
-static void prvCheckTask( void *pvParameters )
+static void prvCheckTask( void * pvParameters )
{
-TickType_t xNextWakeTime;
-const TickType_t xCycleFrequency = pdMS_TO_TICKS( 10000UL );
-HeapStats_t xHeapStats;
-
- /* Just to remove compiler warning. */
- ( void ) pvParameters;
-
- /* Initialise xNextWakeTime - this only needs to be done once. */
- xNextWakeTime = xTaskGetTickCount();
-
- for( ;; )
- {
- /* Place this task in the blocked state until it is time to run again. */
- vTaskDelayUntil( &xNextWakeTime, xCycleFrequency );
-
- /* Check the standard demo tasks are running without error. */
- #if( configUSE_PREEMPTION != 0 )
- {
- /* These tasks are only created when preemption is used. */
- if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE )
- {
- pcStatusMessage = "Error: TimerDemo";
- }
- }
- #endif
-
- if( xAreStreamBufferTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: StreamBuffer";
- }
- else if( xAreMessageBufferTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: MessageBuffer";
- }
- else if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: Notification";
- }
- // else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE )
- // {
- // pcStatusMessage = "Error: NotificationArray";
- // }
- else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: IntSem";
- }
- else if( xAreEventGroupTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: EventGroup";
- }
- else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: IntMath";
- }
- else if( xAreGenericQueueTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: GenQueue";
- }
- else if( xAreQueuePeekTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: QueuePeek";
- }
- else if( xAreBlockingQueuesStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: BlockQueue";
- }
- else if( xAreSemaphoreTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: SemTest";
- }
- else if( xArePollingQueuesStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: PollQueue";
- }
- else if( xAreMathsTaskStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Flop";
- }
- else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: RecMutex";
- }
- else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: CountSem";
- }
- else if( xIsCreateTaskStillRunning() != pdTRUE )
- {
- pcStatusMessage = "Error: Death";
- }
- else if( xAreDynamicPriorityTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Dynamic";
- }
- else if( xIsQueueOverwriteTaskStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Queue overwrite";
- }
- else if( xAreBlockTimeTestTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Block time";
- }
- else if( xAreAbortDelayTestTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Abort delay";
- }
- else if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Stream buffer interrupt";
- }
- else if( xAreMessageBufferAMPTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Message buffer AMP";
- }
-
- #if( configUSE_QUEUE_SETS == 1 )
- else if( xAreQueueSetTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Queue set";
- }
- else if( xAreQueueSetPollTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Queue set polling";
- }
- #endif
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- else if( xAreStaticAllocationTasksStillRunning() != pdPASS )
- {
- pcStatusMessage = "Error: Static allocation";
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
-
- printf( "%s - tick count %u \r\n",
- pcStatusMessage,
- xTaskGetTickCount() );
-
- // Reset the error condition
- pcStatusMessage = "OK: No errors";
- }
+ TickType_t xNextWakeTime;
+ const TickType_t xCycleFrequency = pdMS_TO_TICKS( 10000UL );
+ HeapStats_t xHeapStats;
+
+ /* Just to remove compiler warning. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ; ; )
+ {
+ /* Place this task in the blocked state until it is time to run again. */
+ vTaskDelayUntil( &xNextWakeTime, xCycleFrequency );
+
+ /* Check the standard demo tasks are running without error. */
+ #if ( configUSE_PREEMPTION != 0 )
+ {
+ /* These tasks are only created when preemption is used. */
+ if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE )
+ {
+ pcStatusMessage = "Error: TimerDemo";
+ xErrorCount++;
+ }
+ }
+ #endif
+
+ if( xAreStreamBufferTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: StreamBuffer";
+ xErrorCount++;
+ }
+ else if( xAreMessageBufferTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: MessageBuffer";
+ xErrorCount++;
+ }
+ else if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: Notification";
+ xErrorCount++;
+ }
+
+ /* else if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE )
+ * {
+ * pcStatusMessage = "Error: NotificationArray";
+ * xErrorCount++;
+ * } */
+ else if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: IntSem";
+ xErrorCount++;
+ }
+ else if( xAreEventGroupTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: EventGroup";
+ xErrorCount++;
+ }
+ else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: IntMath";
+ xErrorCount++;
+ }
+ else if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: GenQueue";
+ xErrorCount++;
+ }
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: QueuePeek";
+ xErrorCount++;
+ }
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: BlockQueue";
+ xErrorCount++;
+ }
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: SemTest";
+ xErrorCount++;
+ }
+ else if( xArePollingQueuesStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: PollQueue";
+ xErrorCount++;
+ }
+ else if( xAreMathsTaskStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Flop";
+ xErrorCount++;
+ }
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: RecMutex";
+ xErrorCount++;
+ }
+ else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: CountSem";
+ xErrorCount++;
+ }
+ else if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ pcStatusMessage = "Error: Death";
+ xErrorCount++;
+ }
+ else if( xAreDynamicPriorityTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Dynamic";
+ xErrorCount++;
+ }
+ else if( xIsQueueOverwriteTaskStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Queue overwrite";
+ xErrorCount++;
+ }
+ else if( xAreBlockTimeTestTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Block time";
+ xErrorCount++;
+ }
+ else if( xAreAbortDelayTestTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Abort delay";
+ xErrorCount++;
+ }
+ else if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Stream buffer interrupt";
+ xErrorCount++;
+ }
+ else if( xAreMessageBufferAMPTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Message buffer AMP";
+ xErrorCount++;
+ }
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ else if( xAreQueueSetTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Queue set";
+ xErrorCount++;
+ }
+ else if( xAreQueueSetPollTasksStillRunning() != pdPASS )
+ {
+ pcStatusMessage = "Error: Queue set polling";
+ xErrorCount++;
+ }
+ #endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+
+ #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+ else if( xAreStaticAllocationTasksStillRunning() != pdPASS )
+ {
+ xErrorCount++;
+ pcStatusMessage = "Error: Static allocation";
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ printf( "%s - tick count %u \r\n",
+ pcStatusMessage,
+ xTaskGetTickCount() );
+
+ if( xErrorCount != 0 )
+ {
+ exit( 1 );
+ }
+
+ /* Reset the error condition */
+ pcStatusMessage = "OK: No errors";
+ }
}
/*-----------------------------------------------------------*/
-static void prvTestTask( void *pvParameters )
+static void prvTestTask( void * pvParameters )
{
-const unsigned long ulMSToSleep = 5;
+ const unsigned long ulMSToSleep = 5;
- /* Just to remove compiler warnings. */
- ( void ) pvParameters;
+ /* Just to remove compiler warnings. */
+ ( void ) pvParameters;
- /* This task is just used to test the eTaskStateGet() function. It
- does not have anything to do. */
- for( ;; )
- {
- /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are
- tasks waiting to be terminated by the idle task. */
+ /* This task is just used to test the eTaskStateGet() function. It
+ * does not have anything to do. */
+ for( ; ; )
+ {
+ /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are
+ * tasks waiting to be terminated by the idle task. */
struct timespec ts;
- ts.tv_sec = ulMSToSleep / 1000;
- ts.tv_nsec = ulMSToSleep % 1000l * 1000000l;
- nanosleep( &ts, NULL );
- }
+ ts.tv_sec = ulMSToSleep / 1000;
+ ts.tv_nsec = ulMSToSleep % 1000l * 1000000l;
+ nanosleep( &ts, NULL );
+ }
}
/*-----------------------------------------------------------*/
/* Called from vApplicationIdleHook(), which is defined in main.c. */
void vFullDemoIdleFunction( void )
{
-const unsigned long ulMSToSleep = 15;
-void *pvAllocated;
-
- /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are
- tasks waiting to be terminated by the idle task. */
- struct timespec ts;
- ts.tv_sec = ulMSToSleep / 1000;
- ts.tv_nsec = ulMSToSleep % 1000l * 1000000l;
- nanosleep( &ts, NULL );
-
- /* Demonstrate a few utility functions that are not demonstrated by any of
- the standard demo tasks. */
- prvDemonstrateTaskStateAndHandleGetFunctions();
-
- /* Demonstrate the use of xTimerPendFunctionCall(), which is not
- demonstrated by any of the standard demo tasks. */
- prvDemonstratePendingFunctionCall();
-
- /* Demonstrate the use of functions that query information about a software
- timer. */
- prvDemonstrateTimerQueryFunctions();
-
- /* If xMutexToDelete has not already been deleted, then delete it now.
- This is done purely to demonstrate the use of, and test, the
- vSemaphoreDelete() macro. Care must be taken not to delete a semaphore
- that has tasks blocked on it. */
- if( xMutexToDelete != NULL )
- {
- /* For test purposes, add the mutex to the registry, then remove it
- again, before it is deleted - checking its name is as expected before
- and after the assertion into the registry and its removal from the
- registry. */
- configASSERT( pcQueueGetName( xMutexToDelete ) == NULL );
- vQueueAddToRegistry( xMutexToDelete, "Test_Mutex" );
- configASSERT( strcmp( pcQueueGetName( xMutexToDelete ), "Test_Mutex" ) == 0 );
- vQueueUnregisterQueue( xMutexToDelete );
- configASSERT( pcQueueGetName( xMutexToDelete ) == NULL );
-
- vSemaphoreDelete( xMutexToDelete );
- xMutexToDelete = NULL;
- }
-
- /* Exercise heap_5 a bit. The malloc failed hook will trap failed
- allocations so there is no need to test here. */
- pvAllocated = pvPortMalloc( ( rand() % 500 ) + 1 );
- vPortFree( pvAllocated );
-
- /* Exit after a fixed time so code coverage results are written to the
- disk. */
- #if( projCOVERAGE_TEST == 1 )
- {
- const TickType_t xMaxRunTime = pdMS_TO_TICKS( 30000UL );
-
- /* Exercise code not otherwise executed by standard demo/test tasks. */
- if( xRunCodeCoverageTestAdditions() != pdPASS )
- {
- pcStatusMessage = "Code coverage additions failed.\r\n";
- }
-
- if( ( xTaskGetTickCount() - configINITIAL_TICK_COUNT ) >= xMaxRunTime )
- {
- vTaskEndScheduler();
- }
- }
- #endif
+ const unsigned long ulMSToSleep = 15;
+ void * pvAllocated;
+
+ /* Sleep to reduce CPU load, but don't sleep indefinitely in case there are
+ * tasks waiting to be terminated by the idle task. */
+ struct timespec ts;
+
+ ts.tv_sec = ulMSToSleep / 1000;
+ ts.tv_nsec = ulMSToSleep % 1000l * 1000000l;
+ nanosleep( &ts, NULL );
+
+ /* Demonstrate a few utility functions that are not demonstrated by any of
+ * the standard demo tasks. */
+ prvDemonstrateTaskStateAndHandleGetFunctions();
+
+ /* Demonstrate the use of xTimerPendFunctionCall(), which is not
+ * demonstrated by any of the standard demo tasks. */
+ prvDemonstratePendingFunctionCall();
+
+ /* Demonstrate the use of functions that query information about a software
+ * timer. */
+ prvDemonstrateTimerQueryFunctions();
+
+ /* If xMutexToDelete has not already been deleted, then delete it now.
+ * This is done purely to demonstrate the use of, and test, the
+ * vSemaphoreDelete() macro. Care must be taken not to delete a semaphore
+ * that has tasks blocked on it. */
+ if( xMutexToDelete != NULL )
+ {
+ /* For test purposes, add the mutex to the registry, then remove it
+ * again, before it is deleted - checking its name is as expected before
+ * and after the assertion into the registry and its removal from the
+ * registry. */
+ configASSERT( pcQueueGetName( xMutexToDelete ) == NULL );
+ vQueueAddToRegistry( xMutexToDelete, "Test_Mutex" );
+ configASSERT( strcmp( pcQueueGetName( xMutexToDelete ), "Test_Mutex" ) == 0 );
+ vQueueUnregisterQueue( xMutexToDelete );
+ configASSERT( pcQueueGetName( xMutexToDelete ) == NULL );
+
+ vSemaphoreDelete( xMutexToDelete );
+ xMutexToDelete = NULL;
+ }
+
+ /* Exercise heap_5 a bit. The malloc failed hook will trap failed
+ * allocations so there is no need to test here. */
+ pvAllocated = pvPortMalloc( ( rand() % 500 ) + 1 );
+ vPortFree( pvAllocated );
+
+ /* Exit after a fixed time so code coverage results are written to the
+ * disk. */
+ #if ( projCOVERAGE_TEST == 1 )
+ {
+ const TickType_t xMaxRunTime = pdMS_TO_TICKS( 30000UL );
+
+ /* Exercise code not otherwise executed by standard demo/test tasks. */
+ if( xRunCodeCoverageTestAdditions() != pdPASS )
+ {
+ pcStatusMessage = "Code coverage additions failed.\r\n";
+ xErrorCount++;
+ }
+
+ if( ( xTaskGetTickCount() - configINITIAL_TICK_COUNT ) >= xMaxRunTime )
+ {
+ vTaskEndScheduler();
+ }
+ }
+ #endif /* if ( projCOVERAGE_TEST == 1 ) */
}
/*-----------------------------------------------------------*/
/* Called by vApplicationTickHook(), which is defined in main.c. */
void vFullDemoTickHookFunction( void )
{
-TaskHandle_t xTimerTask;
-
- /* Call the periodic timer test, which tests the timer API functions that
- can be called from an ISR. */
- #if( configUSE_PREEMPTION != 0 )
- {
- /* Only created when preemption is used. */
- vTimerPeriodicISRTests();
- }
- #endif
-
- /* Call the periodic queue overwrite from ISR demo. */
- vQueueOverwritePeriodicISRDemo();
-
- #if( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */
- {
- /* Write to a queue that is in use as part of the queue set demo to
- demonstrate using queue sets from an ISR. */
- vQueueSetAccessQueueSetFromISR();
- vQueueSetPollingInterruptAccess();
- }
- #endif
-
- /* Exercise event groups from interrupts. */
- vPeriodicEventGroupsProcessing();
-
- /* Exercise giving mutexes from an interrupt. */
- vInterruptSemaphorePeriodicTest();
-
- /* Exercise using task notifications from an interrupt. */
- xNotifyTaskFromISR();
- // xNotifyArrayTaskFromISR();
-
- /* Writes to stream buffer byte by byte to test the stream buffer trigger
- level functionality. */
- vPeriodicStreamBufferProcessing();
-
- /* Writes a string to a string buffer four bytes at a time to demonstrate
- a stream being sent from an interrupt to a task. */
- vBasicStreamBufferSendFromISR();
-
- /* For code coverage purposes. */
- xTimerTask = xTimerGetTimerDaemonTaskHandle();
- configASSERT( uxTaskPriorityGetFromISR( xTimerTask ) == configTIMER_TASK_PRIORITY );
+ TaskHandle_t xTimerTask;
+
+ /* Call the periodic timer test, which tests the timer API functions that
+ * can be called from an ISR. */
+ #if ( configUSE_PREEMPTION != 0 )
+ {
+ /* Only created when preemption is used. */
+ vTimerPeriodicISRTests();
+ }
+ #endif
+
+ /* Call the periodic queue overwrite from ISR demo. */
+ vQueueOverwritePeriodicISRDemo();
+
+ #if ( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */
+ {
+ /* Write to a queue that is in use as part of the queue set demo to
+ * demonstrate using queue sets from an ISR. */
+ vQueueSetAccessQueueSetFromISR();
+ vQueueSetPollingInterruptAccess();
+ }
+ #endif
+
+ /* Exercise event groups from interrupts. */
+ vPeriodicEventGroupsProcessing();
+
+ /* Exercise giving mutexes from an interrupt. */
+ vInterruptSemaphorePeriodicTest();
+
+ /* Exercise using task notifications from an interrupt. */
+ xNotifyTaskFromISR();
+ /* xNotifyArrayTaskFromISR(); */
+
+ /* Writes to stream buffer byte by byte to test the stream buffer trigger
+ * level functionality. */
+ vPeriodicStreamBufferProcessing();
+
+ /* Writes a string to a string buffer four bytes at a time to demonstrate
+ * a stream being sent from an interrupt to a task. */
+ vBasicStreamBufferSendFromISR();
+
+ /* For code coverage purposes. */
+ xTimerTask = xTimerGetTimerDaemonTaskHandle();
+ configASSERT( uxTaskPriorityGetFromISR( xTimerTask ) == configTIMER_TASK_PRIORITY );
}
/*-----------------------------------------------------------*/
-static void prvPendedFunction( void *pvParameter1, uint32_t ulParameter2 )
+static void prvPendedFunction( void * pvParameter1,
+ uint32_t ulParameter2 )
{
-static intptr_t ulLastParameter1 = 1000UL, ulLastParameter2 = 0UL;
-intptr_t ulParameter1;
+ static intptr_t ulLastParameter1 = 1000UL, ulLastParameter2 = 0UL;
+ intptr_t ulParameter1;
- ulParameter1 = ( intptr_t ) pvParameter1;
+ ulParameter1 = ( intptr_t ) pvParameter1;
- /* Ensure the parameters are as expected. */
- configASSERT( ulParameter1 == ( ulLastParameter1 + 1 ) );
- configASSERT( ulParameter2 == ( ulLastParameter2 + 1 ) );
+ /* Ensure the parameters are as expected. */
+ configASSERT( ulParameter1 == ( ulLastParameter1 + 1 ) );
+ configASSERT( ulParameter2 == ( ulLastParameter2 + 1 ) );
- /* Remember the parameters for the next time the function is called. */
- ulLastParameter1 = ulParameter1;
- ulLastParameter2 = ulParameter2;
+ /* Remember the parameters for the next time the function is called. */
+ ulLastParameter1 = ulParameter1;
+ ulLastParameter2 = ulParameter2;
- /* Remove compiler warnings in case configASSERT() is not defined. */
- ( void ) ulLastParameter1;
- ( void ) ulLastParameter2;
+ /* Remove compiler warnings in case configASSERT() is not defined. */
+ ( void ) ulLastParameter1;
+ ( void ) ulLastParameter2;
}
/*-----------------------------------------------------------*/
static void prvTestTimerCallback( TimerHandle_t xTimer )
{
- /* This is the callback function for the timer accessed by
- prvDemonstrateTimerQueryFunctions(). The callback does not do anything. */
- ( void ) xTimer;
+ /* This is the callback function for the timer accessed by
+ * prvDemonstrateTimerQueryFunctions(). The callback does not do anything. */
+ ( void ) xTimer;
}
/*-----------------------------------------------------------*/
static void prvDemonstrateTimerQueryFunctions( void )
{
-static TimerHandle_t xTimer = NULL;
-const char *pcTimerName = "TestTimer";
-volatile TickType_t xExpiryTime;
-const TickType_t xDontBlock = 0;
-
- if( xTimer == NULL )
- {
- xTimer = xTimerCreate( pcTimerName, portMAX_DELAY, pdTRUE, NULL, prvTestTimerCallback );
-
- if( xTimer != NULL )
- {
- /* Called from the idle task so a block time must not be
- specified. */
- xTimerStart( xTimer, xDontBlock );
- }
- }
-
- if( xTimer != NULL )
- {
- /* Demonstrate querying a timer's name. */
- configASSERT( strcmp( pcTimerGetName( xTimer ), pcTimerName ) == 0 );
-
- /* Demonstrate querying a timer's period. */
- configASSERT( xTimerGetPeriod( xTimer ) == portMAX_DELAY );
-
- /* Demonstrate querying a timer's next expiry time, although nothing is
- done with the returned value. Note if the expiry time is less than the
- maximum tick count then the expiry time has overflowed from the current
- time. In this case the expiry time was set to portMAX_DELAY, so it is
- expected to be less than the current time until the current time has
- itself overflowed. */
- xExpiryTime = xTimerGetExpiryTime( xTimer );
- ( void ) xExpiryTime;
- }
+ static TimerHandle_t xTimer = NULL;
+ const char * pcTimerName = "TestTimer";
+ volatile TickType_t xExpiryTime;
+ const TickType_t xDontBlock = 0;
+
+ if( xTimer == NULL )
+ {
+ xTimer = xTimerCreate( pcTimerName, portMAX_DELAY, pdTRUE, NULL, prvTestTimerCallback );
+
+ if( xTimer != NULL )
+ {
+ /* Called from the idle task so a block time must not be
+ * specified. */
+ xTimerStart( xTimer, xDontBlock );
+ }
+ }
+
+ if( xTimer != NULL )
+ {
+ /* Demonstrate querying a timer's name. */
+ configASSERT( strcmp( pcTimerGetName( xTimer ), pcTimerName ) == 0 );
+
+ /* Demonstrate querying a timer's period. */
+ configASSERT( xTimerGetPeriod( xTimer ) == portMAX_DELAY );
+
+ /* Demonstrate querying a timer's next expiry time, although nothing is
+ * done with the returned value. Note if the expiry time is less than the
+ * maximum tick count then the expiry time has overflowed from the current
+ * time. In this case the expiry time was set to portMAX_DELAY, so it is
+ * expected to be less than the current time until the current time has
+ * itself overflowed. */
+ xExpiryTime = xTimerGetExpiryTime( xTimer );
+ ( void ) xExpiryTime;
+ }
}
/*-----------------------------------------------------------*/
static void prvDemonstratePendingFunctionCall( void )
{
-static intptr_t ulParameter1 = 1000UL, ulParameter2 = 0UL;
-const TickType_t xDontBlock = 0; /* This is called from the idle task so must *not* attempt to block. */
+ static intptr_t ulParameter1 = 1000UL, ulParameter2 = 0UL;
+ const TickType_t xDontBlock = 0; /* This is called from the idle task so must *not* attempt to block. */
- /* prvPendedFunction() just expects the parameters to be incremented by one
- each time it is called. */
- ulParameter1++;
- ulParameter2++;
+ /* prvPendedFunction() just expects the parameters to be incremented by one
+ * each time it is called. */
- /* Pend the function call, sending the parameters. */
- xTimerPendFunctionCall( prvPendedFunction, ( void * ) ulParameter1, ulParameter2, xDontBlock );
+ ulParameter1++;
+ ulParameter2++;
+
+ /* Pend the function call, sending the parameters. */
+ xTimerPendFunctionCall( prvPendedFunction, ( void * ) ulParameter1, ulParameter2, xDontBlock );
}
/*-----------------------------------------------------------*/
static void prvDemonstrateTaskStateAndHandleGetFunctions( void )
{
-TaskHandle_t xIdleTaskHandle, xTimerTaskHandle;
-char *pcTaskName;
-static portBASE_TYPE xPerformedOneShotTests = pdFALSE;
-TaskHandle_t xTestTask;
-TaskStatus_t xTaskInfo;
-extern StackType_t uxTimerTaskStack[];
-
- /* Demonstrate the use of the xTimerGetTimerDaemonTaskHandle() and
- xTaskGetIdleTaskHandle() functions. Also try using the function that sets
- the task number. */
- xIdleTaskHandle = xTaskGetIdleTaskHandle();
- xTimerTaskHandle = xTimerGetTimerDaemonTaskHandle();
-
- /* This is the idle hook, so the current task handle should equal the
- returned idle task handle. */
- if( xTaskGetCurrentTaskHandle() != xIdleTaskHandle )
- {
- pcStatusMessage = "Error: Returned idle task handle was incorrect";
- }
-
- /* Check the same handle is obtained using the idle task's name. First try
- with the wrong name, then the right name. */
- if( xTaskGetHandle( "Idle" ) == xIdleTaskHandle )
- {
- pcStatusMessage = "Error: Returned handle for name Idle was incorrect";
- }
-
- if( xTaskGetHandle( "IDLE" ) != xIdleTaskHandle )
- {
- pcStatusMessage = "Error: Returned handle for name Idle was incorrect";
- }
-
- /* Check the timer task handle was returned correctly. */
- pcTaskName = pcTaskGetName( xTimerTaskHandle );
- if( strcmp( pcTaskName, "Tmr Svc" ) != 0 )
- {
- pcStatusMessage = "Error: Returned timer task handle was incorrect";
- }
-
- if( xTaskGetHandle( "Tmr Svc" ) != xTimerTaskHandle )
- {
- pcStatusMessage = "Error: Returned handle for name Tmr Svc was incorrect";
- }
-
- /* This task is running, make sure it's state is returned as running. */
- if( eTaskStateGet( xIdleTaskHandle ) != eRunning )
- {
- pcStatusMessage = "Error: Returned idle task state was incorrect";
- }
-
- /* If this task is running, then the timer task must be blocked. */
- if( eTaskStateGet( xTimerTaskHandle ) != eBlocked )
- {
- pcStatusMessage = "Error: Returned timer task state was incorrect";
- }
-
- /* Also with the vTaskGetInfo() function. */
- vTaskGetInfo( xTimerTaskHandle, /* The task being queried. */
- &xTaskInfo, /* The structure into which information on the task will be written. */
- pdTRUE, /* Include the task's high watermark in the structure. */
- eInvalid ); /* Include the task state in the structure. */
-
- /* Check the information returned by vTaskGetInfo() is as expected. */
- if( ( xTaskInfo.eCurrentState != eBlocked ) ||
- ( strcmp( xTaskInfo.pcTaskName, "Tmr Svc" ) != 0 ) ||
- ( xTaskInfo.uxCurrentPriority != configTIMER_TASK_PRIORITY ) ||
- ( xTaskInfo.pxStackBase != uxTimerTaskStack ) ||
- ( xTaskInfo.xHandle != xTimerTaskHandle ) )
- {
- pcStatusMessage = "Error: vTaskGetInfo() returned incorrect information about the timer task";
- }
-
- /* Other tests that should only be performed once follow. The test task
- is not created on each iteration because to do so would cause the death
- task to report an error (too many tasks running). */
- if( xPerformedOneShotTests == pdFALSE )
- {
- /* Don't run this part of the test again. */
- xPerformedOneShotTests = pdTRUE;
-
- /* Create a test task to use to test other eTaskStateGet() return values. */
- if( xTaskCreate( prvTestTask, "Test", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTestTask ) == pdPASS )
- {
- /* If this task is running, the test task must be in the ready state. */
- if( eTaskStateGet( xTestTask ) != eReady )
- {
- pcStatusMessage = "Error: Returned test task state was incorrect 1";
- }
-
- /* Now suspend the test task and check its state is reported correctly. */
- vTaskSuspend( xTestTask );
- if( eTaskStateGet( xTestTask ) != eSuspended )
- {
- pcStatusMessage = "Error: Returned test task state was incorrect 2";
- }
-
- /* Now delete the task and check its state is reported correctly. */
- vTaskDelete( xTestTask );
- if( eTaskStateGet( xTestTask ) != eDeleted )
- {
- pcStatusMessage = "Error: Returned test task state was incorrect 3";
- }
- }
- }
+ TaskHandle_t xIdleTaskHandle, xTimerTaskHandle;
+ char * pcTaskName;
+ static portBASE_TYPE xPerformedOneShotTests = pdFALSE;
+ TaskHandle_t xTestTask;
+ TaskStatus_t xTaskInfo;
+ extern StackType_t uxTimerTaskStack[];
+
+ /* Demonstrate the use of the xTimerGetTimerDaemonTaskHandle() and
+ * xTaskGetIdleTaskHandle() functions. Also try using the function that sets
+ * the task number. */
+ xIdleTaskHandle = xTaskGetIdleTaskHandle();
+ xTimerTaskHandle = xTimerGetTimerDaemonTaskHandle();
+
+ /* This is the idle hook, so the current task handle should equal the
+ * returned idle task handle. */
+ if( xTaskGetCurrentTaskHandle() != xIdleTaskHandle )
+ {
+ pcStatusMessage = "Error: Returned idle task handle was incorrect";
+ xErrorCount++;
+ }
+
+ /* Check the same handle is obtained using the idle task's name. First try
+ * with the wrong name, then the right name. */
+ if( xTaskGetHandle( "Idle" ) == xIdleTaskHandle )
+ {
+ pcStatusMessage = "Error: Returned handle for name Idle was incorrect";
+ xErrorCount++;
+ }
+
+ if( xTaskGetHandle( "IDLE" ) != xIdleTaskHandle )
+ {
+ pcStatusMessage = "Error: Returned handle for name Idle was incorrect";
+ xErrorCount++;
+ }
+
+ /* Check the timer task handle was returned correctly. */
+ pcTaskName = pcTaskGetName( xTimerTaskHandle );
+
+ if( strcmp( pcTaskName, "Tmr Svc" ) != 0 )
+ {
+ pcStatusMessage = "Error: Returned timer task handle was incorrect";
+ xErrorCount++;
+ }
+
+ if( xTaskGetHandle( "Tmr Svc" ) != xTimerTaskHandle )
+ {
+ pcStatusMessage = "Error: Returned handle for name Tmr Svc was incorrect";
+ xErrorCount++;
+ }
+
+ /* This task is running, make sure it's state is returned as running. */
+ if( eTaskStateGet( xIdleTaskHandle ) != eRunning )
+ {
+ pcStatusMessage = "Error: Returned idle task state was incorrect";
+ xErrorCount++;
+ }
+
+ /* If this task is running, then the timer task must be blocked. */
+ if( eTaskStateGet( xTimerTaskHandle ) != eBlocked )
+ {
+ pcStatusMessage = "Error: Returned timer task state was incorrect";
+ xErrorCount++;
+ }
+
+ /* Also with the vTaskGetInfo() function. */
+ vTaskGetInfo( xTimerTaskHandle, /* The task being queried. */
+ &xTaskInfo, /* The structure into which information on the task will be written. */
+ pdTRUE, /* Include the task's high watermark in the structure. */
+ eInvalid ); /* Include the task state in the structure. */
+
+ /* Check the information returned by vTaskGetInfo() is as expected. */
+ if( ( xTaskInfo.eCurrentState != eBlocked ) ||
+ ( strcmp( xTaskInfo.pcTaskName, "Tmr Svc" ) != 0 ) ||
+ ( xTaskInfo.uxCurrentPriority != configTIMER_TASK_PRIORITY ) ||
+ ( xTaskInfo.pxStackBase != uxTimerTaskStack ) ||
+ ( xTaskInfo.xHandle != xTimerTaskHandle ) )
+ {
+ pcStatusMessage = "Error: vTaskGetInfo() returned incorrect information about the timer task";
+ xErrorCount++;
+ }
+
+ /* Other tests that should only be performed once follow. The test task
+ * is not created on each iteration because to do so would cause the death
+ * task to report an error (too many tasks running). */
+ if( xPerformedOneShotTests == pdFALSE )
+ {
+ /* Don't run this part of the test again. */
+ xPerformedOneShotTests = pdTRUE;
+
+ /* Create a test task to use to test other eTaskStateGet() return values. */
+ if( xTaskCreate( prvTestTask, "Test", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTestTask ) == pdPASS )
+ {
+ /* If this task is running, the test task must be in the ready state. */
+ if( eTaskStateGet( xTestTask ) != eReady )
+ {
+ pcStatusMessage = "Error: Returned test task state was incorrect 1";
+ xErrorCount++;
+ }
+
+ /* Now suspend the test task and check its state is reported correctly. */
+ vTaskSuspend( xTestTask );
+
+ if( eTaskStateGet( xTestTask ) != eSuspended )
+ {
+ pcStatusMessage = "Error: Returned test task state was incorrect 2";
+ xErrorCount++;
+ }
+
+ /* Now delete the task and check its state is reported correctly. */
+ vTaskDelete( xTestTask );
+
+ if( eTaskStateGet( xTestTask ) != eDeleted )
+ {
+ pcStatusMessage = "Error: Returned test task state was incorrect 3";
+ xErrorCount++;
+ }
+ }
+ }
}
/*-----------------------------------------------------------*/
-static void prvDemoQueueSpaceFunctions( void *pvParameters )
+static void prvDemoQueueSpaceFunctions( void * pvParameters )
{
-QueueHandle_t xQueue = NULL;
-const unsigned portBASE_TYPE uxQueueLength = 10;
-unsigned portBASE_TYPE uxReturn, x;
-
- /* Remove compiler warnings. */
- ( void ) pvParameters;
-
- /* Create the queue that will be used. Nothing is actually going to be
- sent or received so the queue item size is set to 0. */
- xQueue = xQueueCreate( uxQueueLength, 0 );
- configASSERT( xQueue );
-
- for( ;; )
- {
- for( x = 0; x < uxQueueLength; x++ )
- {
- /* Ask how many messages are available... */
- uxReturn = uxQueueMessagesWaiting( xQueue );
-
- /* Check the number of messages being reported as being available
- is as expected, and force an assert if not. */
- if( uxReturn != x )
- {
- /* xQueue cannot be NULL so this is deliberately causing an
- assert to be triggered as there is an error. */
- configASSERT( xQueue == NULL );
- }
-
- /* Ask how many spaces remain in the queue... */
- uxReturn = uxQueueSpacesAvailable( xQueue );
-
- /* Check the number of spaces being reported as being available
- is as expected, and force an assert if not. */
- if( uxReturn != ( uxQueueLength - x ) )
- {
- /* xQueue cannot be NULL so this is deliberately causing an
- assert to be triggered as there is an error. */
- configASSERT( xQueue == NULL );
- }
-
- /* Fill one more space in the queue. */
- xQueueSendToBack( xQueue, NULL, 0 );
- }
-
- /* Perform the same check while the queue is full. */
- uxReturn = uxQueueMessagesWaiting( xQueue );
- if( uxReturn != uxQueueLength )
- {
- configASSERT( xQueue == NULL );
- }
-
- uxReturn = uxQueueSpacesAvailable( xQueue );
-
- if( uxReturn != 0 )
- {
- configASSERT( xQueue == NULL );
- }
-
- /* The queue is full, start again. */
- xQueueReset( xQueue );
-
- #if( configUSE_PREEMPTION == 0 )
- taskYIELD();
- #endif
- }
+ QueueHandle_t xQueue = NULL;
+ const unsigned portBASE_TYPE uxQueueLength = 10;
+ unsigned portBASE_TYPE uxReturn, x;
+
+ /* Remove compiler warnings. */
+ ( void ) pvParameters;
+
+ /* Create the queue that will be used. Nothing is actually going to be
+ * sent or received so the queue item size is set to 0. */
+ xQueue = xQueueCreate( uxQueueLength, 0 );
+ configASSERT( xQueue );
+
+ for( ; ; )
+ {
+ for( x = 0; x < uxQueueLength; x++ )
+ {
+ /* Ask how many messages are available... */
+ uxReturn = uxQueueMessagesWaiting( xQueue );
+
+ /* Check the number of messages being reported as being available
+ * is as expected, and force an assert if not. */
+ if( uxReturn != x )
+ {
+ /* xQueue cannot be NULL so this is deliberately causing an
+ * assert to be triggered as there is an error. */
+ configASSERT( xQueue == NULL );
+ }
+
+ /* Ask how many spaces remain in the queue... */
+ uxReturn = uxQueueSpacesAvailable( xQueue );
+
+ /* Check the number of spaces being reported as being available
+ * is as expected, and force an assert if not. */
+ if( uxReturn != ( uxQueueLength - x ) )
+ {
+ /* xQueue cannot be NULL so this is deliberately causing an
+ * assert to be triggered as there is an error. */
+ configASSERT( xQueue == NULL );
+ }
+
+ /* Fill one more space in the queue. */
+ xQueueSendToBack( xQueue, NULL, 0 );
+ }
+
+ /* Perform the same check while the queue is full. */
+ uxReturn = uxQueueMessagesWaiting( xQueue );
+
+ if( uxReturn != uxQueueLength )
+ {
+ configASSERT( xQueue == NULL );
+ }
+
+ uxReturn = uxQueueSpacesAvailable( xQueue );
+
+ if( uxReturn != 0 )
+ {
+ configASSERT( xQueue == NULL );
+ }
+
+ /* The queue is full, start again. */
+ xQueueReset( xQueue );
+
+ #if ( configUSE_PREEMPTION == 0 )
+ taskYIELD();
+ #endif
+ }
}
/*-----------------------------------------------------------*/
-static void prvPermanentlyBlockingSemaphoreTask( void *pvParameters )
+static void prvPermanentlyBlockingSemaphoreTask( void * pvParameters )
{
-SemaphoreHandle_t xSemaphore;
+ SemaphoreHandle_t xSemaphore;
- /* Prevent compiler warning about unused parameter in the case that
- configASSERT() is not defined. */
- ( void ) pvParameters;
+ /* Prevent compiler warning about unused parameter in the case that
+ * configASSERT() is not defined. */
+ ( void ) pvParameters;
- /* This task should block on a semaphore, and never return. */
- xSemaphore = xSemaphoreCreateBinary();
- configASSERT( xSemaphore );
+ /* This task should block on a semaphore, and never return. */
+ xSemaphore = xSemaphoreCreateBinary();
+ configASSERT( xSemaphore );
- xSemaphoreTake( xSemaphore, portMAX_DELAY );
+ xSemaphoreTake( xSemaphore, portMAX_DELAY );
- /* The above xSemaphoreTake() call should never return, force an assert if
- it does. */
- configASSERT( pvParameters != NULL );
- vTaskDelete( NULL );
+ /* The above xSemaphoreTake() call should never return, force an assert if
+ * it does. */
+ configASSERT( pvParameters != NULL );
+ vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
-static void prvPermanentlyBlockingNotificationTask( void *pvParameters )
+static void prvPermanentlyBlockingNotificationTask( void * pvParameters )
{
- /* Prevent compiler warning about unused parameter in the case that
- configASSERT() is not defined. */
- ( void ) pvParameters;
+ /* Prevent compiler warning about unused parameter in the case that
+ * configASSERT() is not defined. */
+ ( void ) pvParameters;
- /* This task should block on a task notification, and never return. */
- ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
+ /* This task should block on a task notification, and never return. */
+ ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
- /* The above ulTaskNotifyTake() call should never return, force an assert
- if it does. */
- configASSERT( pvParameters != NULL );
- vTaskDelete( NULL );
+ /* The above ulTaskNotifyTake() call should never return, force an assert
+ * if it does. */
+ configASSERT( pvParameters != NULL );
+ vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvReloadModeTestTimerCallback( TimerHandle_t xTimer )
{
-intptr_t ulTimerID;
+ intptr_t ulTimerID;
- /* Increment the timer's ID to show the callback has executed. */
- ulTimerID = ( intptr_t ) pvTimerGetTimerID( xTimer );
- ulTimerID++;
- vTimerSetTimerID( xTimer, ( void * ) ulTimerID );
+ /* Increment the timer's ID to show the callback has executed. */
+ ulTimerID = ( intptr_t ) pvTimerGetTimerID( xTimer );
+ ulTimerID++;
+ vTimerSetTimerID( xTimer, ( void * ) ulTimerID );
}
/*-----------------------------------------------------------*/
-static void prvDemonstrateChangingTimerReloadMode( void *pvParameters )
+static void prvDemonstrateChangingTimerReloadMode( void * pvParameters )
{
-TimerHandle_t xTimer;
-const char * const pcTimerName = "TestTimer";
-const TickType_t x100ms = pdMS_TO_TICKS( 100UL );
-
- /* Avoid compiler warnings about unused parameter. */
- ( void ) pvParameters;
-
- xTimer = xTimerCreate( pcTimerName,
- x100ms,
- pdFALSE, /* Created as a one-shot timer. */
- 0,
- prvReloadModeTestTimerCallback );
- configASSERT( xTimer );
- configASSERT( xTimerIsTimerActive( xTimer ) == pdFALSE );
- configASSERT( xTimerGetTimerDaemonTaskHandle() != NULL );
- configASSERT( strcmp( pcTimerName, pcTimerGetName( xTimer ) ) == 0 );
- configASSERT( xTimerGetPeriod( xTimer ) == x100ms );
-
- /* Timer was created as a one-shot timer. Its callback just increments the
- timer's ID - so set the ID to 0, let the timer run for a number of timeout
- periods, then check the timer has only executed once. */
- vTimerSetTimerID( xTimer, ( void * ) 0 );
- xTimerStart( xTimer, portMAX_DELAY );
- vTaskDelay( 3UL * x100ms );
- configASSERT( ( ( uintptr_t ) ( pvTimerGetTimerID( xTimer ) ) ) == 1UL );
-
- /* Now change the timer to be an auto-reload timer and check it executes
- the expected number of times. */
- vTimerSetReloadMode( xTimer, pdTRUE );
- vTimerSetTimerID( xTimer, ( void * ) 0 );
- xTimerStart( xTimer, 0 );
- vTaskDelay( ( 3UL * x100ms ) + ( x100ms / 2UL ) ); /* Three full periods. */
- configASSERT( ( uintptr_t ) ( pvTimerGetTimerID( xTimer ) ) == 3UL );
- configASSERT( xTimerStop( xTimer, 0 ) != pdFAIL );
-
- /* Now change the timer back to be a one-shot timer and check it only
- executes once. */
- vTimerSetReloadMode( xTimer, pdFALSE );
- vTimerSetTimerID( xTimer, ( void * ) 0 );
- xTimerStart( xTimer, 0 );
- vTaskDelay( 3UL * x100ms );
- configASSERT( xTimerStop( xTimer, 0 ) != pdFAIL );
- configASSERT( ( uintptr_t ) ( pvTimerGetTimerID( xTimer ) ) == 1UL );
-
- /* Clean up at the end. */
- xTimerDelete( xTimer, portMAX_DELAY );
- vTaskDelete( NULL );
+ TimerHandle_t xTimer;
+ const char * const pcTimerName = "TestTimer";
+ const TickType_t x100ms = pdMS_TO_TICKS( 100UL );
+
+ /* Avoid compiler warnings about unused parameter. */
+ ( void ) pvParameters;
+
+ xTimer = xTimerCreate( pcTimerName,
+ x100ms,
+ pdFALSE, /* Created as a one-shot timer. */
+ 0,
+ prvReloadModeTestTimerCallback );
+ configASSERT( xTimer );
+ configASSERT( xTimerIsTimerActive( xTimer ) == pdFALSE );
+ configASSERT( xTimerGetTimerDaemonTaskHandle() != NULL );
+ configASSERT( strcmp( pcTimerName, pcTimerGetName( xTimer ) ) == 0 );
+ configASSERT( xTimerGetPeriod( xTimer ) == x100ms );
+
+ /* Timer was created as a one-shot timer. Its callback just increments the
+ * timer's ID - so set the ID to 0, let the timer run for a number of timeout
+ * periods, then check the timer has only executed once. */
+ vTimerSetTimerID( xTimer, ( void * ) 0 );
+ xTimerStart( xTimer, portMAX_DELAY );
+ vTaskDelay( 3UL * x100ms );
+ configASSERT( ( ( uintptr_t ) ( pvTimerGetTimerID( xTimer ) ) ) == 1UL );
+
+ /* Now change the timer to be an auto-reload timer and check it executes
+ * the expected number of times. */
+ vTimerSetReloadMode( xTimer, pdTRUE );
+ vTimerSetTimerID( xTimer, ( void * ) 0 );
+ xTimerStart( xTimer, 0 );
+ vTaskDelay( ( 3UL * x100ms ) + ( x100ms / 2UL ) ); /* Three full periods. */
+ configASSERT( ( uintptr_t ) ( pvTimerGetTimerID( xTimer ) ) == 3UL );
+ configASSERT( xTimerStop( xTimer, 0 ) != pdFAIL );
+
+ /* Now change the timer back to be a one-shot timer and check it only
+ * executes once. */
+ vTimerSetReloadMode( xTimer, pdFALSE );
+ vTimerSetTimerID( xTimer, ( void * ) 0 );
+ xTimerStart( xTimer, 0 );
+ vTaskDelay( 3UL * x100ms );
+ configASSERT( xTimerStop( xTimer, 0 ) != pdFAIL );
+ configASSERT( ( uintptr_t ) ( pvTimerGetTimerID( xTimer ) ) == 1UL );
+
+ /* Clean up at the end. */
+ xTimerDelete( xTimer, portMAX_DELAY );
+ vTaskDelete( NULL );
}
diff --git a/Demo/Posix_GCC/run-time-stats-utils.c b/Demo/Posix_GCC/run-time-stats-utils.c
index d43042a38..b9cb95917 100644
--- a/Demo/Posix_GCC/run-time-stats-utils.c
+++ b/Demo/Posix_GCC/run-time-stats-utils.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -34,7 +34,7 @@
*
* Also note that it is assumed this demo is going to be used for short periods
* of time only, and therefore timer overflows are not handled.
-*/
+ */
#include
@@ -48,20 +48,20 @@ static unsigned long ulStartTimeNs;
void vConfigureTimerForRunTimeStats( void )
{
-struct timespec xNow;
+ struct timespec xNow;
- clock_gettime(CLOCK_MONOTONIC, &xNow);
- ulStartTimeNs = xNow.tv_sec * 1000000000ul + xNow.tv_nsec;
+ clock_gettime( CLOCK_MONOTONIC, &xNow );
+ ulStartTimeNs = xNow.tv_sec * 1000000000ul + xNow.tv_nsec;
}
/*-----------------------------------------------------------*/
unsigned long ulGetRunTimeCounterValue( void )
{
-struct timespec xNow;
+ struct timespec xNow;
- /* Time at start. */
- clock_gettime(CLOCK_MONOTONIC, &xNow);
+ /* Time at start. */
+ clock_gettime( CLOCK_MONOTONIC, &xNow );
- return xNow.tv_sec * 1000000000ul + xNow.tv_nsec - ulStartTimeNs;
+ return xNow.tv_sec * 1000000000ul + xNow.tv_nsec - ulStartTimeNs;
}
/*-----------------------------------------------------------*/
diff --git a/Demo/Posix_GCC/trcConfig.h b/Demo/Posix_GCC/trcConfig.h
index 30e049658..d39de12cf 100644
--- a/Demo/Posix_GCC/trcConfig.h
+++ b/Demo/Posix_GCC/trcConfig.h
@@ -46,13 +46,13 @@
******************************************************************************/
#ifndef TRC_CONFIG_H
-#define TRC_CONFIG_H
+ #define TRC_CONFIG_H
-#ifdef __cplusplus
-extern "C" {
-#endif
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
-#include "trcPortDefines.h"
+ #include "trcPortDefines.h"
/******************************************************************************
* Include of processor header file
@@ -61,7 +61,7 @@ extern "C" {
* required at least for the ARM Cortex-M port, that uses the ARM CMSIS API.
* Try that in case of build problems. Otherwise, remove the #error line below.
*****************************************************************************/
-//#error "Trace Recorder: Please include your processor's header file here and remove this line."
+/*#error "Trace Recorder: Please include your processor's header file here and remove this line." */
/*******************************************************************************
* Configuration Macro: TRC_CFG_HARDWARE_PORT
@@ -81,7 +81,7 @@ extern "C" {
* See trcHardwarePort.h for available ports and information on how to
* define your own port, if not already present.
******************************************************************************/
-#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_Win32
+ #define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_Win32
/*******************************************************************************
* Configuration Macro: TRC_CFG_RECORDER_MODE
@@ -97,7 +97,8 @@ extern "C" {
* TRC_RECORDER_MODE_SNAPSHOT
* TRC_RECORDER_MODE_STREAMING
******************************************************************************/
-#define TRC_CFG_RECORDER_MODE TRC_RECORDER_MODE_SNAPSHOT
+ #define TRC_CFG_RECORDER_MODE TRC_RECORDER_MODE_SNAPSHOT
+
/******************************************************************************
* TRC_CFG_FREERTOS_VERSION
*
@@ -105,7 +106,7 @@ extern "C" {
* trace recorder library with an older version of FreeRTOS).
*
* TRC_FREERTOS_VERSION_7_3_X If using FreeRTOS v7.3.X
- * TRC_FREERTOS_VERSION_7_4_X If using FreeRTOS v7.4.X
+ * TRC_FREERTOS_VERSION_7_4_X If using FreeRTOS v7.4.X
* TRC_FREERTOS_VERSION_7_5_X If using FreeRTOS v7.5.X
* TRC_FREERTOS_VERSION_7_6_X If using FreeRTOS v7.6.X
* TRC_FREERTOS_VERSION_8_X_X If using FreeRTOS v8.X.X
@@ -122,7 +123,7 @@ extern "C" {
* TRC_FREERTOS_VERSION_10_3_1 If using FreeRTOS v10.3.1
* TRC_FREERTOS_VERSION_10_4_0 If using FreeRTOS v10.4.0 or later
*****************************************************************************/
-#define TRC_CFG_FREERTOS_VERSION TRC_FREERTOS_VERSION_10_4_0
+ #define TRC_CFG_FREERTOS_VERSION TRC_FREERTOS_VERSION_10_4_0
/*******************************************************************************
* TRC_CFG_SCHEDULING_ONLY
@@ -134,9 +135,9 @@ extern "C" {
*
* Default value is 0 (= include additional events).
******************************************************************************/
-#define TRC_CFG_SCHEDULING_ONLY 0
+ #define TRC_CFG_SCHEDULING_ONLY 0
- /******************************************************************************
+/******************************************************************************
* TRC_CFG_INCLUDE_MEMMANG_EVENTS
*
* Macro which should be defined as either zero (0) or one (1).
@@ -146,20 +147,20 @@ extern "C" {
*
* Default value is 1.
*****************************************************************************/
-#define TRC_CFG_INCLUDE_MEMMANG_EVENTS 1
+ #define TRC_CFG_INCLUDE_MEMMANG_EVENTS 1
- /******************************************************************************
+/******************************************************************************
* TRC_CFG_INCLUDE_USER_EVENTS
*
* Macro which should be defined as either zero (0) or one (1).
*
- * If this is zero (0), all code related to User Events is excluded in order
+ * If this is zero (0), all code related to User Events is excluded in order
* to reduce code size. Any attempts of storing User Events are then silently
* ignored.
*
- * User Events are application-generated events, like "printf" but for the
- * trace log, generated using vTracePrint and vTracePrintF.
- * The formatting is done on host-side, by Tracealyzer. User Events are
+ * User Events are application-generated events, like "printf" but for the
+ * trace log, generated using vTracePrint and vTracePrintF.
+ * The formatting is done on host-side, by Tracealyzer. User Events are
* therefore much faster than a console printf and can often be used
* in timing critical code without problems.
*
@@ -171,84 +172,84 @@ extern "C" {
*
* Default value is 1.
*****************************************************************************/
-#define TRC_CFG_INCLUDE_USER_EVENTS 1
+ #define TRC_CFG_INCLUDE_USER_EVENTS 1
- /*****************************************************************************
- * TRC_CFG_INCLUDE_ISR_TRACING
- *
- * Macro which should be defined as either zero (0) or one (1).
- *
- * If this is zero (0), the code for recording Interrupt Service Routines is
- * excluded, in order to reduce code size.
- *
- * Default value is 1.
- *
- * Note: tracing ISRs requires that you insert calls to vTraceStoreISRBegin
- * and vTraceStoreISREnd in your interrupt handlers.
- *****************************************************************************/
-#define TRC_CFG_INCLUDE_ISR_TRACING 1
+/*****************************************************************************
+* TRC_CFG_INCLUDE_ISR_TRACING
+*
+* Macro which should be defined as either zero (0) or one (1).
+*
+* If this is zero (0), the code for recording Interrupt Service Routines is
+* excluded, in order to reduce code size.
+*
+* Default value is 1.
+*
+* Note: tracing ISRs requires that you insert calls to vTraceStoreISRBegin
+* and vTraceStoreISREnd in your interrupt handlers.
+*****************************************************************************/
+ #define TRC_CFG_INCLUDE_ISR_TRACING 1
- /*****************************************************************************
- * TRC_CFG_INCLUDE_READY_EVENTS
- *
- * Macro which should be defined as either zero (0) or one (1).
- *
- * If one (1), events are recorded when tasks enter scheduling state "ready".
- * This allows Tracealyzer to show the initial pending time before tasks enter
- * the execution state, and present accurate response times.
- * If zero (0), "ready events" are not created, which allows for recording
- * longer traces in the same amount of RAM.
- *
- * Default value is 1.
- *****************************************************************************/
-#define TRC_CFG_INCLUDE_READY_EVENTS 1
+/*****************************************************************************
+* TRC_CFG_INCLUDE_READY_EVENTS
+*
+* Macro which should be defined as either zero (0) or one (1).
+*
+* If one (1), events are recorded when tasks enter scheduling state "ready".
+* This allows Tracealyzer to show the initial pending time before tasks enter
+* the execution state, and present accurate response times.
+* If zero (0), "ready events" are not created, which allows for recording
+* longer traces in the same amount of RAM.
+*
+* Default value is 1.
+*****************************************************************************/
+ #define TRC_CFG_INCLUDE_READY_EVENTS 1
- /*****************************************************************************
- * TRC_CFG_INCLUDE_OSTICK_EVENTS
- *
- * Macro which should be defined as either zero (0) or one (1).
- *
- * If this is one (1), events will be generated whenever the OS clock is
- * increased. If zero (0), OS tick events are not generated, which allows for
- * recording longer traces in the same amount of RAM.
- *
- * Default value is 1.
- *****************************************************************************/
-#define TRC_CFG_INCLUDE_OSTICK_EVENTS 1
+/*****************************************************************************
+* TRC_CFG_INCLUDE_OSTICK_EVENTS
+*
+* Macro which should be defined as either zero (0) or one (1).
+*
+* If this is one (1), events will be generated whenever the OS clock is
+* increased. If zero (0), OS tick events are not generated, which allows for
+* recording longer traces in the same amount of RAM.
+*
+* Default value is 1.
+*****************************************************************************/
+ #define TRC_CFG_INCLUDE_OSTICK_EVENTS 1
- /*****************************************************************************
- * TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS
- *
- * Macro which should be defined as either zero (0) or one (1).
- *
- * If this is zero (0), the trace will exclude any "event group" events.
- *
- * Default value is 0 (excluded) since dependent on event_groups.c
- *****************************************************************************/
-#define TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS 1
+/*****************************************************************************
+* TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS
+*
+* Macro which should be defined as either zero (0) or one (1).
+*
+* If this is zero (0), the trace will exclude any "event group" events.
+*
+* Default value is 0 (excluded) since dependent on event_groups.c
+*****************************************************************************/
+ #define TRC_CFG_INCLUDE_EVENT_GROUP_EVENTS 1
- /*****************************************************************************
- * TRC_CFG_INCLUDE_TIMER_EVENTS
- *
- * Macro which should be defined as either zero (0) or one (1).
- *
- * If this is zero (0), the trace will exclude any Timer events.
- *
- * Default value is 0 since dependent on timers.c
- *****************************************************************************/
-#define TRC_CFG_INCLUDE_TIMER_EVENTS 1
+/*****************************************************************************
+* TRC_CFG_INCLUDE_TIMER_EVENTS
+*
+* Macro which should be defined as either zero (0) or one (1).
+*
+* If this is zero (0), the trace will exclude any Timer events.
+*
+* Default value is 0 since dependent on timers.c
+*****************************************************************************/
+ #define TRC_CFG_INCLUDE_TIMER_EVENTS 1
- /*****************************************************************************
- * TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS
- *
- * Macro which should be defined as either zero (0) or one (1).
- *
- * If this is zero (0), the trace will exclude any "pending function call"
- * events, such as xTimerPendFunctionCall().
- *
- * Default value is 0 since dependent on timers.c
- *****************************************************************************/
-#define TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS 1
+/*****************************************************************************
+* TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS
+*
+* Macro which should be defined as either zero (0) or one (1).
+*
+* If this is zero (0), the trace will exclude any "pending function call"
+* events, such as xTimerPendFunctionCall().
+*
+* Default value is 0 since dependent on timers.c
+*****************************************************************************/
+ #define TRC_CFG_INCLUDE_PEND_FUNC_CALL_EVENTS 1
/*******************************************************************************
* Configuration Macro: TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS
@@ -260,7 +261,7 @@ extern "C" {
*
* Default value is 0 since dependent on stream_buffer.c (new in FreeRTOS v10)
******************************************************************************/
-#define TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS 1
+ #define TRC_CFG_INCLUDE_STREAM_BUFFER_EVENTS 1
/*******************************************************************************
* Configuration Macro: TRC_CFG_RECORDER_BUFFER_ALLOCATION
@@ -278,7 +279,7 @@ extern "C" {
* The custom mode allows you to control how and where the allocation is made,
* for details see TRC_ALLOC_CUSTOM_BUFFER and vTraceSetRecorderDataBuffer().
******************************************************************************/
-#define TRC_CFG_RECORDER_BUFFER_ALLOCATION TRC_RECORDER_BUFFER_ALLOCATION_STATIC
+ #define TRC_CFG_RECORDER_BUFFER_ALLOCATION TRC_RECORDER_BUFFER_ALLOCATION_STATIC
/******************************************************************************
* TRC_CFG_MAX_ISR_NESTING
@@ -293,17 +294,17 @@ extern "C" {
*
* Default value: 8
*****************************************************************************/
-#define TRC_CFG_MAX_ISR_NESTING 8
+ #define TRC_CFG_MAX_ISR_NESTING 8
/* Specific configuration, depending on Streaming/Snapshot mode */
-#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)
-#include "trcSnapshotConfig.h"
-#elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
-#include "trcStreamingConfig.h"
-#endif
+ #if ( TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT )
+ #include "trcSnapshotConfig.h"
+ #elif ( TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING )
+ #include "trcStreamingConfig.h"
+ #endif
-#ifdef __cplusplus
-}
-#endif
+ #ifdef __cplusplus
+ }
+ #endif
#endif /* _TRC_CONFIG_H */
diff --git a/Demo/Posix_GCC/trcSnapshotConfig.h b/Demo/Posix_GCC/trcSnapshotConfig.h
index 45c920584..c543e28d2 100644
--- a/Demo/Posix_GCC/trcSnapshotConfig.h
+++ b/Demo/Posix_GCC/trcSnapshotConfig.h
@@ -46,8 +46,8 @@
#ifndef TRC_SNAPSHOT_CONFIG_H
#define TRC_SNAPSHOT_CONFIG_H
-#define TRC_SNAPSHOT_MODE_RING_BUFFER (0x01)
-#define TRC_SNAPSHOT_MODE_STOP_WHEN_FULL (0x02)
+#define TRC_SNAPSHOT_MODE_RING_BUFFER ( 0x01 )
+#define TRC_SNAPSHOT_MODE_STOP_WHEN_FULL ( 0x02 )
/******************************************************************************
* TRC_CFG_SNAPSHOT_MODE
@@ -67,7 +67,7 @@
* recording is stopped when the buffer becomes full. This is useful for
* recording events following a specific state, e.g., the startup sequence.
*****************************************************************************/
-#define TRC_CFG_SNAPSHOT_MODE TRC_SNAPSHOT_MODE_RING_BUFFER
+#define TRC_CFG_SNAPSHOT_MODE TRC_SNAPSHOT_MODE_RING_BUFFER
/*******************************************************************************
* TRC_CFG_EVENT_BUFFER_SIZE
@@ -82,7 +82,7 @@
* Default value is 1000, which means that 4000 bytes is allocated for the
* event buffer.
******************************************************************************/
-#define TRC_CFG_EVENT_BUFFER_SIZE 32000
+#define TRC_CFG_EVENT_BUFFER_SIZE 32000
/*******************************************************************************
* TRC_CFG_NTASK, TRC_CFG_NISR, TRC_CFG_NQUEUE, TRC_CFG_NSEMAPHORE...
@@ -106,15 +106,15 @@
* check the actual usage by selecting View menu -> Trace Details ->
* Resource Usage -> Object Table.
******************************************************************************/
-#define TRC_CFG_NTASK 150
-#define TRC_CFG_NISR 90
-#define TRC_CFG_NQUEUE 90
-#define TRC_CFG_NSEMAPHORE 90
-#define TRC_CFG_NMUTEX 90
-#define TRC_CFG_NTIMER 250
-#define TRC_CFG_NEVENTGROUP 90
-#define TRC_CFG_NSTREAMBUFFER 100
-#define TRC_CFG_NMESSAGEBUFFER 100
+#define TRC_CFG_NTASK 150
+#define TRC_CFG_NISR 90
+#define TRC_CFG_NQUEUE 90
+#define TRC_CFG_NSEMAPHORE 90
+#define TRC_CFG_NMUTEX 90
+#define TRC_CFG_NTIMER 250
+#define TRC_CFG_NEVENTGROUP 90
+#define TRC_CFG_NSTREAMBUFFER 100
+#define TRC_CFG_NMESSAGEBUFFER 100
/******************************************************************************
@@ -133,7 +133,7 @@
*
* Default value is 0.
*****************************************************************************/
-#define TRC_CFG_INCLUDE_FLOAT_SUPPORT 0
+#define TRC_CFG_INCLUDE_FLOAT_SUPPORT 0
/*******************************************************************************
* TRC_CFG_SYMBOL_TABLE_SIZE
@@ -149,10 +149,10 @@
*
* Default value is 800.
******************************************************************************/
-#define TRC_CFG_SYMBOL_TABLE_SIZE 32000
+#define TRC_CFG_SYMBOL_TABLE_SIZE 32000
-#if (TRC_CFG_SYMBOL_TABLE_SIZE == 0)
-#error "TRC_CFG_SYMBOL_TABLE_SIZE may not be zero!"
+#if ( TRC_CFG_SYMBOL_TABLE_SIZE == 0 )
+ #error "TRC_CFG_SYMBOL_TABLE_SIZE may not be zero!"
#endif
/******************************************************************************
@@ -162,15 +162,15 @@
* kernel objects, such as tasks and queues. If longer names are used, they will
* be truncated when stored in the recorder.
*****************************************************************************/
-#define TRC_CFG_NAME_LEN_TASK 15
-#define TRC_CFG_NAME_LEN_ISR 15
-#define TRC_CFG_NAME_LEN_QUEUE 15
-#define TRC_CFG_NAME_LEN_SEMAPHORE 15
-#define TRC_CFG_NAME_LEN_MUTEX 15
-#define TRC_CFG_NAME_LEN_TIMER 15
-#define TRC_CFG_NAME_LEN_EVENTGROUP 15
-#define TRC_CFG_NAME_LEN_STREAMBUFFER 15
-#define TRC_CFG_NAME_LEN_MESSAGEBUFFER 15
+#define TRC_CFG_NAME_LEN_TASK 15
+#define TRC_CFG_NAME_LEN_ISR 15
+#define TRC_CFG_NAME_LEN_QUEUE 15
+#define TRC_CFG_NAME_LEN_SEMAPHORE 15
+#define TRC_CFG_NAME_LEN_MUTEX 15
+#define TRC_CFG_NAME_LEN_TIMER 15
+#define TRC_CFG_NAME_LEN_EVENTGROUP 15
+#define TRC_CFG_NAME_LEN_STREAMBUFFER 15
+#define TRC_CFG_NAME_LEN_MESSAGEBUFFER 15
/******************************************************************************
*** ADVANCED SETTINGS ********************************************************
@@ -190,7 +190,7 @@
*
* Default value is 0.
******************************************************************************/
-#define TRC_CFG_HEAP_SIZE_BELOW_16M 0
+#define TRC_CFG_HEAP_SIZE_BELOW_16M 0
/******************************************************************************
* TRC_CFG_USE_IMPLICIT_IFE_RULES
@@ -222,7 +222,7 @@
* For details, see trcSnapshotKernelPort.h and look for references to the
* macro trcKERNEL_HOOKS_SET_TASK_INSTANCE_FINISHED.
*****************************************************************************/
-#define TRC_CFG_USE_IMPLICIT_IFE_RULES 1
+#define TRC_CFG_USE_IMPLICIT_IFE_RULES 1
/******************************************************************************
* TRC_CFG_USE_16BIT_OBJECT_HANDLES
@@ -246,7 +246,7 @@
* the event buffer whenever the object is referenced. Moreover, some internal
* tables in the recorder gets slightly larger when using 16-bit handles.
*****************************************************************************/
-#define TRC_CFG_USE_16BIT_OBJECT_HANDLES 0
+#define TRC_CFG_USE_16BIT_OBJECT_HANDLES 0
/******************************************************************************
* TRC_CFG_USE_TRACE_ASSERT
@@ -264,7 +264,7 @@
* parameters. Can be switched off to reduce the footprint of the tracing, but
* we recommend to have it enabled initially.
*****************************************************************************/
-#define TRC_CFG_USE_TRACE_ASSERT 1
+#define TRC_CFG_USE_TRACE_ASSERT 1
/*******************************************************************************
* TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER
@@ -320,9 +320,9 @@
*
* // Finds the existing UB channel
* vTracePrintF(chn2, "%Z: %d", value2);
-
+ *
******************************************************************************/
-#define TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER 0
+#define TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER 0
/*******************************************************************************
* TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE
@@ -334,7 +334,7 @@
*
* Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1.
******************************************************************************/
-#define TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE 200
+#define TRC_CFG_SEPARATE_USER_EVENT_BUFFER_SIZE 200
/*******************************************************************************
* TRC_CFG_UB_CHANNELS
@@ -348,7 +348,7 @@
*
* Only applicable if TRC_CFG_USE_SEPARATE_USER_EVENT_BUFFER is 1.
******************************************************************************/
-#define TRC_CFG_UB_CHANNELS 32
+#define TRC_CFG_UB_CHANNELS 32
/*******************************************************************************
* TRC_CFG_ISR_TAILCHAINING_THRESHOLD
@@ -373,6 +373,6 @@
* Note: This setting has separate definitions in trcSnapshotConfig.h and
* trcStreamingConfig.h, since it is affected by the recorder mode.
******************************************************************************/
-#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0
+#define TRC_CFG_ISR_TAILCHAINING_THRESHOLD 0
#endif /*TRC_SNAPSHOT_CONFIG_H*/
diff --git a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h
index 607f99c97..3e0f9ac65 100644
--- a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h
+++ b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- FreeRTOS V202104.00
+ FreeRTOS V202111.00
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
diff --git a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c
index 2aa914415..5cd9cb837 100644
--- a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c
+++ b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/blinky_demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
index 58ddeee2e..bf47c9e8c 100644
--- a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
+++ b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/RegTest.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c
index 5d804c3ea..323ec9396 100644
--- a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c
+++ b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/full_demo/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c
index c4bc2b1b5..5d1335e88 100644
--- a/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c
+++ b/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/RISC-V-Qemu-virt_GCC/FreeRTOSConfig.h b/Demo/RISC-V-Qemu-virt_GCC/FreeRTOSConfig.h
new file mode 100644
index 000000000..a034ab31f
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/FreeRTOSConfig.h
@@ -0,0 +1,104 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "riscv-virt.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+#define configMTIME_BASE_ADDRESS ( CLINT_ADDR + CLINT_MTIME )
+#define configMTIMECMP_BASE_ADDRESS ( CLINT_ADDR + CLINT_MTIMECMP )
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 1
+#define configCPU_CLOCK_HZ ( 1000000 )
+#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES ( 7 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 512 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 64500 )
+#define configMAX_TASK_NAME_LEN ( 16 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 6
+#define configTIMER_TASK_STACK_DEPTH ( 110 )
+
+/* RISC-V definitions. */
+#define configISR_STACK_SIZE_WORDS 2048
+
+/* Task priorities. Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+ #define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 1
+#define INCLUDE_xTaskGetHandle 1
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/RISC-V-Qemu-virt_GCC/Makefile b/Demo/RISC-V-Qemu-virt_GCC/Makefile
new file mode 100644
index 000000000..4d806bf49
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/Makefile
@@ -0,0 +1,70 @@
+CROSS = riscv64-unknown-elf-
+CC = $(CROSS)gcc
+OBJCOPY = $(CROSS)objcopy
+ARCH = $(CROSS)ar
+
+BUILD_DIR = build
+RTOS_SOURCE_DIR = $(abspath ../../Source)
+DEMO_SOURCE_DIR = $(abspath ../Common/Minimal)
+
+CPPFLAGS = \
+ -D__riscv_float_abi_soft \
+ -DportasmHANDLE_INTERRUPT=handle_trap \
+ -I . -I ../Common/include \
+ -I $(RTOS_SOURCE_DIR)/include \
+ -I $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V \
+ -I $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions
+CFLAGS = -march=rv32ima -mabi=ilp32 -mcmodel=medany \
+ -Wall \
+ -fmessage-length=0 \
+ -ffunction-sections \
+ -fdata-sections \
+ -fno-builtin-printf
+ASFLAGS = -march=rv32ima -mabi=ilp32 -mcmodel=medany
+LDFLAGS = -nostartfiles -Tfake_rom.lds \
+ -Xlinker --gc-sections \
+ -Xlinker --defsym=__stack_size=300
+
+ifeq ($(DEBUG), 1)
+ CFLAGS += -Og -ggdb3
+else
+ CFLAGS += -O2
+endif
+
+SRCS = main.c main_blinky.c riscv-virt.c ns16550.c \
+ $(DEMO_SOURCE_DIR)/EventGroupsDemo.c \
+ $(DEMO_SOURCE_DIR)/TaskNotify.c \
+ $(DEMO_SOURCE_DIR)/TimerDemo.c \
+ $(DEMO_SOURCE_DIR)/blocktim.c \
+ $(DEMO_SOURCE_DIR)/dynamic.c \
+ $(DEMO_SOURCE_DIR)/recmutex.c \
+ $(RTOS_SOURCE_DIR)/event_groups.c \
+ $(RTOS_SOURCE_DIR)/list.c \
+ $(RTOS_SOURCE_DIR)/queue.c \
+ $(RTOS_SOURCE_DIR)/stream_buffer.c \
+ $(RTOS_SOURCE_DIR)/tasks.c \
+ $(RTOS_SOURCE_DIR)/timers.c \
+ $(RTOS_SOURCE_DIR)/portable/MemMang/heap_4.c \
+ $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V/port.c
+
+ASMS = start.S \
+ $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V/portASM.S
+
+OBJS = $(SRCS:%.c=$(BUILD_DIR)/%.o) $(ASMS:%.S=$(BUILD_DIR)/%.o)
+DEPS = $(SRCS:%.c=$(BUILD_DIR)/%.d) $(ASMS:%.S=$(BUILD_DIR)/%.d)
+
+$(BUILD_DIR)/RTOSDemo.axf: $(OBJS) fake_rom.lds Makefile
+ $(CC) $(LDFLAGS) $(OBJS) -o $@
+
+$(BUILD_DIR)/%.o: %.c Makefile
+ @mkdir -p $(@D)
+ $(CC) $(CPPFLAGS) $(CFLAGS) -MMD -MP -c $< -o $@
+
+$(BUILD_DIR)/%.o: %.S Makefile
+ @mkdir -p $(@D)
+ $(CC) $(CPPFLAGS) $(ASFLAGS) -MMD -MP -c $< -o $@
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+-include $(DEPS)
diff --git a/Demo/RISC-V-Qemu-virt_GCC/Readme.md b/Demo/RISC-V-Qemu-virt_GCC/Readme.md
new file mode 100644
index 000000000..86282ea67
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/Readme.md
@@ -0,0 +1,104 @@
+# Emulating generic RISC-V 32bit machine on QEMU
+
+## Requirements
+
+1. GNU RISC-V toolchains (tested on Crosstool-NG)
+1. qemu-riscv32-system (tested on Debian 10 package)
+1. Linux OS (tested on Debian 10)
+
+
+## How to build toolchain
+
+Clone the Crosstool-NG and build.
+
+```
+$ git clone https://github.com/crosstool-ng/crosstool-ng
+$ ./configure --enable-local
+$ make
+
+$ ./ct-ng menuconfig
+```
+
+Change the following configs:
+
+```
+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+CT_ARCH_64=y
+CT_ARCH_ARCH=rv32ima
+CT_ARCH_ABI=ilp32
+CT_MULTILIB=y
+CT_DEBUG_GDB=y
+```
+
+Build the GNU toolchain for RISC-V.
+
+```
+$ ./ct-ng build
+```
+
+A toolchain is installed at ~/x-tools/riscv64-unknown-elf directory.
+
+
+## How to build
+
+Add path of toolchain that is described above section.
+
+```
+$ export PATH=~/x-tools/riscv64-unknown-elf:$PATH
+```
+
+For release build:
+
+```
+$ make
+```
+
+For debug build:
+
+```
+$ make DEBUG=1
+```
+
+If success to build, executable file RTOSDemo.axf in ./build directory.
+
+
+## How to run
+
+```
+$ qemu-system-riscv32 -nographic -machine virt -net none \
+ -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -bios none \
+ -smp 4 -kernel ./build/RTOSDemo.axf
+```
+
+
+## How to debug with gdb
+
+Append -s and -S options to the previous qemu command.
+
+- -s: enable to attach gdb to QEMU at port 1234
+- -S: start and halted CPU (wait for attach from gdb)
+
+This is just recommend to use 'debug build' for more efficient debugging.
+Run these commands after starting the QEMU with above options:
+
+```
+$ riscv64-unknown-elf-gdb build/RTOSDemo.axf
+
+(gdb) target remote localhost:1234
+(gdb) break main
+Breakpoint 1 at 0x80000110
+
+(gdb) c
+Continuing.
+
+Breakpoint 1, 0x80000110 in main ()
+```
+
+
+## Description
+
+This demo just prints Tx/Rx message of queue to serial port, use no
+other hardware and use only primary core (currently hart 0).
+Other cores are simply going to wfi state and execute nothing else.
diff --git a/Demo/RISC-V-Qemu-virt_GCC/fake_rom.lds b/Demo/RISC-V-Qemu-virt_GCC/fake_rom.lds
new file mode 100644
index 000000000..b63fad8f0
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/fake_rom.lds
@@ -0,0 +1,117 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY( _start )
+
+MEMORY
+{
+ /* Fake ROM area */
+ rom (rxa) : ORIGIN = 0x80000000, LENGTH = 512K
+ ram (wxa) : ORIGIN = 0x80080000, LENGTH = 512K
+}
+
+SECTIONS
+{
+ .init :
+ {
+ _text = .;
+ KEEP (*(SORT_NONE(.init)))
+ } >rom AT>rom
+
+ .text :
+ {
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >rom AT>rom
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ _etext = .;
+ } >rom AT>rom
+
+ .rodata.align :
+ {
+ . = ALIGN(4);
+ _rodata = .;
+ } >rom AT>rom
+
+ .rodata.start :
+ {
+ _rodata_lma = LOADADDR(.rodata.start);
+ } >rom AT>rom
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ . = ALIGN(4);
+ _erodata = .;
+ } >rom AT>rom
+
+ .data.align :
+ {
+ . = ALIGN(4);
+ _data = .;
+ } >ram AT>rom
+
+ .data.start :
+ {
+ _data_lma = LOADADDR(.data.start);
+ } >ram AT>rom
+
+ .data :
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2 .sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+
+ . = ALIGN(4);
+ _edata = .;
+ } >ram AT>rom
+
+ .bss.align :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ } >ram AT>rom
+
+ .bss.start :
+ {
+ _bss_lma = LOADADDR(.bss.start);
+ } >ram AT>rom
+
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >ram AT>rom
+
+ . = ALIGN(8);
+ _end = .;
+
+ .stack :
+ {
+ . = ALIGN(16);
+ . += __stack_size;
+ _stack_top = .;
+ } >ram AT>ram
+}
diff --git a/Demo/RISC-V-Qemu-virt_GCC/main.c b/Demo/RISC-V-Qemu-virt_GCC/main.c
new file mode 100644
index 000000000..24dfd289f
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/main.c
@@ -0,0 +1,117 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS kernel includes. */
+#include
+#include
+
+/* Run a simple demo just prints 'Blink' */
+#define DEMO_BLINKY 1
+
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+int main_blinky( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+ int ret;
+
+#if defined(DEMO_BLINKY)
+ ret = main_blinky();
+#else
+#error "Please add or select demo."
+#endif
+
+ return ret;
+}
+
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c or heap_2.c are used, then the size of the
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile uint32_t ulSetTo1ToExitFunction = 0;
+
+ taskDISABLE_INTERRUPTS();
+ while( ulSetTo1ToExitFunction != 1 )
+ {
+ __asm volatile( "NOP" );
+ }
+}
diff --git a/Demo/RISC-V-Qemu-virt_GCC/main_blinky.c b/Demo/RISC-V-Qemu-virt_GCC/main_blinky.c
new file mode 100644
index 000000000..b1c445b36
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/main_blinky.c
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS kernel includes. */
+#include
+#include
+#include
+
+#include
+
+#include "riscv-virt.h"
+#include "ns16550.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue. The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold. The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue. Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+const char * const pcMessage1 = "Transfer1";
+const char * const pcMessage2 = "Transfer2";
+int f = 1;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ char buf[40];
+
+ sprintf( buf, "%d: %s: %s", xGetCoreID(),
+ pcTaskGetName( xTaskGetCurrentTaskHandle() ),
+ ( f ) ? pcMessage1 : pcMessage2 );
+ vSendString( buf );
+ f = !f;
+
+ /* Place this task in the blocked state until it is time to run again. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ toggle the LED. 0 is used as the block time so the sending operation
+ will not block - it shouldn't need to block as the queue should always
+ be empty at this point in the code. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+const char * const pcMessage1 = "Blink1";
+const char * const pcMessage2 = "Blink2";
+const char * const pcFailMessage = "Unexpected value received\r\n";
+int f = 1;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ char buf[40];
+
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, toggle the LED. */
+ if( ulReceivedValue == ulExpectedValue )
+ {
+ sprintf( buf, "%d: %s: %s", xGetCoreID(),
+ pcTaskGetName( xTaskGetCurrentTaskHandle() ),
+ ( f ) ? pcMessage1 : pcMessage2 );
+ vSendString( buf );
+ f = !f;
+
+ ulReceivedValue = 0U;
+ }
+ else
+ {
+ vSendString( pcFailMessage );
+ }
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+int main_blinky( void )
+{
+ vSendString( "Hello FreeRTOS!" );
+
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+ if( xQueue != NULL )
+ {
+ /* Start the two tasks as described in the comments at the top of this
+ file. */
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE * 2U, NULL,
+ mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );
+ xTaskCreate( prvQueueSendTask, "Tx", configMINIMAL_STACK_SIZE * 2U, NULL,
+ mainQUEUE_SEND_TASK_PRIORITY, NULL );
+ }
+
+ vTaskStartScheduler();
+
+ return 0;
+}
diff --git a/Demo/RISC-V-Qemu-virt_GCC/ns16550.c b/Demo/RISC-V-Qemu-virt_GCC/ns16550.c
new file mode 100644
index 000000000..1fd248fb1
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/ns16550.c
@@ -0,0 +1,75 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include
+
+#include "ns16550.h"
+
+/* register definitions */
+#define REG_RBR 0x00 /* Receiver buffer reg. */
+#define REG_THR 0x00 /* Transmitter holding reg. */
+#define REG_IER 0x01 /* Interrupt enable reg. */
+#define REG_IIR 0x02 /* Interrupt ID reg. */
+#define REG_FCR 0x02 /* FIFO control reg. */
+#define REG_LCR 0x03 /* Line control reg. */
+#define REG_MCR 0x04 /* Modem control reg. */
+#define REG_LSR 0x05 /* Line status reg. */
+#define REG_MSR 0x06 /* Modem status reg. */
+#define REG_SCR 0x07 /* Scratch reg. */
+#define REG_BRDL 0x00 /* Divisor latch (LSB) */
+#define REG_BRDH 0x01 /* Divisor latch (MSB) */
+
+/* Line status */
+#define LSR_DR 0x01 /* Data ready */
+#define LSR_OE 0x02 /* Overrun error */
+#define LSR_PE 0x04 /* Parity error */
+#define LSR_FE 0x08 /* Framing error */
+#define LSR_BI 0x10 /* Break interrupt */
+#define LSR_THRE 0x20 /* Transmitter holding register empty */
+#define LSR_TEMT 0x40 /* Transmitter empty */
+#define LSR_EIRF 0x80 /* Error in RCVR FIFO */
+
+static uint8_t readb( uintptr_t addr )
+{
+ return *( (uint8_t *) addr );
+}
+
+static void writeb( uint8_t b, uintptr_t addr )
+{
+ *( (uint8_t *) addr ) = b;
+}
+
+void vOutNS16550( struct device *dev, unsigned char c )
+{
+ uintptr_t addr = dev->addr;
+
+ while ( (readb( addr + REG_LSR ) & LSR_THRE) == 0 ) {
+ /* busy wait */
+ }
+
+ writeb( c, addr + REG_THR );
+}
diff --git a/Demo/RISC-V-Qemu-virt_GCC/ns16550.h b/Demo/RISC-V-Qemu-virt_GCC/ns16550.h
new file mode 100644
index 000000000..92e2afd45
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/ns16550.h
@@ -0,0 +1,39 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef NS16550_H_
+#define NS16550_H_
+
+#include
+
+struct device {
+ uintptr_t addr;
+};
+
+void vOutNS16550( struct device *dev, unsigned char c );
+
+#endif /* NS16550_H_ */
diff --git a/Demo/RISC-V-Qemu-virt_GCC/riscv-reg.h b/Demo/RISC-V-Qemu-virt_GCC/riscv-reg.h
new file mode 100644
index 000000000..e3f5658e0
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/riscv-reg.h
@@ -0,0 +1,43 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef RISCV_REG_H_
+#define RISCV_REG_H_
+
+#if __riscv_xlen == 32
+#define REGSIZE 4
+#define REGSHIFT 2
+#define LOAD lw
+#define STOR sw
+#elif __riscv_xlen == 64
+#define REGSIZE 8
+#define REGSHIFT 3
+#define LOAD ld
+#define STOR sd
+#endif /* __riscv_xlen */
+
+#endif /* RISCV_REG_H_ */
diff --git a/Demo/RISC-V-Qemu-virt_GCC/riscv-virt.c b/Demo/RISC-V-Qemu-virt_GCC/riscv-virt.c
new file mode 100644
index 000000000..e6ec142e8
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/riscv-virt.c
@@ -0,0 +1,65 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include
+
+#include
+
+#include "riscv-virt.h"
+#include "ns16550.h"
+
+int xGetCoreID( void )
+{
+int id;
+
+ __asm ("csrr %0, mhartid" : "=r" ( id ) );
+
+ return id;
+}
+
+void vSendString( const char *s )
+{
+struct device dev;
+size_t i;
+
+ dev.addr = NS16550_ADDR;
+
+ portENTER_CRITICAL();
+
+ for (i = 0; i < strlen(s); i++) {
+ vOutNS16550( &dev, s[i] );
+ }
+ vOutNS16550( &dev, '\n' );
+
+ portEXIT_CRITICAL();
+}
+
+void handle_trap(void)
+{
+ while (1)
+ ;
+}
diff --git a/Demo/RISC-V-Qemu-virt_GCC/riscv-virt.h b/Demo/RISC-V-Qemu-virt_GCC/riscv-virt.h
new file mode 100644
index 000000000..aa17d7760
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/riscv-virt.h
@@ -0,0 +1,55 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef RISCV_VIRT_H_
+#define RISCV_VIRT_H_
+
+#include "riscv-reg.h"
+
+#ifdef __ASSEMBLER__
+#define CONS(NUM, TYPE)NUM
+#else
+#define CONS(NUM, TYPE)NUM##TYPE
+#endif /* __ASSEMBLER__ */
+
+#define PRIM_HART 0
+
+#define CLINT_ADDR CONS(0x02000000, UL)
+#define CLINT_MSIP CONS(0x0000, UL)
+#define CLINT_MTIMECMP CONS(0x4000, UL)
+#define CLINT_MTIME CONS(0xbff8, UL)
+
+#define NS16550_ADDR CONS(0x10000000, UL)
+
+#ifndef __ASSEMBLER__
+
+int xGetCoreID( void );
+void vSendString( const char * s );
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* RISCV_VIRT_H_ */
diff --git a/Demo/RISC-V-Qemu-virt_GCC/start.S b/Demo/RISC-V-Qemu-virt_GCC/start.S
new file mode 100644
index 000000000..b0ce2d34a
--- /dev/null
+++ b/Demo/RISC-V-Qemu-virt_GCC/start.S
@@ -0,0 +1,85 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://www.github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "riscv-virt.h"
+
+ .section .init
+ .globl _start
+ .type _start,@function
+_start:
+ .cfi_startproc
+ .cfi_undefined ra
+.option push
+.option norelax
+ la gp, __global_pointer$
+.option pop
+
+ // Continue primary hart
+ csrr a0, mhartid
+ li a1, PRIM_HART
+ bne a0, a1, secondary
+
+ // Primary hart
+ la sp, _stack_top
+
+ // Load data section
+ la a0, _data_lma
+ la a1, _data
+ la a2, _edata
+ bgeu a1, a2, 2f
+1:
+ LOAD t0, (a0)
+ STOR t0, (a1)
+ addi a0, a0, REGSIZE
+ addi a1, a1, REGSIZE
+ bltu a1, a2, 1b
+2:
+
+ // Clear bss section
+ la a0, _bss
+ la a1, _ebss
+ bgeu a0, a1, 2f
+1:
+ STOR zero, (a0)
+ addi a0, a0, REGSIZE
+ bltu a0, a1, 1b
+2:
+
+ // argc, argv, envp is 0
+ li a0, 0
+ li a1, 0
+ li a2, 0
+ jal main
+1:
+ wfi
+ j 1b
+
+secondary:
+ // TODO: Multicore is not supported
+ wfi
+ j secondary
+ .cfi_endproc
diff --git a/Demo/RISC-V-spike-htif_GCC/FreeRTOSConfig.h b/Demo/RISC-V-spike-htif_GCC/FreeRTOSConfig.h
new file mode 100644
index 000000000..87b3e6cbe
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/FreeRTOSConfig.h
@@ -0,0 +1,103 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "riscv-virt.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+#define configMTIME_BASE_ADDRESS ( CLINT_ADDR + CLINT_MTIME )
+#define configMTIMECMP_BASE_ADDRESS ( CLINT_ADDR + CLINT_MTIMECMP )
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 1
+#define configCPU_CLOCK_HZ ( 1000000 )
+#define configTICK_RATE_HZ ( ( TickType_t ) 10 )
+#define configMAX_PRIORITIES ( 7 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 512 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 64500 )
+#define configMAX_TASK_NAME_LEN ( 16 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_MALLOC_FAILED_HOOK 1
+#define configUSE_APPLICATION_TASK_TAG 0
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH 6
+#define configTIMER_TASK_STACK_DEPTH ( 110 )
+
+/* RISC-V definitions. */
+#define configISR_STACK_SIZE_WORDS 2048
+
+/* Task priorities. Allow these to be overridden. */
+#ifndef uartPRIMARY_PRIORITY
+ #define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
+#endif
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 1
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_eTaskGetState 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xTaskAbortDelay 1
+#define INCLUDE_xTaskGetHandle 1
+#define INCLUDE_xSemaphoreGetMutexHolder 1
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/RISC-V-spike-htif_GCC/Makefile b/Demo/RISC-V-spike-htif_GCC/Makefile
new file mode 100644
index 000000000..c9e0bf390
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/Makefile
@@ -0,0 +1,89 @@
+XLEN ?= 32
+CROSS = riscv$(XLEN)-unknown-elf-
+CC = $(CROSS)gcc
+CPP = $(CROSS)cpp
+OBJCOPY = $(CROSS)objcopy
+ARCH = $(CROSS)ar
+DEBUG ?= 0
+BASE_ADDRESS ?= 0x80000000
+
+ifeq ($(XLEN), 64)
+ MARCH = rv64ima
+ MABI = lp64
+ STACK_SIZE = 600
+else
+ MARCH = rv32ima
+ MABI = ilp32
+ STACK_SIZE = 300
+endif
+
+BUILD_DIR = build
+RTOS_SOURCE_DIR = $(abspath ../../Source)
+DEMO_SOURCE_DIR = $(abspath ../Common/Minimal)
+
+CPPFLAGS = \
+ -D__riscv_float_abi_soft \
+ -DportasmHANDLE_INTERRUPT=handle_trap \
+ -I . -I ../Common/include \
+ -I $(RTOS_SOURCE_DIR)/include \
+ -I $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V \
+ -I $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions
+CFLAGS = -march=$(MARCH) -mabi=$(MABI) -mcmodel=medany \
+ -Wall \
+ -fmessage-length=0 \
+ -ffunction-sections \
+ -fdata-sections \
+ -fno-builtin-printf
+ASFLAGS = -march=$(MARCH) -mabi=$(MABI) -mcmodel=medany
+LDFLAGS = -nostartfiles \
+ -Xlinker --gc-sections \
+ -Xlinker --defsym=__stack_size=$(STACK_SIZE)
+
+ifeq ($(DEBUG), 1)
+ CFLAGS += -Og -ggdb3
+else
+ CFLAGS += -Os
+endif
+
+SRCS = main.c main_blinky.c riscv-virt.c htif.c \
+ $(DEMO_SOURCE_DIR)/EventGroupsDemo.c \
+ $(DEMO_SOURCE_DIR)/TaskNotify.c \
+ $(DEMO_SOURCE_DIR)/TimerDemo.c \
+ $(DEMO_SOURCE_DIR)/blocktim.c \
+ $(DEMO_SOURCE_DIR)/dynamic.c \
+ $(DEMO_SOURCE_DIR)/recmutex.c \
+ $(RTOS_SOURCE_DIR)/event_groups.c \
+ $(RTOS_SOURCE_DIR)/list.c \
+ $(RTOS_SOURCE_DIR)/queue.c \
+ $(RTOS_SOURCE_DIR)/stream_buffer.c \
+ $(RTOS_SOURCE_DIR)/tasks.c \
+ $(RTOS_SOURCE_DIR)/timers.c \
+ $(RTOS_SOURCE_DIR)/portable/MemMang/heap_4.c \
+ $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V/port.c
+
+ASMS = start.S \
+ $(RTOS_SOURCE_DIR)/portable/GCC/RISC-V/portASM.S
+
+OBJS = $(SRCS:%.c=$(BUILD_DIR)/%$(XLEN).o) $(ASMS:%.S=$(BUILD_DIR)/%$(XLEN).o)
+DEPS = $(SRCS:%.c=$(BUILD_DIR)/%$(XLEN).d) $(ASMS:%.S=$(BUILD_DIR)/%$(XLEN).d)
+
+$(BUILD_DIR)/RTOSDemo$(XLEN).axf: $(OBJS) $(BUILD_DIR)/fake_rom$(BASE_ADDRESS).lds Makefile
+ $(CC) $(LDFLAGS) $(OBJS) -T$(BUILD_DIR)/fake_rom$(BASE_ADDRESS).lds -o $@
+
+$(BUILD_DIR)/%$(XLEN).o: %.c Makefile
+ @mkdir -p $(@D)
+ $(CC) $(CPPFLAGS) $(CFLAGS) -MMD -MP -c $< -o $@
+
+$(BUILD_DIR)/%$(XLEN).o: %.S Makefile
+ @mkdir -p $(@D)
+ $(CC) $(CPPFLAGS) $(ASFLAGS) -MMD -MP -c $< -o $@
+
+# Run lds through the C preprocessor, to replace BASE_ADDRESS with the actual
+# value. It might be simpler to use sed instead.
+$(BUILD_DIR)/%$(BASE_ADDRESS).lds: fake_rom.lds Makefile
+ $(CPP) $(CPPFLAGS) -DBASE_ADDRESS=$(BASE_ADDRESS) $< | grep -v '^#' > $@
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+-include $(DEPS)
diff --git a/Demo/RISC-V-spike-htif_GCC/README.md b/Demo/RISC-V-spike-htif_GCC/README.md
new file mode 100644
index 000000000..74f024802
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/README.md
@@ -0,0 +1,106 @@
+# Emulating generic RISC-V 32bit machine on spike
+
+## Requirements
+
+1. GNU RISC-V toolchains (tested on Crosstool-NG)
+2. spike from https://github.com/riscv/riscv-isa-sim
+3. OpenOCD from https://github.com/riscv/riscv-openocd
+
+## How to build toolchain
+
+Clone the Crosstool-NG and build.
+
+```
+$ git clone https://github.com/crosstool-ng/crosstool-ng
+$ cd crosstool-ng
+$ ./bootstrap
+$ ./configure --enable-local
+$ make
+$ ./ct-ng menuconfig
+```
+
+For RV32 builds, change the following configs:
+
+```
+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+CT_ARCH_64=n
+CT_ARCH_ARCH=rv32ima
+CT_ARCH_ABI=ilp32
+CT_TARGET_CFLAGS="-mcmodel=medany"
+CT_TARGET_LDFLAGS="-mcmodel=medany"
+CT_MULTILIB=y
+CT_DEBUG_GDB=y
+```
+
+For RV64 builds, change the following configs:
+
+```
+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+CT_ARCH_64=y
+CT_ARCH_ARCH=rv32ima
+CT_ARCH_ABI=ilp32
+CT_TARGET_CFLAGS="-mcmodel=medany"
+CT_TARGET_LDFLAGS="-mcmodel=medany"
+CT_MULTILIB=y
+CT_DEBUG_GDB=y
+```
+
+Build the GNU toolchain for RISC-V.
+
+```
+$ ./ct-ng build
+```
+
+A toolchain is installed at ~/x-tools/riscv64-unknown-elf directory.
+
+
+## How to build
+
+Add path of toolchain that is described above section.
+
+```
+$ export PATH=~/x-tools/riscv64-unknown-elf/bin:$PATH
+```
+
+To build, simply run `make`. If you want a debug build, pass `DEBUG=1`. If
+you want an RV64 build, pass `XLEN=64`.
+
+The resulting executable file is ./build/RTOSDemo32.axf or ./build/RTOSDemo64.axf.
+
+## How to run
+
+RV32:
+```
+$ spike -p1 --isa RV32IMA -m0x80000000:0x10000000 --rbb-port 9824 \
+ ./build/RTOSDemo32.axf
+```
+
+RV64:
+```
+$ spike -p1 --isa RV64IMA -m0x80000000:0x10000000 --rbb-port 9824 \
+ ./build/RTOSDemo64.axf
+```
+
+## How to debug with gdb
+
+Start OpenOCD in one terminal:
+```
+$ openocd -f spike-1.cfg
+```
+
+Start gdb in another:
+```
+$ riscv64-unknown-elf-gdb ./build/RTOSDemo.axf
+...
+(gdb) target extended-remote localhost:3333
+...
+(gdb) info threads
+```
+
+(As of 3/22/2021 OpenOCD's RISC-V FreeRTOS awareness is still incomplete.)
+
+## Description
+
+This demo starts separate transmit and receive threads. The transmit thread sends integers through a queue. Both threads print out what they're sending/receiving using HTIF.
diff --git a/Demo/RISC-V-spike-htif_GCC/fake_rom.lds b/Demo/RISC-V-spike-htif_GCC/fake_rom.lds
new file mode 100644
index 000000000..abac8091a
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/fake_rom.lds
@@ -0,0 +1,118 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY( _start )
+
+MEMORY
+{
+ /* Fake ROM area */
+ /* BASE_ADDRESS is replaced with the real value by the Makefile. */
+ rom (rxa) : ORIGIN = BASE_ADDRESS, LENGTH = 512K
+ ram (wxa) : ORIGIN = BASE_ADDRESS + 512K, LENGTH = 512K
+}
+
+SECTIONS
+{
+ .init :
+ {
+ _text = .;
+ KEEP (*(SORT_NONE(.init)))
+ } >rom AT>rom
+
+ .text :
+ {
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >rom AT>rom
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ _etext = .;
+ } >rom AT>rom
+
+ .rodata.align :
+ {
+ . = ALIGN(4);
+ _rodata = .;
+ } >rom AT>rom
+
+ .rodata.start :
+ {
+ _rodata_lma = LOADADDR(.rodata.start);
+ } >rom AT>rom
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ . = ALIGN(4);
+ _erodata = .;
+ } >rom AT>rom
+
+ .data.align :
+ {
+ . = ALIGN(4);
+ _data = .;
+ } >ram AT>rom
+
+ .data.start :
+ {
+ _data_lma = LOADADDR(.data.start);
+ } >ram AT>rom
+
+ .data :
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2 .sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+
+ . = ALIGN(4);
+ _edata = .;
+ } >ram AT>rom
+
+ .bss.align :
+ {
+ . = ALIGN(4);
+ _bss = .;
+ } >ram AT>rom
+
+ .bss.start :
+ {
+ _bss_lma = LOADADDR(.bss.start);
+ } >ram AT>rom
+
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .;
+ } >ram AT>rom
+
+ . = ALIGN(8);
+ _end = .;
+
+ .stack :
+ {
+ . = ALIGN(16);
+ . += __stack_size;
+ _stack_top = .;
+ } >ram AT>ram
+}
diff --git a/Demo/RISC-V-spike-htif_GCC/htif.c b/Demo/RISC-V-spike-htif_GCC/htif.c
new file mode 100644
index 000000000..74c30c23c
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/htif.c
@@ -0,0 +1,142 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2010-2020, The Regents of the University of California
+ * (Regents). All Rights Reserved.
+ */
+
+#include
+
+#define HTIF_DATA_BITS 48
+#define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1)
+#define HTIF_DATA_SHIFT 0
+#define HTIF_CMD_BITS 8
+#define HTIF_CMD_MASK ((1ULL << HTIF_CMD_BITS) - 1)
+#define HTIF_CMD_SHIFT 48
+#define HTIF_DEV_BITS 8
+#define HTIF_DEV_MASK ((1ULL << HTIF_DEV_BITS) - 1)
+#define HTIF_DEV_SHIFT 56
+
+#define HTIF_DEV_SYSTEM 0
+#define HTIF_DEV_CONSOLE 1
+
+#define HTIF_CONSOLE_CMD_GETC 0
+#define HTIF_CONSOLE_CMD_PUTC 1
+
+#if __riscv_xlen == 64
+# define TOHOST_CMD(dev, cmd, payload) \
+ (((uint64_t)(dev) << HTIF_DEV_SHIFT) | \
+ ((uint64_t)(cmd) << HTIF_CMD_SHIFT) | \
+ (uint64_t)(payload))
+#else
+# define TOHOST_CMD(dev, cmd, payload) ({ \
+ if ((dev) || (cmd)) __builtin_trap(); \
+ (payload); })
+#endif
+#define FROMHOST_DEV(fromhost_value) \
+ ((uint64_t)((fromhost_value) >> HTIF_DEV_SHIFT) & HTIF_DEV_MASK)
+#define FROMHOST_CMD(fromhost_value) \
+ ((uint64_t)((fromhost_value) >> HTIF_CMD_SHIFT) & HTIF_CMD_MASK)
+#define FROMHOST_DATA(fromhost_value) \
+ ((uint64_t)((fromhost_value) >> HTIF_DATA_SHIFT) & HTIF_DATA_MASK)
+
+#define PK_SYS_write 64
+
+volatile uint64_t tohost __attribute__((section(".htif")));
+volatile uint64_t fromhost __attribute__((section(".htif")));
+static int htif_console_buf;
+
+static void __check_fromhost()
+{
+ uint64_t fh = fromhost;
+ if (!fh)
+ return;
+ fromhost = 0;
+
+ /* this should be from the console */
+ if (FROMHOST_DEV(fh) != HTIF_DEV_CONSOLE)
+ __builtin_trap();
+ switch (FROMHOST_CMD(fh)) {
+ case HTIF_CONSOLE_CMD_GETC:
+ htif_console_buf = 1 + (uint8_t)FROMHOST_DATA(fh);
+ break;
+ case HTIF_CONSOLE_CMD_PUTC:
+ break;
+ default:
+ __builtin_trap();
+ }
+}
+
+static void __set_tohost(uint64_t dev, uint64_t cmd, uint64_t data)
+{
+ while (tohost)
+ __check_fromhost();
+ tohost = TOHOST_CMD(dev, cmd, data);
+}
+
+#if __riscv_xlen == 32
+static void do_tohost_fromhost(uint64_t dev, uint64_t cmd, uint64_t data)
+{
+ __set_tohost(HTIF_DEV_SYSTEM, cmd, data);
+
+ while (1) {
+ uint64_t fh = fromhost;
+ if (fh) {
+ if (FROMHOST_DEV(fh) == HTIF_DEV_SYSTEM &&
+ FROMHOST_CMD(fh) == cmd) {
+ fromhost = 0;
+ break;
+ }
+ __check_fromhost();
+ }
+ }
+}
+
+void htif_putc(char ch)
+{
+ /* HTIF devices are not supported on RV32, so do a proxy write call */
+ volatile uint64_t magic_mem[8];
+ magic_mem[0] = PK_SYS_write;
+ magic_mem[1] = HTIF_DEV_CONSOLE;
+ magic_mem[2] = (uint64_t)(uintptr_t)&ch;
+ magic_mem[3] = HTIF_CONSOLE_CMD_PUTC;
+ do_tohost_fromhost(HTIF_DEV_SYSTEM, 0, (uint64_t)(uintptr_t)magic_mem);
+}
+#else
+void htif_putc(char ch)
+{
+ __set_tohost(HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_PUTC, ch);
+}
+#endif
+
+int htif_getc(void)
+{
+ int ch;
+
+#if __riscv_xlen == 32
+ /* HTIF devices are not supported on RV32 */
+ return -1;
+#endif
+
+ __check_fromhost();
+ ch = htif_console_buf;
+ if (ch >= 0) {
+ htif_console_buf = -1;
+ __set_tohost(HTIF_DEV_CONSOLE, HTIF_CONSOLE_CMD_GETC, 0);
+ }
+
+ return ch - 1;
+}
+
+int htif_system_reset_check(uint32_t type, uint32_t reason)
+{
+ return 1;
+}
+
+void htif_system_reset(uint32_t type, uint32_t reason)
+{
+ while (1) {
+ fromhost = 0;
+ tohost = 1;
+ }
+}
diff --git a/Demo/RISC-V-spike-htif_GCC/htif.h b/Demo/RISC-V-spike-htif_GCC/htif.h
new file mode 100644
index 000000000..1b08d365b
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/htif.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2010-2020, The Regents of the University of California
+ * (Regents). All Rights Reserved.
+ */
+
+#ifndef __HTIF_H__
+#define __HTIF_H__
+
+#include
+
+void htif_putc(char ch);
+
+int htif_getc(void);
+
+int htif_system_reset_check(uint32_t type, uint32_t reason);
+
+void htif_system_reset(uint32_t type, uint32_t reason);
+
+#endif
diff --git a/Demo/RISC-V-spike-htif_GCC/main.c b/Demo/RISC-V-spike-htif_GCC/main.c
new file mode 100644
index 000000000..981bbaf1b
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/main.c
@@ -0,0 +1,116 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* FreeRTOS kernel includes. */
+#include
+#include
+
+/* Run a simple demo just prints 'Blink' */
+#define DEMO_BLINKY 1
+
+void vApplicationMallocFailedHook( void );
+void vApplicationIdleHook( void );
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
+void vApplicationTickHook( void );
+
+int main_blinky( void );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+ int ret;
+
+#if defined(DEMO_BLINKY)
+ ret = main_blinky();
+#else
+#error "Please add or select demo."
+#endif
+
+ return ret;
+}
+
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c or heap_2.c are used, then the size of the
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+volatile uint32_t ulSetTo1ToExitFunction = 0;
+
+ taskDISABLE_INTERRUPTS();
+ while( ulSetTo1ToExitFunction != 1 )
+ {
+ __asm volatile( "NOP" );
+ }
+}
diff --git a/Demo/RISC-V-spike-htif_GCC/main_blinky.c b/Demo/RISC-V-spike-htif_GCC/main_blinky.c
new file mode 100644
index 000000000..da62e2bf6
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/main_blinky.c
@@ -0,0 +1,137 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* FreeRTOS kernel includes. */
+#include
+#include
+#include
+
+#include
+
+#include "riscv-virt.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue. The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold. The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue. Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+ TickType_t xNextWakeTime;
+ unsigned long ulValueToSend = 0UL;
+
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Place this task in the blocked state until it is time to run again. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+ ulValueToSend++;
+
+ char buf[40];
+ sprintf( buf, "%d: %s: send %ld", xGetCoreID(),
+ pcTaskGetName( xTaskGetCurrentTaskHandle() ),
+ ulValueToSend );
+ vSendString( buf );
+
+ /* 0 is used as the block time so the sending operation will not block -
+ * it shouldn't need to block as the queue should always be empty at
+ * this point in the code. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+ /* Remove compiler warning about unused parameter. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+
+ unsigned long ulReceivedValue;
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue. */
+ char buf[40];
+ sprintf( buf, "%d: %s: received %ld", xGetCoreID(),
+ pcTaskGetName( xTaskGetCurrentTaskHandle() ),
+ ulReceivedValue );
+ vSendString( buf );
+ }
+}
+
+/*-----------------------------------------------------------*/
+
+int main_blinky( void )
+{
+ vSendString( "Hello FreeRTOS!" );
+
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+
+ if( xQueue != NULL )
+ {
+ /* Start the two tasks as described in the comments at the top of this
+ file. */
+ xTaskCreate( prvQueueReceiveTask, "Rx", configMINIMAL_STACK_SIZE * 2U, NULL,
+ mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );
+ xTaskCreate( prvQueueSendTask, "Tx", configMINIMAL_STACK_SIZE * 2U, NULL,
+ mainQUEUE_SEND_TASK_PRIORITY, NULL );
+ }
+
+ vTaskStartScheduler();
+
+ return 0;
+}
diff --git a/Demo/RISC-V-spike-htif_GCC/riscv-reg.h b/Demo/RISC-V-spike-htif_GCC/riscv-reg.h
new file mode 100644
index 000000000..371bb3131
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/riscv-reg.h
@@ -0,0 +1,42 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef RISCV_REG_H_
+#define RISCV_REG_H_
+
+#if __riscv_xlen == 32
+#define REGSIZE 4
+#define REGSHIFT 2
+#define LOAD lw
+#define STOR sw
+#elif __riscv_xlen == 64
+#define REGSIZE 8
+#define REGSHIFT 3
+#define LOAD ld
+#define STOR sd
+#endif /* __riscv_xlen */
+
+#endif /* RISCV_REG_H_ */
diff --git a/Demo/RISC-V-spike-htif_GCC/riscv-virt.c b/Demo/RISC-V-spike-htif_GCC/riscv-virt.c
new file mode 100644
index 000000000..24af20133
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/riscv-virt.c
@@ -0,0 +1,66 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include
+
+#include
+
+#include "riscv-virt.h"
+#include "htif.h"
+
+int xGetCoreID( void )
+{
+ int id;
+
+ __asm ("csrr %0, mhartid" : "=r" ( id ) );
+
+ return id;
+}
+
+/* Use a debugger to set this to 0 if this binary was loaded through gdb instead
+ * of spike's ELF loader. HTIF only works if spike's ELF loader was used. */
+volatile int use_htif = 1;
+
+void vSendString( const char *s )
+{
+ portENTER_CRITICAL();
+
+ if (use_htif) {
+ while (*s) {
+ htif_putc(*s);
+ s++;
+ }
+ htif_putc('\n');
+ }
+
+ portEXIT_CRITICAL();
+}
+
+void handle_trap(void)
+{
+ while (1)
+ ;
+}
diff --git a/Demo/RISC-V-spike-htif_GCC/riscv-virt.h b/Demo/RISC-V-spike-htif_GCC/riscv-virt.h
new file mode 100644
index 000000000..38bc80b29
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/riscv-virt.h
@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef RISCV_VIRT_H_
+#define RISCV_VIRT_H_
+
+#include "riscv-reg.h"
+
+#ifdef __ASSEMBLER__
+#define CONS(NUM, TYPE)NUM
+#else
+#define CONS(NUM, TYPE)NUM##TYPE
+#endif /* __ASSEMBLER__ */
+
+#define PRIM_HART 0
+
+#define CLINT_ADDR CONS(0x02000000, UL)
+#define CLINT_MSIP CONS(0x0000, UL)
+#define CLINT_MTIMECMP CONS(0x4000, UL)
+#define CLINT_MTIME CONS(0xbff8, UL)
+
+#ifndef __ASSEMBLER__
+
+int xGetCoreID( void );
+void vSendString( const char * s );
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* RISCV_VIRT_H_ */
diff --git a/Demo/RISC-V-spike-htif_GCC/spike-1.cfg b/Demo/RISC-V-spike-htif_GCC/spike-1.cfg
new file mode 100644
index 000000000..572a94ea2
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/spike-1.cfg
@@ -0,0 +1,33 @@
+adapter_khz 10000
+
+interface remote_bitbang
+remote_bitbang_host localhost
+remote_bitbang_port 9824
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos auto
+#target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
+
+init
+
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
+
+reg mstatus 0
+
+arm semihosting enable
diff --git a/Demo/RISC-V-spike-htif_GCC/start.S b/Demo/RISC-V-spike-htif_GCC/start.S
new file mode 100644
index 000000000..70b77d390
--- /dev/null
+++ b/Demo/RISC-V-spike-htif_GCC/start.S
@@ -0,0 +1,84 @@
+/*
+ * FreeRTOS V202111.00
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "riscv-virt.h"
+
+ .section .init
+ .globl _start
+ .type _start,@function
+_start:
+ .cfi_startproc
+ .cfi_undefined ra
+.option push
+.option norelax
+ la gp, __global_pointer$
+.option pop
+
+ // Continue primary hart
+ csrr a0, mhartid
+ li a1, PRIM_HART
+ bne a0, a1, secondary
+
+ // Primary hart
+ la sp, _stack_top
+
+ // Load data section
+ la a0, _data_lma
+ la a1, _data
+ la a2, _edata
+ bgeu a1, a2, 2f
+1:
+ LOAD t0, (a0)
+ STOR t0, (a1)
+ addi a0, a0, REGSIZE
+ addi a1, a1, REGSIZE
+ bltu a1, a2, 1b
+2:
+
+ // Clear bss section
+ la a0, _bss
+ la a1, _ebss
+ bgeu a0, a1, 2f
+1:
+ STOR zero, (a0)
+ addi a0, a0, REGSIZE
+ bltu a0, a1, 1b
+2:
+
+ // argc, argv, envp is 0
+ li a0, 0
+ li a1, 0
+ li a2, 0
+ jal main
+1:
+ wfi
+ j 1b
+
+secondary:
+ // TODO: Multicore is not supported
+ wfi
+ j secondary
+ .cfi_endproc
diff --git a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h
index 2c9a6bdac..905a476b4 100644
--- a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h
+++ b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- FreeRTOS V202104.00
+ FreeRTOS V202111.00
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
@@ -72,6 +72,7 @@
#define FREERTOS_CONFIG_H
#include "clock_config.h"
+#include "fsl_debug_console.h"
/*-----------------------------------------------------------
* Application specific definitions.
@@ -148,5 +149,7 @@ header file. */
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configKERNEL_INTERRUPT_PRIORITY 7
+/* Map to the platform printf function. */
+#define configPRINT_STRING( pcString ) PRINTF( pcString )
#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c
index 1c91a8dc9..a99c4fa17 100644
--- a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c
+++ b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/blinky_demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -175,7 +175,6 @@ unsigned long ulReceivedValue;
const unsigned long ulExpectedValue = 100UL;
const char * const pcPassMessage = "Blink\r\n";
const char * const pcFailMessage = "Unexpected value received\r\n";
-extern void vSendString( const char * const pcString );
extern void vToggleLED( void );
/* Remove compiler warning about unused parameter. */
@@ -192,13 +191,13 @@ extern void vToggleLED( void );
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
- vSendString( pcPassMessage );
+ configPRINT_STRING( pcPassMessage );
vToggleLED();
ulReceivedValue = 0U;
}
else
{
- vSendString( pcFailMessage );
+ configPRINT_STRING( pcFailMessage );
}
}
}
diff --git a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
index b5c5a86de..9455172c2 100644
--- a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
+++ b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/RegTest.S
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c
index feaa43db5..2fb132292 100644
--- a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c
+++ b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/full_demo/main_full.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -112,6 +112,8 @@ stack. */
/* Size of the stacks to allocated for the register check tasks. */
#define mainREG_TEST_STACK_SIZE_WORDS 150
+/* Success output messages. This is used by the CI - do not change. */
+#define mainDEMO_SUCCESS_MESSAGE "FreeRTOS Demo SUCCESS\r\n"
/*-----------------------------------------------------------*/
/*
@@ -217,17 +219,15 @@ static void prvCheckTask( void *pvParameters )
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
TickType_t xLastExecutionTime;
uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
-char * const pcPassMessage = ".";
+char * const pcPassMessage = mainDEMO_SUCCESS_MESSAGE;
char * pcStatusMessage = pcPassMessage;
-extern void vSendString( const char * const pcString );
extern void vToggleLED( void );
/* Just to stop compiler warnings. */
( void ) pvParameters;
- /* Output "pass", then an additional '.' character for each successful
- loop. */
- vSendString( "Pass" );
+ /* Demo start marker. */
+ configPRINT_STRING( "FreeRTOS Demo Start\r\n" );
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
works correctly. */
@@ -248,86 +248,86 @@ extern void vToggleLED( void );
that they are all still running, and that none have detected an error. */
if( xAreDynamicPriorityTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Dynamic priority demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Dynamic priority demo/tests.\r\n";
}
if( xAreBlockTimeTestTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Block time demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Block time demo/tests.\r\n";
}
if( xAreGenericQueueTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Generic queue demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Generic queue demo/tests.\r\n";
}
if( xAreRecursiveMutexTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Recursive mutex demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Recursive mutex demo/tests.\r\n";
}
if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) == pdFALSE )
{
- pcStatusMessage = "ERROR: Timer demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Timer demo/tests.\r\n";
}
if( xAreEventGroupTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Event group demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Event group demo/tests.\r\n";
}
if( xAreTaskNotificationTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Task notification demo/tests.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Task notification demo/tests.\r\n";
}
if( xAreAbortDelayTestTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Abort delay.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Abort delay.\r\n";
}
if( xAreCountingSemaphoreTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Counting semaphores.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Counting semaphores.\r\n";
}
if( xIsCreateTaskStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Suicide tasks.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Suicide tasks.\r\n";
}
if( xAreMessageBufferTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Message buffer.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Message buffer.\r\n";
}
if( xAreStreamBufferTasksStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Stream buffer.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Stream buffer.\r\n";
}
if( xIsInterruptStreamBufferDemoStillRunning() == pdFALSE )
{
- pcStatusMessage = "ERROR: Stream buffer interrupt.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Stream buffer interrupt.\r\n";
}
/* Check that the register test 1 task is still running. */
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
{
- pcStatusMessage = "ERROR: Register test 1.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Register test 1.\r\n";
}
ulLastRegTest1Value = ulRegTest1LoopCounter;
/* Check that the register test 2 task is still running. */
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
{
- pcStatusMessage = "ERROR: Register test 2.\r\n";
+ pcStatusMessage = "FreeRTOS Demo ERROR: Register test 2.\r\n";
}
ulLastRegTest2Value = ulRegTest2LoopCounter;
/* Write the status message to the UART. */
vToggleLED();
- vSendString( pcStatusMessage );
+ configPRINT_STRING( pcStatusMessage );
/* If an error has been found then increase the LED toggle rate by
increasing the cycle frequency. */
diff --git a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c
index c18f7ad6e..b76d36d7a 100644
--- a/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c
+++ b/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/main.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -19,10 +19,9 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
*
- * 1 tab == 4 spaces!
*/
@@ -90,9 +89,6 @@ void vApplicationTickHook( void );
/* Prepare hardware to run the demo. */
static void prvSetupHardware( void );
-/* Send a message to the UART initialised in prvSetupHardware. */
-void vSendString( const char * const pcString );
-
/*-----------------------------------------------------------*/
void main( void )
@@ -135,12 +131,6 @@ void vToggleLED( void )
}
/*-----------------------------------------------------------*/
-void vSendString( const char * const pcString )
-{
- PRINTF( pcString );
-}
-/*-----------------------------------------------------------*/
-
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
@@ -215,7 +205,7 @@ void LPIT0_IRQHandler( void )
BaseType_t xTaskIncrementTick( void );
void vTaskSwitchContext( void );
-#warning requires critical section if interrpt nesting is used.
+#warning requires critical section if interrupt nesting is used.
/* vPortSetupTimerInterrupt() uses LPIT0 to generate the tick interrupt. */
if( xTaskIncrementTick() != 0 )
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject
index 038643d0a..baa18f1aa 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/.cproject
@@ -1,176 +1,93 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h
index 18a3ca0fa..419cca159 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
@@ -99,4 +99,7 @@ header file. */
void vAssertCalled( void );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
+/* Map to the platform write function. */
+#define configPRINT_STRING( pcString ) write( STDOUT_FILENO, pcString, strlen( pcString ) )
+
#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c
index e4e572e1f..9a2aecbe5 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/blinky_demo/main_blinky.c
@@ -1,5 +1,5 @@
/*
- * FreeRTOS V202104.00
+ * FreeRTOS V202111.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/README.md b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/README.md
new file mode 100644
index 000000000..f5abca5bf
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/README.md
@@ -0,0 +1,13 @@
+HiFive1 Rev B is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications.
+
+This target is ideal for getting familiar with the RISC-V ISA instruction set and the freedom-metal libraries. It supports:
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Memory Protection with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 interrupt line
+- Serial port with 1 interrupt line
+- 1 RGB LEDS
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/core.dts b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/core.dts
new file mode 100644
index 000000000..f68e58441
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/core.dts
@@ -0,0 +1,262 @@
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sifive,hifive1-revb";
+ model = "sifive,hifive1-revb";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "sifive,fe310-g000";
+ L6: cpu@0 {
+ clocks = <&hfclk>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&spi0>;
+ reg = <0>;
+ riscv,isa = "rv32imac";
+ riscv,pmpregions = <8>;
+ sifive,itim = <&itim>;
+ sifive,dtim = <&dtim>;
+ status = "okay";
+ timebase-frequency = <16000000>;
+ hardware-exec-breakpoint-count = <4>;
+ hlic: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #clock-cells = <1>;
+ compatible = "sifive,hifive1";
+ ranges;
+ hfxoscin: clock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ };
+ hfxoscout: clock@1 {
+ compatible = "sifive,fe310-g000,hfxosc";
+ clocks = <&hfxoscin>;
+ reg = <&prci 0x4>;
+ reg-names = "config";
+ };
+ hfroscin: clock@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <72000000>;
+ };
+ hfroscout: clock@3 {
+ compatible = "sifive,fe310-g000,hfrosc";
+ clocks = <&hfroscin>;
+ reg = <&prci 0x0>;
+ reg-names = "config";
+ };
+ hfclk: clock@4 {
+ compatible = "sifive,fe310-g000,pll";
+ clocks = <&hfxoscout &hfroscout>;
+ clock-names = "pllref", "pllsel0";
+ reg = <&prci 0x8 &prci 0xc>;
+ reg-names = "config", "divider";
+ clock-frequency = <16000000>;
+ };
+ lfrosc: clock@5 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+ psdlfaltclk: clock@6 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+ lfclk: clock@7 {
+ compatible = "sifive,fe310-g000,lfrosc";
+ clocks = <&lfrosc &psdlfaltclk>;
+ clock-names = "lfrosc", "psdlfaltclk";
+ reg = <&aon 0x70 &aon 0x7C>;
+ reg-names = "config", "mux";
+ };
+ debug-controller@0 {
+ compatible = "sifive,debug-011", "riscv,debug-011";
+ interrupts-extended = <&hlic 65535>;
+ reg = <0x0 0x1000>;
+ reg-names = "control";
+ };
+ /* Missing: Error device */
+ maskrom@1000 {
+ reg = <0x1000 0x2000>;
+ reg-names = "mem";
+ };
+ otp@20000 {
+ reg = <0x20000 0x2000 0x10010000 0x1000>;
+ reg-names = "mem", "control";
+ };
+ clint: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&hlic 3 &hlic 7>;
+ reg = <0x2000000 0x10000>;
+ reg-names = "control";
+ };
+ itim: itim@8000000 {
+ compatible = "sifive,itim0";
+ reg = <0x8000000 0x2000>;
+ reg-names = "mem";
+ };
+ plic: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <&hlic 11>;
+ reg = <0xc000000 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <52>;
+ };
+ aon: aon@10000000 {
+ compatible = "sifive,aon0";
+ reg = <0x10000000 0x8000>;
+ reg-names = "mem";
+ interrupt-parent = <&plic>;
+ interrupts = <1 2>;
+ clocks = <&lfclk>;
+ };
+ prci: prci@10008000 {
+ compatible = "sifive,fe310-g000,prci";
+ reg = <0x10008000 0x8000>;
+ reg-names = "mem";
+ };
+ gpio0: gpio@10012000 {
+ compatible = "sifive,gpio0";
+ interrupt-parent = <&plic>;
+ interrupts = <8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+ 23 24 25 26 27 28 29 30 31 32 33 34 35 36
+ 27 28 29>;
+ reg = <0x10012000 0x1000>;
+ reg-names = "control";
+ };
+ led@0 {
+ compatible = "sifive,gpio-leds";
+ label = "LD0red";
+ gpios = <&gpio0 22>;
+ linux,default-trigger = "none";
+ };
+ led@1 {
+ compatible = "sifive,gpio-leds";
+ label = "LD0green";
+ gpios = <&gpio0 19>;
+ linux,default-trigger = "none";
+ };
+ led@2 {
+ compatible = "sifive,gpio-leds";
+ label = "LD0blue";
+ gpios = <&gpio0 21>;
+ linux,default-trigger = "none";
+ };
+ uart0: serial@10013000 {
+ compatible = "sifive,uart0";
+ interrupt-parent = <&plic>;
+ interrupts = <3>;
+ reg = <0x10013000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0 0x30000>;
+ };
+ spi0: spi@10014000 {
+ compatible = "sifive,spi0";
+ interrupt-parent = <&plic>;
+ interrupts = <5>;
+ reg = <0x10014000 0x1000 0x20000000 0x7A120>;
+ reg-names = "control", "mem";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0 0x0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x20000000 0x424000>;
+ };
+ };
+ pwm0: pwm@10015000 {
+ compatible = "sifive,pwm0";
+ sifive,comparator-widthbits = <8>;
+ sifive,ncomparators = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <40 41 42 43>;
+ reg = <0x10015000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0F 0x0F>;
+ };
+ i2c0: i2c@10016000 {
+ compatible = "sifive,i2c0";
+ interrupt-parent = <&plic>;
+ interrupts = <52>;
+ reg = <0x10016000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0 0x3000>;
+ };
+ uart1: serial@10023000 {
+ compatible = "sifive,uart0";
+ interrupt-parent = <&plic>;
+ interrupts = <4>;
+ reg = <0x10023000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0 0x840000>;
+ };
+ spi1: spi@10024000 {
+ compatible = "sifive,spi0";
+ interrupt-parent = <&plic>;
+ interrupts = <6>;
+ reg = <0x10024000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0 0x0003C>;
+ };
+ pwm1: pwm@10025000 {
+ compatible = "sifive,pwm0";
+ sifive,comparator-widthbits = <16>;
+ sifive,ncomparators = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <44 45 46 47>;
+ reg = <0x10025000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x780000 0x780000>;
+ };
+ spi2: spi@10034000 {
+ compatible = "sifive,spi0";
+ interrupt-parent = <&plic>;
+ interrupts = <7>;
+ reg = <0x10034000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x0 0xFC000000>;
+ };
+ pwm2: pwm@10035000 {
+ compatible = "sifive,pwm0";
+ sifive,comparator-widthbits = <16>;
+ sifive,ncomparators = <4>;
+ interrupt-parent = <&plic>;
+ interrupts = <48 49 50 51>;
+ reg = <0x10035000 0x1000>;
+ reg-names = "control";
+ clocks = <&hfclk>;
+ pinmux = <&gpio0 0x3C00 0x3C00>;
+ };
+ dtim: dtim@80000000 {
+ compatible = "sifive,dtim0";
+ reg = <0x80000000 0x4000>;
+ reg-names = "mem";
+ };
+ };
+};
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.dts b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.dts
index 970d3be72..098c25c4b 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.dts
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.dts
@@ -1,209 +1,10 @@
-/dts-v1/;
-
+/include/ "core.dts"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "sifive,hifive1-revb";
- model = "sifive,hifive1-revb";
-
- chosen {
- stdout-path = "/soc/serial@10013000:115200";
- metal,entry = <&spi0 0x10000>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "sifive,fe310-g000";
- L6: cpu@0 {
- clocks = <&hfclk>;
- compatible = "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- next-level-cache = <&spi0>;
- reg = <0>;
- riscv,isa = "rv32imac";
- riscv,pmpregions = <8>;
- sifive,dtim = <&dtim>;
- status = "okay";
- timebase-frequency = <1000000>;
- hardware-exec-breakpoint-count = <4>;
- hlic: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- #clock-cells = <1>;
- compatible = "sifive,hifive1";
- ranges;
- hfxoscin: clock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <16000000>;
- };
- hfxoscout: clock@1 {
- compatible = "sifive,fe310-g000,hfxosc";
- clocks = <&hfxoscin>;
- reg = <&prci 0x4>;
- reg-names = "config";
- };
- hfroscin: clock@2 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <72000000>;
- };
- hfroscout: clock@3 {
- compatible = "sifive,fe310-g000,hfrosc";
- clocks = <&hfroscin>;
- reg = <&prci 0x0>;
- reg-names = "config";
- };
- hfclk: clock@4 {
- compatible = "sifive,fe310-g000,pll";
- clocks = <&hfxoscout &hfroscout>;
- clock-names = "pllref", "pllsel0";
- reg = <&prci 0x8 &prci 0xc>;
- reg-names = "config", "divider";
- clock-frequency = <16000000>;
- };
-
- lfroscin: clock@5 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32000000>;
- };
- lfclk: clock@6 {
- compatible = "sifive,fe310-g000,lfrosc";
- clocks = <&lfroscin>;
- reg = <&aon 0x70>;
- reg-names = "config";
- };
-
- aon: aon@10000000 {
- compatible = "sifive,aon0";
- reg = <0x10000000 0x8000>;
- reg-names = "mem";
- };
-
- prci: prci@10008000 {
- compatible = "sifive,fe310-g000,prci";
- reg = <0x10008000 0x8000>;
- reg-names = "mem";
- };
-
- clint: clint@2000000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&hlic 3 &hlic 7>;
- reg = <0x2000000 0x10000>;
- reg-names = "control";
- };
- local-external-interrupts-0 {
- compatible = "sifive,local-external-interrupts0";
- interrupt-parent = <&hlic>;
- interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
- };
- plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,plic0";
- interrupt-controller;
- interrupts-extended = <&hlic 11>;
- reg = <0xc000000 0x4000000>;
- reg-names = "control";
- riscv,max-priority = <7>;
- riscv,ndev = <26>;
- };
- global-external-interrupts {
- compatile = "sifive,global-external-interrupts0";
- interrupt-parent = <&plic>;
- interrupts = <1 2 3 4>;
- };
-
- debug-controller@0 {
- compatible = "sifive,debug-011", "riscv,debug-011";
- interrupts-extended = <&hlic 65535>;
- reg = <0x0 0x100>;
- reg-names = "control";
- };
-
- maskrom@1000 {
- reg = <0x1000 0x2000>;
- reg-names = "mem";
- };
- otp@20000 {
- reg = <0x20000 0x2000 0x10010000 0x1000>;
- reg-names = "mem", "control";
- };
-
- dtim: dtim@80000000 {
- compatible = "sifive,dtim0";
- reg = <0x80000000 0x4000>;
- reg-names = "mem";
- };
-
- pwm@10015000 {
- compatible = "sifive,pwm0";
- interrupt-parent = <&plic>;
- interrupts = <23 24 25 26>;
- reg = <0x10015000 0x1000>;
- reg-names = "control";
- };
- gpio0: gpio@10012000 {
- compatible = "sifive,gpio0";
- interrupt-parent = <&plic>;
- interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
- reg = <0x10012000 0x1000>;
- reg-names = "control";
- };
- uart0: serial@10013000 {
- compatible = "sifive,uart0";
- interrupt-parent = <&plic>;
- interrupts = <5>;
- reg = <0x10013000 0x1000>;
- reg-names = "control";
- clocks = <&hfclk>;
- pinmux = <&gpio0 0x30000 0x30000>;
- };
- spi0: spi@10014000 {
- compatible = "sifive,spi0";
- interrupt-parent = <&plic>;
- interrupts = <6>;
- reg = <0x10014000 0x1000 0x20000000 0x7A120>;
- reg-names = "control", "mem";
- clocks = <&hfclk>;
- pinmux = <&gpio0 0x0003C 0x0003C>;
- };
- i2c0: i2c@10016000 {
- compatible = "sifive,i2c0";
- interrupt-parent = <&plic>;
- interrupts = <52>;
- reg = <0x10016000 0x1000>;
- reg-names = "control";
- };
- led@0red {
- compatible = "sifive,gpio-leds";
- label = "LD0red";
- gpios = <&gpio0 22>;
- linux,default-trigger = "none";
- };
- led@0green {
- compatible = "sifive,gpio-leds";
- label = "LD0green";
- gpios = <&gpio0 19>;
- linux,default-trigger = "none";
- };
- led@0blue {
- compatible = "sifive,gpio-leds";
- label = "LD0blue";
- gpios = <&gpio0 21>;
- linux,default-trigger = "none";
- };
- };
+ chosen {
+ metal,entry = <&spi0 1 65536>;
+ metal,boothart = <&L6>;
+ stdout-path = "/soc/serial@10013000:115200";
+ metal,itim = <&itim 0 0>;
+ metal,ram = <&dtim 0 0>;
+ };
};
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.svd b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.svd
new file mode 100644
index 000000000..3ad2768bd
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/design.svd
@@ -0,0 +1,3169 @@
+
+
+ sifive_hifive1_revb
+ 0.1
+ From sifive,hifive1-revb,model device generator
+ 8
+ 32
+ 32
+ read-write
+
+
+ riscv_clint0_0
+ From riscv,clint0,control peripheral generator
+ 0x2000000
+
+ 0
+ 0x10000
+ registers
+
+
+
+ msip_0
+ MSIP Register for hart 0
+ 0x0
+
+
+ mtimecmp_0
+ MTIMECMP Register for hart 0
+ 0x4000
+ 64
+
+
+ mtime
+ MTIME Register
+ 0xBFF8
+ 64
+
+
+
+
+ riscv_plic0_0
+ From riscv,plic0,control peripheral generator
+ 0xC000000
+
+ 0
+ 0x4000000
+ registers
+
+
+
+ priority_1
+ PRIORITY Register for interrupt id 1
+ 0x4
+
+
+ priority_2
+ PRIORITY Register for interrupt id 2
+ 0x8
+
+
+ priority_3
+ PRIORITY Register for interrupt id 3
+ 0xC
+
+
+ priority_4
+ PRIORITY Register for interrupt id 4
+ 0x10
+
+
+ priority_5
+ PRIORITY Register for interrupt id 5
+ 0x14
+
+
+ priority_6
+ PRIORITY Register for interrupt id 6
+ 0x18
+
+
+ priority_7
+ PRIORITY Register for interrupt id 7
+ 0x1C
+
+
+ priority_8
+ PRIORITY Register for interrupt id 8
+ 0x20
+
+
+ priority_9
+ PRIORITY Register for interrupt id 9
+ 0x24
+
+
+ priority_10
+ PRIORITY Register for interrupt id 10
+ 0x28
+
+
+ priority_11
+ PRIORITY Register for interrupt id 11
+ 0x2C
+
+
+ priority_12
+ PRIORITY Register for interrupt id 12
+ 0x30
+
+
+ priority_13
+ PRIORITY Register for interrupt id 13
+ 0x34
+
+
+ priority_14
+ PRIORITY Register for interrupt id 14
+ 0x38
+
+
+ priority_15
+ PRIORITY Register for interrupt id 15
+ 0x3C
+
+
+ priority_16
+ PRIORITY Register for interrupt id 16
+ 0x40
+
+
+ priority_17
+ PRIORITY Register for interrupt id 17
+ 0x44
+
+
+ priority_18
+ PRIORITY Register for interrupt id 18
+ 0x48
+
+
+ priority_19
+ PRIORITY Register for interrupt id 19
+ 0x4C
+
+
+ priority_20
+ PRIORITY Register for interrupt id 20
+ 0x50
+
+
+ priority_21
+ PRIORITY Register for interrupt id 21
+ 0x54
+
+
+ priority_22
+ PRIORITY Register for interrupt id 22
+ 0x58
+
+
+ priority_23
+ PRIORITY Register for interrupt id 23
+ 0x5C
+
+
+ priority_24
+ PRIORITY Register for interrupt id 24
+ 0x60
+
+
+ priority_25
+ PRIORITY Register for interrupt id 25
+ 0x64
+
+
+ priority_26
+ PRIORITY Register for interrupt id 26
+ 0x68
+
+
+ priority_27
+ PRIORITY Register for interrupt id 27
+ 0x6C
+
+
+ priority_28
+ PRIORITY Register for interrupt id 28
+ 0x70
+
+
+ priority_29
+ PRIORITY Register for interrupt id 29
+ 0x74
+
+
+ priority_30
+ PRIORITY Register for interrupt id 30
+ 0x78
+
+
+ priority_31
+ PRIORITY Register for interrupt id 31
+ 0x7C
+
+
+ priority_32
+ PRIORITY Register for interrupt id 32
+ 0x80
+
+
+ priority_33
+ PRIORITY Register for interrupt id 33
+ 0x84
+
+
+ priority_34
+ PRIORITY Register for interrupt id 34
+ 0x88
+
+
+ priority_35
+ PRIORITY Register for interrupt id 35
+ 0x8C
+
+
+ priority_36
+ PRIORITY Register for interrupt id 36
+ 0x90
+
+
+ priority_37
+ PRIORITY Register for interrupt id 37
+ 0x94
+
+
+ priority_38
+ PRIORITY Register for interrupt id 38
+ 0x98
+
+
+ priority_39
+ PRIORITY Register for interrupt id 39
+ 0x9C
+
+
+ priority_40
+ PRIORITY Register for interrupt id 40
+ 0xA0
+
+
+ priority_41
+ PRIORITY Register for interrupt id 41
+ 0xA4
+
+
+ priority_42
+ PRIORITY Register for interrupt id 42
+ 0xA8
+
+
+ priority_43
+ PRIORITY Register for interrupt id 43
+ 0xAC
+
+
+ priority_44
+ PRIORITY Register for interrupt id 44
+ 0xB0
+
+
+ priority_45
+ PRIORITY Register for interrupt id 45
+ 0xB4
+
+
+ priority_46
+ PRIORITY Register for interrupt id 46
+ 0xB8
+
+
+ priority_47
+ PRIORITY Register for interrupt id 47
+ 0xBC
+
+
+ priority_48
+ PRIORITY Register for interrupt id 48
+ 0xC0
+
+
+ priority_49
+ PRIORITY Register for interrupt id 49
+ 0xC4
+
+
+ priority_50
+ PRIORITY Register for interrupt id 50
+ 0xC8
+
+
+ priority_51
+ PRIORITY Register for interrupt id 51
+ 0xCC
+
+
+ priority_52
+ PRIORITY Register for interrupt id 52
+ 0xD0
+
+
+ pending_0
+ PENDING Register for interrupt ids 31 to 0
+ 0x1000
+
+
+ pending_1
+ PENDING Register for interrupt ids 52 to 32
+ 0x1004
+
+
+ enable_0_0
+ ENABLE Register for interrupt ids 31 to 0 for hart 0
+ 0x2000
+
+
+ enable_1_0
+ ENABLE Register for interrupt ids 52 to 32 for hart 0
+ 0x2004
+
+
+ threshold_0
+ PRIORITY THRESHOLD Register for hart 0
+ 0x200000
+
+
+ claimplete_0
+ CLAIM and COMPLETE Register for hart 0
+ 0x200004
+
+
+
+
+ sifive_aon0_0
+ From sifive,aon0,mem peripheral generator
+ 0x10000000
+
+ 0
+ 0x8000
+ registers
+
+
+
+ backup_0
+ Backup Register 0
+ 0x80
+
+
+ backup_1
+ Backup Register 1
+ 0x84
+
+
+ backup_2
+ Backup Register 2
+ 0x88
+
+
+ backup_3
+ Backup Register 3
+ 0x8C
+
+
+ backup_4
+ Backup Register 4
+ 0x90
+
+
+ backup_5
+ Backup Register 5
+ 0x94
+
+
+ backup_6
+ Backup Register 6
+ 0x98
+
+
+ backup_7
+ Backup Register 7
+ 0x9C
+
+
+ backup_8
+ Backup Register 8
+ 0xA0
+
+
+ backup_9
+ Backup Register 9
+ 0xA4
+
+
+ backup_10
+ Backup Register 10
+ 0xA8
+
+
+ backup_11
+ Backup Register 11
+ 0xAC
+
+
+ backup_12
+ Backup Register 12
+ 0xB0
+
+
+ backup_13
+ Backup Register 13
+ 0xB4
+
+
+ backup_14
+ Backup Register 14
+ 0xB8
+
+
+ backup_15
+ Backup Register 15
+ 0xBC
+
+
+ wdogcfg
+ wdog Configuration
+ 0x0
+
+
+ wdogscale
+ Counter scale value.
+ [3:0]
+ read-write
+
+
+ wdogrsten
+ Controls whether the comparator output can set the wdogrst bit and hence cause a full reset.
+ [8:8]
+ read-write
+
+
+ wdogzerocmp
+ Reset counter to zero after match.
+ [9:9]
+ read-write
+
+
+ wdogenalways
+ Enable Always - run continuously
+ [12:12]
+ read-write
+
+
+ wdogcoreawake
+ Increment the watchdog counter if the processor is not asleep
+ [13:13]
+ read-write
+
+
+ wdogip0
+ Interrupt 0 Pending
+ [28:28]
+ read-write
+
+
+
+
+ wdogcount
+ Counter Register
+ 0x8
+
+
+ wdogs
+ Scaled value of Counter
+ 0x10
+
+
+ wdogfeed
+ Feed register
+ 0x18
+
+
+ wdogkey
+ Key Register
+ 0x1C
+
+
+ wdogcmp0
+ Comparator 0
+ 0x20
+
+
+ rtccfg
+ rtc Configuration
+ 0x40
+
+
+ rtcscale
+ Counter scale value.
+ [3:0]
+ read-write
+
+
+ rtcenalways
+ Enable Always - run continuously
+ [12:12]
+ read-write
+
+
+ rtcip0
+ Interrupt 0 Pending
+ [28:28]
+ read-write
+
+
+
+
+ rtccountlo
+ Low bits of Counter
+ 0x48
+
+
+ rtccounthi
+ High bits of Counter
+ 0x4C
+
+
+ rtcs
+ Scaled value of Counter
+ 0x50
+
+
+ rtccmp0
+ Comparator 0
+ 0x60
+
+
+ pmuwakeupi0
+ Wakeup program instruction 0
+ 0x100
+
+
+ pmuwakeupi1
+ Wakeup program instruction 1
+ 0x104
+
+
+ pmuwakeupi2
+ Wakeup program instruction 2
+ 0x108
+
+
+ pmuwakeupi3
+ Wakeup program instruction 3
+ 0x10C
+
+
+ pmuwakeupi4
+ Wakeup program instruction 4
+ 0x110
+
+
+ pmuwakeupi5
+ Wakeup program instruction 5
+ 0x114
+
+
+ pmuwakeupi6
+ Wakeup program instruction 6
+ 0x118
+
+
+ pmuwakeupi7
+ Wakeup program instruction 7
+ 0x11C
+
+
+ pmusleepi0
+ Sleep program instruction 0
+ 0x120
+
+
+ pmusleepi1
+ Sleep program instruction 1
+ 0x124
+
+
+ pmusleepi2
+ Sleep program instruction 2
+ 0x128
+
+
+ pmusleepi3
+ Sleep program instruction 3
+ 0x12C
+
+
+ pmusleepi4
+ Sleep program instruction 4
+ 0x130
+
+
+ pmusleepi5
+ Sleep program instruction 5
+ 0x134
+
+
+ pmusleepi6
+ Sleep program instruction 6
+ 0x138
+
+
+ pmusleepi7
+ Sleep program instruction 7
+ 0x13C
+
+
+ pmuie
+ PMU Interrupt Enables
+ 0x140
+
+
+ pmucause
+ PMU Wakeup Cause
+ 0x144
+
+
+ pmusleep
+ Initiate PMU Sleep Sequence
+ 0x148
+
+
+ pmukey
+ PMU Key. Reads as 1 when PMU is unlocked
+ 0x14C
+
+
+ aoncfg
+ AON Block Configuration Information
+ 0x300
+
+
+ has_bandgap
+ Bandgap feature is present
+ [0:0]
+ read-only
+
+
+ has_bod
+ Brownout detector feature is present
+ [1:1]
+ read-only
+
+
+ has_lfrosc
+ Low Frequency Ring Oscillator feature is present
+ [2:2]
+ read-only
+
+
+ has_lfrcosc
+ Low Frequency RC Oscillator feature is present
+ [3:3]
+ read-only
+
+
+ has_lfxosc
+ Low Frequency Crystal Oscillator feature is present
+ [4:4]
+ read-only
+
+
+ has_por
+ Power-On-Reset feature is present
+ [5:5]
+ read-only
+
+
+ has_ldo
+ Low Dropout Regulator feature is present
+ [6:6]
+ read-only
+
+
+
+
+ lfrosccfg
+ Ring Oscillator Configuration and Status
+ 0x70
+
+
+ lfroscdiv
+ Ring Oscillator Divider Register
+ [5:0]
+ read-write
+
+
+ lfrosctrim
+ Ring Oscillator Trim Register
+ [20:16]
+ read-write
+
+
+ lfroscen
+ Ring Oscillator Enable
+ [30:30]
+ read-write
+
+
+ lfroscrdy
+ Ring Oscillator Ready
+ [31:31]
+ read-only
+
+
+
+
+ lfclkmux
+ Low-Frequency Clock Mux Control and Status
+ 0x7C
+
+
+ lfextclk_sel
+ Low Frequency Clock Source Selector
+ [0:0]
+ read-write
+
+
+ internal
+ Use internal LF clock source
+ 0
+
+
+ external
+ Use external LF clock source
+ 1
+
+
+
+
+ lfextclk_mux_status
+ Setting of the aon_lfclksel pin
+ [31:31]
+ read-only
+
+
+ external
+ Use external LF clock source
+ 0
+
+
+ sw
+ Use clock source selected by lfextclk_sel
+ 1
+
+
+
+
+
+
+
+
+ sifive_fe310_g000_prci_0
+ From sifive,fe310-g000,prci,mem peripheral generator
+ 0x10008000
+
+ 0
+ 0x8000
+ registers
+
+
+
+ hfrosccfg
+ Ring Oscillator Configuration and Status
+ 0x0
+
+
+ hfroscdiv
+ Ring Oscillator Divider Register
+ [5:0]
+ read-write
+
+
+ hfrosctrim
+ Ring Oscillator Trim Register
+ [20:16]
+ read-write
+
+
+ hfroscen
+ Ring Oscillator Enable
+ [30:30]
+ read-write
+
+
+ hfroscrdy
+ Ring Oscillator Ready
+ [31:31]
+ read-only
+
+
+
+
+ hfxosccfg
+ Crystal Oscillator Configuration and Status
+ 0x4
+
+
+ hfxoscen
+ Crystal Oscillator Enable
+ [30:30]
+ read-write
+
+
+ hfxoscrdy
+ Crystal Oscillator Ready
+ [31:31]
+ read-only
+
+
+
+
+ pllcfg
+ PLL Configuration and Status
+ 0x8
+
+
+ pllr
+ PLL R Value
+ [2:0]
+ read-write
+
+
+ pllf
+ PLL F Value
+ [9:4]
+ read-write
+
+
+ pllq
+ PLL Q Value
+ [11:10]
+ read-write
+
+
+ pllsel
+ PLL Select
+ [16:16]
+ read-write
+
+
+ pllrefsel
+ PLL Reference Select
+ [17:17]
+ read-write
+
+
+ pllbypass
+ PLL Bypass
+ [18:18]
+ read-write
+
+
+ plllock
+ PLL Lock
+ [31:31]
+ read-only
+
+
+
+
+ plloutdiv
+ PLL Final Divide Configuration
+ 0xC
+
+
+ plloutdiv
+ PLL Final Divider Value
+ [5:0]
+ read-write
+
+
+ plloutdivby1
+ PLL Final Divide By 1
+ [13:8]
+ read-write
+
+
+
+
+ procmoncfg
+ Process Monitor Configuration and Status
+ 0xF0
+
+
+ procmon_div_sel
+ Proccess Monitor Divider
+ [4:0]
+ read-write
+
+
+ procmon_delay_sel
+ Process Monitor Delay Selector
+ [12:8]
+ read-write
+
+
+ procmon_en
+ Process Monitor Enable
+ [16:16]
+ read-write
+
+
+ procomon_sel
+ Process Monitor Select
+ [25:24]
+ read-write
+
+
+
+
+
+
+ sifive_gpio0_0
+ From sifive,gpio0,control peripheral generator
+ 0x10012000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ input_val
+ Pin value
+ 0x0
+
+
+ input_en
+ Pin input enable
+ 0x4
+
+
+ output_en
+ Pin output enable
+ 0x8
+
+
+ output_val
+ Output value
+ 0xC
+
+
+ pue
+ Internal pull-up enable
+ 0x10
+
+
+ ds
+ Pin drive strength
+ 0x14
+
+
+ rise_ie
+ Rise interrupt enable
+ 0x18
+
+
+ rise_ip
+ Rise interrupt pending
+ 0x1C
+
+
+ fall_ie
+ Fall interrupt enable
+ 0x20
+
+
+ fall_ip
+ Fall interrupt pending
+ 0x24
+
+
+ high_ie
+ High interrupt enable
+ 0x28
+
+
+ high_ip
+ High interrupt pending
+ 0x2C
+
+
+ low_ie
+ Low interrupt enable
+ 0x30
+
+
+ low_ip
+ Low interrupt pending
+ 0x34
+
+
+ iof_en
+ I/O function enable
+ 0x38
+
+
+ iof_sel
+ I/O function select
+ 0x3C
+
+
+ out_xor
+ Output XOR (invert)
+ 0x40
+
+
+
+
+ sifive_uart0_0
+ From sifive,uart0,control peripheral generator
+ 0x10013000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ txdata
+ Transmit data register
+ 0x0
+
+
+ data
+ Transmit data
+ [7:0]
+ read-write
+
+
+ full
+ Transmit FIFO full
+ [31:31]
+ read-only
+
+
+
+
+ rxdata
+ Receive data register
+ 0x4
+
+
+ data
+ Received data
+ [7:0]
+ read-only
+
+
+ empty
+ Receive FIFO empty
+ [31:31]
+ read-only
+
+
+
+
+ txctrl
+ Transmit control register
+ 0x8
+
+
+ txen
+ Transmit enable
+ [0:0]
+ read-write
+
+
+ nstop
+ Number of stop bits
+ [1:1]
+ read-write
+
+
+ txcnt
+ Transmit watermark level
+ [18:16]
+ read-write
+
+
+
+
+ rxctrl
+ Receive control register
+ 0xC
+
+
+ rxen
+ Receive enable
+ [0:0]
+ read-write
+
+
+ rxcnt
+ Receive watermark level
+ [18:16]
+ read-write
+
+
+
+
+ ie
+ UART interrupt enable
+ 0x10
+
+
+ txwm
+ Transmit watermark interrupt enable
+ [0:0]
+ read-write
+
+
+ rxwm
+ Receive watermark interrupt enable
+ [1:1]
+ read-write
+
+
+
+
+ ip
+ UART interrupt pending
+ 0x14
+
+
+ txwm
+ Transmit watermark interrupt pending
+ [0:0]
+ read-only
+
+
+ rxwm
+ Receive watermark interrupt pending
+ [1:1]
+ read-only
+
+
+
+
+ div
+ Baud rate divisor
+ 0x18
+
+
+ div
+ Baud rate divisor.
+ [15:0]
+ read-write
+
+
+
+
+
+
+ sifive_spi0_0
+ From sifive,spi0,control peripheral generator
+ 0x10014000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ sckdiv
+ Serial clock divisor
+ 0x0
+
+
+ div
+ Divisor for serial clock.
+ [11:0]
+ read-write
+
+
+
+
+ sckmode
+ Serial clock mode
+ 0x4
+
+
+ pha
+ Serial clock phase
+ [0:0]
+ read-write
+
+
+ pol
+ Serial clock polarity
+ [1:1]
+ read-write
+
+
+
+
+ csid
+ Chip select ID
+ 0x10
+
+
+ csid
+ Chip select ID.
+ [31:0]
+ read-write
+
+
+
+
+ csdef
+ Chip select default
+ 0x14
+
+
+ csdef
+ Chip select default value. Reset to all-1s.
+ [31:0]
+ read-write
+
+
+
+
+ csmode
+ Chip select mode
+ 0x18
+
+
+ mode
+ Chip select mode
+ [1:0]
+ read-write
+
+
+
+
+ delay0
+ Delay control 0
+ 0x28
+
+
+ cssck
+ CS to SCK Delay
+ [7:0]
+ read-write
+
+
+ sckcs
+ SCK to CS Delay
+ [23:16]
+ read-write
+
+
+
+
+ delay1
+ Delay control 1
+ 0x2C
+
+
+ intercs
+ Minimum CS inactive time
+ [7:0]
+ read-write
+
+
+ interxfr
+ Maximum interframe delay
+ [23:16]
+ read-write
+
+
+
+
+ extradel
+ SPI extra sampling delay to increase the SPI frequency
+ 0x38
+
+
+ coarse
+ Coarse grain sample delay (multiples of system clocks)
+ [11:0]
+ read-write
+
+
+ fine
+ Fine grain sample delay (multiples of process-specific buffer delay)
+ [16:12]
+ read-write
+
+
+
+
+ sampledel
+ Number of delay stages from slave to the SPI controller
+ 0x3C
+
+
+ sd
+ Number of delay stages from slave to SPI controller
+ [4:0]
+ read-write
+
+
+
+
+ fmt
+ Frame format
+ 0x40
+
+
+ proto
+ SPI protocol
+ [1:0]
+ read-write
+
+
+ endian
+ SPI endianness
+ [2:2]
+ read-write
+
+
+ dir
+ SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise.
+ [3:3]
+ read-write
+
+
+ len
+ Number of bits per frame
+ [19:16]
+ read-write
+
+
+
+
+ txdata
+ Tx FIFO Data
+ 0x48
+
+
+ data
+ Transmit data
+ [7:0]
+ read-write
+
+
+ full
+ FIFO full flag
+ [31:31]
+ read-only
+
+
+
+
+ rxdata
+ Rx FIFO data
+ 0x4C
+
+
+ data
+ Received data
+ [7:0]
+ read-only
+
+
+ empty
+ FIFO empty flag
+ [31:31]
+ read-write
+
+
+
+
+ txmark
+ Tx FIFO watermark
+ 0x50
+
+
+ txmark
+ Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise.
+ [2:0]
+ read-write
+
+
+
+
+ rxmark
+ Rx FIFO watermark
+ 0x54
+
+
+ rxmark
+ Receive watermark
+ [2:0]
+ read-write
+
+
+
+
+ fctrl
+ SPI flash interface control
+ 0x60
+
+
+ en
+ SPI Flash Mode Select
+ [0:0]
+ read-write
+
+
+
+
+ ffmt
+ SPI flash instruction format
+ 0x64
+
+
+ cmd_en
+ Enable sending of command
+ [0:0]
+ read-write
+
+
+ addr_len
+ Number of address bytes (0 to 4)
+ [3:1]
+ read-write
+
+
+ pad_cnt
+ Number of dummy cycles
+ [7:4]
+ read-write
+
+
+ cmd_proto
+ Protocol for transmitting command
+ [9:8]
+ read-write
+
+
+ addr_proto
+ Protocol for transmitting address and padding
+ [11:10]
+ read-write
+
+
+ data_proto
+ Protocol for receiving data bytes
+ [13:12]
+ read-write
+
+
+ cmd_code
+ Value of command byte
+ [23:16]
+ read-write
+
+
+ pad_code
+ First 8 bits to transmit during dummy cycles
+ [31:24]
+ read-write
+
+
+
+
+ ie
+ SPI interrupt enable
+ 0x70
+
+
+ txwm
+ Transmit watermark enable
+ [0:0]
+ read-write
+
+
+ rxwm
+ Receive watermark enable
+ [1:1]
+ read-write
+
+
+
+
+ ip
+ SPI interrupt pending
+ 0x74
+
+
+ txwm
+ Transmit watermark pending
+ [0:0]
+ read-only
+
+
+ rxwm
+ Receive watermark pending
+ [1:1]
+ read-only
+
+
+
+
+
+
+ sifive_pwm0_0
+ From sifive,pwm0,control peripheral generator
+ 0x10015000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ pwmcfg
+ PWM configuration register
+ 0x0
+
+
+ pwmscale
+ PWM Counter scale
+ [3:0]
+ read-write
+
+
+ pwmsticky
+ PWM Sticky - disallow clearing pwmcmpXip bits
+ [8:8]
+ read-write
+
+
+ pwmzerocmp
+ PWM Zero - counter resets to zero after match
+ [9:9]
+ read-write
+
+
+ pwmdeglitch
+ PWM Deglitch - latch pwmcmpXip within same cycle
+ [10:10]
+ read-write
+
+
+ pwmenalways
+ PWM enable always - run continuously
+ [12:12]
+ read-write
+
+
+ pwmenoneshot
+ PWM enable one shot - run one cycle
+ [13:13]
+ read-write
+
+
+ pwmcmp0center
+ PWM0 Compare Center
+ [16:16]
+ read-write
+
+
+ pwmcmp1center
+ PWM1 Compare Center
+ [17:17]
+ read-write
+
+
+ pwmcmp2center
+ PWM2 Compare Center
+ [18:18]
+ read-write
+
+
+ pwmcmp3center
+ PWM3 Compare Center
+ [19:19]
+ read-write
+
+
+ pwmcmp0invert
+ PWM0 Invert
+ [20:20]
+ read-write
+
+
+ pwmcmp1invert
+ PWM1 Invert
+ [21:21]
+ read-write
+
+
+ pwmcmp2invert
+ PWM2 Invert
+ [22:22]
+ read-write
+
+
+ pwmcmp3invert
+ PWM3 Invert
+ [23:23]
+ read-write
+
+
+ pwmcmp0gang
+ PWM0/PWM1 Compare Gang
+ [24:24]
+ read-write
+
+
+ pwmcmp1gang
+ PWM1/PWM2 Compare Gang
+ [25:25]
+ read-write
+
+
+ pwmcmp2gang
+ PWM2/PWM3 Compare Gang
+ [26:26]
+ read-write
+
+
+ pwmcmp3gang
+ PWM3/PWM0 Compare Gang
+ [27:27]
+ read-write
+
+
+ pwmcmp0ip
+ PWM0 Interrupt Pending
+ [28:28]
+ read-write
+
+
+ pwmcmp1ip
+ PWM1 Interrupt Pending
+ [29:29]
+ read-write
+
+
+ pwmcmp2ip
+ PWM2 Interrupt Pending
+ [30:30]
+ read-write
+
+
+ pwmcmp3ip
+ PWM3 Interrupt Pending
+ [31:31]
+ read-write
+
+
+
+
+ pwmcount
+ PWM count register
+ 0x8
+
+
+ pwmcount
+ PWM count register.
+ [30:0]
+ read-write
+
+
+
+
+ pwms
+ Scaled PWM count register
+ 0x10
+
+
+ pwms
+ Scaled PWM count register.
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp0
+ PWM 0 compare register
+ 0x20
+
+
+ pwmcmp0
+ PWM 0 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp1
+ PWM 1 compare register
+ 0x24
+
+
+ pwmcmp1
+ PWM 1 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp2
+ PWM 2 compare register
+ 0x28
+
+
+ pwmcmp2
+ PWM 2 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp3
+ PWM 3 compare register
+ 0x2C
+
+
+ pwmcmp3
+ PWM 3 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+
+
+ sifive_i2c0_0
+ From sifive,i2c0,control peripheral generator
+ 0x10016000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ prescale_low
+ Clock Prescale register lo-byte
+ 0x0
+
+
+ prescale_high
+ Clock Prescale register hi-byte
+ 0x4
+
+
+ control
+ Control register
+ 0x8
+
+
+ en
+ I2C core enable bit
+ [6:6]
+ read-write
+
+
+ ien
+ I2C core interrupt enable bit
+ [7:7]
+ read-write
+
+
+
+
+ transmit__receive
+ Transmit and receive data byte register
+ 0xC
+
+
+ command__status
+ Command write and status read register
+ 0x10
+
+
+ wr_iack__rd_if
+ Clear interrupt and Interrupt pending
+ [0:0]
+ read-write
+
+
+ wr_res__rd_tip
+ Reserved and Transfer in progress
+ [1:1]
+ read-write
+
+
+ wr_res__rd_res
+ Reserved and Reserved
+ [2:2]
+ read-write
+
+
+ wr_ack__rd_res
+ Send ACK/NACK and Reserved
+ [3:3]
+ read-write
+
+
+ wr_txd__rd_res
+ Transmit data and Reserved
+ [4:4]
+ read-write
+
+
+ wr_rxd__rd_al
+ Receive data and Arbitration lost
+ [5:5]
+ read-write
+
+
+ wr_sto__rd_busy
+ Generate stop and I2C bus busy
+ [6:6]
+ read-write
+
+
+ wr_sta__rd_rxack
+ Generate start and Got ACK/NACK
+ [7:7]
+ read-write
+
+
+
+
+
+
+ sifive_uart0_1
+ From sifive,uart0,control peripheral generator
+ 0x10023000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ txdata
+ Transmit data register
+ 0x0
+
+
+ data
+ Transmit data
+ [7:0]
+ read-write
+
+
+ full
+ Transmit FIFO full
+ [31:31]
+ read-only
+
+
+
+
+ rxdata
+ Receive data register
+ 0x4
+
+
+ data
+ Received data
+ [7:0]
+ read-only
+
+
+ empty
+ Receive FIFO empty
+ [31:31]
+ read-only
+
+
+
+
+ txctrl
+ Transmit control register
+ 0x8
+
+
+ txen
+ Transmit enable
+ [0:0]
+ read-write
+
+
+ nstop
+ Number of stop bits
+ [1:1]
+ read-write
+
+
+ txcnt
+ Transmit watermark level
+ [18:16]
+ read-write
+
+
+
+
+ rxctrl
+ Receive control register
+ 0xC
+
+
+ rxen
+ Receive enable
+ [0:0]
+ read-write
+
+
+ rxcnt
+ Receive watermark level
+ [18:16]
+ read-write
+
+
+
+
+ ie
+ UART interrupt enable
+ 0x10
+
+
+ txwm
+ Transmit watermark interrupt enable
+ [0:0]
+ read-write
+
+
+ rxwm
+ Receive watermark interrupt enable
+ [1:1]
+ read-write
+
+
+
+
+ ip
+ UART interrupt pending
+ 0x14
+
+
+ txwm
+ Transmit watermark interrupt pending
+ [0:0]
+ read-only
+
+
+ rxwm
+ Receive watermark interrupt pending
+ [1:1]
+ read-only
+
+
+
+
+ div
+ Baud rate divisor
+ 0x18
+
+
+ div
+ Baud rate divisor.
+ [15:0]
+ read-write
+
+
+
+
+
+
+ sifive_spi0_1
+ From sifive,spi0,control peripheral generator
+ 0x10024000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ sckdiv
+ Serial clock divisor
+ 0x0
+
+
+ div
+ Divisor for serial clock.
+ [11:0]
+ read-write
+
+
+
+
+ sckmode
+ Serial clock mode
+ 0x4
+
+
+ pha
+ Serial clock phase
+ [0:0]
+ read-write
+
+
+ pol
+ Serial clock polarity
+ [1:1]
+ read-write
+
+
+
+
+ csid
+ Chip select ID
+ 0x10
+
+
+ csid
+ Chip select ID.
+ [31:0]
+ read-write
+
+
+
+
+ csdef
+ Chip select default
+ 0x14
+
+
+ csdef
+ Chip select default value. Reset to all-1s.
+ [31:0]
+ read-write
+
+
+
+
+ csmode
+ Chip select mode
+ 0x18
+
+
+ mode
+ Chip select mode
+ [1:0]
+ read-write
+
+
+
+
+ delay0
+ Delay control 0
+ 0x28
+
+
+ cssck
+ CS to SCK Delay
+ [7:0]
+ read-write
+
+
+ sckcs
+ SCK to CS Delay
+ [23:16]
+ read-write
+
+
+
+
+ delay1
+ Delay control 1
+ 0x2C
+
+
+ intercs
+ Minimum CS inactive time
+ [7:0]
+ read-write
+
+
+ interxfr
+ Maximum interframe delay
+ [23:16]
+ read-write
+
+
+
+
+ extradel
+ SPI extra sampling delay to increase the SPI frequency
+ 0x38
+
+
+ coarse
+ Coarse grain sample delay (multiples of system clocks)
+ [11:0]
+ read-write
+
+
+ fine
+ Fine grain sample delay (multiples of process-specific buffer delay)
+ [16:12]
+ read-write
+
+
+
+
+ sampledel
+ Number of delay stages from slave to the SPI controller
+ 0x3C
+
+
+ sd
+ Number of delay stages from slave to SPI controller
+ [4:0]
+ read-write
+
+
+
+
+ fmt
+ Frame format
+ 0x40
+
+
+ proto
+ SPI protocol
+ [1:0]
+ read-write
+
+
+ endian
+ SPI endianness
+ [2:2]
+ read-write
+
+
+ dir
+ SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise.
+ [3:3]
+ read-write
+
+
+ len
+ Number of bits per frame
+ [19:16]
+ read-write
+
+
+
+
+ txdata
+ Tx FIFO Data
+ 0x48
+
+
+ data
+ Transmit data
+ [7:0]
+ read-write
+
+
+ full
+ FIFO full flag
+ [31:31]
+ read-only
+
+
+
+
+ rxdata
+ Rx FIFO data
+ 0x4C
+
+
+ data
+ Received data
+ [7:0]
+ read-only
+
+
+ empty
+ FIFO empty flag
+ [31:31]
+ read-write
+
+
+
+
+ txmark
+ Tx FIFO watermark
+ 0x50
+
+
+ txmark
+ Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise.
+ [2:0]
+ read-write
+
+
+
+
+ rxmark
+ Rx FIFO watermark
+ 0x54
+
+
+ rxmark
+ Receive watermark
+ [2:0]
+ read-write
+
+
+
+
+ fctrl
+ SPI flash interface control
+ 0x60
+
+
+ en
+ SPI Flash Mode Select
+ [0:0]
+ read-write
+
+
+
+
+ ffmt
+ SPI flash instruction format
+ 0x64
+
+
+ cmd_en
+ Enable sending of command
+ [0:0]
+ read-write
+
+
+ addr_len
+ Number of address bytes (0 to 4)
+ [3:1]
+ read-write
+
+
+ pad_cnt
+ Number of dummy cycles
+ [7:4]
+ read-write
+
+
+ cmd_proto
+ Protocol for transmitting command
+ [9:8]
+ read-write
+
+
+ addr_proto
+ Protocol for transmitting address and padding
+ [11:10]
+ read-write
+
+
+ data_proto
+ Protocol for receiving data bytes
+ [13:12]
+ read-write
+
+
+ cmd_code
+ Value of command byte
+ [23:16]
+ read-write
+
+
+ pad_code
+ First 8 bits to transmit during dummy cycles
+ [31:24]
+ read-write
+
+
+
+
+ ie
+ SPI interrupt enable
+ 0x70
+
+
+ txwm
+ Transmit watermark enable
+ [0:0]
+ read-write
+
+
+ rxwm
+ Receive watermark enable
+ [1:1]
+ read-write
+
+
+
+
+ ip
+ SPI interrupt pending
+ 0x74
+
+
+ txwm
+ Transmit watermark pending
+ [0:0]
+ read-only
+
+
+ rxwm
+ Receive watermark pending
+ [1:1]
+ read-only
+
+
+
+
+
+
+ sifive_pwm0_1
+ From sifive,pwm0,control peripheral generator
+ 0x10025000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ pwmcfg
+ PWM configuration register
+ 0x0
+
+
+ pwmscale
+ PWM Counter scale
+ [3:0]
+ read-write
+
+
+ pwmsticky
+ PWM Sticky - disallow clearing pwmcmpXip bits
+ [8:8]
+ read-write
+
+
+ pwmzerocmp
+ PWM Zero - counter resets to zero after match
+ [9:9]
+ read-write
+
+
+ pwmdeglitch
+ PWM Deglitch - latch pwmcmpXip within same cycle
+ [10:10]
+ read-write
+
+
+ pwmenalways
+ PWM enable always - run continuously
+ [12:12]
+ read-write
+
+
+ pwmenoneshot
+ PWM enable one shot - run one cycle
+ [13:13]
+ read-write
+
+
+ pwmcmp0center
+ PWM0 Compare Center
+ [16:16]
+ read-write
+
+
+ pwmcmp1center
+ PWM1 Compare Center
+ [17:17]
+ read-write
+
+
+ pwmcmp2center
+ PWM2 Compare Center
+ [18:18]
+ read-write
+
+
+ pwmcmp3center
+ PWM3 Compare Center
+ [19:19]
+ read-write
+
+
+ pwmcmp0invert
+ PWM0 Invert
+ [20:20]
+ read-write
+
+
+ pwmcmp1invert
+ PWM1 Invert
+ [21:21]
+ read-write
+
+
+ pwmcmp2invert
+ PWM2 Invert
+ [22:22]
+ read-write
+
+
+ pwmcmp3invert
+ PWM3 Invert
+ [23:23]
+ read-write
+
+
+ pwmcmp0gang
+ PWM0/PWM1 Compare Gang
+ [24:24]
+ read-write
+
+
+ pwmcmp1gang
+ PWM1/PWM2 Compare Gang
+ [25:25]
+ read-write
+
+
+ pwmcmp2gang
+ PWM2/PWM3 Compare Gang
+ [26:26]
+ read-write
+
+
+ pwmcmp3gang
+ PWM3/PWM0 Compare Gang
+ [27:27]
+ read-write
+
+
+ pwmcmp0ip
+ PWM0 Interrupt Pending
+ [28:28]
+ read-write
+
+
+ pwmcmp1ip
+ PWM1 Interrupt Pending
+ [29:29]
+ read-write
+
+
+ pwmcmp2ip
+ PWM2 Interrupt Pending
+ [30:30]
+ read-write
+
+
+ pwmcmp3ip
+ PWM3 Interrupt Pending
+ [31:31]
+ read-write
+
+
+
+
+ pwmcount
+ PWM count register
+ 0x8
+
+
+ pwmcount
+ PWM count register.
+ [30:0]
+ read-write
+
+
+
+
+ pwms
+ Scaled PWM count register
+ 0x10
+
+
+ pwms
+ Scaled PWM count register.
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp0
+ PWM 0 compare register
+ 0x20
+
+
+ pwmcmp0
+ PWM 0 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp1
+ PWM 1 compare register
+ 0x24
+
+
+ pwmcmp1
+ PWM 1 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp2
+ PWM 2 compare register
+ 0x28
+
+
+ pwmcmp2
+ PWM 2 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp3
+ PWM 3 compare register
+ 0x2C
+
+
+ pwmcmp3
+ PWM 3 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+
+
+ sifive_spi0_2
+ From sifive,spi0,control peripheral generator
+ 0x10034000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ sckdiv
+ Serial clock divisor
+ 0x0
+
+
+ div
+ Divisor for serial clock.
+ [11:0]
+ read-write
+
+
+
+
+ sckmode
+ Serial clock mode
+ 0x4
+
+
+ pha
+ Serial clock phase
+ [0:0]
+ read-write
+
+
+ pol
+ Serial clock polarity
+ [1:1]
+ read-write
+
+
+
+
+ csid
+ Chip select ID
+ 0x10
+
+
+ csid
+ Chip select ID.
+ [31:0]
+ read-write
+
+
+
+
+ csdef
+ Chip select default
+ 0x14
+
+
+ csdef
+ Chip select default value. Reset to all-1s.
+ [31:0]
+ read-write
+
+
+
+
+ csmode
+ Chip select mode
+ 0x18
+
+
+ mode
+ Chip select mode
+ [1:0]
+ read-write
+
+
+
+
+ delay0
+ Delay control 0
+ 0x28
+
+
+ cssck
+ CS to SCK Delay
+ [7:0]
+ read-write
+
+
+ sckcs
+ SCK to CS Delay
+ [23:16]
+ read-write
+
+
+
+
+ delay1
+ Delay control 1
+ 0x2C
+
+
+ intercs
+ Minimum CS inactive time
+ [7:0]
+ read-write
+
+
+ interxfr
+ Maximum interframe delay
+ [23:16]
+ read-write
+
+
+
+
+ extradel
+ SPI extra sampling delay to increase the SPI frequency
+ 0x38
+
+
+ coarse
+ Coarse grain sample delay (multiples of system clocks)
+ [11:0]
+ read-write
+
+
+ fine
+ Fine grain sample delay (multiples of process-specific buffer delay)
+ [16:12]
+ read-write
+
+
+
+
+ sampledel
+ Number of delay stages from slave to the SPI controller
+ 0x3C
+
+
+ sd
+ Number of delay stages from slave to SPI controller
+ [4:0]
+ read-write
+
+
+
+
+ fmt
+ Frame format
+ 0x40
+
+
+ proto
+ SPI protocol
+ [1:0]
+ read-write
+
+
+ endian
+ SPI endianness
+ [2:2]
+ read-write
+
+
+ dir
+ SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise.
+ [3:3]
+ read-write
+
+
+ len
+ Number of bits per frame
+ [19:16]
+ read-write
+
+
+
+
+ txdata
+ Tx FIFO Data
+ 0x48
+
+
+ data
+ Transmit data
+ [7:0]
+ read-write
+
+
+ full
+ FIFO full flag
+ [31:31]
+ read-only
+
+
+
+
+ rxdata
+ Rx FIFO data
+ 0x4C
+
+
+ data
+ Received data
+ [7:0]
+ read-only
+
+
+ empty
+ FIFO empty flag
+ [31:31]
+ read-write
+
+
+
+
+ txmark
+ Tx FIFO watermark
+ 0x50
+
+
+ txmark
+ Transmit watermark. The reset value is 1 for flash-enabled controllers, 0 otherwise.
+ [2:0]
+ read-write
+
+
+
+
+ rxmark
+ Rx FIFO watermark
+ 0x54
+
+
+ rxmark
+ Receive watermark
+ [2:0]
+ read-write
+
+
+
+
+ fctrl
+ SPI flash interface control
+ 0x60
+
+
+ en
+ SPI Flash Mode Select
+ [0:0]
+ read-write
+
+
+
+
+ ffmt
+ SPI flash instruction format
+ 0x64
+
+
+ cmd_en
+ Enable sending of command
+ [0:0]
+ read-write
+
+
+ addr_len
+ Number of address bytes (0 to 4)
+ [3:1]
+ read-write
+
+
+ pad_cnt
+ Number of dummy cycles
+ [7:4]
+ read-write
+
+
+ cmd_proto
+ Protocol for transmitting command
+ [9:8]
+ read-write
+
+
+ addr_proto
+ Protocol for transmitting address and padding
+ [11:10]
+ read-write
+
+
+ data_proto
+ Protocol for receiving data bytes
+ [13:12]
+ read-write
+
+
+ cmd_code
+ Value of command byte
+ [23:16]
+ read-write
+
+
+ pad_code
+ First 8 bits to transmit during dummy cycles
+ [31:24]
+ read-write
+
+
+
+
+ ie
+ SPI interrupt enable
+ 0x70
+
+
+ txwm
+ Transmit watermark enable
+ [0:0]
+ read-write
+
+
+ rxwm
+ Receive watermark enable
+ [1:1]
+ read-write
+
+
+
+
+ ip
+ SPI interrupt pending
+ 0x74
+
+
+ txwm
+ Transmit watermark pending
+ [0:0]
+ read-only
+
+
+ rxwm
+ Receive watermark pending
+ [1:1]
+ read-only
+
+
+
+
+
+
+ sifive_pwm0_2
+ From sifive,pwm0,control peripheral generator
+ 0x10035000
+
+ 0
+ 0x1000
+ registers
+
+
+
+ pwmcfg
+ PWM configuration register
+ 0x0
+
+
+ pwmscale
+ PWM Counter scale
+ [3:0]
+ read-write
+
+
+ pwmsticky
+ PWM Sticky - disallow clearing pwmcmpXip bits
+ [8:8]
+ read-write
+
+
+ pwmzerocmp
+ PWM Zero - counter resets to zero after match
+ [9:9]
+ read-write
+
+
+ pwmdeglitch
+ PWM Deglitch - latch pwmcmpXip within same cycle
+ [10:10]
+ read-write
+
+
+ pwmenalways
+ PWM enable always - run continuously
+ [12:12]
+ read-write
+
+
+ pwmenoneshot
+ PWM enable one shot - run one cycle
+ [13:13]
+ read-write
+
+
+ pwmcmp0center
+ PWM0 Compare Center
+ [16:16]
+ read-write
+
+
+ pwmcmp1center
+ PWM1 Compare Center
+ [17:17]
+ read-write
+
+
+ pwmcmp2center
+ PWM2 Compare Center
+ [18:18]
+ read-write
+
+
+ pwmcmp3center
+ PWM3 Compare Center
+ [19:19]
+ read-write
+
+
+ pwmcmp0invert
+ PWM0 Invert
+ [20:20]
+ read-write
+
+
+ pwmcmp1invert
+ PWM1 Invert
+ [21:21]
+ read-write
+
+
+ pwmcmp2invert
+ PWM2 Invert
+ [22:22]
+ read-write
+
+
+ pwmcmp3invert
+ PWM3 Invert
+ [23:23]
+ read-write
+
+
+ pwmcmp0gang
+ PWM0/PWM1 Compare Gang
+ [24:24]
+ read-write
+
+
+ pwmcmp1gang
+ PWM1/PWM2 Compare Gang
+ [25:25]
+ read-write
+
+
+ pwmcmp2gang
+ PWM2/PWM3 Compare Gang
+ [26:26]
+ read-write
+
+
+ pwmcmp3gang
+ PWM3/PWM0 Compare Gang
+ [27:27]
+ read-write
+
+
+ pwmcmp0ip
+ PWM0 Interrupt Pending
+ [28:28]
+ read-write
+
+
+ pwmcmp1ip
+ PWM1 Interrupt Pending
+ [29:29]
+ read-write
+
+
+ pwmcmp2ip
+ PWM2 Interrupt Pending
+ [30:30]
+ read-write
+
+
+ pwmcmp3ip
+ PWM3 Interrupt Pending
+ [31:31]
+ read-write
+
+
+
+
+ pwmcount
+ PWM count register
+ 0x8
+
+
+ pwmcount
+ PWM count register.
+ [30:0]
+ read-write
+
+
+
+
+ pwms
+ Scaled PWM count register
+ 0x10
+
+
+ pwms
+ Scaled PWM count register.
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp0
+ PWM 0 compare register
+ 0x20
+
+
+ pwmcmp0
+ PWM 0 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp1
+ PWM 1 compare register
+ 0x24
+
+
+ pwmcmp1
+ PWM 1 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp2
+ PWM 2 compare register
+ 0x28
+
+
+ pwmcmp2
+ PWM 2 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+ pwmcmp3
+ PWM 3 compare register
+ 0x2C
+
+
+ pwmcmp3
+ PWM 3 Compare Value
+ [15:0]
+ read-write
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/atomic.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/atomic.h
new file mode 100644
index 000000000..32a33abd7
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/atomic.h
@@ -0,0 +1,259 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef METAL__ATOMIC_H
+#define METAL__ATOMIC_H
+
+#include
+
+#include
+
+typedef volatile int32_t metal_atomic_t;
+
+#define METAL_ATOMIC_DECLARE(name) \
+ __attribute((section(".data.atomics"))) metal_atomic_t name
+
+#define _METAL_STORE_AMO_ACCESS_FAULT 7
+
+/* This macro stores the memory address in mtval like a normal store/amo access
+ * fault, triggers a trap, and then if execution returns, returns 0 as an
+ * arbitrary choice */
+#define _METAL_TRAP_AMO_ACCESS(addr) \
+ __asm__("csrw mtval, %[atomic]" ::[atomic] "r"(a)); \
+ _metal_trap(_METAL_STORE_AMO_ACCESS_FAULT); \
+ return 0;
+
+/*!
+ * @brief Check if the platform supports atomic operations
+ *
+ * @return 1 if atomic operations are supported, 0 if not
+ */
+__inline__ int32_t metal_atomic_available(void) {
+#ifdef __riscv_atomic
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+/*!
+ * @brief Atomically increment a metal_atomic_t and return its old value
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to increment
+ * @param increment the amount to increment the value
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_add(metal_atomic_t *a, int32_t increment) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amoadd.w %[old], %[increment], (%[atomic])"
+ : [old] "=r"(old)
+ : [increment] "r"(increment), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically bitwise-AND a metal_atomic_t and return its old value
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to bitwise-AND
+ * @param mask the bitmask to AND
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_and(metal_atomic_t *a, int32_t mask) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amoand.w %[old], %[mask], (%[atomic])"
+ : [old] "=r"(old)
+ : [mask] "r"(mask), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically bitwise-OR a metal_atomic_t and return its old value
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to bitwise-OR
+ * @param mask the bitmask to OR
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_or(metal_atomic_t *a, int32_t mask) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amoor.w %[old], %[mask], (%[atomic])"
+ : [old] "=r"(old)
+ : [mask] "r"(mask), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically swap a metal_atomic_t and return its old value
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to swap
+ * @param new_value the value to store in the metal_atomic_t
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_swap(metal_atomic_t *a, int32_t new_value) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amoswap.w %[old], %[newval], (%[atomic])"
+ : [old] "=r"(old)
+ : [newval] "r"(new_value), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically bitwise-XOR a metal_atomic_t and return its old value
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to bitwise-XOR
+ * @param mask the bitmask to XOR
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_xor(metal_atomic_t *a, int32_t mask) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amoxor.w %[old], %[mask], (%[atomic])"
+ : [old] "=r"(old)
+ : [mask] "r"(mask), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically set the value of a memory location to the greater of
+ * its current value or a value to compare it with.
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to swap
+ * @param compare the value to compare with the value in memory
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_max(metal_atomic_t *a, int32_t compare) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amomax.w %[old], %[compare], (%[atomic])"
+ : [old] "=r"(old)
+ : [compare] "r"(compare), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically set the value of a memory location to the (unsigned)
+ * greater of its current value or a value to compare it with.
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to swap
+ * @param compare the value to compare with the value in memory
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ uint32_t metal_atomic_max_u(metal_atomic_t *a, uint32_t compare) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amomaxu.w %[old], %[compare], (%[atomic])"
+ : [old] "=r"(old)
+ : [compare] "r"(compare), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically set the value of a memory location to the lesser of
+ * its current value or a value to compare it with.
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to swap
+ * @param compare the value to compare with the value in memory
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ int32_t metal_atomic_min(metal_atomic_t *a, int32_t compare) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amomin.w %[old], %[compare], (%[atomic])"
+ : [old] "=r"(old)
+ : [compare] "r"(compare), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+/*!
+ * @brief Atomically set the value of a memory location to the (unsigned) lesser
+ * of its current value or a value to compare it with.
+ *
+ * If atomics are not supported on the platform, this function will trap with
+ * a Store/AMO access fault.
+ *
+ * @param a The pointer to the value to swap
+ * @param compare the value to compare with the value in memory
+ *
+ * @return The previous value of the metal_atomic_t
+ */
+__inline__ uint32_t metal_atomic_min_u(metal_atomic_t *a, uint32_t compare) {
+#ifdef __riscv_atomic
+ int32_t old;
+ __asm__ volatile("amominu.w %[old], %[compare], (%[atomic])"
+ : [old] "=r"(old)
+ : [compare] "r"(compare), [atomic] "r"(a)
+ : "memory");
+ return old;
+#else
+ _METAL_TRAP_AMO_ACCESS(a);
+#endif
+}
+
+#endif /* METAL__ATOMIC_H */
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/button.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/button.h
index 0c26f435a..bef645967 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/button.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/button.h
@@ -15,7 +15,8 @@ struct metal_button;
struct metal_button_vtable {
int (*button_exist)(struct metal_button *button, char *label);
- struct metal_interrupt* (*interrupt_controller)(struct metal_button *button);
+ struct metal_interrupt *(*interrupt_controller)(
+ struct metal_button *button);
int (*get_interrupt_id)(struct metal_button *button);
};
@@ -35,8 +36,7 @@ struct metal_button {
* @param label The DeviceTree label for the button
* @return A handle for the button
*/
-struct metal_button* metal_button_get(char *label);
-
+struct metal_button *metal_button_get(char *label);
/*!
* @brief Get the interrupt controller for a button
@@ -45,8 +45,10 @@ struct metal_button* metal_button_get(char *label);
* @return A pointer to the interrupt controller responsible for handling
* button interrupts.
*/
-inline struct metal_interrupt*
- metal_button_interrupt_controller(struct metal_button *button) { return button->vtable->interrupt_controller(button); }
+__inline__ struct metal_interrupt *
+metal_button_interrupt_controller(struct metal_button *button) {
+ return button->vtable->interrupt_controller(button);
+}
/*!
* @brief Get the interrupt id for a button
@@ -54,6 +56,8 @@ inline struct metal_interrupt*
* @param button The handle for the button
* @return The interrupt id corresponding to a button.
*/
-inline int metal_button_get_interrupt_id(struct metal_button *button) { return button->vtable->get_interrupt_id(button); }
+__inline__ int metal_button_get_interrupt_id(struct metal_button *button) {
+ return button->vtable->get_interrupt_id(button);
+}
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cache.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cache.h
index a8a60ada6..673a8b13e 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cache.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cache.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 SiFive, Inc */
+/* Copyright 2020 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#ifndef METAL__CACHE_H
@@ -9,40 +9,58 @@
*
* @brief API for configuring caches
*/
-
-struct metal_cache;
-
-struct __metal_cache_vtable {
- void (*init)(struct metal_cache *cache, int ways);
- int (*get_enabled_ways)(struct metal_cache *cache);
- int (*set_enabled_ways)(struct metal_cache *cache, int ways);
-};
+#include
/*!
* @brief a handle for a cache
+ * Note: To be deprecated in next release.
*/
struct metal_cache {
- const struct __metal_cache_vtable *vtable;
+ uint8_t __no_empty_structs;
};
+/*!
+ * @brief Initialize L2 cache controller.
+ * Enables all available cache ways.
+ * @param None
+ * @return 0 If no error
+ */
+int metal_l2cache_init(void);
+
+/*!
+ * @brief Get the current number of enabled L2 cache ways
+ * @param None
+ * @return The current number of enabled L2 cache ways
+ */
+int metal_l2cache_get_enabled_ways(void);
+
+/*!
+ * @brief Enable the requested number of L2 cache ways
+ * @param ways Number of ways to enable
+ * @return 0 if the ways are successfully enabled
+ */
+int metal_l2cache_set_enabled_ways(int ways);
+
/*!
* @brief Initialize a cache
* @param cache The handle for the cache to initialize
* @param ways The number of ways to enable
*
* Initializes a cache with the requested number of ways enabled.
+ * Note: API to be deprecated in next release.
*/
-inline void metal_cache_init(struct metal_cache *cache, int ways) {
- return cache->vtable->init(cache, ways);
+__inline__ void metal_cache_init(struct metal_cache *cache, int ways) {
+ metal_l2cache_init();
}
/*!
* @brief Get the current number of enabled cache ways
* @param cache The handle for the cache
* @return The current number of enabled cache ways
+ * Note: API to be deprecated in next release.
*/
-inline int metal_cache_get_enabled_ways(struct metal_cache *cache) {
- return cache->vtable->get_enabled_ways(cache);
+__inline__ int metal_cache_get_enabled_ways(struct metal_cache *cache) {
+ return metal_l2cache_get_enabled_ways();
}
/*!
@@ -50,9 +68,41 @@ inline int metal_cache_get_enabled_ways(struct metal_cache *cache) {
* @param cache The handle for the cache
* @param ways The number of ways to enabled
* @return 0 if the ways are successfully enabled
+ * Note: API to be deprecated in next release.
*/
-inline int metal_cache_set_enabled_ways(struct metal_cache *cache, int ways) {
- return cache->vtable->set_enabled_ways(cache, ways);
+__inline__ int metal_cache_set_enabled_ways(struct metal_cache *cache,
+ int ways) {
+ return metal_l2cache_set_enabled_ways(ways);
}
+/*!
+ * @brief Check if dcache is supported on the core
+ * @param hartid The core to check
+ * @return 1 if dcache is present
+ */
+int metal_dcache_l1_available(int hartid);
+
+/*!
+ * @brief Flush dcache for L1 on the requested core with write back
+ * @param hartid The core to flush
+ * @param address The virtual address of cacheline to invalidate
+ * @return None
+ */
+void metal_dcache_l1_flush(int hartid, uintptr_t address);
+
+/*!
+ * @brief Discard dcache for L1 on the requested core with no write back
+ * @param hartid The core to discard
+ * @param address The virtual address of cacheline to invalidate
+ * @return None
+ */
+void metal_dcache_l1_discard(int hartid, uintptr_t address);
+
+/*!
+ * @brief Check if icache is supported on the core
+ * @param hartid The core to check
+ * @return 1 if icache is present
+ */
+int metal_icache_l1_available(int hartid);
+
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/clock.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/clock.h
index 277841e01..cfe29f6b7 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/clock.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/clock.h
@@ -4,11 +4,12 @@
#ifndef METAL__CLOCK_H
#define METAL__CLOCK_H
-/*!
+/*!
* @file clock.h
* @brief API for manipulating clock sources
*
- * The clock interface allows for controlling the rate of various clocks in the system.
+ * The clock interface allows for controlling the rate of various clocks in the
+ * system.
*/
struct metal_clock;
@@ -22,37 +23,82 @@ struct __metal_clock_vtable {
};
/*!
- * @brief Function signature of clock pre-rate change callbacks
+ * @brief Function signature of clock rate change callbacks
+ */
+typedef void (*metal_clock_rate_change_callback)(void *priv);
+
+struct _metal_clock_callback_t;
+struct _metal_clock_callback_t {
+ /* The callback function */
+ metal_clock_rate_change_callback callback;
+
+ /* Private data for the callback function */
+ void *priv;
+
+ struct _metal_clock_callback_t *_next;
+};
+
+/*!
+ * @brief Type for the linked list of callbacks for clock rate changes
*/
-typedef void (*metal_clock_pre_rate_change_callback)(void *priv);
+typedef struct _metal_clock_callback_t metal_clock_callback;
/*!
- * @brief Function signature of clock post-rate change callbacks
+ * @brief Call all callbacks in the linked list, if any are registered
*/
-typedef void (*metal_clock_post_rate_change_callback)(void *priv);
+__inline__ void
+_metal_clock_call_all_callbacks(const metal_clock_callback *const list) {
+ const metal_clock_callback *current = list;
+ while (current) {
+ current->callback(current->priv);
+ current = current->_next;
+ }
+}
+
+/*!
+ * @brief Append a callback to the linked list and return the head of the list
+ */
+__inline__ metal_clock_callback *
+_metal_clock_append_to_callbacks(metal_clock_callback *list,
+ metal_clock_callback *const cb) {
+ cb->_next = NULL;
+
+ if (!list) {
+ return cb;
+ }
+
+ metal_clock_callback *current = list;
+
+ while ((current->_next) != NULL) {
+ current = current->_next;
+ }
+
+ current->_next = cb;
+
+ return list;
+}
/*!
* @struct metal_clock
* @brief The handle for a clock
*
- * Clocks are defined as a pointer to a `struct metal_clock`, the contents of which
- * are implementation defined. Users of the clock interface must call functions
- * which accept a `struct metal_clock *` as an argument to interract with the clock.
+ * Clocks are defined as a pointer to a `struct metal_clock`, the contents of
+ * which are implementation defined. Users of the clock interface must call
+ * functions which accept a `struct metal_clock *` as an argument to interract
+ * with the clock.
*
- * Note that no mechanism for obtaining a pointer to a `struct metal_clock` has been
- * defined, making it impossible to call any of these functions without invoking
- * implementation-defined behavior.
+ * Note that no mechanism for obtaining a pointer to a `struct metal_clock` has
+ * been defined, making it impossible to call any of these functions without
+ * invoking implementation-defined behavior.
*/
struct metal_clock {
const struct __metal_clock_vtable *vtable;
- /* Pre-rate change callback */
- metal_clock_pre_rate_change_callback _pre_rate_change_callback;
- void *_pre_rate_change_callback_priv;
+ /* Pre-rate change callback linked list */
+ metal_clock_callback *_pre_rate_change_callback;
- /* Post-rate change callback */
- metal_clock_post_rate_change_callback _post_rate_change_callback;
- void *_post_rate_change_callback_priv;
+ /* Post-rate change callback linked list */
+ metal_clock_callback *_post_rate_change_callback;
};
/*!
@@ -61,7 +107,9 @@ struct metal_clock {
* @param clk The handle for the clock
* @return The current rate of the clock in Hz
*/
-inline long metal_clock_get_rate_hz(const struct metal_clock *clk) { return clk->vtable->get_rate_hz(clk); }
+__inline__ long metal_clock_get_rate_hz(const struct metal_clock *clk) {
+ return clk->vtable->get_rate_hz(clk);
+}
/*!
* @brief Set the current rate of a clock
@@ -74,18 +122,15 @@ inline long metal_clock_get_rate_hz(const struct metal_clock *clk) { return clk-
* to the given rate in Hz. Returns the actual value that's been selected, which
* could be anything!
*
- * Prior to and after the rate change of the clock, this will call the registered
- * pre- and post-rate change callbacks.
+ * Prior to and after the rate change of the clock, this will call the
+ * registered pre- and post-rate change callbacks.
*/
-inline long metal_clock_set_rate_hz(struct metal_clock *clk, long hz)
-{
- if(clk->_pre_rate_change_callback != NULL)
- clk->_pre_rate_change_callback(clk->_pre_rate_change_callback_priv);
+__inline__ long metal_clock_set_rate_hz(struct metal_clock *clk, long hz) {
+ _metal_clock_call_all_callbacks(clk->_pre_rate_change_callback);
long out = clk->vtable->set_rate_hz(clk, hz);
- if (clk->_post_rate_change_callback != NULL)
- clk->_post_rate_change_callback(clk->_post_rate_change_callback_priv);
+ _metal_clock_call_all_callbacks(clk->_post_rate_change_callback);
return out;
}
@@ -95,12 +140,12 @@ inline long metal_clock_set_rate_hz(struct metal_clock *clk, long hz)
*
* @param clk The handle for the clock
* @param cb The callback to be registered
- * @param priv Private data for the callback handler
*/
-inline void metal_clock_register_pre_rate_change_callback(struct metal_clock *clk, metal_clock_pre_rate_change_callback cb, void *priv)
-{
- clk->_pre_rate_change_callback = cb;
- clk->_pre_rate_change_callback_priv = priv;
+__inline__ void
+metal_clock_register_pre_rate_change_callback(struct metal_clock *clk,
+ metal_clock_callback *cb) {
+ clk->_pre_rate_change_callback =
+ _metal_clock_append_to_callbacks(clk->_pre_rate_change_callback, cb);
}
/*!
@@ -108,12 +153,12 @@ inline void metal_clock_register_pre_rate_change_callback(struct metal_clock *cl
*
* @param clk The handle for the clock
* @param cb The callback to be registered
- * @param priv Private data for the callback handler
*/
-inline void metal_clock_register_post_rate_change_callback(struct metal_clock *clk, metal_clock_post_rate_change_callback cb, void *priv)
-{
- clk->_post_rate_change_callback = cb;
- clk->_post_rate_change_callback_priv = priv;
+__inline__ void
+metal_clock_register_post_rate_change_callback(struct metal_clock *clk,
+ metal_clock_callback *cb) {
+ clk->_post_rate_change_callback =
+ _metal_clock_append_to_callbacks(clk->_post_rate_change_callback, cb);
}
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/compiler.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/compiler.h
index 62c0ea975..80ca5fee4 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/compiler.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/compiler.h
@@ -4,18 +4,19 @@
#ifndef METAL__COMPILER_H
#define METAL__COMPILER_H
-#define __METAL_DECLARE_VTABLE(type) \
- extern const struct type type;
+#define __METAL_DECLARE_VTABLE(type) extern const struct type type;
-#define __METAL_DEFINE_VTABLE(type) \
- const struct type type
+#define __METAL_DEFINE_VTABLE(type) const struct type type
-#define __METAL_GET_FIELD(reg, mask) \
+#define __METAL_GET_FIELD(reg, mask) \
(((reg) & (mask)) / ((mask) & ~((mask) << 1)))
/* Set field with mask for a given value */
-#define __METAL_SET_FIELD(reg, mask, val) \
- (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+#define __METAL_SET_FIELD(reg, mask, val) \
+ (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+#define __METAL_MIN(a, b) ((a) < (b) ? (a) : (b))
+#define __METAL_MAX(a, b) ((a) > (b) ? (a) : (b))
void _metal_trap(int ecode);
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cpu.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cpu.h
index 453bd12de..98d7e6680 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cpu.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/cpu.h
@@ -9,33 +9,35 @@
#ifndef METAL__CPU_H
#define METAL__CPU_H
-#include
#include
+#include
struct metal_cpu;
/*!
* @brief Function signature for exception handlers
*/
-typedef void (*metal_exception_handler_t) (struct metal_cpu *cpu, int ecode);
+typedef void (*metal_exception_handler_t)(struct metal_cpu *cpu, int ecode);
struct metal_cpu_vtable {
- unsigned long long (*timer_get)(struct metal_cpu *cpu);
+ unsigned long long (*mcycle_get)(struct metal_cpu *cpu);
unsigned long long (*timebase_get)(struct metal_cpu *cpu);
unsigned long long (*mtime_get)(struct metal_cpu *cpu);
int (*mtimecmp_set)(struct metal_cpu *cpu, unsigned long long time);
- struct metal_interrupt* (*tmr_controller_interrupt)(struct metal_cpu *cpu);
+ struct metal_interrupt *(*tmr_controller_interrupt)(struct metal_cpu *cpu);
int (*get_tmr_interrupt_id)(struct metal_cpu *cpu);
- struct metal_interrupt* (*sw_controller_interrupt)(struct metal_cpu *cpu);
+ struct metal_interrupt *(*sw_controller_interrupt)(struct metal_cpu *cpu);
int (*get_sw_interrupt_id)(struct metal_cpu *cpu);
int (*set_sw_ipi)(struct metal_cpu *cpu, int hartid);
int (*clear_sw_ipi)(struct metal_cpu *cpu, int hartid);
int (*get_msip)(struct metal_cpu *cpu, int hartid);
- struct metal_interrupt* (*controller_interrupt)(struct metal_cpu *cpu);
- int (*exception_register)(struct metal_cpu *cpu, int ecode, metal_exception_handler_t handler);
+ struct metal_interrupt *(*controller_interrupt)(struct metal_cpu *cpu);
+ int (*exception_register)(struct metal_cpu *cpu, int ecode,
+ metal_exception_handler_t handler);
int (*get_ilen)(struct metal_cpu *cpu, uintptr_t epc);
uintptr_t (*get_epc)(struct metal_cpu *cpu);
int (*set_epc)(struct metal_cpu *cpu, uintptr_t epc);
+ struct metal_buserror *(*get_buserror)(struct metal_cpu *cpu);
};
/*! @brief A device handle for a CPU hart
@@ -49,17 +51,17 @@ struct metal_cpu {
* @param hartid The ID of the desired CPU hart
* @return A pointer to the CPU device handle
*/
-struct metal_cpu* metal_cpu_get(int hartid);
+struct metal_cpu *metal_cpu_get(unsigned int hartid);
/*! @brief Get the hartid of the CPU hart executing this function
*
* @return The hartid of the current CPU hart */
-int metal_cpu_get_current_hartid();
+int metal_cpu_get_current_hartid(void);
/*! @brief Get the number of CPU harts
- *
+ *
* @return The number of CPU harts */
-int metal_cpu_get_num_harts();
+int metal_cpu_get_num_harts(void);
/*! @brief Get the CPU cycle count timer value
*
@@ -68,8 +70,9 @@ int metal_cpu_get_num_harts();
* @param cpu The CPU device handle
* @return The value of the CPU cycle count timer
*/
-inline unsigned long long metal_cpu_get_timer(struct metal_cpu *cpu)
-{ return cpu->vtable->timer_get(cpu); }
+__inline__ unsigned long long metal_cpu_get_timer(struct metal_cpu *cpu) {
+ return cpu->vtable->mcycle_get(cpu);
+}
/*! @brief Get the timebase of the CPU
*
@@ -78,8 +81,9 @@ inline unsigned long long metal_cpu_get_timer(struct metal_cpu *cpu)
* @param cpu The CPU device handle
* @return The value of the cycle count timer timebase
*/
-inline unsigned long long metal_cpu_get_timebase(struct metal_cpu *cpu)
-{ return cpu->vtable->timebase_get(cpu); }
+__inline__ unsigned long long metal_cpu_get_timebase(struct metal_cpu *cpu) {
+ return cpu->vtable->timebase_get(cpu);
+}
/*! @brief Get the value of the mtime RTC
*
@@ -90,8 +94,9 @@ inline unsigned long long metal_cpu_get_timebase(struct metal_cpu *cpu)
* @param cpu The CPU device handle
* @return The value of mtime, or 0 if failure
*/
-inline unsigned long long metal_cpu_get_mtime(struct metal_cpu *cpu)
-{ return cpu->vtable->mtime_get(cpu); }
+__inline__ unsigned long long metal_cpu_get_mtime(struct metal_cpu *cpu) {
+ return cpu->vtable->mtime_get(cpu);
+}
/*! @brief Set the value of the RTC mtimecmp RTC
*
@@ -103,20 +108,24 @@ inline unsigned long long metal_cpu_get_mtime(struct metal_cpu *cpu)
* @param time The value to set the compare register to
* @return The value of mtimecmp or -1 if error
*/
-inline int metal_cpu_set_mtimecmp(struct metal_cpu *cpu, unsigned long long time)
-{ return cpu->vtable->mtimecmp_set(cpu, time); }
+__inline__ int metal_cpu_set_mtimecmp(struct metal_cpu *cpu,
+ unsigned long long time) {
+ return cpu->vtable->mtimecmp_set(cpu, time);
+}
/*! @brief Get a reference to RTC timer interrupt controller
*
- * Get a reference to the interrupt controller for the real-time clock interrupt.
- * The controller returned by this function must be initialized before any interrupts
- * are registered or enabled with it.
+ * Get a reference to the interrupt controller for the real-time clock
+ * interrupt. The controller returned by this function must be initialized
+ * before any interrupts are registered or enabled with it.
*
* @param cpu The CPU device handle
* @return A pointer to the timer interrupt handle
*/
-inline struct metal_interrupt* metal_cpu_timer_interrupt_controller(struct metal_cpu *cpu)
-{ return cpu->vtable->tmr_controller_interrupt(cpu); }
+__inline__ struct metal_interrupt *
+metal_cpu_timer_interrupt_controller(struct metal_cpu *cpu) {
+ return cpu->vtable->tmr_controller_interrupt(cpu);
+}
/*! @brief Get the RTC timer interrupt id
*
@@ -125,20 +134,23 @@ inline struct metal_interrupt* metal_cpu_timer_interrupt_controller(struct metal
* @param cpu The CPU device handle
* @return The timer interrupt ID
*/
-inline int metal_cpu_timer_get_interrupt_id(struct metal_cpu *cpu)
-{ return cpu->vtable->get_tmr_interrupt_id(cpu); }
+__inline__ int metal_cpu_timer_get_interrupt_id(struct metal_cpu *cpu) {
+ return cpu->vtable->get_tmr_interrupt_id(cpu);
+}
/*! @brief Get a reference to the software interrupt controller
*
* Get a reference to the interrupt controller for the software/inter-process
- * interrupt. The controller returned by this function must be initialized before
- * any interrupts are registered or enabled with it.
+ * interrupt. The controller returned by this function must be initialized
+ * before any interrupts are registered or enabled with it.
*
* @param cpu The CPU device handle
* @return A pointer to the software interrupt handle
*/
-inline struct metal_interrupt* metal_cpu_software_interrupt_controller(struct metal_cpu *cpu)
-{ return cpu->vtable->sw_controller_interrupt(cpu); }
+__inline__ struct metal_interrupt *
+metal_cpu_software_interrupt_controller(struct metal_cpu *cpu) {
+ return cpu->vtable->sw_controller_interrupt(cpu);
+}
/*! @brief Get the software interrupt id
*
@@ -147,8 +159,9 @@ inline struct metal_interrupt* metal_cpu_software_interrupt_controller(struct me
* @param cpu The CPU device handle
* @return the software interrupt ID
*/
-inline int metal_cpu_software_get_interrupt_id(struct metal_cpu *cpu)
-{ return cpu->vtable->get_sw_interrupt_id(cpu); }
+__inline__ int metal_cpu_software_get_interrupt_id(struct metal_cpu *cpu) {
+ return cpu->vtable->get_sw_interrupt_id(cpu);
+}
/*!
* @brief Set the inter-process interrupt for a hart
@@ -161,8 +174,9 @@ inline int metal_cpu_software_get_interrupt_id(struct metal_cpu *cpu)
* @param hartid The CPU hart ID to be interrupted
* @return 0 upon success
*/
-inline int metal_cpu_software_set_ipi(struct metal_cpu *cpu, int hartid)
-{ return cpu->vtable->set_sw_ipi(cpu, hartid); }
+__inline__ int metal_cpu_software_set_ipi(struct metal_cpu *cpu, int hartid) {
+ return cpu->vtable->set_sw_ipi(cpu, hartid);
+}
/*!
* @brief Clear the inter-process interrupt for a hart
@@ -175,8 +189,9 @@ inline int metal_cpu_software_set_ipi(struct metal_cpu *cpu, int hartid)
* @param hartid The CPU hart ID to clear
* @return 0 upon success
*/
-inline int metal_cpu_software_clear_ipi(struct metal_cpu *cpu, int hartid)
-{ return cpu->vtable->clear_sw_ipi(cpu, hartid); }
+__inline__ int metal_cpu_software_clear_ipi(struct metal_cpu *cpu, int hartid) {
+ return cpu->vtable->clear_sw_ipi(cpu, hartid);
+}
/*!
* @brief Get the value of MSIP for the given hart
@@ -190,8 +205,9 @@ inline int metal_cpu_software_clear_ipi(struct metal_cpu *cpu, int hartid)
* @param hartid The CPU hart to read
* @return 0 upon success
*/
-inline int metal_cpu_get_msip(struct metal_cpu *cpu, int hartid)
-{ return cpu->vtable->get_msip(cpu, hartid); }
+__inline__ int metal_cpu_get_msip(struct metal_cpu *cpu, int hartid) {
+ return cpu->vtable->get_msip(cpu, hartid);
+}
/*!
* @brief Get the interrupt controller for the CPU
@@ -204,22 +220,26 @@ inline int metal_cpu_get_msip(struct metal_cpu *cpu, int hartid)
* @param cpu The CPU device handle
* @return The handle for the CPU interrupt controller
*/
-inline struct metal_interrupt* metal_cpu_interrupt_controller(struct metal_cpu *cpu)
-{ return cpu->vtable->controller_interrupt(cpu); }
+__inline__ struct metal_interrupt *
+metal_cpu_interrupt_controller(struct metal_cpu *cpu) {
+ return cpu->vtable->controller_interrupt(cpu);
+}
/*!
* @brief Register an exception handler
- *
- * Register an exception handler for the CPU. The CPU interrupt controller must be initialized
- * before this function is called.
+ *
+ * Register an exception handler for the CPU. The CPU interrupt controller must
+ * be initialized before this function is called.
*
* @param cpu The CPU device handle
* @param ecode The exception code to register a handler for
* @param handler Callback function for the exception handler
* @return 0 upon success
*/
-inline int metal_cpu_exception_register(struct metal_cpu *cpu, int ecode, metal_exception_handler_t handler)
-{ return cpu->vtable->exception_register(cpu, ecode, handler); }
+__inline__ int metal_cpu_exception_register(struct metal_cpu *cpu, int ecode,
+ metal_exception_handler_t handler) {
+ return cpu->vtable->exception_register(cpu, ecode, handler);
+}
/*!
* @brief Get the length of an instruction in bytes
@@ -237,8 +257,10 @@ inline int metal_cpu_exception_register(struct metal_cpu *cpu, int ecode, metal_
* @param epc The address of the instruction to measure
* @return the length of the instruction in bytes
*/
-inline int metal_cpu_get_instruction_length(struct metal_cpu *cpu, uintptr_t epc)
-{ return cpu->vtable->get_ilen(cpu, epc); }
+__inline__ int metal_cpu_get_instruction_length(struct metal_cpu *cpu,
+ uintptr_t epc) {
+ return cpu->vtable->get_ilen(cpu, epc);
+}
/*!
* @brief Get the program counter of the current exception.
@@ -249,8 +271,9 @@ inline int metal_cpu_get_instruction_length(struct metal_cpu *cpu, uintptr_t epc
* @param cpu The CPU device handle
* @return The value of the program counter at the time of the exception
*/
-inline uintptr_t metal_cpu_get_exception_pc(struct metal_cpu *cpu)
-{ return cpu->vtable->get_epc(cpu); }
+__inline__ uintptr_t metal_cpu_get_exception_pc(struct metal_cpu *cpu) {
+ return cpu->vtable->get_epc(cpu);
+}
/*!
* @brief Set the exception program counter
@@ -265,7 +288,20 @@ inline uintptr_t metal_cpu_get_exception_pc(struct metal_cpu *cpu)
* @param epc The address to set the exception program counter to
* @return 0 upon success
*/
-inline int metal_cpu_set_exception_pc(struct metal_cpu *cpu, uintptr_t epc)
-{ return cpu->vtable->set_epc(cpu, epc); }
+__inline__ int metal_cpu_set_exception_pc(struct metal_cpu *cpu,
+ uintptr_t epc) {
+ return cpu->vtable->set_epc(cpu, epc);
+}
+
+/*!
+ * @brief Get the handle for the hart's bus error unit
+ *
+ * @param cpu The CPU device handle
+ * @return A pointer to the bus error unit handle
+ */
+__inline__ struct metal_buserror *
+metal_cpu_get_buserror(struct metal_cpu *cpu) {
+ return cpu->vtable->get_buserror(cpu);
+}
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/csr.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/csr.h
new file mode 100644
index 000000000..8375d8a44
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/csr.h
@@ -0,0 +1,32 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef METAL__CSR_H
+#define METAL__CSR_H
+
+#include
+#include
+#include
+
+/*!
+ * @file csr.h
+ * @brief A collection of APIs for get and set CSR registers
+ */
+
+/*!
+ * @brief Read a given CSR register without checking validity of CSR offset
+ * @param crs Register label or hex value offset to read from
+ * @param value Variable name of uintprt_t type to get the value
+ */
+#define METAL_CPU_GET_CSR(reg, value) \
+ __asm__ volatile("csrr %0, " #reg : "=r"(value));
+
+/*!
+ * @brief Write to a given CSR register without checking validity of CSR offset
+ * @param crs Register label or hex value offset to write to
+ * @param value Variable name of uintprt_t type to set the value
+ */
+#define METAL_CPU_SET_CSR(reg, value) \
+ __asm__ volatile("csrw " #reg ", %0" : : "r"(value));
+
+#endif // METAL__CSR_H
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-clock.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-clock.h
index 2647c5981..b25f54144 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-clock.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-clock.h
@@ -6,8 +6,8 @@
struct __metal_driver_fixed_clock;
-#include
#include
+#include
struct __metal_driver_vtable_fixed_clock {
struct __metal_clock_vtable clock;
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-factor-clock.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-factor-clock.h
index 936ce8d77..84e4fd580 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-factor-clock.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/fixed-factor-clock.h
@@ -6,8 +6,8 @@
struct __metal_driver_fixed_factor_clock;
-#include
#include
+#include
struct __metal_driver_vtable_fixed_factor_clock {
struct __metal_clock_vtable clock;
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_clint0.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_clint0.h
index 08d571e1c..ceda473e2 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_clint0.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_clint0.h
@@ -21,4 +21,7 @@ struct __metal_driver_riscv_clint0 {
};
#undef __METAL_MACHINE_MACROS
+int __metal_driver_riscv_clint0_command_request(
+ struct metal_interrupt *controller, int command, void *data);
+
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_cpu.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_cpu.h
index eb1e5b8ca..f3005f01f 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_cpu.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_cpu.h
@@ -4,148 +4,154 @@
#ifndef METAL__DRIVERS__RISCV_CPU_H
#define METAL__DRIVERS__RISCV_CPU_H
-#include
-#include
#include
+#include
+#include
-#define METAL_MAX_CORES 8
-#define METAL_MAX_MI 32 /* Per ISA MCause interrupts 32+ are Reserved */
-#define METAL_MAX_ME 12 /* Per ISA Exception codes 12+ are Reserved */
-#define METAL_DEFAULT_RTC_FREQ 32768
-
-#define METAL_DISABLE 0
-#define METAL_ENABLE 1
-
-#define METAL_ISA_A_EXTENSIONS 0x0001
-#define METAL_ISA_C_EXTENSIONS 0x0004
-#define METAL_ISA_D_EXTENSIONS 0x0008
-#define METAL_ISA_E_EXTENSIONS 0x0010
-#define METAL_ISA_F_EXTENSIONS 0x0020
-#define METAL_ISA_G_EXTENSIONS 0x0040
-#define METAL_ISA_I_EXTENSIONS 0x0100
-#define METAL_ISA_M_EXTENSIONS 0x1000
-#define METAL_ISA_N_EXTENSIONS 0x2000
-#define METAL_ISA_Q_EXTENSIONS 0x10000
-#define METAL_ISA_S_EXTENSIONS 0x40000
-#define METAL_ISA_U_EXTENSIONS 0x100000
-#define METAL_ISA_V_EXTENSIONS 0x200000
-#define METAL_ISA_XL32_EXTENSIONS 0x40000000UL
-#define METAL_ISA_XL64_EXTENSIONS 0x8000000000000000UL
+#define METAL_MAX_CORES 8
+#define METAL_MAX_MI 32 /* Per ISA MCause interrupts 32+ are Reserved */
+#define METAL_MAX_ME 12 /* Per ISA Exception codes 12+ are Reserved */
+#define METAL_DEFAULT_RTC_FREQ 32768
+
+#define METAL_DISABLE 0
+#define METAL_ENABLE 1
+
+#define METAL_ISA_A_EXTENSIONS 0x0001
+#define METAL_ISA_C_EXTENSIONS 0x0004
+#define METAL_ISA_D_EXTENSIONS 0x0008
+#define METAL_ISA_E_EXTENSIONS 0x0010
+#define METAL_ISA_F_EXTENSIONS 0x0020
+#define METAL_ISA_G_EXTENSIONS 0x0040
+#define METAL_ISA_I_EXTENSIONS 0x0100
+#define METAL_ISA_M_EXTENSIONS 0x1000
+#define METAL_ISA_N_EXTENSIONS 0x2000
+#define METAL_ISA_Q_EXTENSIONS 0x10000
+#define METAL_ISA_S_EXTENSIONS 0x40000
+#define METAL_ISA_U_EXTENSIONS 0x100000
+#define METAL_ISA_V_EXTENSIONS 0x200000
+#define METAL_ISA_XL32_EXTENSIONS 0x40000000UL
+#define METAL_ISA_XL64_EXTENSIONS 0x8000000000000000UL
#define METAL_ISA_XL128_EXTENSIONS 0xC000000000000000UL
-#define METAL_MTVEC_DIRECT 0x00
-#define METAL_MTVEC_VECTORED 0x01
-#define METAL_MTVEC_CLIC 0x02
-#define METAL_MTVEC_CLIC_VECTORED 0x03
-#define METAL_MTVEC_CLIC_RESERVED 0x3C
-#define METAL_MTVEC_MASK 0x3F
+#define METAL_MTVEC_DIRECT 0x00
+#define METAL_MTVEC_VECTORED 0x01
+#define METAL_MTVEC_CLIC 0x02
+#define METAL_MTVEC_CLIC_VECTORED 0x03
+#define METAL_MTVEC_CLIC_RESERVED 0x3C
+#define METAL_MTVEC_MASK 0x3F
#if __riscv_xlen == 32
-#define METAL_MCAUSE_INTR 0x80000000UL
-#define METAL_MCAUSE_CAUSE 0x000003FFUL
+#define METAL_MCAUSE_INTR 0x80000000UL
+#define METAL_MCAUSE_CAUSE 0x000003FFUL
#else
-#define METAL_MCAUSE_INTR 0x8000000000000000UL
-#define METAL_MCAUSE_CAUSE 0x00000000000003FFUL
+#define METAL_MCAUSE_INTR 0x8000000000000000UL
+#define METAL_MCAUSE_CAUSE 0x00000000000003FFUL
#endif
-#define METAL_MCAUSE_MINHV 0x40000000UL
-#define METAL_MCAUSE_MPP 0x30000000UL
-#define METAL_MCAUSE_MPIE 0x08000000UL
-#define METAL_MCAUSE_MPIL 0x00FF0000UL
-#define METAL_MSTATUS_MIE 0x00000008UL
-#define METAL_MSTATUS_MPIE 0x00000080UL
-#define METAL_MSTATUS_MPP 0x00001800UL
-#define METAL_MSTATUS_FS_INIT 0x00002000UL
-#define METAL_MSTATUS_FS_CLEAN 0x00004000UL
-#define METAL_MSTATUS_FS_DIRTY 0x00006000UL
-#define METAL_MSTATUS_MPRV 0x00020000UL
-#define METAL_MSTATUS_MXR 0x00080000UL
-#define METAL_MINTSTATUS_MIL 0xFF000000UL
-#define METAL_MINTSTATUS_SIL 0x0000FF00UL
-#define METAL_MINTSTATUS_UIL 0x000000FFUL
-
-#define METAL_LOCAL_INTR(X) (16 + X)
-#define METAL_MCAUSE_EVAL(cause) (cause & METAL_MCAUSE_INTR)
-#define METAL_INTERRUPT(cause) (METAL_MCAUSE_EVAL(cause) ? 1 : 0)
-#define METAL_EXCEPTION(cause) (METAL_MCAUSE_EVAL(cause) ? 0 : 1)
-#define METAL_SW_INTR_EXCEPTION (METAL_MCAUSE_INTR + 3)
-#define METAL_TMR_INTR_EXCEPTION (METAL_MCAUSE_INTR + 7)
-#define METAL_EXT_INTR_EXCEPTION (METAL_MCAUSE_INTR + 11)
+#define METAL_MCAUSE_MINHV 0x40000000UL
+#define METAL_MCAUSE_MPP 0x30000000UL
+#define METAL_MCAUSE_MPIE 0x08000000UL
+#define METAL_MCAUSE_MPIL 0x00FF0000UL
+#define METAL_MSTATUS_MIE 0x00000008UL
+#define METAL_MSTATUS_MPIE 0x00000080UL
+#define METAL_MSTATUS_MPP 0x00001800UL
+#define METAL_MSTATUS_FS_INIT 0x00002000UL
+#define METAL_MSTATUS_FS_CLEAN 0x00004000UL
+#define METAL_MSTATUS_FS_DIRTY 0x00006000UL
+#define METAL_MSTATUS_MPRV 0x00020000UL
+#define METAL_MSTATUS_MXR 0x00080000UL
+#define METAL_MINTSTATUS_MIL 0xFF000000UL
+#define METAL_MINTSTATUS_SIL 0x0000FF00UL
+#define METAL_MINTSTATUS_UIL 0x000000FFUL
+
+#define METAL_LOCAL_INTR(X) (16 + X)
+#define METAL_MCAUSE_EVAL(cause) (cause & METAL_MCAUSE_INTR)
+#define METAL_INTERRUPT(cause) (METAL_MCAUSE_EVAL(cause) ? 1 : 0)
+#define METAL_EXCEPTION(cause) (METAL_MCAUSE_EVAL(cause) ? 0 : 1)
+#define METAL_SW_INTR_EXCEPTION (METAL_MCAUSE_INTR + 3)
+#define METAL_TMR_INTR_EXCEPTION (METAL_MCAUSE_INTR + 7)
+#define METAL_EXT_INTR_EXCEPTION (METAL_MCAUSE_INTR + 11)
#define METAL_LOCAL_INTR_EXCEPTION(X) (METAL_MCAUSE_INTR + METAL_LOCAL_INTR(X))
-#define METAL_LOCAL_INTR_RESERVE0 1
-#define METAL_LOCAL_INTR_RESERVE1 2
-#define METAL_LOCAL_INTR_RESERVE2 4
-#define METAL_LOCAL_INTERRUPT_SW 8 /* Bit3 0x008 */
-#define METAL_LOCAL_INTR_RESERVE4 16
-#define METAL_LOCAL_INTR_RESERVE5 32
-#define METAL_LOCAL_INTR_RESERVE6 64
-#define METAL_LOCAL_INTERRUPT_TMR 128 /* Bit7 0x080 */
-#define METAL_LOCAL_INTR_RESERVE8 256
-#define METAL_LOCAL_INTR_RESERVE9 512
-#define METAL_LOCAL_INTR_RESERVE10 1024
-#define METAL_LOCAL_INTERRUPT_EXT 2048 /* Bit11 0x800 */
+#define METAL_LOCAL_INTR_RESERVE0 1
+#define METAL_LOCAL_INTR_RESERVE1 2
+#define METAL_LOCAL_INTR_RESERVE2 4
+#define METAL_LOCAL_INTERRUPT_SW 8 /* Bit3 0x008 */
+#define METAL_LOCAL_INTR_RESERVE4 16
+#define METAL_LOCAL_INTR_RESERVE5 32
+#define METAL_LOCAL_INTR_RESERVE6 64
+#define METAL_LOCAL_INTERRUPT_TMR 128 /* Bit7 0x080 */
+#define METAL_LOCAL_INTR_RESERVE8 256
+#define METAL_LOCAL_INTR_RESERVE9 512
+#define METAL_LOCAL_INTR_RESERVE10 1024
+#define METAL_LOCAL_INTERRUPT_EXT 2048 /* Bit11 0x800 */
/* Bit12 to Bit15 are Reserved */
-#define METAL_LOCAL_INTERRUPT(X) (0x10000 << X) /* Bit16+ Start of Custom Local Interrupt */
-#define METAL_MIE_INTERRUPT METAL_MSTATUS_MIE
+#define METAL_LOCAL_INTERRUPT(X) \
+ (0x10000 << X) /* Bit16+ Start of Custom Local Interrupt */
+#define METAL_MIE_INTERRUPT METAL_MSTATUS_MIE
+
+#define METAL_INSN_LENGTH_MASK 3
+#define METAL_INSN_NOT_COMPRESSED 3
typedef enum {
- METAL_MACHINE_PRIVILEGE_MODE,
- METAL_SUPERVISOR_PRIVILEGE_MODE,
- METAL_USER_PRIVILEGE_MODE,
+ METAL_MACHINE_PRIVILEGE_MODE,
+ METAL_SUPERVISOR_PRIVILEGE_MODE,
+ METAL_USER_PRIVILEGE_MODE,
} metal_privilege_mode_e;
typedef enum {
- METAL_INTERRUPT_ID_BASE,
- METAL_INTERRUPT_ID_SW = (METAL_INTERRUPT_ID_BASE + 3),
- METAL_INTERRUPT_ID_TMR = (METAL_INTERRUPT_ID_BASE + 7),
- METAL_INTERRUPT_ID_EXT = (METAL_INTERRUPT_ID_BASE + 11),
- METAL_INTERRUPT_ID_LC0 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(0)),
- METAL_INTERRUPT_ID_LC1 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(1)),
- METAL_INTERRUPT_ID_LC2 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(2)),
- METAL_INTERRUPT_ID_LC3 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(3)),
- METAL_INTERRUPT_ID_LC4 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(4)),
- METAL_INTERRUPT_ID_LC5 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(5)),
- METAL_INTERRUPT_ID_LC6 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(6)),
- METAL_INTERRUPT_ID_LC7 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(7)),
- METAL_INTERRUPT_ID_LC8 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(8)),
- METAL_INTERRUPT_ID_LC9 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(9)),
- METAL_INTERRUPT_ID_LC10 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(10)),
- METAL_INTERRUPT_ID_LC11 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(11)),
- METAL_INTERRUPT_ID_LC12 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(12)),
- METAL_INTERRUPT_ID_LC13 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(13)),
- METAL_INTERRUPT_ID_LC14 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(14)),
- METAL_INTERRUPT_ID_LC15 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(15)),
- METAL_INTERRUPT_ID_LCMX,
- METAL_INTERRUPT_ID_GL0 = METAL_INTERRUPT_ID_LCMX,
- METAL_INTERRUPT_ID_GLMX = (METAL_MCAUSE_CAUSE + 1),
+ METAL_INTERRUPT_ID_BASE,
+ METAL_INTERRUPT_ID_SW = (METAL_INTERRUPT_ID_BASE + 3),
+ METAL_INTERRUPT_ID_TMR = (METAL_INTERRUPT_ID_BASE + 7),
+ METAL_INTERRUPT_ID_EXT = (METAL_INTERRUPT_ID_BASE + 11),
+ METAL_INTERRUPT_ID_CSW = (METAL_INTERRUPT_ID_BASE + 12),
+ METAL_INTERRUPT_ID_LC0 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(0)),
+ METAL_INTERRUPT_ID_LC1 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(1)),
+ METAL_INTERRUPT_ID_LC2 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(2)),
+ METAL_INTERRUPT_ID_LC3 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(3)),
+ METAL_INTERRUPT_ID_LC4 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(4)),
+ METAL_INTERRUPT_ID_LC5 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(5)),
+ METAL_INTERRUPT_ID_LC6 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(6)),
+ METAL_INTERRUPT_ID_LC7 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(7)),
+ METAL_INTERRUPT_ID_LC8 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(8)),
+ METAL_INTERRUPT_ID_LC9 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(9)),
+ METAL_INTERRUPT_ID_LC10 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(10)),
+ METAL_INTERRUPT_ID_LC11 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(11)),
+ METAL_INTERRUPT_ID_LC12 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(12)),
+ METAL_INTERRUPT_ID_LC13 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(13)),
+ METAL_INTERRUPT_ID_LC14 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(14)),
+ METAL_INTERRUPT_ID_LC15 = (METAL_INTERRUPT_ID_BASE + METAL_LOCAL_INTR(15)),
+ METAL_INTERRUPT_ID_LCMX,
+ METAL_INTERRUPT_ID_GL0 = METAL_INTERRUPT_ID_LCMX,
+ METAL_INTERRUPT_ID_GLMX = (METAL_MCAUSE_CAUSE + 1),
+ METAL_INTERRUPT_ID_BEU = 128,
} metal_interrupt_id_e;
typedef enum {
- METAL_IAM_EXCEPTION_CODE, /* Instruction address misaligned */
- METAL_IAF_EXCEPTION_CODE, /* Instruction access faultd */
- METAL_II_EXCEPTION_CODE, /* Illegal instruction */
- METAL_BREAK_EXCEPTION_CODE, /* Breakpoint */
- METAL_LAM_EXCEPTION_CODE, /* Load address misaligned */
- METAL_LAF_EXCEPTION_CODE, /* Load access fault */
- METAL_SAMOAM_EXCEPTION_CODE, /* Store/AMO address misaligned */
- METAL_SAMOAF_EXCEPTION_CODE, /* Store/AMO access fault */
- METAL_ECALL_U_EXCEPTION_CODE, /* Environment call from U-mode */
- METAL_R9_EXCEPTION_CODE, /* Reserved */
- METAL_R10_EXCEPTION_CODE, /* Reserved */
- METAL_ECALL_M_EXCEPTION_CODE, /* Environment call from M-mode */
- METAL_MAX_EXCEPTION_CODE,
+ METAL_IAM_EXCEPTION_CODE, /* Instruction address misaligned */
+ METAL_IAF_EXCEPTION_CODE, /* Instruction access faultd */
+ METAL_II_EXCEPTION_CODE, /* Illegal instruction */
+ METAL_BREAK_EXCEPTION_CODE, /* Breakpoint */
+ METAL_LAM_EXCEPTION_CODE, /* Load address misaligned */
+ METAL_LAF_EXCEPTION_CODE, /* Load access fault */
+ METAL_SAMOAM_EXCEPTION_CODE, /* Store/AMO address misaligned */
+ METAL_SAMOAF_EXCEPTION_CODE, /* Store/AMO access fault */
+ METAL_ECALL_U_EXCEPTION_CODE, /* Environment call from U-mode */
+ METAL_R9_EXCEPTION_CODE, /* Reserved */
+ METAL_R10_EXCEPTION_CODE, /* Reserved */
+ METAL_ECALL_M_EXCEPTION_CODE, /* Environment call from M-mode */
+ METAL_MAX_EXCEPTION_CODE,
} metal_exception_code_e;
typedef enum {
- METAL_TIMER_MTIME_GET = 1,
- METAL_SOFTWARE_IPI_CLEAR,
- METAL_SOFTWARE_IPI_SET,
- METAL_SOFTWARE_MSIP_GET,
- METAL_MAX_INTERRUPT_GET,
- METAL_INDEX_INTERRUPT_GET,
+ METAL_TIMER_MTIME_GET = 1,
+ METAL_SOFTWARE_IPI_CLEAR,
+ METAL_SOFTWARE_IPI_SET,
+ METAL_SOFTWARE_MSIP_GET,
+ METAL_MAX_INTERRUPT_GET,
+ METAL_INDEX_INTERRUPT_GET,
} metal_interrup_cmd_e;
typedef struct __metal_interrupt_data {
long long pad : 64;
- metal_interrupt_handler_t handler;
+ metal_interrupt_handler_t handler;
void *sub_int;
void *exint_data;
} __metal_interrupt_data;
@@ -154,30 +160,15 @@ typedef struct __metal_interrupt_data {
uintptr_t __metal_myhart_id(void);
-struct __metal_driver_interrupt_controller_vtable {
- void (*interrupt_init)(struct metal_interrupt *controller);
- int (*interrupt_register)(struct metal_interrupt *controller,
- int id, metal_interrupt_handler_t isr, void *priv_data);
- int (*interrupt_enable)(struct metal_interrupt *controller, int id);
- int (*interrupt_disable)(struct metal_interrupt *controller, int id);
- int (*command_request)(struct metal_interrupt *intr, int cmd, void *data);
-};
-
struct __metal_driver_vtable_riscv_cpu_intc {
- struct metal_interrupt_vtable controller_vtable;
+ struct metal_interrupt_vtable controller_vtable;
};
-
void __metal_interrupt_global_enable(void);
void __metal_interrupt_global_disable(void);
-void __metal_controller_interrupt_vector(metal_vector_mode mode, void *vec_table);
-inline int __metal_controller_interrupt_is_selective_vectored (void)
-{
- uintptr_t val;
-
- asm volatile ("csrr %0, mtvec" : "=r"(val));
- return ((val & METAL_MTVEC_CLIC_VECTORED) == METAL_MTVEC_CLIC);
-}
+metal_vector_mode __metal_controller_interrupt_vector_mode(void);
+void __metal_controller_interrupt_vector(metal_vector_mode mode,
+ void *vec_table);
__METAL_DECLARE_VTABLE(__metal_driver_vtable_riscv_cpu_intc)
@@ -186,18 +177,20 @@ struct __metal_driver_riscv_cpu_intc {
int init_done;
uintptr_t metal_mtvec_table[METAL_MAX_MI];
__metal_interrupt_data metal_int_table[METAL_MAX_MI];
+ __metal_interrupt_data metal_int_beu;
metal_exception_handler_t metal_exception_table[METAL_MAX_ME];
};
/* CPU driver*/
struct __metal_driver_vtable_cpu {
- struct metal_cpu_vtable cpu_vtable;
+ struct metal_cpu_vtable cpu_vtable;
};
__METAL_DECLARE_VTABLE(__metal_driver_vtable_cpu)
struct __metal_driver_cpu {
struct metal_cpu cpu;
+ unsigned int hpm_count; /* Available HPM counters per CPU */
};
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_plic0.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_plic0.h
index 159ee6d69..fac76fbc3 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_plic0.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/riscv_plic0.h
@@ -7,10 +7,10 @@
#include
#include
-#define METAL_PLIC_SOURCE_MASK 0x1F
-#define METAL_PLIC_SOURCE_SHIFT 5
-#define METAL_PLIC_SOURCE_PRIORITY_SHIFT 2
-#define METAL_PLIC_SOURCE_PENDING_SHIFT 0
+#define METAL_PLIC_SOURCE_MASK 0x1F
+#define METAL_PLIC_SOURCE_SHIFT 5
+#define METAL_PLIC_SOURCE_PRIORITY_SHIFT 2
+#define METAL_PLIC_SOURCE_PENDING_SHIFT 0
struct __metal_driver_vtable_riscv_plic0 {
struct metal_interrupt_vtable plic_vtable;
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_buserror0.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_buserror0.h
new file mode 100644
index 000000000..20972109b
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_buserror0.h
@@ -0,0 +1,184 @@
+/* Copyright 2020 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef METAL__DRIVERS__SIFIVE_BUSERROR0_H
+#define METAL__DRIVERS__SIFIVE_BUSERROR0_H
+
+/*!
+ * @file sifive_buserror0.h
+ *
+ * @brief API for configuring the SiFive Bus Error Unit
+ */
+
+#include
+#include
+#include
+
+/*!
+ * @brief The set of possible events handled by a SiFive Bus Error Unit
+ */
+typedef enum {
+ /*! @brief No event or error has been detected */
+ METAL_BUSERROR_EVENT_NONE = 0,
+
+ /*! @brief A correctable ECC error has occurred in the I$ or ITIM */
+ METAL_BUSERROR_EVENT_INST_CORRECTABLE_ECC_ERROR = (1 << 2),
+ /*! @brief An uncorrectable ECC error has occurred in the I$ or ITIM */
+ METAL_BUSERROR_EVENT_INST_UNCORRECTABLE_ECC_ERROR = (1 << 3),
+ /*! @brief A TileLink load or store bus error has occurred */
+ METAL_BUSERROR_EVENT_LOAD_STORE_ERROR = (1 << 5),
+ /*! @brief A correctable ECC error has occurred in the D$ or DTIM */
+ METAL_BUSERROR_EVENT_DATA_CORRECTABLE_ECC_ERROR = (1 << 6),
+ /*! @brief An uncorrectable ECC error has occurred in the D$ or DTIM */
+ METAL_BUSERROR_EVENT_DATA_UNCORRECTABLE_ECC_ERROR = (1 << 7),
+
+ /*! @brief Used to set/clear all interrupts or query/clear all accrued
+ events */
+ METAL_BUSERROR_EVENT_ALL =
+ METAL_BUSERROR_EVENT_INST_CORRECTABLE_ECC_ERROR |
+ METAL_BUSERROR_EVENT_INST_UNCORRECTABLE_ECC_ERROR |
+ METAL_BUSERROR_EVENT_LOAD_STORE_ERROR |
+ METAL_BUSERROR_EVENT_DATA_CORRECTABLE_ECC_ERROR |
+ METAL_BUSERROR_EVENT_DATA_UNCORRECTABLE_ECC_ERROR,
+ /*! @brief A synonym of METAL_BUSERROR_EVENT_ALL */
+ METAL_BUSERROR_EVENT_ANY = METAL_BUSERROR_EVENT_ALL,
+
+ /*! @brief A value which is impossible for the bus error unit to report.
+ * Indicates an error has occurred if provided as a return value. */
+ METAL_BUSERROR_EVENT_INVALID = (1 << 8),
+} metal_buserror_event_t;
+
+/*!
+ * @brief The handle for a bus error unit
+ */
+struct metal_buserror {
+ uint8_t __no_empty_structs;
+};
+
+/*!
+ * @brief Enable bus error events
+ *
+ * Enabling bus error events causes them to be registered as accrued and,
+ * if the corresponding interrupt is inabled, trigger interrupts.
+ *
+ * @param beu The bus error unit handle
+ * @param events A mask of error events to enable
+ * @param enabled True if the mask should be enabled, false if they should be
+ * disabled
+ * @return 0 upon success
+ */
+int metal_buserror_set_event_enabled(struct metal_buserror *beu,
+ metal_buserror_event_t events,
+ bool enabled);
+
+/*!
+ * @brief Get enabled bus error events
+ * @param beu The bus error unit handle
+ * @return A mask of all enabled events
+ */
+metal_buserror_event_t
+metal_buserror_get_event_enabled(struct metal_buserror *beu);
+
+/*!
+ * @brief Enable or disable the platform interrupt
+ *
+ * @param beu The bus error unit handle
+ * @param event The error event which would trigger the interrupt
+ * @param enabled True if the interrupt should be enabled
+ * @return 0 upon success
+ */
+int metal_buserror_set_platform_interrupt(struct metal_buserror *beu,
+ metal_buserror_event_t events,
+ bool enabled);
+
+/*!
+ * @brief Enable or disable the hart-local interrupt
+ *
+ * @param beu The bus error unit handle
+ * @param event The error event which would trigger the interrupt
+ * @param enabled True if the interrupt should be enabled
+ * @return 0 upon success
+ */
+int metal_buserror_set_local_interrupt(struct metal_buserror *beu,
+ metal_buserror_event_t events,
+ bool enabled);
+
+/*!
+ * @brief Get the error event which caused the most recent interrupt
+ *
+ * This method should be called from within the interrupt handler for the bus
+ * error unit interrupt
+ *
+ * @param beu The bus error unit handle
+ * @return The event which caused the interrupt
+ */
+metal_buserror_event_t metal_buserror_get_cause(struct metal_buserror *beu);
+
+/*!
+ * @brief Clear the cause register for the bus error unit
+ *
+ * This method should be called from within the interrupt handler for the bus
+ * error unit to un-latch the cause register for the next event
+ *
+ * @param beu The bus error unit handle
+ * @return 0 upon success
+ */
+int metal_buserror_clear_cause(struct metal_buserror *beu);
+
+/*!
+ * @brief Get the physical address of the error event
+ *
+ * This method should be called from within the interrupt handler for the bus
+ * error unit.
+ *
+ * @param beu The bus error unit handle
+ * @return The address of the error event
+ */
+uintptr_t metal_buserror_get_event_address(struct metal_buserror *beu);
+
+/*!
+ * @brief Returns true if the event is set in the accrued register
+ *
+ * @param beu The bus error unit handle
+ * @param event The event to query
+ * @return True if the event is set in the accrued register
+ */
+bool metal_buserror_is_event_accrued(struct metal_buserror *beu,
+ metal_buserror_event_t events);
+
+/*!
+ * @brief Clear the given event from the accrued register
+ *
+ * @param beu The bus error unit handle
+ * @param event The event to clear
+ * @return 0 upon success
+ */
+int metal_buserror_clear_event_accrued(struct metal_buserror *beu,
+ metal_buserror_event_t events);
+
+/*!
+ * @brief get the platform-level interrupt parent of the bus error unit
+ *
+ * @param beu The bus error unit handle
+ * @return A pointer to the interrupt parent
+ */
+struct metal_interrupt *
+metal_buserror_get_platform_interrupt_parent(struct metal_buserror *beu);
+
+/*!
+ * @brief Get the platform-level interrupt id for the bus error unit interrupt
+ *
+ * @param beu The bus error unit handle
+ * @return The interrupt id
+ */
+int metal_buserror_get_platform_interrupt_id(struct metal_buserror *beu);
+
+/*!
+ * @brief Get the hart-local interrupt id for the bus error unit interrupt
+ *
+ * @param beu The bus error unit handle
+ * @return The interrupt id
+ */
+int metal_buserror_get_local_interrupt_id(struct metal_buserror *beu);
+
+#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_ccache0.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_ccache0.h
new file mode 100644
index 000000000..13a47c0b9
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_ccache0.h
@@ -0,0 +1,140 @@
+/* Copyright 2020 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef METAL__DRIVERS__SIFIVE_CCACHE0_H
+#define METAL__DRIVERS__SIFIVE_CCACHE0_H
+
+/*!
+ * @file sifive_ccache0.h
+ *
+ * @brief API for configuring the SiFive L2 cache controller
+ */
+
+#include
+#include
+
+/*! @brief Cache configuration data */
+typedef struct {
+ uint32_t num_bank;
+ uint32_t num_ways;
+ uint32_t num_sets;
+ uint32_t block_size;
+} sifive_ccache0_config;
+
+/*! @brief Set of values for ECC error type */
+typedef enum {
+ SIFIVE_CCACHE0_DATA = 0,
+ SIFIVE_CCACHE0_DIR = 1,
+} sifive_ccache0_ecc_errtype_t;
+
+/*! @brief Initialize cache controller, enables all available
+ * cache-ways.
+ * Note: If LIM is in use, corresponding cache ways are not enabled.
+ * @param None.
+ * @return 0 If no error.*/
+int sifive_ccache0_init(void);
+
+/*! @brief Get cache configuration data.
+ * @param config User specified data buffer.
+ * @return None.*/
+void sifive_ccache0_get_config(sifive_ccache0_config *config);
+
+/*! @brief Get currently active cache ways.
+ * @param None.
+ * @return Number of cache ways enabled.*/
+uint32_t sifive_ccache0_get_enabled_ways(void);
+
+/*! @brief Enable specified cache ways.
+ * @param ways Number of ways to be enabled.
+ * @return 0 If no error.*/
+int sifive_ccache0_set_enabled_ways(uint32_t ways);
+
+/*! @brief Inject ECC error into data or meta-data.
+ * @param bitindex Bit index to be corrupted on next cache operation.
+ * @param type ECC error target location.
+ * @return None.*/
+void sifive_ccache0_inject_ecc_error(uint32_t bitindex,
+ sifive_ccache0_ecc_errtype_t type);
+
+/*! @brief Flush out entire cache block containing given address.
+ * @param flush_addr Address for the cache block to be flushed.
+ * @return None.*/
+void sifive_ccache0_flush(uintptr_t flush_addr);
+
+/*! @brief Get most recently ECC corrected address.
+ * @param type ECC error target location.
+ * @return Last corrected ECC address.*/
+uintptr_t sifive_ccache0_get_ecc_fix_addr(sifive_ccache0_ecc_errtype_t type);
+
+/*! @brief Get number of times ECC errors were corrected.
+ * Clears related ECC interrupt signals.
+ * @param type ECC error target location.
+ * @return Corrected ECC error count.*/
+uint32_t sifive_ccache0_get_ecc_fix_count(sifive_ccache0_ecc_errtype_t type);
+
+/*! @brief Get address location of most recent uncorrected ECC error.
+ * @param type ECC error target location.
+ * @return Last uncorrected ECC address.*/
+uintptr_t sifive_ccache0_get_ecc_fail_addr(sifive_ccache0_ecc_errtype_t type);
+
+/*! @brief Get number of times ECC errors were not corrected.
+ * Clears related ECC interrupt signals.
+ * @param type ECC error target location.
+ * @return Uncorrected ECC error count.*/
+uint32_t sifive_ccache0_get_ecc_fail_count(sifive_ccache0_ecc_errtype_t type);
+
+/*! @brief Get currently active way enable mask value for the given master ID.
+ * @param master_id Cache controller master ID.
+ * @return Way enable mask. */
+uint64_t sifive_ccache0_get_way_mask(uint32_t master_id);
+
+/*! @brief Set way enable mask for the given master ID.
+ * @param master_id Cache controller master ID.
+ * @param waymask Specify ways to be enabled.
+ * @return 0 If no error.*/
+int sifive_ccache0_set_way_mask(uint32_t master_id, uint64_t waymask);
+
+/*! @brief Select cache performance events to be counted.
+ * @param counter Cache performance monitor counter index.
+ * @param mask Event selection mask.
+ * @return None.*/
+void sifive_ccache0_set_pmevent_selector(uint32_t counter, uint64_t mask);
+
+/*! @brief Get currently set events for the given counter index.
+ * @param counter Cache performance monitor counter index.
+ * @return Event selection mask.*/
+uint64_t sifive_ccache0_get_pmevent_selector(uint32_t counter);
+
+/*! @brief Clears specified cache performance counter.
+ * @param counter Cache performance monitor counter index.
+ * @return None.*/
+void sifive_ccache0_clr_pmevent_counter(uint32_t counter);
+
+/*! @brief Reads specified cache performance counter.
+ * @param counter Cache performance monitor counter index.
+ * @return Counter value.*/
+uint64_t sifive_ccache0_get_pmevent_counter(uint32_t counter);
+
+/*! @brief Select cache clients to be excluded from performance monitoring.
+ * @param mask Client disable mask.
+ * @return None.*/
+void sifive_ccache0_set_client_filter(uint64_t mask);
+
+/*! @brief Get currently set cache client disable mask.
+ * @param None.
+ * @return Client disable mask.*/
+uint64_t sifive_ccache0_get_client_filter(void);
+
+/*! @brief Get interrupt IDs for the cache controller.
+ * @param src Interrupt trigger source index.
+ * @return Interrupt id.*/
+int sifive_ccache0_get_interrupt_id(uint32_t src);
+
+/*! @brief Get interrupt controller of the cache.
+ * The interrupt controller must be initialized before any interrupts can be
+ * registered or enabled with it.
+ * @param None.
+ * @return Handle for the interrupt controller.*/
+struct metal_interrupt *sifive_ccache0_interrupt_controller(void);
+
+#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_clic0.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_clic0.h
index db9674625..b8ff82271 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_clic0.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_clic0.h
@@ -7,21 +7,21 @@
#include
#include
-#define METAL_CLIC_MAX_NMBITS 2
-#define METAL_CLIC_MAX_NLBITS 8
-#define METAL_CLIC_MAX_NVBITS 1
+#define METAL_CLIC_MAX_NMBITS 2
+#define METAL_CLIC_MAX_NLBITS 8
+#define METAL_CLIC_MAX_NVBITS 1
-#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_MMODE 0x00
-#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_SMODE1 0x20
-#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_SMODE2 0x40
-#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_MASK 0x60
-#define METAL_SIFIVE_CLIC0_CLICCFG_NLBITS_MASK 0x1E
-#define METAL_SIFIVE_CLIC0_CLICCFG_NVBIT_MASK 0x01
+#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_MMODE 0x00
+#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_SMODE1 0x20
+#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_SMODE2 0x40
+#define METAL_SIFIVE_CLIC0_CLICCFG_NMBITS_MASK 0x60
+#define METAL_SIFIVE_CLIC0_CLICCFG_NLBITS_MASK 0x1E
+#define METAL_SIFIVE_CLIC0_CLICCFG_NVBIT_MASK 0x01
-#define METAL_CLIC_ICTRL_SMODE1_MASK 0x7F /* b8 set imply M-mode */
-#define METAL_CLIC_ICTRL_SMODE2_MASK 0x3F /* b8 set M-mode, b7 clear U-mode */
+#define METAL_CLIC_ICTRL_SMODE1_MASK 0x7F /* b8 set imply M-mode */
+#define METAL_CLIC_ICTRL_SMODE2_MASK 0x3F /* b8 set M-mode, b7 clear U-mode */
-#define METAL_MAX_INTERRUPT_LEVEL ((1 << METAL_CLIC_MAX_NLBITS) - 1)
+#define METAL_MAX_INTERRUPT_LEVEL ((1 << METAL_CLIC_MAX_NLBITS) - 1)
struct __metal_driver_vtable_sifive_clic0 {
struct metal_interrupt_vtable clic_vtable;
@@ -34,9 +34,15 @@ __METAL_DECLARE_VTABLE(__metal_driver_vtable_sifive_clic0)
struct __metal_driver_sifive_clic0 {
struct metal_interrupt controller;
int init_done;
- metal_interrupt_handler_t metal_mtvt_table[__METAL_CLIC_SUBINTERRUPTS];
+ struct {
+ } __attribute__((aligned(64)));
+ metal_interrupt_vector_handler_t
+ metal_mtvt_table[__METAL_CLIC_SUBINTERRUPTS];
__metal_interrupt_data metal_exint_table[__METAL_CLIC_SUBINTERRUPTS];
};
#undef __METAL_MACHINE_MACROS
+int __metal_driver_sifive_clic0_command_request(
+ struct metal_interrupt *controller, int command, void *data);
+
#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_hfrosc.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_hfrosc.h
index d311f0cf2..d60d3a3bd 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_hfrosc.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_hfrosc.h
@@ -4,9 +4,9 @@
#ifndef METAL__DRIVERS__SIFIVE_FE310_G000_HFROSC_H
#define METAL__DRIVERS__SIFIVE_FE310_G000_HFROSC_H
-#include
-#include
#include
+#include
+#include
#include
struct __metal_driver_vtable_sifive_fe310_g000_hfrosc {
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_lfrosc.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_lfrosc.h
new file mode 100644
index 000000000..2650584ad
--- /dev/null
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_lfrosc.h
@@ -0,0 +1,21 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#ifndef METAL__DRIVERS__SIFIVE_FE310_G000_LFROSC_H
+#define METAL__DRIVERS__SIFIVE_FE310_G000_LFROSC_H
+
+#include
+#include
+#include
+
+struct __metal_driver_vtable_sifive_fe310_g000_lfrosc {
+ struct __metal_clock_vtable clock;
+};
+
+__METAL_DECLARE_VTABLE(__metal_driver_vtable_sifive_fe310_g000_lfrosc)
+
+struct __metal_driver_sifive_fe310_g000_lfrosc {
+ struct metal_clock clock;
+};
+
+#endif
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_prci.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_prci.h
index 87c9ca985..4fca30167 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_prci.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fe310-g000_prci.h
@@ -10,14 +10,16 @@
struct __metal_driver_sifive_fe310_g000_prci;
struct __metal_driver_vtable_sifive_fe310_g000_prci {
- long (*get_reg)(const struct __metal_driver_sifive_fe310_g000_prci *, long offset);
- long (*set_reg)(const struct __metal_driver_sifive_fe310_g000_prci *, long offset, long value);
+ long (*get_reg)(const struct __metal_driver_sifive_fe310_g000_prci *,
+ long offset);
+ long (*set_reg)(const struct __metal_driver_sifive_fe310_g000_prci *,
+ long offset, long value);
};
__METAL_DECLARE_VTABLE(__metal_driver_vtable_sifive_fe310_g000_prci)
struct __metal_driver_sifive_fe310_g000_prci {
+ const struct __metal_driver_vtable_sifive_fe310_g000_prci *vtable;
};
#endif
-
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fu540-c000_l2.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fu540-c000_l2.h
deleted file mode 100644
index 8c3cf907e..000000000
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_fu540-c000_l2.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright 2018 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-
-#ifndef METAL__DRIVERS__SIFIVE_FU540_C000_L2_H
-#define METAL__DRIVERS__SIFIVE_FU540_C000_L2_H
-
-struct __metal_driver_sifive_fu540_c000_l2;
-
-#include
-#include
-
-struct __metal_driver_vtable_sifive_fu540_c000_l2 {
- struct __metal_cache_vtable cache;
-};
-
-__METAL_DECLARE_VTABLE(__metal_driver_vtable_sifive_fu540_c000_l2)
-
-struct __metal_driver_sifive_fu540_c000_l2 {
- struct metal_cache cache;
-};
-
-#endif
-
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-buttons.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-buttons.h
index a0caeaba8..7227eee02 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-buttons.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-buttons.h
@@ -4,12 +4,12 @@
#ifndef METAL__DRIVERS__SIFIVE_GPIO_BUTTONS_H
#define METAL__DRIVERS__SIFIVE_GPIO_BUTTONS_H
-#include
#include
#include
+#include
struct __metal_driver_vtable_sifive_button {
- struct metal_button_vtable button_vtable;
+ struct metal_button_vtable button_vtable;
};
__METAL_DECLARE_VTABLE(__metal_driver_vtable_sifive_button)
diff --git a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-leds.h b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-leds.h
index a8dacf116..abfca01c2 100644
--- a/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-leds.h
+++ b/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/install/include/metal/drivers/sifive_gpio-leds.h
@@ -4,12 +4,12 @@
#ifndef METAL__DRIVERS__SIFIVE_GPIO_LEDS_H
#define METAL__DRIVERS__SIFIVE_GPIO_LEDS_H
+#include