DanBUK / gentoo-eeepc
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Description: Some files to assit in setting up Gentoo on a eee PC 901
Homepage: http://danb-uk.net/
Clone URL: git://github.com/DanBUK/gentoo-eeepc.git
gentoo-eeepc / kernel / atl2-2.6.26-4.patch
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73e74fbf » DanBUK 2008-11-12 Updated to work with 2.6.27 1 --- a/drivers/net/Kconfig 2008-11-12 14:08:55.000000000 +0000
2 +++ b/drivers/net/Kconfig 2008-11-12 14:12:34.000000000 +0000
3 @@ -1840,6 +1840,17 @@
4 Say Y here if you want to use the NE2000 compatible
5 controller on the Renesas H8/300 processor.
aa31a1c6 » DanBUK 2008-11-12 Original version from http:... 6
7 +config ATL2
73e74fbf » DanBUK 2008-11-12 Updated to work with 2.6.27 8 + tristate "Atheros L2 Fast Ethernet support"
9 + depends on PCI
10 + select CRC32
11 + select MII
12 + help
13 + This driver supports the Atheros L2 fast ethernet adapter.
aa31a1c6 » DanBUK 2008-11-12 Original version from http:... 14 +
73e74fbf » DanBUK 2008-11-12 Updated to work with 2.6.27 15 + To compile this driver as a module, choose M here. The module
16 + will be called atl2.
aa31a1c6 » DanBUK 2008-11-12 Original version from http:... 17 +
18 source "drivers/net/fs_enet/Kconfig"
19
73e74fbf » DanBUK 2008-11-12 Updated to work with 2.6.27 20 endif # NET_ETHERNET
21 --- a/drivers/net/Makefile 2008-11-12 14:17:09.000000000 +0000
22 +++ b/drivers/net/Makefile 2008-11-12 14:17:48.000000000 +0000
23 @@ -16,6 +16,7 @@
aa31a1c6 » DanBUK 2008-11-12 Original version from http:... 24 obj-$(CONFIG_BONDING) += bonding/
25 obj-$(CONFIG_ATL1) += atlx/
73e74fbf » DanBUK 2008-11-12 Updated to work with 2.6.27 26 obj-$(CONFIG_ATL1E) += atl1e/
aa31a1c6 » DanBUK 2008-11-12 Original version from http:... 27 +obj-$(CONFIG_ATL2) += atlx/
28 obj-$(CONFIG_GIANFAR) += gianfar_driver.o
29 obj-$(CONFIG_TEHUTI) += tehuti.o
73e74fbf » DanBUK 2008-11-12 Updated to work with 2.6.27 30
aa31a1c6 » DanBUK 2008-11-12 Original version from http:... 31 diff --git a/drivers/net/atlx/Makefile b/drivers/net/atlx/Makefile
32 index ca45553..e546aba 100644
33 --- a/drivers/net/atlx/Makefile
34 +++ b/drivers/net/atlx/Makefile
35 @@ -1 +1,2 @@
36 obj-$(CONFIG_ATL1) += atl1.o
37 +obj-$(CONFIG_ATL2) += atl2.o
38 diff --git a/drivers/net/atlx/atl2.c b/drivers/net/atlx/atl2.c
39 new file mode 100644
40 index 0000000..0a6b618
41 --- /dev/null
42 +++ b/drivers/net/atlx/atl2.c
43 @@ -0,0 +1,3167 @@
44 +/*
45 + * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
46 + * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
47 + *
48 + * Derived from Intel e1000 driver
49 + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
50 + *
51 + * This program is free software; you can redistribute it and/or modify it
52 + * under the terms of the GNU General Public License as published by the Free
53 + * Software Foundation; either version 2 of the License, or (at your option)
54 + * any later version.
55 + *
56 + * This program is distributed in the hope that it will be useful, but WITHOUT
57 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
58 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
59 + * more details.
60 + *
61 + * You should have received a copy of the GNU General Public License along with
62 + * this program; if not, write to the Free Software Foundation, Inc., 59
63 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
64 + */
65 +
66 +#include <asm/atomic.h>
67 +#include <linux/crc32.h>
68 +#include <linux/dma-mapping.h>
69 +#include <linux/etherdevice.h>
70 +#include <linux/ethtool.h>
71 +#include <linux/hardirq.h>
72 +#include <linux/if_vlan.h>
73 +#include <linux/in.h>
74 +#include <linux/interrupt.h>
75 +#include <linux/ip.h>
76 +#include <linux/irqflags.h>
77 +#include <linux/irqreturn.h>
78 +#include <linux/mii.h>
79 +#include <linux/net.h>
80 +#include <linux/netdevice.h>
81 +#include <linux/pci.h>
82 +#include <linux/pci_ids.h>
83 +#include <linux/pm.h>
84 +#include <linux/skbuff.h>
85 +#include <linux/spinlock.h>
86 +#include <linux/string.h>
87 +#include <linux/tcp.h>
88 +#include <linux/timer.h>
89 +#include <linux/types.h>
90 +#include <linux/workqueue.h>
91 +
92 +#include "atl2.h"
93 +
94 +#define ATL2_DRV_VERSION "2.2.3"
95 +
96 +char atl2_driver_name[] = "atl2";
97 +static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
98 +static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
99 +char atl2_driver_version[] = ATL2_DRV_VERSION;
100 +
101 +MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
102 +MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
103 +MODULE_LICENSE("GPL");
104 +MODULE_VERSION(ATL2_DRV_VERSION);
105 +
106 +/*
107 + * atl2_pci_tbl - PCI Device ID Table
108 + */
109 +static struct pci_device_id atl2_pci_tbl[] = {
110 + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
111 + /* required last entry */
112 + {0,}
113 +};
114 +MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
115 +
116 +void atl2_set_ethtool_ops(struct net_device *netdev);
117 +#ifdef ETHTOOL_OPS_COMPAT
118 +extern int ethtool_ioctl(struct ifreq *ifr);
119 +#endif
120 +
121 +#define COPYBREAK_DEFAULT 256
122 +static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
123 +module_param(copybreak, uint, 0644);
124 +MODULE_PARM_DESC(copybreak, "Maximum size of packet that is copied to a new buffer on receive");
125 +
126 +void atl2_check_options(struct atl2_adapter *adapter);
127 +#ifdef SIOCDEVPRIVATE
128 +int atl2_priv_ioctl(struct net_device* netdev, struct ifreq* ifr);
129 +#endif
130 +
131 +/*
132 + * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
133 + * @adapter: board private structure to initialize
134 + *
135 + * atl2_sw_init initializes the Adapter private data structure.
136 + * Fields are initialized based on PCI device information and
137 + * OS network device settings (MTU size).
138 + */
139 +static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
140 +{
141 + struct atl2_hw *hw = &adapter->hw;
142 + struct pci_dev *pdev = adapter->pdev;
143 +
144 + /* PCI config space info */
145 + hw->vendor_id = pdev->vendor;
146 + hw->device_id = pdev->device;
147 + hw->subsystem_vendor_id = pdev->subsystem_vendor;
148 + hw->subsystem_id = pdev->subsystem_device;
149 +
150 + pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
151 + pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
152 +
153 + adapter->wol = 0;
154 + adapter->ict = 50000; // 100ms
155 + adapter->link_speed = SPEED_0; // hardware init
156 + adapter->link_duplex = FULL_DUPLEX;
157 +
158 + hw->phy_configured = false;
159 + hw->preamble_len = 7;
160 + hw->ipgt = 0x60;
161 + hw->min_ifg = 0x50;
162 + hw->ipgr1 = 0x40;
163 + hw->ipgr2 = 0x60;
164 + hw->retry_buf = 2;
165 + hw->max_retry = 0xf;
166 + hw->lcol = 0x37;
167 + hw->jam_ipg = 7;
168 + hw->fc_rxd_hi = 0;
169 + hw->fc_rxd_lo = 0;
170 + hw->max_frame_size = adapter->netdev->mtu;
171 +
172 + spin_lock_init(&adapter->stats_lock);
173 + spin_lock_init(&adapter->tx_lock);
174 +
175 + set_bit(__ATL2_DOWN, &adapter->flags);
176 +
177 + return 0;
178 +}
179 +
180 +/*
181 + * atl2_set_multi - Multicast and Promiscuous mode set
182 + * @netdev: network interface device structure
183 + *
184 + * The set_multi entry point is called whenever the multicast address
185 + * list or the network interface flags are updated. This routine is
186 + * responsible for configuring the hardware for proper multicast,
187 + * promiscuous mode, and all-multi behavior.
188 + */
189 +static void atl2_set_multi(struct net_device *netdev)
190 +{
191 + struct atl2_adapter *adapter = netdev_priv(netdev);
192 + struct atl2_hw *hw = &adapter->hw;
193 + struct dev_mc_list *mc_ptr;
194 + u32 rctl;
195 + u32 hash_value;
196 +
197 + /* Check for Promiscuous and All Multicast modes */
198 + rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
199 +
200 + if(netdev->flags & IFF_PROMISC) {
201 + rctl |= MAC_CTRL_PROMIS_EN;
202 + } else if(netdev->flags & IFF_ALLMULTI) {
203 + rctl |= MAC_CTRL_MC_ALL_EN;
204 + rctl &= ~MAC_CTRL_PROMIS_EN;
205 + } else {
206 + rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
207 + }
208 +
209 + ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
210 +
211 + /* clear the old settings from the multicast hash table */
212 + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
213 + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
214 +
215 + /* comoute mc addresses' hash value ,and put it into hash table */
216 + for(mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
217 + hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
218 + atl2_hash_set(hw, hash_value);
219 + }
220 +}
221 +
222 +static void init_ring_ptrs(struct atl2_adapter *adapter)
223 +{
224 + // Read / Write Ptr Initialize:
225 + adapter->txd_write_ptr = 0;
226 + atomic_set(&adapter->txd_read_ptr, 0);
227 +
228 + adapter->rxd_read_ptr = 0;
229 + adapter->rxd_write_ptr = 0;
230 +
231 + atomic_set(&adapter->txs_write_ptr, 0);
232 + adapter->txs_next_clear = 0;
233 +}
234 +
235 +/*
236 + * atl2_configure - Configure Transmit&Receive Unit after Reset
237 + * @adapter: board private structure
238 + *
239 + * Configure the Tx /Rx unit of the MAC after a reset.
240 + */
241 +static int atl2_configure(struct atl2_adapter *adapter)
242 +{
243 + struct atl2_hw * hw = &adapter->hw;
244 + u32 value;
245 +
246 + // clear interrupt status
247 + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
248 +
249 + // set MAC Address
250 + value = (((u32)hw->mac_addr[2]) << 24) |
251 + (((u32)hw->mac_addr[3]) << 16) |
252 + (((u32)hw->mac_addr[4]) << 8 ) |
253 + (((u32)hw->mac_addr[5]) ) ;
254 + ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
255 + value = (((u32)hw->mac_addr[0]) << 8 ) |
256 + (((u32)hw->mac_addr[1]) ) ;
257 + ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
258 +
259 + // HI base address
260 + ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
261 + (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
262 +
263 + // LO base address
264 + ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
265 + (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
266 + ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
267 + (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
268 + ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
269 + (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
270 +
271 + // element count
272 + ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
273 + ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
274 + ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
275 +
276 + /* config Internal SRAM */
277 +/*
278 + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
279 + ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
280 +*/
281 +
282 + /* config IPG/IFG */
283 + value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << MAC_IPG_IFG_IPGT_SHIFT) |
284 + (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << MAC_IPG_IFG_MIFG_SHIFT) |
285 + (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << MAC_IPG_IFG_IPGR1_SHIFT)|
286 + (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << MAC_IPG_IFG_IPGR2_SHIFT);
287 + ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
288 +
289 + /* config Half-Duplex Control */
290 + value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
291 + (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
292 + MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
293 + MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
294 + (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
295 + (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
296 + MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
297 + ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
298 +
299 + /* set Interrupt Moderator Timer */
300 + ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
301 + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
302 +
303 + /* set Interrupt Clear Timer */
304 + ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
305 +
306 + /* set MTU */
307 + ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
308 + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
309 +
310 + /* 1590 */
311 + ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
312 +
313 + /* flow control */
314 + ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
315 + ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
316 +
317 + /* Init mailbox */
318 + ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
319 + ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
320 +
321 + /* enable DMA read/write */
322 + ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
323 + ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
324 +
325 + value = ATL2_READ_REG(&adapter->hw, REG_ISR);
326 + if ((value & ISR_PHY_LINKDOWN) != 0) {
327 + value = 1; // config failed
328 + } else {
329 + value = 0;
330 + }
331 +
332 + // clear all interrupt status
333 + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
334 + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
335 + return value;
336 +}
337 +
338 +/*
339 + * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
340 + * @adapter: board private structure
341 + *
342 + * Return 0 on success, negative on failure
343 + */
344 +static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
345 +{
346 + struct pci_dev *pdev = adapter->pdev;
347 + int size;
348 + u8 offset = 0;
349 +
350 + /* real ring DMA buffer */
351 + adapter->ring_size = size =
352 + adapter->txd_ring_size * 1 + 7 + // dword align
353 + adapter->txs_ring_size * 4 + 7 + // dword align
354 + adapter->rxd_ring_size * 1536 + 127; // 128bytes align
355 +
356 + adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, &adapter->ring_dma);
357 + if (!adapter->ring_vir_addr) {
358 + return -ENOMEM;
359 + }
360 +#if 0
361 + if (adapter->pci_using_64) {
362 + // test whether HIDWORD dma buffer is not cross boundary
363 + if ( ((adapter->ring_dma &0xffffffff00000000ULL)>>32)
364 + != (((adapter->ring_dma+size)&0xffffffff00000000ULL)>>32) ) {
365 + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, adapter->ring_dma);
366 + DEBUGOUT("memory allocated cross 32bit boundary !");
367 + return -ENOMEM;
368 + }
369 + }
370 +#endif
371 + memset(adapter->ring_vir_addr, 0, adapter->ring_size);
372 +
373 + // Init TXD Ring
374 + adapter->txd_dma = adapter->ring_dma ;
375 + offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
376 + adapter->txd_dma += offset;
377 + adapter->txd_ring = (tx_pkt_header_t*) (adapter->ring_vir_addr + offset);
378 +
379 + // Init TXS Ring
380 + adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
381 + offset = (adapter->txs_dma & 0x7) ? (8- (adapter->txs_dma & 0x7)) : 0;
382 + adapter->txs_dma += offset;
383 + adapter->txs_ring = (tx_pkt_status_t*)
384 + (((u8*)adapter->txd_ring) + (adapter->txd_ring_size+offset));
385 +
386 + // Init RXD Ring
387 + adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size*4;
388 + offset = (adapter->rxd_dma & 127) ? (128 - (adapter->rxd_dma & 127)) : 0;
389 + if (offset > 7) {
390 + offset -= 8;
391 + } else {
392 + offset += (128 - 8);
393 + }
394 + adapter->rxd_dma += offset;
395 + adapter->rxd_ring = (rx_desc_t*) (((u8*)adapter->txs_ring) +
396 + (adapter->txs_ring_size*4 + offset));
397 +
398 +// Read / Write Ptr Initialize:
399 +// init_ring_ptrs(adapter);
400 +
401 + return ATL2_SUCCESS;
402 +}
403 +
404 +/*
405 + * atl2_irq_enable - Enable default interrupt generation settings
406 + * @adapter: board private structure
407 + */
408 +static inline void atl2_irq_enable(struct atl2_adapter *adapter)
409 +{
410 + ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
411 + ATL2_WRITE_FLUSH(&adapter->hw);
412 +}
413 +
414 +/*
415 + * atl2_irq_disable - Mask off interrupt generation on the NIC
416 + * @adapter: board private structure
417 + */
418 +static inline void atl2_irq_disable(struct atl2_adapter *adapter)
419 +{
420 + ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
421 + ATL2_WRITE_FLUSH(&adapter->hw);
422 + synchronize_irq(adapter->pdev->irq);
423 +}
424 +
425 +#ifdef NETIF_F_HW_VLAN_TX
426 +static void atl2_vlan_rx_register(struct net_device *netdev,
427 + struct vlan_group *grp)
428 +{
429 + struct atl2_adapter *adapter = netdev_priv(netdev);
430 + u32 ctrl;
431 +
432 + atl2_irq_disable(adapter);
433 + adapter->vlgrp = grp;
434 +
435 + if(grp) {
436 + /* enable VLAN tag insert/strip */
437 + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
438 + ctrl |= MAC_CTRL_RMV_VLAN;
439 + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
440 + } else {
441 + /* disable VLAN tag insert/strip */
442 + ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
443 + ctrl &= ~MAC_CTRL_RMV_VLAN;
444 + ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
445 + }
446 +
447 + atl2_irq_enable(adapter);
448 +}
449 +
450 +static void atl2_restore_vlan(struct atl2_adapter *adapter)
451 +{
452 + atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
453 +}
454 +#endif
455 +
456 +static void atl2_intr_rx(struct atl2_adapter* adapter)
457 +{
458 + struct net_device *netdev = adapter->netdev;
459 + rx_desc_t* rxd;
460 + struct sk_buff* skb;
461 +
462 + do {
463 + rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
464 + if (!rxd->status.update)
465 + break; // end of tx
466 +
467 + // clear this flag at once
468 + rxd->status.update = 0;
469 +
470 + if (rxd->status.ok && rxd->status.pkt_size >= 60) {
471 + int rx_size = (int)(rxd->status.pkt_size - 4);
472 + // alloc new buffer
473 + skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
474 + if (NULL == skb) {
475 + printk(KERN_WARNING"%s: Memory squeeze, deferring packet.\n",
476 + netdev->name);
477 + /* We should check that some rx space is free.
478 + * If not, free one and mark stats->rx_dropped++. */
479 + adapter->net_stats.rx_dropped++;
480 + break;
481 + }
482 +/* FIXME: ???
483 + if (rx_size > 1400) {
484 + int s,c;
485 + c = 0;
486 + printk("rx_size= %d\n", rx_size);
487 + for (s=0; s < 800; s++) {
488 + if (0 == c) {
489 + printk("%04x ", s);
490 + }
491 + printk("%02x ", rxd->packet[s]);
492 + if (++c == 16) {
493 + c = 0;
494 + printk("\n");
495 + }
496 + }
497 + printk(KERN_WARNING"\n");
498 + }
499 +*/
500 + skb_reserve(skb, NET_IP_ALIGN);
501 + skb->dev = netdev;
502 +/* gone in 2.6.23, just use memcpy? -- CHS
503 + eth_copy_and_sum(skb, rxd->packet, rx_size, 0); */
504 + memcpy(skb->data, rxd->packet, rx_size); /* totally untested -- CHS */
505 + skb_put(skb, rx_size);
506 + /* FIXME ???
507 + memcpy(skb_put(skb, rx_size),
508 + rxd->packet,
509 + rx_size);
510 + */
511 + skb->protocol = eth_type_trans(skb, netdev);
512 +#ifdef NETIF_F_HW_VLAN_TX
513 + if(adapter->vlgrp && (rxd->status.vlan)) {
514 + u16 vlan_tag = (rxd->status.vtag>>4) |
515 + ((rxd->status.vtag&7) << 13) |
516 + ((rxd->status.vtag&8) << 9);
517 + vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
518 + } else
519 +#endif
520 + netif_rx(skb);
521 + adapter->net_stats.rx_bytes += rx_size;
522 + adapter->net_stats.rx_packets++;
523 + netdev->last_rx = jiffies;
524 + } else {
525 + adapter->net_stats.rx_errors++;
526 +
527 + if (rxd->status.ok && rxd->status.pkt_size <= 60) {
528 + adapter->net_stats.rx_length_errors++;
529 + }
530 + if (rxd->status.mcast) adapter->net_stats.multicast++;
531 + if (rxd->status.crc) adapter->net_stats.rx_crc_errors++;
532 + if (rxd->status.align) adapter->net_stats.rx_frame_errors++;
533 + }
534 +
535 + // advance write ptr
536 + if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
537 + adapter->rxd_write_ptr = 0;
538 + } while (1);
539 +
540 + // update mailbox ?
541 + adapter->rxd_read_ptr = adapter->rxd_write_ptr;
542 + ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
543 +}
544 +
545 +static void atl2_intr_tx(struct atl2_adapter* adapter)
546 +{
547 + u32 txd_read_ptr;
548 + u32 txs_write_ptr;
549 + tx_pkt_status_t* txs;
550 + tx_pkt_header_t* txph;
551 + int free_hole = 0;
552 +
553 + do {
554 + txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
555 + txs = adapter->txs_ring + txs_write_ptr;
556 + if (!txs->update)
557 + break; // tx stop here
558 +
559 + free_hole = 1;
560 + txs->update = 0;
561 +
562 + if (++txs_write_ptr == adapter->txs_ring_size)
563 + txs_write_ptr = 0;
564 + atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
565 +
566 + txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
567 + txph = (tx_pkt_header_t*) (((u8*)adapter->txd_ring) + txd_read_ptr);
568 +
569 + if ( txph->pkt_size != txs->pkt_size) {
570 + tx_pkt_status_t* old_txs = txs;
571 + printk(KERN_WARNING
572 + "%s: txs packet size do not coinsist with txd"
573 + " txd_:0x%08x, txs_:0x%08x!\n",
574 + adapter->netdev->name,
575 + *(u32*)txph, *(u32*)txs);
576 + printk(KERN_WARNING
577 + "txd read ptr: 0x%x\n",
578 + txd_read_ptr);
579 + txs = adapter->txs_ring + txs_write_ptr;
580 + printk(KERN_WARNING
581 + "txs-behind:0x%08x\n",
582 + *(u32*)txs);
583 + if (txs_write_ptr < 2) {
584 + txs = adapter->txs_ring +
585 + (adapter->txs_ring_size +
586 + txs_write_ptr - 2);
587 + } else {
588 + txs = adapter->txs_ring + (txs_write_ptr - 2);
589 + }
590 + printk(KERN_WARNING
591 + "txs-before:0x%08x\n",
592 + *(u32*)txs);
593 + txs = old_txs;
594 + }
595 +
596 + txd_read_ptr += (((u32)(txph->pkt_size)+7)& ~3);//4for TPH
597 + if (txd_read_ptr >= adapter->txd_ring_size)
598 + txd_read_ptr -= adapter->txd_ring_size;
599 +
600 + atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
601 +
602 + // tx statistics:
603 + if (txs->ok)
604 + adapter->net_stats.tx_packets++;
605 + else
606 + adapter->net_stats.tx_errors++;
607 +
608 + if (txs->defer) adapter->net_stats.collisions++;
609 + if (txs->abort_col) adapter->net_stats.tx_aborted_errors++;
610 + if (txs->late_col) adapter->net_stats.tx_window_errors++;
611 + if (txs->underun) adapter->net_stats.tx_fifo_errors++;
612 + } while (1);
613 +
614 + if (free_hole) {
615 + if(netif_queue_stopped(adapter->netdev) &&
616 + netif_carrier_ok(adapter->netdev))
617 + netif_wake_queue(adapter->netdev);
618 + }
619 +}
620 +
621 +static void atl2_check_for_link(struct atl2_adapter* adapter)
622 +{
623 + struct net_device *netdev = adapter->netdev;
624 + u16 phy_data = 0;
625 +
626 + spin_lock(&adapter->stats_lock);
627 + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
628 + atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
629 + spin_unlock(&adapter->stats_lock);
630 +
631 + // notify upper layer link down ASAP
632 + if (!(phy_data & BMSR_LSTATUS)) { // Link Down
633 + if (netif_carrier_ok(netdev)) { // old link state: Up
634 + printk(KERN_INFO "%s: %s NIC Link is Down\n",
635 + atl2_driver_name, netdev->name);
636 + adapter->link_speed = SPEED_0;
637 + netif_carrier_off(netdev);
638 + netif_stop_queue(netdev);
639 + }
640 + }
641 + schedule_work(&adapter->link_chg_task);
642 +}
643 +
644 +static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
645 +{
646 + u16 phy_data;
647 + spin_lock(&adapter->stats_lock);
648 + atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
649 + spin_unlock(&adapter->stats_lock);
650 +}
651 +
652 +/*
653 + * atl2_intr - Interrupt Handler
654 + * @irq: interrupt number
655 + * @data: pointer to a network interface device structure
656 + * @pt_regs: CPU registers structure
657 + */
658 +static irqreturn_t atl2_intr(int irq, void *data)
659 +{
660 + struct atl2_adapter *adapter = netdev_priv(data);
661 + struct atl2_hw *hw = &adapter->hw;
662 + u32 status;
663 +
664 + status = ATL2_READ_REG(hw, REG_ISR);
665 + if (0 == status)
666 + return IRQ_NONE;
667 +
668 + // link event
669 + if (status & ISR_PHY) {
670 + atl2_clear_phy_int(adapter);
671 + }
672 +
673 + // clear ISR status, and Enable CMB DMA/Disable Interrupt
674 + ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
675 +
676 + // FIXME: if PCIe link is down, how did we read the register? -- CHS
677 + // check if PCIE PHY Link down
678 + if (status & ISR_PHY_LINKDOWN) {
679 + if(netif_running(adapter->netdev)) { // reset MAC
680 + ATL2_WRITE_REG(hw, REG_ISR, 0);
681 + ATL2_WRITE_REG(hw, REG_IMR, 0);
682 + ATL2_WRITE_FLUSH(hw);
683 + schedule_work(&adapter->reset_task);
684 + return IRQ_HANDLED;
685 + }
686 + }
687 +
688 + // check if DMA read/write error ?
689 + if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST))
690 + {
691 + //ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
692 + ATL2_WRITE_REG(hw, REG_ISR, 0);
693 + ATL2_WRITE_REG(hw, REG_IMR, 0);
694 + ATL2_WRITE_FLUSH(hw);
695 + schedule_work(&adapter->reset_task);
696 + return IRQ_HANDLED;
697 + }
698 +
699 + // link event
700 + if (status & (ISR_PHY | ISR_MANUAL))
701 + {
702 + adapter->net_stats.tx_carrier_errors++;
703 + atl2_check_for_link(adapter);
704 + }
705 +
706 + // transmit event
707 + if (status & ISR_TX_EVENT) {
708 + atl2_intr_tx(adapter);
709 + }
710 +
711 + // rx exception
712 + if (status & ISR_RX_EVENT) {
713 + atl2_intr_rx(adapter);
714 + }
715 +
716 + // re-enable Interrupt
717 + ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
718 + return IRQ_HANDLED;
719 +}
720 +
721 +static int atl2_request_irq(struct atl2_adapter *adapter)
722 +{
723 + struct net_device *netdev = adapter->netdev;
724 + int flags, err = 0;
725 +
726 + flags = IRQF_SHARED;
727 +#ifdef CONFIG_PCI_MSI
728 + adapter->have_msi = true;
729 + if ((err = pci_enable_msi(adapter->pdev)))
730 + adapter->have_msi = false;
731 +
732 + if (adapter->have_msi)
733 + flags &= ~IRQF_SHARED;
734 +#endif
735 +
736 + return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name, netdev);
737 +}
738 +
739 +/*
740 + * atl2_free_ring_resources - Free Tx / RX descriptor Resources
741 + * @adapter: board private structure
742 + *
743 + * Free all transmit software resources
744 + */
745 +static void atl2_free_ring_resources(struct atl2_adapter *adapter)
746 +{
747 + struct pci_dev *pdev = adapter->pdev;
748 + pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, adapter->ring_dma);
749 +}
750 +
751 +/*
752 + * atl2_open - Called when a network interface is made active
753 + * @netdev: network interface device structure
754 + *
755 + * Returns 0 on success, negative value on failure
756 + *
757 + * The open entry point is called when a network interface is made
758 + * active by the system (IFF_UP). At this point all resources needed
759 + * for transmit and receive operations are allocated, the interrupt
760 + * handler is registered with the OS, the watchdog timer is started,
761 + * and the stack is notified that the interface is ready.
762 + */
763 +static int atl2_open(struct net_device *netdev)
764 +{
765 + struct atl2_adapter *adapter = netdev_priv(netdev);
766 + int err;
767 + u32 val;
768 +
769 + /* disallow open during test */
770 + if (test_bit(__ATL2_TESTING, &adapter->flags))
771 + return -EBUSY;
772 +
773 + /* allocate transmit descriptors */
774 + if((err = atl2_setup_ring_resources(adapter)))
775 + return err;
776 +
777 + if((err = atl2_init_hw(&adapter->hw))) {
778 + err = -EIO;
779 + goto err_init_hw;
780 + }
781 +
782 + /* hardware has been reset, we need to reload some things */
783 + atl2_set_multi(netdev);
784 + init_ring_ptrs(adapter);
785 +
786 +#ifdef NETIF_F_HW_VLAN_TX
787 + atl2_restore_vlan(adapter);
788 +#endif
789 +
790 + if (atl2_configure(adapter)) {
791 + err = -EIO;
792 + goto err_config;
793 + }
794 +
795 + if ((err = atl2_request_irq(adapter)))
796 + goto err_req_irq;
797 +
798 + clear_bit(__ATL2_DOWN, &adapter->flags);
799 +
800 + mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ);
801 +
802 + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
803 + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | MASTER_CTRL_MANUAL_INT);
804 +
805 + atl2_irq_enable(adapter);
806 +
807 + return 0;
808 +
809 +err_init_hw:
810 +err_req_irq:
811 +err_config:
812 + atl2_free_ring_resources(adapter);
813 + atl2_reset_hw(&adapter->hw);
814 +
815 + return err;
816 +}
817 +
818 +void atl2_down(struct atl2_adapter *adapter)
819 +{
820 + struct net_device *netdev = adapter->netdev;
821 +
822 + /* signal that we're down so the interrupt handler does not
823 + * reschedule our watchdog timer */
824 + set_bit(__ATL2_DOWN, &adapter->flags);
825 +
826 +#ifdef NETIF_F_LLTX
827 + netif_stop_queue(netdev);
828 +#else
829 + netif_tx_disable(netdev);
830 +#endif
831 +
832 + /* reset MAC to disable all RX/TX */
833 + atl2_reset_hw(&adapter->hw);
834 + msleep(1);
835 +
836 + atl2_irq_disable(adapter);
837 +
838 + del_timer_sync(&adapter->watchdog_timer);
839 + del_timer_sync(&adapter->phy_config_timer);
840 + clear_bit(0, &adapter->cfg_phy);
841 +
842 + netif_carrier_off(netdev);
843 + adapter->link_speed = SPEED_0;
844 + adapter->link_duplex = -1;
845 +
846 +// atl2_reset(adapter);
847 +}
848 +
849 +static void atl2_free_irq(struct atl2_adapter *adapter)
850 +{
851 + struct net_device *netdev = adapter->netdev;
852 +
853 + free_irq(adapter->pdev->irq, netdev);
854 +
855 +#ifdef CONFIG_PCI_MSI
856 + if (adapter->have_msi)
857 + pci_disable_msi(adapter->pdev);
858 +#endif
859 +}
860 +
861 +/*
862 + * atl2_close - Disables a network interface
863 + * @netdev: network interface device structure
864 + *
865 + * Returns 0, this is not allowed to fail
866 + *
867 + * The close entry point is called when an interface is de-activated
868 + * by the OS. The hardware is still under the drivers control, but
869 + * needs to be disabled. A global MAC reset is issued to stop the
870 + * hardware, and all transmit and receive resources are freed.
871 + */
872 +static int atl2_close(struct net_device *netdev)
873 +{
874 + struct atl2_adapter *adapter = netdev_priv(netdev);
875 +
876 + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
877 +
878 + atl2_down(adapter);
879 + atl2_free_irq(adapter);
880 + atl2_free_ring_resources(adapter);
881 +
882 + return 0;
883 +}
884 +
885 +static inline int TxsFreeUnit(struct atl2_adapter *adapter)
886 +{
887 + u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
888 +
889 + return (adapter->txs_next_clear >= txs_write_ptr) ?
890 + (int) (adapter->txs_ring_size - adapter->txs_next_clear +
891 + txs_write_ptr - 1) :
892 + (int) (txs_write_ptr - adapter->txs_next_clear - 1);
893 +}
894 +
895 +static inline int TxdFreeBytes(struct atl2_adapter *adapter)
896 +{
897 + u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
898 +
899 + return (adapter->txd_write_ptr >= txd_read_ptr) ?
900 + (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
901 + txd_read_ptr - 1):
902 + (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
903 +}
904 +
905 +static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
906 +{
907 + struct atl2_adapter *adapter = netdev_priv(netdev);
908 + unsigned long flags;
909 + tx_pkt_header_t* txph;
910 + u32 offset, copy_len;
911 + int txs_unused;
912 + int txbuf_unused;
913 +
914 + if (test_bit(__ATL2_DOWN, &adapter->flags)) {
915 + dev_kfree_skb_any(skb);
916 + return NETDEV_TX_OK;
917 + }
918 +
919 + if (unlikely(skb->len <= 0)) {
920 + dev_kfree_skb_any(skb);
921 + return NETDEV_TX_OK;
922 + }
923 +
924 +#ifdef NETIF_F_LLTX
925 + local_irq_save(flags);
926 + if (!spin_trylock(&adapter->tx_lock)) {
927 + /* Collision - tell upper layer to requeue */
928 + local_irq_restore(flags);
929 + return NETDEV_TX_LOCKED;
930 + }
931 +#else
932 + spin_lock_irqsave(&adapter->tx_lock, flags);
933 +#endif
934 + txs_unused = TxsFreeUnit(adapter);
935 + txbuf_unused = TxdFreeBytes(adapter);
936 +
937 + if (txs_unused < 1 || skb->len > txbuf_unused) {
938 + // no enough resource
939 + netif_stop_queue(netdev);
940 + spin_unlock_irqrestore(&adapter->tx_lock, flags);
941 + return NETDEV_TX_BUSY;
942 + }
943 +
944 + offset = adapter->txd_write_ptr;
945 +
946 + txph = (tx_pkt_header_t*) (((u8*)adapter->txd_ring)+offset);
947 +
948 + *(u32*)txph = 0;
949 + txph->pkt_size = skb->len;
950 +
951 + offset += 4;
952 + if (offset >= adapter->txd_ring_size)
953 + offset -= adapter->txd_ring_size;
954 + copy_len = adapter->txd_ring_size - offset;
955 + if (copy_len >= skb->len) {
956 + memcpy(((u8*)adapter->txd_ring)+offset, skb->data, skb->len);
957 + offset += ((u32)(skb->len+3)&~3);
958 + } else {
959 + memcpy(((u8*)adapter->txd_ring)+offset, skb->data, copy_len);
960 + memcpy((u8*)adapter->txd_ring, skb->data+copy_len, skb->len-copy_len);
961 + offset = ((u32)(skb->len-copy_len+3)&~3);
962 + }
963 +#ifdef NETIF_F_HW_VLAN_TX
964 + if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
965 + u16 vlan_tag = vlan_tx_tag_get(skb);
966 + vlan_tag = (vlan_tag << 4) |
967 + (vlan_tag >> 13) |
968 + ((vlan_tag >>9) & 0x8);
969 + txph->ins_vlan = 1;
970 + txph->vlan = vlan_tag;
971 + }
972 +#endif
973 + if (offset >= adapter->txd_ring_size)
974 + offset -= adapter->txd_ring_size;
975 + adapter->txd_write_ptr = offset;
976 +
977 + // clear txs before send
978 + adapter->txs_ring[adapter->txs_next_clear].update = 0;
979 + if (++adapter->txs_next_clear == adapter->txs_ring_size)
980 + adapter->txs_next_clear = 0;
981 +
982 + ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, (adapter->txd_write_ptr >> 2));
983 +
984 + spin_unlock_irqrestore(&adapter->tx_lock, flags);
985 +
986 + netdev->trans_start = jiffies;
987 + dev_kfree_skb_any(skb);
988 + return NETDEV_TX_OK;
989 +}
990 +
991 +/*
992 + * atl2_get_stats - Get System Network Statistics
993 + * @netdev: network interface device structure
994 + *
995 + * Returns the address of the device statistics structure.
996 + * The statistics are actually updated from the timer callback.
997 + */
998 +static struct net_device_stats * atl2_get_stats(struct net_device *netdev)
999 +{
1000 + struct atl2_adapter *adapter = netdev_priv(netdev);
1001 +
1002 + return &adapter->net_stats;
1003 +}
1004 +
1005 +/*
1006 + * atl2_change_mtu - Change the Maximum Transfer Unit
1007 + * @netdev: network interface device structure
1008 + * @new_mtu: new value for maximum frame size
1009 + *
1010 + * Returns 0 on success, negative on failure
1011 + */
1012 +static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
1013 +{
1014 + struct atl2_adapter *adapter = netdev_priv(netdev);
1015 + struct atl2_hw *hw = &adapter->hw;
1016 +
1017 + if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
1018 + return -EINVAL;
1019 +
1020 + /* set MTU */
1021 + if (hw->max_frame_size != new_mtu) {
1022 +// while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1023 +// msleep(1);
1024 + netdev->mtu = new_mtu;
1025 +
1026 + ATL2_WRITE_REG(hw, REG_MTU,
1027 + new_mtu + ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
1028 +// clear_bit(__ATL2_RESETTING, &adapter->flags);
1029 + }
1030 +
1031 + return 0;
1032 +}
1033 +
1034 +/*
1035 + * atl2_set_mac - Change the Ethernet Address of the NIC
1036 + * @netdev: network interface device structure
1037 + * @p: pointer to an address structure
1038 + *
1039 + * Returns 0 on success, negative on failure
1040 + */
1041 +static int atl2_set_mac(struct net_device *netdev, void *p)
1042 +{
1043 + struct atl2_adapter *adapter = netdev_priv(netdev);
1044 + struct sockaddr *addr = p;
1045 +
1046 + if (!is_valid_ether_addr(addr->sa_data))
1047 + return -EADDRNOTAVAIL;
1048 +
1049 + if (netif_running(netdev))
1050 + return -EBUSY;
1051 +
1052 + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1053 + memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
1054 +
1055 + atl2_set_mac_addr(&adapter->hw);
1056 +
1057 + return 0;
1058 +}
1059 +
1060 +/*
1061 + * atl2_mii_ioctl -
1062 + * @netdev:
1063 + * @ifreq:
1064 + * @cmd:
1065 + */
1066 +static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1067 +{
1068 + struct atl2_adapter *adapter = netdev_priv(netdev);
1069 + struct mii_ioctl_data *data = if_mii(ifr);
1070 + unsigned long flags;
1071 +
1072 + switch (cmd) {
1073 + case SIOCGMIIPHY:
1074 + data->phy_id = 0;
1075 + break;
1076 + case SIOCGMIIREG:
1077 + if (!capable(CAP_NET_ADMIN))
1078 + return -EPERM;
1079 + spin_lock_irqsave(&adapter->stats_lock, flags);
1080 + if (atl2_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, &data->val_out)) {
1081 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1082 + return -EIO;
1083 + }
1084 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1085 + break;
1086 + case SIOCSMIIREG:
1087 + if (!capable(CAP_NET_ADMIN))
1088 + return -EPERM;
1089 + if (data->reg_num & ~(0x1F))
1090 + return -EFAULT;
1091 + spin_lock_irqsave(&adapter->stats_lock, flags);
1092 + if (atl2_write_phy_reg(&adapter->hw, data->reg_num, data->val_in)) {
1093 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1094 + return -EIO;
1095 + }
1096 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1097 + break;
1098 + default:
1099 + return -EOPNOTSUPP;
1100 + }
1101 + return ATL2_SUCCESS;
1102 +}
1103 +
1104 +/*
1105 + * atl2_ioctl -
1106 + * @netdev:
1107 + * @ifreq:
1108 + * @cmd:
1109 + */
1110 +static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1111 +{
1112 + switch (cmd) {
1113 + case SIOCGMIIPHY:
1114 + case SIOCGMIIREG:
1115 + case SIOCSMIIREG:
1116 + return atl2_mii_ioctl(netdev, ifr, cmd);
1117 +#ifdef ETHTOOL_OPS_COMPAT
1118 + case SIOCETHTOOL:
1119 + return ethtool_ioctl(ifr);
1120 +#endif
1121 + default:
1122 + return -EOPNOTSUPP;
1123 + }
1124 +}
1125 +
1126 +/*
1127 + * atl2_tx_timeout - Respond to a Tx Hang
1128 + * @netdev: network interface device structure
1129 + */
1130 +static void atl2_tx_timeout(struct net_device *netdev)
1131 +{
1132 + struct atl2_adapter *adapter = netdev_priv(netdev);
1133 +
1134 + /* Do the reset outside of interrupt context */
1135 + schedule_work(&adapter->reset_task);
1136 +}
1137 +
1138 +/*
1139 + * atl2_watchdog - Timer Call-back
1140 + * @data: pointer to netdev cast into an unsigned long
1141 + */
1142 +static void atl2_watchdog(unsigned long data)
1143 +{
1144 + struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1145 + u32 drop_rxd, drop_rxs;
1146 + unsigned long flags;
1147 +
1148 + if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1149 + spin_lock_irqsave(&adapter->stats_lock, flags);
1150 + drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1151 + drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1152 + adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs);
1153 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1154 +
1155 + /* Reset the timer */
1156 + mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ);
1157 + }
1158 +}
1159 +
1160 +/*
1161 + * atl2_phy_config - Timer Call-back
1162 + * @data: pointer to netdev cast into an unsigned long
1163 + */
1164 +static void atl2_phy_config(unsigned long data)
1165 +{
1166 + struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1167 + struct atl2_hw *hw = &adapter->hw;
1168 + unsigned long flags;
1169 +
1170 + spin_lock_irqsave(&adapter->stats_lock, flags);
1171 + atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1172 + atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET|MII_CR_AUTO_NEG_EN|MII_CR_RESTART_AUTO_NEG);
1173 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1174 + clear_bit(0, &adapter->cfg_phy);
1175 +}
1176 +
1177 +int atl2_up(struct atl2_adapter *adapter)
1178 +{
1179 + struct net_device *netdev = adapter->netdev;
1180 + int err = 0;
1181 + u32 val;
1182 +
1183 + /* hardware has been reset, we need to reload some things */
1184 +
1185 + err = atl2_init_hw(&adapter->hw);
1186 + if (err) {
1187 + err = -EIO;
1188 + return err;
1189 + }
1190 +
1191 + atl2_set_multi(netdev);
1192 + init_ring_ptrs(adapter);
1193 +
1194 +#ifdef NETIF_F_HW_VLAN_TX
1195 + atl2_restore_vlan(adapter);
1196 +#endif
1197 +
1198 + if (atl2_configure(adapter)) {
1199 + err = -EIO;
1200 + goto err_up;
1201 + }
1202 +
1203 + clear_bit(__ATL2_DOWN, &adapter->flags);
1204 +
1205 + val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1206 + ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | MASTER_CTRL_MANUAL_INT);
1207 +
1208 + atl2_irq_enable(adapter);
1209 +
1210 +err_up:
1211 + return err;
1212 +}
1213 +
1214 +void atl2_reinit_locked(struct atl2_adapter *adapter)
1215 +{
1216 + WARN_ON(in_interrupt());
1217 + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1218 + msleep(1);
1219 + atl2_down(adapter);
1220 + atl2_up(adapter);
1221 + clear_bit(__ATL2_RESETTING, &adapter->flags);
1222 +}
1223 +
1224 +static void atl2_reset_task(struct work_struct *work)
1225 +{
1226 + struct atl2_adapter *adapter;
1227 + adapter = container_of(work, struct atl2_adapter, reset_task);
1228 +
1229 + atl2_reinit_locked(adapter);
1230 +}
1231 +
1232 +static inline void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1233 +{
1234 + u32 value;
1235 + struct atl2_hw* hw = &adapter->hw;
1236 + struct net_device* netdev = adapter->netdev;
1237 +
1238 + /* Config MAC CTRL Register */
1239 + value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1240 +
1241 + // duplex
1242 + if (FULL_DUPLEX == adapter->link_duplex)
1243 + value |= MAC_CTRL_DUPLX;
1244 +
1245 + // flow control
1246 + value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1247 +
1248 + // PAD & CRC
1249 + value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1250 +
1251 + // preamble length
1252 + value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1253 + MAC_CTRL_PRMLEN_SHIFT);
1254 +
1255 + // vlan
1256 + if (adapter->vlgrp)
1257 + value |= MAC_CTRL_RMV_VLAN;
1258 +
1259 + // filter mode
1260 + value |= MAC_CTRL_BC_EN;
1261 + if (netdev->flags & IFF_PROMISC)
1262 + value |= MAC_CTRL_PROMIS_EN;
1263 + else if (netdev->flags & IFF_ALLMULTI)
1264 + value |= MAC_CTRL_MC_ALL_EN;
1265 +
1266 + // half retry buffer
1267 + value |= (((u32)(adapter->hw.retry_buf & MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1268 + MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1269 +
1270 + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1271 +}
1272 +
1273 +static int atl2_check_link(struct atl2_adapter *adapter)
1274 +{
1275 + struct atl2_hw *hw = &adapter->hw;
1276 + struct net_device * netdev = adapter->netdev;
1277 + int ret_val;
1278 + u16 speed, duplex, phy_data;
1279 + int reconfig = 0;
1280 +
1281 + // MII_BMSR must read twise
1282 + atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1283 + atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1284 + if (!(phy_data&BMSR_LSTATUS)) { // link down
1285 + if (netif_carrier_ok(netdev)) { // old link state: Up
1286 + u32 value;
1287 + //disable rx
1288 + value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1289 + value &= ~MAC_CTRL_RX_EN;
1290 + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1291 + adapter->link_speed = SPEED_0;
1292 + netif_carrier_off(netdev);
1293 + netif_stop_queue(netdev);
1294 + }
1295 + return ATL2_SUCCESS;
1296 + }
1297 +
1298 + // Link Up
1299 + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1300 + if (ret_val)
1301 + return ret_val;
1302 + switch( hw->MediaType ) {
1303 + case MEDIA_TYPE_100M_FULL:
1304 + if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1305 + reconfig = 1;
1306 + break;
1307 + case MEDIA_TYPE_100M_HALF:
1308 + if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1309 + reconfig = 1;
1310 + break;
1311 + case MEDIA_TYPE_10M_FULL:
1312 + if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1313 + reconfig = 1;
1314 + break;
1315 + case MEDIA_TYPE_10M_HALF:
1316 + if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1317 + reconfig = 1;
1318 + break;
1319 + }
1320 + // link result is our setting
1321 + if (0 == reconfig) {
1322 + if (adapter->link_speed != speed || adapter->link_duplex != duplex ) {
1323 + adapter->link_speed = speed;
1324 + adapter->link_duplex = duplex;
1325 + atl2_setup_mac_ctrl(adapter);
1326 + printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1327 + atl2_driver_name, netdev->name,
1328 + adapter->link_speed,
1329 + adapter->link_duplex == FULL_DUPLEX ?
1330 + "Full Duplex" : "Half Duplex");
1331 + }
1332 +
1333 + if (!netif_carrier_ok(netdev)) { // Link down -> Up
1334 + netif_carrier_on(netdev);
1335 + netif_wake_queue(netdev);
1336 + }
1337 + return ATL2_SUCCESS;
1338 + }
1339 +
1340 + // change orignal link status
1341 + if (netif_carrier_ok(netdev)) {
1342 + u32 value;
1343 + // disable rx
1344 + value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1345 + value &= ~MAC_CTRL_RX_EN;
1346 + ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1347 +
1348 + adapter->link_speed = SPEED_0;
1349 + netif_carrier_off(netdev);
1350 + netif_stop_queue(netdev);
1351 + }
1352 +
1353 + // auto-neg, insert timer to re-config phy (if interval smaller than 5 seconds, something strange)
1354 + if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1355 + if (!test_and_set_bit(0, &adapter->cfg_phy)) {
1356 + mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
1357 + }
1358 + }
1359 +
1360 + return ATL2_SUCCESS;
1361 +}
1362 +
1363 +/*
1364 + * atl2_link_chg_task - deal with link change event Out of interrupt context
1365 + * @netdev: network interface device structure
1366 + */
1367 +static void atl2_link_chg_task(struct work_struct *work)
1368 +{
1369 + struct atl2_adapter *adapter;
1370 + unsigned long flags;
1371 +
1372 + adapter = container_of(work, struct atl2_adapter, link_chg_task);
1373 +
1374 + spin_lock_irqsave(&adapter->stats_lock, flags);
1375 + atl2_check_link(adapter);
1376 + spin_unlock_irqrestore(&adapter->stats_lock, flags);
1377 +}
1378 +
1379 +static void atl2_setup_pcicmd(struct pci_dev *pdev)
1380 +{
1381 + u16 cmd;
1382 +
1383 + pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1384 +
1385 + if (cmd & PCI_COMMAND_INTX_DISABLE)
1386 + cmd &= ~PCI_COMMAND_INTX_DISABLE;
1387 + if (cmd & PCI_COMMAND_IO)
1388 + cmd &= ~PCI_COMMAND_IO;
1389 + if (0 == (cmd & PCI_COMMAND_MEMORY))
1390 + cmd |= PCI_COMMAND_MEMORY;
1391 + if (0 == (cmd & PCI_COMMAND_MASTER))
1392 + cmd |= PCI_COMMAND_MASTER;
1393 + pci_write_config_word(pdev, PCI_COMMAND, cmd);
1394 +
1395 + /*
1396 + * some motherboards BIOS(PXE/EFI) driver may set PME
1397 + * while they transfer control to OS (Windows/Linux)
1398 + * so we should clear this bit before NIC work normally
1399 + */
1400 + pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1401 +}
1402 +
1403 +/*
1404 + * atl2_probe - Device Initialization Routine
1405 + * @pdev: PCI device information struct
1406 + * @ent: entry in atl2_pci_tbl
1407 + *
1408 + * Returns 0 on success, negative on failure
1409 + *
1410 + * atl2_probe initializes an adapter identified by a pci_dev structure.
1411 + * The OS initialization, configuring of the adapter private structure,
1412 + * and a hardware reset occur.
1413 + */
1414 +static int __devinit atl2_probe(struct pci_dev *pdev,
1415 + const struct pci_device_id *ent)
1416 +{
1417 + struct net_device *netdev;
1418 + struct atl2_adapter *adapter;
1419 + static int cards_found = 0;
1420 + unsigned long mmio_start;
1421 + int mmio_len;
1422 + int err;
1423 +
1424 + if((err = pci_enable_device(pdev)))
1425 + return err;
1426 +
1427 + /*
1428 + * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1429 + * until the kernel has the proper infrastructure to support 64-bit DMA
1430 + * on these devices.
1431 + */
1432 + if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
1433 + (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1434 + printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1435 + goto err_dma;
1436 + }
1437 +
1438 + // Mark all PCI regions associated with PCI device
1439 + // pdev as being reserved by owner atl2_driver_name
1440 + if((err = pci_request_regions(pdev, atl2_driver_name)))
1441 + goto err_pci_reg;
1442 +
1443 + // Enables bus-mastering on the device and calls
1444 + // pcibios_set_master to do the needed arch specific settings
1445 + pci_set_master(pdev);
1446 +
1447 + err = -ENOMEM;
1448 + netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1449 + if(!netdev)
1450 + goto err_alloc_etherdev;
1451 +
1452 + SET_NETDEV_DEV(netdev, &pdev->dev);
1453 +
1454 + pci_set_drvdata(pdev, netdev);
1455 + adapter = netdev_priv(netdev);
1456 + adapter->netdev = netdev;
1457 + adapter->pdev = pdev;
1458 + adapter->hw.back = adapter;
1459 +
1460 + mmio_start = pci_resource_start(pdev, 0x0);
1461 + mmio_len = pci_resource_len(pdev, 0x0);
1462 +
1463 + adapter->hw.mem_rang = (u32)mmio_len;
1464 + adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1465 + if(!adapter->hw.hw_addr) {
1466 + err = -EIO;
1467 + goto err_ioremap;
1468 + }
1469 +
1470 + atl2_setup_pcicmd(pdev);
1471 +
1472 + netdev->open = &atl2_open;
1473 + netdev->stop = &atl2_close;
1474 + netdev->hard_start_xmit = &atl2_xmit_frame;
1475 + netdev->get_stats = &atl2_get_stats;
1476 + netdev->set_multicast_list = &atl2_set_multi;
1477 + netdev->set_mac_address = &atl2_set_mac;
1478 + netdev->change_mtu = &atl2_change_mtu;
1479 + netdev->do_ioctl = &atl2_ioctl;
1480 + atl2_set_ethtool_ops(netdev);
1481 +
1482 +#ifdef HAVE_TX_TIMEOUT
1483 + netdev->tx_timeout = &atl2_tx_timeout;
1484 + netdev->watchdog_timeo = 5 * HZ; //FIXME -- CHS
1485 +#endif
1486 +#ifdef NETIF_F_HW_VLAN_TX
1487 + netdev->vlan_rx_register = atl2_vlan_rx_register;
1488 +#endif
1489 + strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1490 +
1491 + netdev->mem_start = mmio_start;
1492 + netdev->mem_end = mmio_start + mmio_len;
1493 + //netdev->base_addr = adapter->io_base;
1494 + adapter->bd_number = cards_found;
1495 + adapter->pci_using_64 = false;
1496 +
1497 + /* setup the private structure */
1498 +
1499 + if((err = atl2_sw_init(adapter)))
1500 + goto err_sw_init;
1501 +
1502 + err = -EIO;
1503 +
1504 +#ifdef NETIF_F_HW_VLAN_TX
1505 + netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX );
1506 +#endif
1507 +
1508 +#ifdef NETIF_F_LLTX
1509 + netdev->features |= NETIF_F_LLTX;
1510 +#endif
1511 +
1512 + /* Init PHY as early as possible due to power saving issue */
1513 + atl2_phy_init(&adapter->hw);
1514 +
1515 + /* reset the controller to
1516 + * put the device in a known good starting state */
1517 +
1518 + if (atl2_reset_hw(&adapter->hw)) {
1519 + err = -EIO;
1520 + goto err_reset;
1521 + }
1522 +
1523 + /* copy the MAC address out of the EEPROM */
1524 + atl2_read_mac_addr(&adapter->hw);
1525 + memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1526 +//FIXME: do we still need this?
1527 +#ifdef ETHTOOL_GPERMADDR
1528 + memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1529 +
1530 + if (!is_valid_ether_addr(netdev->perm_addr)) {
1531 +#else
1532 + if (!is_valid_ether_addr(netdev->dev_addr)) {
1533 +#endif
1534 + err = -EIO;
1535 + goto err_eeprom;
1536 + }
1537 +
1538 + atl2_check_options(adapter);
1539 +
1540 + init_timer(&adapter->watchdog_timer);
1541 + adapter->watchdog_timer.function = &atl2_watchdog;
1542 + adapter->watchdog_timer.data = (unsigned long) adapter;
1543 +
1544 + init_timer(&adapter->phy_config_timer);
1545 + adapter->phy_config_timer.function = &atl2_phy_config;
1546 + adapter->phy_config_timer.data = (unsigned long) adapter;
1547 +
1548 + INIT_WORK(&adapter->reset_task, atl2_reset_task);
1549 + INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1550 +
1551 + strcpy(netdev->name, "eth%d"); // ??
1552 + if((err = register_netdev(netdev)))
1553 + goto err_register;
1554 +
1555 + /* assume we have no link for now */
1556 + netif_carrier_off(netdev);
1557 + netif_stop_queue(netdev);
1558 +
1559 + cards_found++;
1560 +
1561 + return 0;
1562 +
1563 +//err_init_hw:
1564 +err_reset:
1565 +err_register:
1566 +err_sw_init:
1567 +err_eeprom:
1568 + iounmap(adapter->hw.hw_addr);
1569 +err_ioremap:
1570 + free_netdev(netdev);
1571 +err_alloc_etherdev:
1572 + pci_release_regions(pdev);
1573 +err_pci_reg:
1574 +err_dma:
1575 + pci_disable_device(pdev);
1576 + return err;
1577 +}
1578 +
1579 +/*
1580 + * atl2_remove - Device Removal Routine
1581 + * @pdev: PCI device information struct
1582 + *
1583 + * atl2_remove is called by the PCI subsystem to alert the driver
1584 + * that it should release a PCI device. The could be caused by a
1585 + * Hot-Plug event, or because the driver is going to be removed from
1586 + * memory.
1587 + */
1588 +/* FIXME: write the original MAC address back in case it was changed from a
1589 + * BIOS-set value, as in atl1 -- CHS */
1590 +static void __devexit atl2_remove(struct pci_dev *pdev)
1591 +{
1592 + struct net_device *netdev = pci_get_drvdata(pdev);
1593 + struct atl2_adapter *adapter = netdev_priv(netdev);
1594 +
1595 + /* flush_scheduled work may reschedule our watchdog task, so
1596 + * explicitly disable watchdog tasks from being rescheduled */
1597 + set_bit(__ATL2_DOWN, &adapter->flags);
1598 +
1599 + del_timer_sync(&adapter->watchdog_timer);
1600 + del_timer_sync(&adapter->phy_config_timer);
1601 +
1602 + flush_scheduled_work();
1603 +
1604 + unregister_netdev(netdev);
1605 +
1606 + atl2_force_ps(&adapter->hw);
1607 +
1608 + iounmap(adapter->hw.hw_addr);
1609 + pci_release_regions(pdev);
1610 +
1611 + free_netdev(netdev);
1612 +
1613 + pci_disable_device(pdev);
1614 +}
1615 +
1616 +static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1617 +{
1618 + struct net_device *netdev = pci_get_drvdata(pdev);
1619 + struct atl2_adapter *adapter = netdev_priv(netdev);
1620 + struct atl2_hw * hw = &adapter->hw;
1621 + u16 speed, duplex;
1622 + u32 ctrl = 0;
1623 + u32 wufc = adapter->wol;
1624 +
1625 +#ifdef CONFIG_PM
1626 + int retval = 0;
1627 +#endif
1628 +
1629 + netif_device_detach(netdev);
1630 +
1631 + if (netif_running(netdev)) {
1632 + WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1633 + atl2_down(adapter);
1634 + }
1635 +
1636 +#ifdef CONFIG_PM
1637 + retval = pci_save_state(pdev);
1638 + if (retval)
1639 + return retval;
1640 +#endif
1641 +
1642 + atl2_read_phy_reg(hw, MII_BMSR, (u16*)&ctrl);
1643 + atl2_read_phy_reg(hw, MII_BMSR, (u16*)&ctrl);
1644 + if(ctrl & BMSR_LSTATUS)
1645 + wufc &= ~ATL2_WUFC_LNKC;
1646 +
1647 + if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1648 + u32 ret_val;
1649 + /* get current link speed & duplex */
1650 + ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1651 + if (ret_val) {
1652 + printk(KERN_DEBUG "%s: get speed&duplex error while suspend\n", atl2_driver_name);
1653 + goto wol_dis;
1654 + }
1655 +
1656 + ctrl = 0;
1657 +
1658 + /* turn on magic packet wol */
1659 + if (wufc & ATL2_WUFC_MAG)
1660 + ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1661 +
1662 + /* ignore Link Chg event when Link is up */
1663 + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1664 +
1665 + /* Config MAC CTRL Register */
1666 + ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1667 + if (FULL_DUPLEX == adapter->link_duplex)
1668 + ctrl |= MAC_CTRL_DUPLX;
1669 + ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1670 + ctrl |= (((u32)adapter->hw.preamble_len &
1671 + MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1672 + ctrl |= (((u32)(adapter->hw.retry_buf &
1673 + MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1674 + MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1675 + if (wufc & ATL2_WUFC_MAG) {
1676 + /* magic packet maybe Broadcast&multicast&Unicast frame */
1677 + ctrl |= MAC_CTRL_BC_EN;
1678 + }
1679 +
1680 + ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1681 +
1682 + /* pcie patch */
1683 + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1684 + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1685 + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1686 + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1687 + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1688 + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1689 +
1690 + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1691 + goto suspend_exit;
1692 + }
1693 +
1694 + if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATL2_WUFC_LNKC)) {
1695 + /* link is down, so only LINK CHG WOL event enable */
1696 + ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1697 + ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1698 + ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1699 +
1700 + /* pcie patch */
1701 + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1702 + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1703 + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1704 + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1705 + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1706 + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1707 +
1708 + hw->phy_configured = false; /* re-init PHY when resume */
1709 +
1710 + pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1711 +
1712 + goto suspend_exit;
1713 + }
1714 +
1715 +wol_dis:
1716 + /* WOL disabled */
1717 + ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1718 +
1719 + /* pcie patch */
1720 + ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1721 + ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1722 + ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1723 + ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1724 + ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1725 + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1726 +
1727 + atl2_force_ps(hw);
1728 + hw->phy_configured = false; /* re-init PHY when resume */
1729 +
1730 + pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1731 +
1732 +suspend_exit:
1733 + if (netif_running(netdev))
1734 + atl2_free_irq(adapter);
1735 +
1736 + pci_disable_device(pdev);
1737 +
1738 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
1739 +
1740 + return 0;
1741 +}
1742 +
1743 +#ifdef CONFIG_PM
1744 +static int atl2_resume(struct pci_dev *pdev)
1745 +{
1746 + struct net_device *netdev = pci_get_drvdata(pdev);
1747 + struct atl2_adapter *adapter = netdev_priv(netdev);
1748 + u32 err;
1749 +
1750 + pci_set_power_state(pdev, PCI_D0);
1751 + pci_restore_state(pdev);
1752 +
1753 + if ((err = pci_enable_device(pdev))) {
1754 + printk(KERN_ERR "atl2: Cannot enable PCI device from suspend\n");
1755 + return err;
1756 + }
1757 +
1758 + pci_set_master(pdev);
1759 +
1760 + ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1761 +
1762 + pci_enable_wake(pdev, PCI_D3hot, 0);
1763 + pci_enable_wake(pdev, PCI_D3cold, 0);
1764 +
1765 + ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1766 +
1767 + if (netif_running(netdev) && (err = atl2_request_irq(adapter)))
1768 + return err;
1769 +
1770 + atl2_reset_hw(&adapter->hw);
1771 +
1772 + if(netif_running(netdev))
1773 + atl2_up(adapter);
1774 +
1775 + netif_device_attach(netdev);
1776 +
1777 + return 0;
1778 +}
1779 +#endif
1780 +
1781 +static void atl2_shutdown(struct pci_dev *pdev)
1782 +{
1783 + atl2_suspend(pdev, PMSG_SUSPEND);
1784 +}
1785 +
1786 +static struct pci_driver atl2_driver = {
1787 + .name = atl2_driver_name,
1788 + .id_table = atl2_pci_tbl,
1789 + .probe = atl2_probe,
1790 + .remove = __devexit_p(atl2_remove),
1791 + /* Power Managment Hooks */
1792 + .suspend = atl2_suspend,
1793 +#ifdef CONFIG_PM
1794 + .resume = atl2_resume,
1795 +#endif
1796 + .shutdown = atl2_shutdown,
1797 +};
1798 +
1799 +/*
1800 + * atl2_init_module - Driver Registration Routine
1801 + *
1802 + * atl2_init_module is the first routine called when the driver is
1803 + * loaded. All it does is register with the PCI subsystem.
1804 + */
1805 +static int __init atl2_init_module(void)
1806 +{
1807 + int ret;
1808 + printk(KERN_INFO "%s - version %s\n", atl2_driver_string, atl2_driver_version);
1809 + printk(KERN_INFO "%s\n", atl2_copyright);
1810 +
1811 + ret = pci_register_driver(&atl2_driver);
1812 +#if 0
1813 + if (copybreak != COPYBREAK_DEFAULT) {
1814 + if (copybreak == 0)
1815 + printk(KERN_INFO "atl2: copybreak disabled\n");
1816 + else
1817 + printk(KERN_INFO "atl2: copybreak enabled for packets <= %u bytes\n", copybreak);
1818 + }
1819 +#endif
1820 + return ret;
1821 +}
1822 +module_init(atl2_init_module);
1823 +
1824 +/*
1825 + * atl2_exit_module - Driver Exit Cleanup Routine
1826 + *
1827 + * atl2_exit_module is called just before the driver is removed
1828 + * from memory.
1829 + */
1830 +static void __exit atl2_exit_module(void)
1831 +{
1832 + pci_unregister_driver(&atl2_driver);
1833 +}
1834 +module_exit(atl2_exit_module);
1835 +
1836 +void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1837 +{
1838 + struct atl2_adapter *adapter = hw->back;
1839 + pci_read_config_word(adapter->pdev, reg, value);
1840 +}
1841 +
1842 +void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1843 +{
1844 + struct atl2_adapter *adapter = hw->back;
1845 + pci_write_config_word(adapter->pdev, reg, *value);
1846 +}
1847 +
1848 +static int atl2_get_settings(struct net_device *netdev,
1849 + struct ethtool_cmd *ecmd)
1850 +{
1851 + struct atl2_adapter *adapter = netdev_priv(netdev);
1852 + struct atl2_hw *hw = &adapter->hw;
1853 +
1854 + ecmd->supported = (SUPPORTED_10baseT_Half |
1855 + SUPPORTED_10baseT_Full |
1856 + SUPPORTED_100baseT_Half |
1857 + SUPPORTED_100baseT_Full |
1858 + SUPPORTED_Autoneg |
1859 + SUPPORTED_TP);
1860 + ecmd->advertising = ADVERTISED_TP;
1861 +
1862 + ecmd->advertising |= ADVERTISED_Autoneg;
1863 + ecmd->advertising |= hw->autoneg_advertised;
1864 +
1865 + ecmd->port = PORT_TP;
1866 + ecmd->phy_address = 0;
1867 + ecmd->transceiver = XCVR_INTERNAL;
1868 +
1869 + if (adapter->link_speed != SPEED_0) {
1870 + ecmd->speed = adapter->link_speed;
1871 + if (adapter->link_duplex == FULL_DUPLEX)
1872 + ecmd->duplex = DUPLEX_FULL;
1873 + else
1874 + ecmd->duplex = DUPLEX_HALF;
1875 + } else {
1876 + ecmd->speed = -1;
1877 + ecmd->duplex = -1;
1878 + }
1879 +
1880 + ecmd->autoneg = AUTONEG_ENABLE;
1881 + return 0;
1882 +}
1883 +
1884 +static int atl2_set_settings(struct net_device *netdev,
1885 + struct ethtool_cmd *ecmd)
1886 +{
1887 + struct atl2_adapter *adapter = netdev_priv(netdev);
1888 + struct atl2_hw *hw = &adapter->hw;
1889 +
1890 + while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1891 + msleep(1);
1892 +
1893 + if (ecmd->autoneg == AUTONEG_ENABLE) {
1894 +#define MY_ADV_MASK (ADVERTISE_10_HALF| \
1895 + ADVERTISE_10_FULL| \
1896 + ADVERTISE_100_HALF| \
1897 + ADVERTISE_100_FULL)
1898 +
1899 + if ((ecmd->advertising&MY_ADV_MASK) == MY_ADV_MASK) {
1900 + hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1901 + hw->autoneg_advertised = MY_ADV_MASK;
1902 + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_100_FULL) {
1903 + hw->MediaType = MEDIA_TYPE_100M_FULL;
1904 + hw->autoneg_advertised = ADVERTISE_100_FULL;
1905 + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_100_HALF) {
1906 + hw->MediaType = MEDIA_TYPE_100M_HALF;
1907 + hw->autoneg_advertised = ADVERTISE_100_HALF;
1908 + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_10_FULL) {
1909 + hw->MediaType = MEDIA_TYPE_10M_FULL;
1910 + hw->autoneg_advertised = ADVERTISE_10_FULL;
1911 + } else if ((ecmd->advertising&MY_ADV_MASK) == ADVERTISE_10_HALF) {
1912 + hw->MediaType = MEDIA_TYPE_10M_HALF;
1913 + hw->autoneg_advertised = ADVERTISE_10_HALF;
1914 + } else {
1915 + clear_bit(__ATL2_RESETTING, &adapter->flags);
1916 + return -EINVAL;
1917 + }
1918 + ecmd->advertising = hw->autoneg_advertised |
1919 + ADVERTISED_TP | ADVERTISED_Autoneg;
1920 + } else {
1921 + clear_bit(__ATL2_RESETTING, &adapter->flags);
1922 + return -EINVAL;
1923 + }
1924 +
1925 + /* reset the link */
1926 + if (netif_running(adapter->netdev)) {
1927 + atl2_down(adapter);
1928 + atl2_up(adapter);
1929 + } else
1930 + atl2_reset_hw(&adapter->hw);
1931 +
1932 + clear_bit(__ATL2_RESETTING, &adapter->flags);
1933 + return 0;
1934 +}
1935 +
1936 +static u32 atl2_get_tx_csum(struct net_device *netdev)
1937 +{
1938 + return (netdev->features & NETIF_F_HW_CSUM) != 0;
1939 +}
1940 +
1941 +static u32 atl2_get_msglevel(struct net_device *netdev)
1942 +{
1943 + return 0;
1944 +}
1945 +
1946 +/*
1947 + * It's sane for this to be empty, but we might want to take advantage of this.
1948 + */
1949 +static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1950 +{
1951 +}
1952 +
1953 +static int atl2_get_regs_len(struct net_device *netdev)
1954 +{
1955 +#define ATL2_REGS_LEN 42
1956 + return ATL2_REGS_LEN * sizeof(u32);
1957 +}
1958 +
1959 +static void atl2_get_regs(struct net_device *netdev,
1960 + struct ethtool_regs *regs, void *p)
1961 +{
1962 + struct atl2_adapter *adapter = netdev_priv(netdev);
1963 + struct atl2_hw *hw = &adapter->hw;
1964 + u32 *regs_buff = p;
1965 + u16 phy_data;
1966 +
1967 + memset(p, 0, ATL2_REGS_LEN * sizeof(u32));
1968 +
1969 + regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1970 +
1971 + regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1972 + regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1973 + regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1974 + regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1975 + regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1976 + regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1977 + regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1978 + regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1979 + regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1980 + regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1981 + regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1982 + regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1983 + regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1984 + regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1985 + regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1986 + regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1987 + regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1988 + regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1989 + regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1990 + regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1991 + regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1992 + regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1993 + regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1994 + regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1995 + regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1996 + regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1997 + regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1998 + regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1999 + regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
2000 + regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
2001 + regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
2002 + regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
2003 + regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
2004 + regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
2005 + regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
2006 + regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
2007 + regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
2008 + regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
2009 + regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
2010 +
2011 + atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
2012 + regs_buff[40] = (u32)phy_data;
2013 + atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
2014 + regs_buff[41] = (u32)phy_data;
2015 +}
2016 +
2017 +static int atl2_get_eeprom_len(struct net_device *netdev)
2018 +{
2019 + struct atl2_adapter *adapter = netdev_priv(netdev);
2020 +
2021 + if (!atl2_check_eeprom_exist(&adapter->hw)) {
2022 + return 512;
2023 + } else
2024 + return 0;
2025 +}
2026 +
2027 +static int atl2_get_eeprom(struct net_device *netdev,
2028 + struct ethtool_eeprom *eeprom, u8 *bytes)
2029 +{
2030 + struct atl2_adapter *adapter = netdev_priv(netdev);
2031 + struct atl2_hw *hw = &adapter->hw;
2032 + u32 *eeprom_buff;
2033 + int first_dword, last_dword;
2034 + int ret_val = 0;
2035 + int i;
2036 +
2037 + if (eeprom->len == 0)
2038 + return -EINVAL;
2039 +
2040 + if (atl2_check_eeprom_exist(hw)) {
2041 + return -EINVAL;
2042 + }
2043 +
2044 + eeprom->magic = hw->vendor_id | (hw->device_id << 16);
2045 +
2046 + first_dword = eeprom->offset >> 2;
2047 + last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2048 +
2049 + eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), GFP_KERNEL);
2050 + if (!eeprom_buff)
2051 + return -ENOMEM;
2052 +
2053 + for (i=first_dword; i < last_dword; i++) {
2054 + if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
2055 + return -EIO;
2056 + }
2057 +
2058 + memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
2059 + eeprom->len);
2060 + kfree(eeprom_buff);
2061 +
2062 + return ret_val;
2063 +}
2064 +
2065 +static int atl2_set_eeprom(struct net_device *netdev,
2066 + struct ethtool_eeprom *eeprom, u8 *bytes)
2067 +{
2068 + struct atl2_adapter *adapter = netdev_priv(netdev);
2069 + struct atl2_hw *hw = &adapter->hw;
2070 + u32 *eeprom_buff;
2071 + u32 *ptr;
2072 + int max_len, first_dword, last_dword, ret_val = 0;
2073 + int i;
2074 +
2075 + if (eeprom->len == 0)
2076 + return -EOPNOTSUPP;
2077 +
2078 + if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
2079 + return -EFAULT;
2080 +
2081 + max_len = 512;
2082 +
2083 + first_dword = eeprom->offset >> 2;
2084 + last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2085 + eeprom_buff = kmalloc(max_len, GFP_KERNEL);
2086 + if (!eeprom_buff)
2087 + return -ENOMEM;
2088 +
2089 + ptr = (u32 *)eeprom_buff;
2090 +
2091 + if (eeprom->offset & 3) {
2092 + /* need read/modify/write of first changed EEPROM word */
2093 + /* only the second byte of the word is being modified */
2094 + if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2095 + return -EIO;
2096 + ptr++;
2097 + }
2098 + if (((eeprom->offset + eeprom->len) & 3) ) {
2099 + /* need read/modify/write of last changed EEPROM word */
2100 + /* only the first byte of the word is being modified */
2101 +
2102 + if (!atl2_read_eeprom(hw, last_dword*4, &(eeprom_buff[last_dword - first_dword])))
2103 + return -EIO;
2104 + }
2105 +
2106 + /* Device's eeprom is always little-endian, word addressable */
2107 + memcpy(ptr, bytes, eeprom->len);
2108 +
2109 + for (i = 0; i < last_dword - first_dword + 1; i++) {
2110 + if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2111 + return -EIO;
2112 + }
2113 +
2114 + kfree(eeprom_buff);
2115 + return ret_val;
2116 +}
2117 +
2118 +static void atl2_get_drvinfo(struct net_device *netdev,
2119 + struct ethtool_drvinfo *drvinfo)
2120 +{
2121 + struct atl2_adapter *adapter = netdev_priv(netdev);
2122 +
2123 + strncpy(drvinfo->driver, atl2_driver_name, 32);
2124 + strncpy(drvinfo->version, atl2_driver_version, 32);
2125 + strncpy(drvinfo->fw_version, "L2", 32);
2126 + strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2127 + drvinfo->n_stats = 0;
2128 + drvinfo->testinfo_len = 0;
2129 + drvinfo->regdump_len = atl2_get_regs_len(netdev);
2130 + drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2131 +}
2132 +
2133 +static void atl2_get_wol(struct net_device *netdev,
2134 + struct ethtool_wolinfo *wol)
2135 +{
2136 + struct atl2_adapter *adapter = netdev_priv(netdev);
2137 +
2138 + wol->supported = WAKE_MAGIC;
2139 + wol->wolopts = 0;
2140 +
2141 + if (adapter->wol & ATL2_WUFC_EX)
2142 + wol->wolopts |= WAKE_UCAST;
2143 + if (adapter->wol & ATL2_WUFC_MC)
2144 + wol->wolopts |= WAKE_MCAST;
2145 + if (adapter->wol & ATL2_WUFC_BC)
2146 + wol->wolopts |= WAKE_BCAST;
2147 + if (adapter->wol & ATL2_WUFC_MAG)
2148 + wol->wolopts |= WAKE_MAGIC;
2149 + if (adapter->wol & ATL2_WUFC_LNKC)
2150 + wol->wolopts |= WAKE_PHY;
2151 +}
2152 +
2153 +static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2154 +{
2155 + struct atl2_adapter *adapter = netdev_priv(netdev);
2156 +
2157 + if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2158 + return -EOPNOTSUPP;
2159 +
2160 + if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2161 + return -EOPNOTSUPP;
2162 +
2163 + /* these settings will always override what we currently have */
2164 + adapter->wol = 0;
2165 +
2166 + if (wol->wolopts & WAKE_MAGIC)
2167 + adapter->wol |= ATL2_WUFC_MAG;
2168 + if (wol->wolopts & WAKE_PHY)
2169 + adapter->wol |= ATL2_WUFC_LNKC;
2170 +
2171 + return 0;
2172 +}
2173 +
2174 +static int atl2_nway_reset(struct net_device *netdev)
2175 +{
2176 + struct atl2_adapter *adapter = netdev_priv(netdev);
2177 + if (netif_running(netdev))
2178 + atl2_reinit_locked(adapter);
2179 + return 0;
2180 +}
2181 +
2182 +static struct ethtool_ops atl2_ethtool_ops = {
2183 + .get_settings = atl2_get_settings,
2184 + .set_settings = atl2_set_settings,
2185 + .get_drvinfo = atl2_get_drvinfo,
2186 + .get_regs_len = atl2_get_regs_len,
2187 + .get_regs = atl2_get_regs,
2188 + .get_wol = atl2_get_wol,
2189 + .set_wol = atl2_set_wol,
2190 + .get_msglevel = atl2_get_msglevel,
2191 + .set_msglevel = atl2_set_msglevel,
2192 + .nway_reset = atl2_nway_reset,
2193 + .get_link = ethtool_op_get_link,
2194 + .get_eeprom_len = atl2_get_eeprom_len,
2195 + .get_eeprom = atl2_get_eeprom,
2196 + .set_eeprom = atl2_set_eeprom,
2197 + .get_tx_csum = atl2_get_tx_csum,
2198 + .get_sg = ethtool_op_get_sg,
2199 + .set_sg = ethtool_op_set_sg,
2200 +#ifdef NETIF_F_TSO
2201 + .get_tso = ethtool_op_get_tso,
2202 +#endif
2203 +#if 0 //FIXME: not implemented?
2204 +//#ifdef ETHTOOL_GPERMADDR
2205 + .get_perm_addr = ethtool_op_get_perm_addr,
2206 +#endif
2207 +};
2208 +
2209 +void atl2_set_ethtool_ops(struct net_device *netdev)
2210 +{
2211 + SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2212 +}
2213 +
2214 +#define LBYTESWAP( a ) ( ( ( (a) & 0x00ff00ff ) << 8 ) | ( ( (a) & 0xff00ff00 ) >> 8 ) )
2215 +#define LONGSWAP( a ) ( ( LBYTESWAP( a ) << 16 ) | ( LBYTESWAP( a ) >> 16 ) )
2216 +#define SHORTSWAP( a ) ( ( (a) << 8 ) | ( (a) >> 8 ) )
2217 +
2218 +/*
2219 + * Reset the transmit and receive units; mask and clear all interrupts.
2220 + *
2221 + * hw - Struct containing variables accessed by shared code
2222 + * return : ATL2_SUCCESS or idle status (if error)
2223 + */
2224 +s32
2225 +atl2_reset_hw(struct atl2_hw *hw)
2226 +{
2227 + u32 icr;
2228 + u16 pci_cfg_cmd_word;
2229 + int i;
2230 +
2231 + /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2232 + atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2233 + if ((pci_cfg_cmd_word &
2234 + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2235 + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2236 + pci_cfg_cmd_word |=
2237 + (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2238 + atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2239 + }
2240 +
2241 + /* Clear Interrupt mask to stop board from generating
2242 + * interrupts & Clear any pending interrupt events
2243 + */
2244 +// ATL2_WRITE_REG(hw, REG_IMR, 0);
2245 +// ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff);
2246 +
2247 + /* Issue Soft Reset to the MAC. This will reset the chip's
2248 + * transmit, receive, DMA. It will not effect
2249 + * the current PCI configuration. The global reset bit is self-
2250 + * clearing, and should clear within a microsecond.
2251 + */
2252 + ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2253 + wmb();
2254 + msec_delay(1); // delay about 1ms
2255 +
2256 + /* Wait at least 10ms for All module to be Idle */
2257 + for (i=0; i < 10; i++) {
2258 + icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2259 + if (!icr)
2260 + break;
2261 + msec_delay(1); // delay 1 ms
2262 + cpu_relax();
2263 + }
2264 +
2265 + if (icr)
2266 + return icr;
2267 +
2268 + return ATL2_SUCCESS;
2269 +}
2270 +
2271 +#define CUSTOM_SPI_CS_SETUP 2
2272 +#define CUSTOM_SPI_CLK_HI 2
2273 +#define CUSTOM_SPI_CLK_LO 2
2274 +#define CUSTOM_SPI_CS_HOLD 2
2275 +#define CUSTOM_SPI_CS_HI 3
2276 +
2277 +static struct atl2_spi_flash_dev flash_table[] =
2278 +{
2279 +/* manu_name WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2280 + {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2281 + {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2282 + {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2283 +};
2284 +
2285 +static bool atl2_spi_read(struct atl2_hw* hw, u32 addr, u32* buf)
2286 +{
2287 + int i;
2288 + u32 value;
2289 +
2290 + ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2291 + ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2292 +
2293 + value = SPI_FLASH_CTRL_WAIT_READY |
2294 + (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2295 + (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << SPI_FLASH_CTRL_CLK_HI_SHIFT |
2296 + (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << SPI_FLASH_CTRL_CLK_LO_SHIFT |
2297 + (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2298 + (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << SPI_FLASH_CTRL_CS_HI_SHIFT |
2299 + (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2300 +
2301 + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2302 +
2303 + value |= SPI_FLASH_CTRL_START;
2304 +
2305 + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2306 +
2307 + for (i = 0; i < 10; i++)
2308 + {
2309 + msec_delay(1); // 1ms
2310 + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2311 + if (!(value & SPI_FLASH_CTRL_START))
2312 + break;
2313 + }
2314 +
2315 + if (value & SPI_FLASH_CTRL_START)
2316 + return false;
2317 +
2318 + *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2319 +
2320 + return true;
2321 +}
2322 +
2323 +/*
2324 + * get_permanent_address
2325 + * return 0 if get valid mac address,
2326 + */
2327 +static int get_permanent_address(struct atl2_hw *hw)
2328 +{
2329 + u32 Addr[2];
2330 + u32 i, Control;
2331 + u16 Register;
2332 + u8 EthAddr[NODE_ADDRESS_SIZE];
2333 + bool KeyValid;
2334 +
2335 + if (is_valid_ether_addr(hw->perm_mac_addr))
2336 + return 0;
2337 +
2338 + Addr[0] = 0;
2339 + Addr[1] = 0;
2340 +
2341 + if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2342 + Register = 0;
2343 + KeyValid = false;
2344 +
2345 + /* Read out all EEPROM content */
2346 + i = 0;
2347 + while (1) {
2348 + if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2349 + if (KeyValid) {
2350 + if (Register == REG_MAC_STA_ADDR)
2351 + Addr[0] = Control;
2352 + else if (Register == (REG_MAC_STA_ADDR + 4))
2353 + Addr[1] = Control;
2354 + KeyValid = false;
2355 + } else if ((Control & 0xff) == 0x5A) {
2356 + KeyValid = true;
2357 + Register = (u16) (Control >> 16);
2358 + } else {
2359 + break; /* assume data end while encount an invalid KEYWORD */
2360 + }
2361 + } else {
2362 + break; /* read error */
2363 + }
2364 + i += 4;
2365 + }
2366 +
2367 + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]);
2368 + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]);
2369 +
2370 + if (is_valid_ether_addr(EthAddr)) {
2371 + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2372 + return 0;
2373 + }
2374 + return 1;
2375 + }
2376 +
2377 + // see if SPI FLASH exists?
2378 + Addr[0] = 0;
2379 + Addr[1] = 0;
2380 + Register = 0;
2381 + KeyValid = false;
2382 + i = 0;
2383 + while (1) {
2384 + if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2385 + if (KeyValid) {
2386 + if (Register == REG_MAC_STA_ADDR)
2387 + Addr[0] = Control;
2388 + else if (Register == (REG_MAC_STA_ADDR + 4))
2389 + Addr[1] = Control;
2390 + KeyValid = false;
2391 + } else if ((Control & 0xff) == 0x5A) {
2392 + KeyValid = true;
2393 + Register = (u16) (Control >> 16);
2394 + } else {
2395 + break; /* data end */
2396 + }
2397 + } else {
2398 + break; /* read error */
2399 + }
2400 + i += 4;
2401 + }
2402 +
2403 + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]);
2404 + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]);
2405 + if (is_valid_ether_addr(EthAddr)) {
2406 + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2407 + return 0;
2408 + }
2409 + /* maybe MAC-address is from BIOS */
2410 + Addr[0] = ATL2_READ_REG(hw,REG_MAC_STA_ADDR);
2411 + Addr[1] = ATL2_READ_REG(hw,REG_MAC_STA_ADDR+4);
2412 + *(u32*) &EthAddr[2] = LONGSWAP(Addr[0]);
2413 + *(u16*) &EthAddr[0] = SHORTSWAP(*(u16*)&Addr[1]);
2414 +
2415 + if (is_valid_ether_addr(EthAddr)) {
2416 + memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2417 + return 0;
2418 + }
2419 +
2420 + return 1;
2421 +}
2422 +
2423 +/*
2424 + * Reads the adapter's MAC address from the EEPROM
2425 + *
2426 + * hw - Struct containing variables accessed by shared code
2427 + */
2428 +s32 atl2_read_mac_addr(struct atl2_hw *hw)
2429 +{
2430 + u16 i;
2431 +
2432 + if (get_permanent_address(hw)) {
2433 + // for test
2434 + hw->perm_mac_addr[0] = 0x00;
2435 + hw->perm_mac_addr[1] = 0x13;
2436 + hw->perm_mac_addr[2] = 0x74;
2437 + hw->perm_mac_addr[3] = 0x00;
2438 + hw->perm_mac_addr[4] = 0x5c;
2439 + hw->perm_mac_addr[5] = 0x38;
2440 + }
2441 +
2442 + for(i = 0; i < NODE_ADDRESS_SIZE; i++)
2443 + hw->mac_addr[i] = hw->perm_mac_addr[i];
2444 +
2445 + return ATL2_SUCCESS;
2446 +}
2447 +
2448 +/*
2449 + * Hashes an address to determine its location in the multicast table
2450 + *
2451 + * hw - Struct containing variables accessed by shared code
2452 + * mc_addr - the multicast address to hash
2453 + *
2454 + * atl2_hash_mc_addr
2455 + * purpose
2456 + * set hash value for a multicast address
2457 + * hash calcu processing :
2458 + * 1. calcu 32bit CRC for multicast address
2459 + * 2. reverse crc with MSB to LSB
2460 + */
2461 +u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2462 +{
2463 + u32 crc32, value=0;
2464 + int i;
2465 +
2466 + crc32 = ether_crc_le(6, mc_addr);
2467 +
2468 + for (i=0; i<32; i++)
2469 + value |= (((crc32>>i)&1)<<(31-i));
2470 +
2471 + return value;
2472 +}
2473 +
2474 +/*
2475 + * Sets the bit in the multicast table corresponding to the hash value.
2476 + *
2477 + * hw - Struct containing variables accessed by shared code
2478 + * hash_value - Multicast address hash value
2479 + */
2480 +void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2481 +{
2482 + u32 hash_bit, hash_reg;
2483 + u32 mta;
2484 +
2485 + /* The HASH Table is a register array of 2 32-bit registers.
2486 + * It is treated like an array of 64 bits. We want to set
2487 + * bit BitArray[hash_value]. So we figure out what register
2488 + * the bit is in, read it, OR in the new bit, then write
2489 + * back the new value. The register is determined by the
2490 + * upper 7 bits of the hash value and the bit within that
2491 + * register are determined by the lower 5 bits of the value.
2492 + */
2493 + hash_reg = (hash_value >> 31) & 0x1;
2494 + hash_bit = (hash_value >> 26) & 0x1F;
2495 +
2496 + mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2497 +
2498 + mta |= (1 << hash_bit);
2499 +
2500 + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2501 +}
2502 +
2503 +/*
2504 + * atl2_init_pcie - init PCIE module
2505 + */
2506 +static void atl2_init_pcie(struct atl2_hw *hw)
2507 +{
2508 + u32 value;
2509 + value = LTSSM_TEST_MODE_DEF;
2510 + ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2511 +
2512 + value = PCIE_DLL_TX_CTRL1_DEF;
2513 + ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2514 +}
2515 +
2516 +void atl2_init_flash_opcode(struct atl2_hw *hw)
2517 +{
2518 + if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) {
2519 + hw->flash_vendor = 0; // ATMEL
2520 + }
2521 + // Init OP table
2522 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, flash_table[hw->flash_vendor].cmdPROGRAM);
2523 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2524 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2525 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, flash_table[hw->flash_vendor].cmdRDID);
2526 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, flash_table[hw->flash_vendor].cmdWREN);
2527 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, flash_table[hw->flash_vendor].cmdRDSR);
2528 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, flash_table[hw->flash_vendor].cmdWRSR);
2529 + ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, flash_table[hw->flash_vendor].cmdREAD);
2530 +}
2531 +
2532 +/********************************************************************
2533 +* Performs basic configuration of the adapter.
2534 +*
2535 +* hw - Struct containing variables accessed by shared code
2536 +* Assumes that the controller has previously been reset and is in a
2537 +* post-reset uninitialized state. Initializes multicast table,
2538 +* and Calls routines to setup link
2539 +* Leaves the transmit and receive units disabled and uninitialized.
2540 +********************************************************************/
2541 +s32 atl2_init_hw(struct atl2_hw *hw)
2542 +{
2543 + u32 ret_val = 0;
2544 +
2545 + atl2_init_pcie(hw);
2546 +
2547 + /* Zero out the Multicast HASH table */
2548 + /* clear the old settings from the multicast hash table */
2549 + ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2550 + ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2551 +
2552 + atl2_init_flash_opcode(hw);
2553 +
2554 + ret_val = atl2_phy_init(hw);
2555 +
2556 + return ret_val;
2557 +}
2558 +
2559 +/*
2560 + * Detects the current speed and duplex settings of the hardware.
2561 + *
2562 + * hw - Struct containing variables accessed by shared code
2563 + * speed - Speed of the connection
2564 + * duplex - Duplex setting of the connection
2565 + */
2566 +s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex)
2567 +{
2568 + s32 ret_val;
2569 + u16 phy_data;
2570 +
2571 + // ; --- Read PHY Specific Status Register (17)
2572 + ret_val = atl2_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
2573 + if (ret_val)
2574 + return ret_val;
2575 +
2576 + if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
2577 + return ATL2_ERR_PHY_RES;
2578 +
2579 + switch(phy_data & MII_AT001_PSSR_SPEED) {
2580 + case MII_AT001_PSSR_100MBS:
2581 + *speed = SPEED_100;
2582 + break;
2583 + case MII_AT001_PSSR_10MBS:
2584 + *speed = SPEED_10;
2585 + break;
2586 + default:
2587 + return ATL2_ERR_PHY_SPEED;
2588 + break;
2589 + }
2590 +
2591 + if (phy_data & MII_AT001_PSSR_DPLX) {
2592 + *duplex = FULL_DUPLEX;
2593 + } else {
2594 + *duplex = HALF_DUPLEX;
2595 + }
2596 +
2597 + return ATL2_SUCCESS;
2598 +}
2599 +
2600 +/*
2601 + * Reads the value from a PHY register
2602 + * hw - Struct containing variables accessed by shared code
2603 + * reg_addr - address of the PHY register to read
2604 + */
2605 +s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2606 +{
2607 + u32 val;
2608 + int i;
2609 +
2610 + val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2611 + MDIO_START |
2612 + MDIO_SUP_PREAMBLE |
2613 + MDIO_RW |
2614 + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2615 + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2616 +
2617 + wmb();
2618 +
2619 + for (i=0; i<MDIO_WAIT_TIMES; i++) {
2620 + usec_delay(2);
2621 + val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2622 + if (!(val & (MDIO_START | MDIO_BUSY))) {
2623 + break;
2624 + }
2625 + wmb();
2626 + }
2627 + if (!(val & (MDIO_START | MDIO_BUSY))) {
2628 + *phy_data = (u16)val;
2629 + return ATL2_SUCCESS;
2630 + }
2631 +
2632 + return ATL2_ERR_PHY;
2633 +}
2634 +
2635 +/*
2636 + * Writes a value to a PHY register
2637 + * hw - Struct containing variables accessed by shared code
2638 + * reg_addr - address of the PHY register to write
2639 + * data - data to write to the PHY
2640 + */
2641 +s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2642 +{
2643 + int i;
2644 + u32 val;
2645 +
2646 + val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2647 + (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2648 + MDIO_SUP_PREAMBLE |
2649 + MDIO_START |
2650 + MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2651 + ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2652 +
2653 + wmb();
2654 +
2655 + for (i=0; i<MDIO_WAIT_TIMES; i++) {
2656 + usec_delay(2);
2657 + val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2658 + if (!(val & (MDIO_START | MDIO_BUSY))) {
2659 + break;
2660 + }
2661 + wmb();
2662 + }
2663 +
2664 + if (!(val & (MDIO_START | MDIO_BUSY)))
2665 + return ATL2_SUCCESS;
2666 +
2667 + return ATL2_ERR_PHY;
2668 +}
2669 +
2670 +/*
2671 + * Configures PHY autoneg and flow control advertisement settings
2672 + *
2673 + * hw - Struct containing variables accessed by shared code
2674 + */
2675 +static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2676 +{
2677 + s32 ret_val;
2678 + s16 mii_autoneg_adv_reg;
2679 +
2680 + /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2681 + mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2682 +
2683 + /* Need to parse autoneg_advertised and set up
2684 + * the appropriate PHY registers. First we will parse for
2685 + * autoneg_advertised software override. Since we can advertise
2686 + * a plethora of combinations, we need to check each bit
2687 + * individually.
2688 + */
2689 +
2690 + /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2691 + * Advertisement Register (Address 4) and the 1000 mb speed bits in
2692 + * the 1000Base-T Control Register (Address 9).
2693 + */
2694 + mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2695 +
2696 + /* Need to parse MediaType and setup the
2697 + * appropriate PHY registers.
2698 + */
2699 + switch (hw->MediaType) {
2700 + case MEDIA_TYPE_AUTO_SENSOR:
2701 + mii_autoneg_adv_reg |=
2702 + (MII_AR_10T_HD_CAPS |
2703 + MII_AR_10T_FD_CAPS |
2704 + MII_AR_100TX_HD_CAPS |
2705 + MII_AR_100TX_FD_CAPS);
2706 + hw->autoneg_advertised =
2707 + ADVERTISE_10_HALF |
2708 + ADVERTISE_10_FULL |
2709 + ADVERTISE_100_HALF |
2710 + ADVERTISE_100_FULL;
2711 + break;
2712 + case MEDIA_TYPE_100M_FULL:
2713 + mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2714 + hw->autoneg_advertised = ADVERTISE_100_FULL;
2715 + break;
2716 + case MEDIA_TYPE_100M_HALF:
2717 + mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2718 + hw->autoneg_advertised = ADVERTISE_100_HALF;
2719 + break;
2720 + case MEDIA_TYPE_10M_FULL:
2721 + mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2722 + hw->autoneg_advertised = ADVERTISE_10_FULL;
2723 + break;
2724 + default:
2725 + mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2726 + hw->autoneg_advertised = ADVERTISE_10_HALF;
2727 + break;
2728 + }
2729 +
2730 + /* flow control fixed to enable all */
2731 + mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2732 +
2733 + hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2734 +
2735 + ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2736 +
2737 + if(ret_val)
2738 + return ret_val;
2739 +
2740 + return ATL2_SUCCESS;
2741 +}
2742 +
2743 +/*
2744 + * Resets the PHY and make all config validate
2745 + *
2746 + * hw - Struct containing variables accessed by shared code
2747 + *
2748 + * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2749 + */
2750 +static s32 atl2_phy_commit(struct atl2_hw *hw)
2751 +{
2752 + s32 ret_val;
2753 + u16 phy_data;
2754 +
2755 +/* FIXME: use or remove -- CHS
2756 + if (hw->MediaType == MEDIA_TYPE_AUTO_SENSOR) {
2757 + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
2758 + } else {
2759 + switch (hw->MediaType)
2760 + {
2761 + case MEDIA_TYPE_100M_FULL:
2762 + phy_data = MII_CR_FULL_DUPLEX|MII_CR_SPEED_100|MII_CR_RESET;
2763 + break;
2764 + case MEDIA_TYPE_100M_HALF:
2765 + phy_data = MII_CR_SPEED_100|MII_CR_RESET;
2766 + break;
2767 + case MEDIA_TYPE_10M_FULL:
2768 + phy_data = MII_CR_FULL_DUPLEX|MII_CR_SPEED_10|MII_CR_RESET;
2769 + break;
2770 + default: // MEDIA_TYPE_10M_HALF:
2771 + phy_data = MII_CR_SPEED_10|MII_CR_RESET;
2772 + break;
2773 + }
2774 + }
2775 +*/
2776 + phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2777 + ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2778 + if (ret_val) { // bug fixed
2779 + u32 val;
2780 + int i;
2781 + /* pcie serdes link may be down ! */
2782 + for (i=0; i < 25; i++) {
2783 + msec_delay(1);
2784 + val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2785 + if (!(val & (MDIO_START | MDIO_BUSY)))
2786 + break;
2787 + }
2788 +
2789 + if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2790 + printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2791 + return ret_val;
2792 + }
2793 + }
2794 + return ATL2_SUCCESS;
2795 +}
2796 +
2797 +s32 atl2_phy_init(struct atl2_hw *hw)
2798 +{
2799 + s32 ret_val;
2800 + u16 phy_val;
2801 +
2802 + if (hw->phy_configured)
2803 + return 0;
2804 +
2805 + /* Enable PHY */
2806 + ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2807 + ATL2_WRITE_FLUSH(hw);
2808 + msec_delay(1);
2809 +
2810 + /* check if the PHY is in powersaving mode */
2811 + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2812 + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2813 +
2814 + /* 024E / 124E 0r 0274 / 1274 ? */
2815 + if (phy_val & 0x1000) {
2816 + phy_val &= ~0x1000;
2817 + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2818 + }
2819 +
2820 + msec_delay(1);
2821 +
2822 +
2823 + /*Enable PHY LinkChange Interrupt */
2824 + ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2825 + if (ret_val)
2826 + return ret_val;
2827 +
2828 + /* setup AutoNeg parameters */
2829 + ret_val = atl2_phy_setup_autoneg_adv(hw);
2830 + if(ret_val)
2831 + return ret_val;
2832 +
2833 + /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2834 + ret_val = atl2_phy_commit(hw);
2835 + if (ret_val)
2836 + return ret_val;
2837 +
2838 + hw->phy_configured = true;
2839 +
2840 + return ret_val;
2841 +}
2842 +
2843 +void atl2_set_mac_addr(struct atl2_hw *hw)
2844 +{
2845 + u32 value;
2846 + // 00-0B-6A-F6-00-DC
2847 + // 0: 6AF600DC 1: 000B
2848 + // low dword
2849 + value = (((u32)hw->mac_addr[2]) << 24) |
2850 + (((u32)hw->mac_addr[3]) << 16) |
2851 + (((u32)hw->mac_addr[4]) << 8 ) |
2852 + (((u32)hw->mac_addr[5]) ) ;
2853 + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2854 + // hight dword
2855 + value = (((u32)hw->mac_addr[0]) << 8 ) |
2856 + (((u32)hw->mac_addr[1]) ) ;
2857 + ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2858 +}
2859 +
2860 +/*
2861 + * check_eeprom_exist
2862 + * return 0 if eeprom exist
2863 + */
2864 +int atl2_check_eeprom_exist(struct atl2_hw *hw)
2865 +{
2866 + u32 value;
2867 +
2868 + value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2869 + if (value & SPI_FLASH_CTRL_EN_VPD) {
2870 + value &= ~SPI_FLASH_CTRL_EN_VPD;
2871 + ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2872 + }
2873 + value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2874 + return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2875 +}
2876 +
2877 +// FIXME: This doesn't look right. -- CHS
2878 +bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2879 +{
2880 + return true;
2881 +}
2882 +
2883 +bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2884 +{
2885 + int i;
2886 + u32 Control;
2887 +
2888 + if (Offset & 0x3)
2889 + return false; /* address do not align */
2890 +
2891 + ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2892 + Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2893 + ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2894 +
2895 + for (i = 0; i < 10; i++) {
2896 + msec_delay(2);
2897 + Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2898 + if (Control & VPD_CAP_VPD_FLAG)
2899 + break;
2900 + }
2901 +
2902 + if (Control & VPD_CAP_VPD_FLAG) {
2903 + *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2904 + return true;
2905 + }
2906 + return false; /* timeout */
2907 +}
2908 +
2909 +void atl2_force_ps(struct atl2_hw *hw)
2910 +{
2911 + u16 phy_val;
2912 +
2913 + atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2914 + atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2915 + atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2916 +
2917 + atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2918 + atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2919 + atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2920 + atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2921 +}
2922 +
2923 +/* This is the only thing that needs to be changed to adjust the
2924 + * maximum number of ports that the driver can manage.
2925 + */
2926 +#define ATL2_MAX_NIC 4
2927 +
2928 +#define OPTION_UNSET -1
2929 +#define OPTION_DISABLED 0
2930 +#define OPTION_ENABLED 1
2931 +
2932 +/* All parameters are treated the same, as an integer array of values.
2933 + * This macro just reduces the need to repeat the same declaration code
2934 + * over and over (plus this helps to avoid typo bugs).
2935 + */
2936 +#define ATL2_PARAM_INIT { [0 ... ATL2_MAX_NIC] = OPTION_UNSET }
2937 +#ifndef module_param_array
2938 +/* Module Parameters are always initialized to -1, so that the driver
2939 + * can tell the difference between no user specified value or the
2940 + * user asking for the default value.
2941 + * The true default values are loaded in when atl2_check_options is called.
2942 + *
2943 + * This is a GCC extension to ANSI C.
2944 + * See the item "Labeled Elements in Initializers" in the section
2945 + * "Extensions to the C Language Family" of the GCC documentation.
2946 + */
2947 +
2948 +#define ATL2_PARAM(X, desc) \
2949 + static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2950 + MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2951 + MODULE_PARM_DESC(X, desc);
2952 +#else
2953 +#define ATL2_PARAM(X, desc) \
2954 + static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2955 + static int num_##X = 0; \
2956 + module_param_array_named(X, X, int, &num_##X, 0); \
2957 + MODULE_PARM_DESC(X, desc);
2958 +#endif
2959 +
2960 +/* Transmit Memory Size
2961 + *
2962 + * Valid Range: 64-2048
2963 + *
2964 + * Default Value: 128
2965 + */
2966 +#define ATL2_MIN_TX_MEMSIZE 4 // 4KB
2967 +#define ATL2_MAX_TX_MEMSIZE 64 // 64KB
2968 +#define ATL2_DEFAULT_TX_MEMSIZE 8 // 8KB
2969 +ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2970 +
2971 +/* Receive Memory Block Count
2972 + *
2973 + * Valid Range: 16-512
2974 + *
2975 + * Default Value: 128
2976 + */
2977 +#define ATL2_MIN_RXD_COUNT 16
2978 +#define ATL2_MAX_RXD_COUNT 512
2979 +#define ATL2_DEFAULT_RXD_COUNT 64
2980 +ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2981 +
2982 +/* User Specified MediaType Override
2983 + *
2984 + * Valid Range: 0-5
2985 + * - 0 - auto-negotiate at all supported speeds
2986 + * - 1 - only link at 1000Mbps Full Duplex
2987 + * - 2 - only link at 100Mbps Full Duplex
2988 + * - 3 - only link at 100Mbps Half Duplex
2989 + * - 4 - only link at 10Mbps Full Duplex
2990 + * - 5 - only link at 10Mbps Half Duplex
2991 + * Default Value: 0
2992 + */
2993 +ATL2_PARAM(MediaType, "MediaType Select");
2994 +
2995 +/* Interrupt Moderate Timer in units of 2 us
2996 + *
2997 + * Valid Range: 10-65535
2998 + *
2999 + * Default Value: 45000(90ms)
3000 + */
3001 +#define INT_MOD_DEFAULT_CNT 100 // 200us
3002 +#define INT_MOD_MAX_CNT 65000
3003 +#define INT_MOD_MIN_CNT 50
3004 +ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
3005 +
3006 +/* FlashVendor
3007 + * Valid Range: 0-2
3008 + * 0 - Atmel
3009 + * 1 - SST
3010 + * 2 - ST
3011 + */
3012 +ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
3013 +
3014 +#define AUTONEG_ADV_DEFAULT 0x2F
3015 +#define AUTONEG_ADV_MASK 0x2F
3016 +#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
3017 +
3018 +#define FLASH_VENDOR_DEFAULT 0
3019 +#define FLASH_VENDOR_MIN 0
3020 +#define FLASH_VENDOR_MAX 2
3021 +
3022 +struct atl2_option {
3023 + enum { enable_option, range_option, list_option } type;
3024 + char *name;
3025 + char *err;
3026 + int def;
3027 + union {
3028 + struct { /* range_option info */
3029 + int min;
3030 + int max;
3031 + } r;
3032 + struct { /* list_option info */
3033 + int nr;
3034 + struct atl2_opt_list { int i; char *str; } *p;
3035 + } l;
3036 + } arg;
3037 +};
3038 +
3039 +static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
3040 +{
3041 + int i;
3042 + struct atl2_opt_list *ent;
3043 +
3044 + if(*value == OPTION_UNSET) {
3045 + *value = opt->def;
3046 + return 0;
3047 + }
3048 +
3049 + switch (opt->type) {
3050 + case enable_option:
3051 + switch (*value) {
3052 + case OPTION_ENABLED:
3053 + printk(KERN_INFO "%s Enabled\n", opt->name);
3054 + return 0;
3055 + break;
3056 + case OPTION_DISABLED:
3057 + printk(KERN_INFO "%s Disabled\n", opt->name);
3058 + return 0;
3059 + break;
3060 + }
3061 + break;
3062 + case range_option:
3063 + if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
3064 + printk(KERN_INFO "%s set to %i\n", opt->name, *value);
3065 + return 0;
3066 + }
3067 + break;
3068 + case list_option:
3069 + for(i = 0; i < opt->arg.l.nr; i++) {
3070 + ent = &opt->arg.l.p[i];
3071 + if(*value == ent->i) {
3072 + if(ent->str[0] != '\0')
3073 + printk(KERN_INFO "%s\n", ent->str);
3074 + return 0;
3075 + }
3076 + }
3077 + break;
3078 + default:
3079 + BUG();
3080 + }
3081 +
3082 + printk(KERN_INFO "Invalid %s specified (%i) %s\n",
3083 + opt->name, *value, opt->err);
3084 + *value = opt->def;
3085 + return -1;
3086 +}
3087 +
3088 +/*
3089 + * atl2_check_options - Range Checking for Command Line Parameters
3090 + * @adapter: board private structure
3091 + *
3092 + * This routine checks all command line parameters for valid user
3093 + * input. If an invalid value is given, or if no user specified
3094 + * value exists, a default value is used. The final value is stored
3095 + * in a variable in the adapter structure.
3096 + */
3097 +void __devinit atl2_check_options(struct atl2_adapter *adapter)
3098 +{
3099 + int val;
3100 + struct atl2_option opt;
3101 + int bd = adapter->bd_number;
3102 + if(bd >= ATL2_MAX_NIC) {
3103 + printk(KERN_NOTICE "Warning: no configuration for board #%i\n", bd);
3104 + printk(KERN_NOTICE "Using defaults for all values\n");
3105 +#ifndef module_param_array
3106 + bd = ATL2_MAX_NIC;
3107 +#endif
3108 + }
3109 +
3110 + /* Bytes of Transmit Memory */
3111 + opt.type = range_option;
3112 + opt.name = "Bytes of Transmit Memory";
3113 + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3114 + opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3115 + opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3116 + opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3117 +#ifdef module_param_array
3118 + if(num_TxMemSize > bd) {
3119 +#endif
3120 + val = TxMemSize[bd];
3121 + atl2_validate_option(&val, &opt);
3122 + adapter->txd_ring_size = ((u32) val) * 1024;
3123 +#ifdef module_param_array
3124 + } else {
3125 + adapter->txd_ring_size = ((u32)opt.def) * 1024;
3126 + }
3127 +#endif
3128 + // txs ring size:
3129 + adapter->txs_ring_size = adapter->txd_ring_size / 128;
3130 + if (adapter->txs_ring_size > 160)
3131 + adapter->txs_ring_size = 160;
3132 +
3133 + /* Receive Memory Block Count */
3134 + opt.type = range_option;
3135 + opt.name = "Number of receive memory block";
3136 + opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3137 + opt.def = ATL2_DEFAULT_RXD_COUNT;
3138 + opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3139 + opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3140 +#ifdef module_param_array
3141 + if(num_RxMemBlock > bd) {
3142 +#endif
3143 + val = RxMemBlock[bd];
3144 + atl2_validate_option(&val, &opt);
3145 + adapter->rxd_ring_size = (u32)val; //((u16)val)&~1; // even number
3146 +#ifdef module_param_array
3147 + } else {
3148 + adapter->rxd_ring_size = (u32)opt.def;
3149 + }
3150 +#endif
3151 + // init RXD Flow control value
3152 + adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size/8)*7;
3153 + adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT/8) > (adapter->rxd_ring_size/12) ?
3154 + (ATL2_MIN_RXD_COUNT/8) : (adapter->rxd_ring_size/12);
3155 +
3156 + /* Interrupt Moderate Timer */
3157 + opt.type = range_option;
3158 + opt.name = "Interrupt Moderate Timer";
3159 + opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3160 + opt.def = INT_MOD_DEFAULT_CNT;
3161 + opt.arg.r.min = INT_MOD_MIN_CNT;
3162 + opt.arg.r.max = INT_MOD_MAX_CNT;
3163 +#ifdef module_param_array
3164 + if(num_IntModTimer > bd) {
3165 +#endif
3166 + val = IntModTimer[bd];
3167 + atl2_validate_option(&val, &opt);
3168 + adapter->imt = (u16) val;
3169 +#ifdef module_param_array
3170 + } else {
3171 + adapter->imt = (u16)(opt.def);
3172 + }
3173 +#endif
3174 + /* Flash Vendor */
3175 + opt.type = range_option;
3176 + opt.name = "SPI Flash Vendor";
3177 + opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3178 + opt.def = FLASH_VENDOR_DEFAULT;
3179 + opt.arg.r.min = FLASH_VENDOR_MIN;
3180 + opt.arg.r.max = FLASH_VENDOR_MAX;
3181 +#ifdef module_param_array
3182 + if(num_FlashVendor > bd) {
3183 +#endif
3184 + val = FlashVendor[bd];
3185 + atl2_validate_option(&val, &opt);
3186 + adapter->hw.flash_vendor = (u8) val;
3187 +#ifdef module_param_array
3188 + } else {
3189 + adapter->hw.flash_vendor = (u8)(opt.def);
3190 + }
3191 +#endif
3192 + /* MediaType */
3193 + opt.type = range_option;
3194 + opt.name = "Speed/Duplex Selection";
3195 + opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3196 + opt.def = MEDIA_TYPE_AUTO_SENSOR;
3197 + opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3198 + opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3199 +#ifdef module_param_array
3200 + if(num_MediaType > bd) {
3201 +#endif
3202 + val = MediaType[bd];
3203 + atl2_validate_option(&val, &opt);
3204 + adapter->hw.MediaType = (u16) val;
3205 +#ifdef module_param_array
3206 + } else {
3207 + adapter->hw.MediaType = (u16)(opt.def);
3208 + }
3209 +#endif
3210 +}
3211 diff --git a/drivers/net/atlx/atl2.h b/drivers/net/atlx/atl2.h
3212 new file mode 100644
3213 index 0000000..32732f9
3214 --- /dev/null
3215 +++ b/drivers/net/atlx/atl2.h
3216 @@ -0,0 +1,894 @@
3217 +/* atl2.h -- atl2 driver definitions
3218 + *
3219 + * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3220 + * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com>
3221 + * Copyright(c) 2007 Chris Snook <csnook@redhat.com>
3222 + *
3223 + * Derived from Intel e1000 driver
3224 + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
3225 + *
3226 + * This program is free software; you can redistribute it and/or modify it
3227 + * under the terms of the GNU General Public License as published by the Free
3228 + * Software Foundation; either version 2 of the License, or (at your option)
3229 + * any later version.
3230 + *
3231 + * This program is distributed in the hope that it will be useful, but WITHOUT
3232 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3233 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3234 + * more details.
3235 + *
3236 + * You should have received a copy of the GNU General Public License along with
3237 + * this program; if not, write to the Free Software Foundation, Inc., 59
3238 + * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3239 + */
3240 +
3241 +#ifndef _ATL2_H_
3242 +#define _ATL2_H_
3243 +
3244 +#include <asm/atomic.h>
3245 +#include <linux/netdevice.h>
3246 +
3247 +#ifndef _ATL2_HW_H_
3248 +#define _ATL2_HW_H_
3249 +
3250 +#ifndef _ATL2_OSDEP_H_
3251 +#define _ATL2_OSDEP_H_
3252 +
3253 +#include <linux/pci.h>
3254 +#include <linux/delay.h>
3255 +#include <linux/interrupt.h>
3256 +#include <linux/if_ether.h>
3257 +
3258 +#define usec_delay(x) udelay(x)
3259 +#ifndef msec_delay
3260 +#define msec_delay(x) do { \
3261 + if(in_interrupt()) BUG(); \
3262 + else msleep(x); \
3263 + } while (0)
3264 +
3265 +/* Some workarounds require millisecond delays and are run during interrupt
3266 + * context. Most notably, when establishing link, the phy may need tweaking
3267 + * but cannot process phy register reads/writes faster than millisecond
3268 + * intervals...and we establish link due to a "link status change" interrupt.
3269 + */
3270 +#define msec_delay_irq(x) mdelay(x)
3271 +#endif
3272 +
3273 +#define PCI_COMMAND_REGISTER PCI_COMMAND
3274 +#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
3275 +#define ETH_ADDR_LEN ETH_ALEN
3276 +
3277 +#define ATL2_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + reg)))
3278 +
3279 +#define ATL2_WRITE_FLUSH(a) (readl((a)->hw_addr))
3280 +
3281 +#define ATL2_READ_REG(a, reg) (readl((a)->hw_addr + reg))
3282 +
3283 +#define ATL2_WRITE_REGB(a, reg, value) (writeb((value), ((a)->hw_addr + reg)))
3284 +
3285 +#define ATL2_READ_REGB(a, reg) (readb((a)->hw_addr + reg))
3286 +
3287 +#define ATL2_WRITE_REGW(a, reg, value) (writew((value), ((a)->hw_addr + reg)))
3288 +
3289 +#define ATL2_READ_REGW(a, reg) (readw((a)->hw_addr + reg))
3290 +
3291 +#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \
3292 + (writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
3293 +
3294 +#define ATL2_READ_REG_ARRAY(a, reg, offset) \
3295 + (readl(((a)->hw_addr + reg) + ((offset) << 2)))
3296 +
3297 +#endif /* _ATL2_OSDEP_H_ */
3298 +
3299 +struct atl2_adapter;
3300 +struct atl2_hw;
3301 +
3302 +/* function prototype */
3303 +s32 atl2_reset_hw(struct atl2_hw *hw);
3304 +s32 atl2_read_mac_addr(struct atl2_hw *hw);
3305 +s32 atl2_init_hw(struct atl2_hw *hw);
3306 +s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, u16 *duplex);
3307 +u32 atl2_auto_get_fc(struct atl2_adapter *adapter, u16 duplex);
3308 +u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr);
3309 +void atl2_hash_set(struct atl2_hw *hw, u32 hash_value);
3310 +s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data);
3311 +s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data);
3312 +void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
3313 +void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
3314 +s32 atl2_validate_mdi_setting(struct atl2_hw *hw);
3315 +void atl2_set_mac_addr(struct atl2_hw *hw);
3316 +bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
3317 +bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value);
3318 +s32 atl2_phy_init(struct atl2_hw *hw);
3319 +int atl2_check_eeprom_exist(struct atl2_hw *hw);
3320 +void atl2_force_ps(struct atl2_hw *hw);
3321 +
3322 +/* register definition */
3323 +#define REG_PM_CTRLSTAT 0x44
3324 +
3325 +#define REG_PCIE_CAP_LIST 0x58
3326 +
3327 +#define REG_VPD_CAP 0x6C
3328 +#define VPD_CAP_ID_MASK 0xff
3329 +#define VPD_CAP_ID_SHIFT 0
3330 +#define VPD_CAP_NEXT_PTR_MASK 0xFF
3331 +#define VPD_CAP_NEXT_PTR_SHIFT 8
3332 +#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
3333 +#define VPD_CAP_VPD_ADDR_SHIFT 16
3334 +#define VPD_CAP_VPD_FLAG 0x80000000
3335 +
3336 +#define REG_VPD_DATA 0x70
3337 +
3338 +#define REG_SPI_FLASH_CTRL 0x200
3339 +#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
3340 +#define SPI_FLASH_CTRL_STS_WEN 0x2
3341 +#define SPI_FLASH_CTRL_STS_WPEN 0x80
3342 +#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
3343 +#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
3344 +#define SPI_FLASH_CTRL_INS_MASK 0x7
3345 +#define SPI_FLASH_CTRL_INS_SHIFT 8
3346 +#define SPI_FLASH_CTRL_START 0x800
3347 +#define SPI_FLASH_CTRL_EN_VPD 0x2000
3348 +#define SPI_FLASH_CTRL_LDSTART 0x8000
3349 +#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
3350 +#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
3351 +#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
3352 +#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
3353 +#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
3354 +#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
3355 +#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
3356 +#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
3357 +#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
3358 +#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
3359 +#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
3360 +#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
3361 +#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
3362 +
3363 +#define REG_SPI_ADDR 0x204
3364 +
3365 +#define REG_SPI_DATA 0x208
3366 +
3367 +#define REG_SPI_FLASH_CONFIG 0x20C
3368 +#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
3369 +#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
3370 +#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
3371 +#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
3372 +#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
3373 +
3374 +#define REG_SPI_FLASH_OP_PROGRAM 0x210
3375 +#define REG_SPI_FLASH_OP_SC_ERASE 0x211
3376 +#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
3377 +#define REG_SPI_FLASH_OP_RDID 0x213
3378 +#define REG_SPI_FLASH_OP_WREN 0x214
3379 +#define REG_SPI_FLASH_OP_RDSR 0x215
3380 +#define REG_SPI_FLASH_OP_WRSR 0x216
3381 +#define REG_SPI_FLASH_OP_READ 0x217
3382 +
3383 +#define REG_TWSI_CTRL 0x218
3384 +#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
3385 +#define TWSI_CTRL_LD_OFFSET_SHIFT 0
3386 +#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
3387 +#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
3388 +#define TWSI_CTRL_SW_LDSTART 0x800
3389 +#define TWSI_CTRL_HW_LDSTART 0x1000
3390 +#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
3391 +#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
3392 +#define TWSI_CTRL_LD_EXIST 0x400000
3393 +#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
3394 +#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
3395 +#define TWSI_CTRL_FREQ_SEL_100K 0
3396 +#define TWSI_CTRL_FREQ_SEL_200K 1
3397 +#define TWSI_CTRL_FREQ_SEL_300K 2
3398 +#define TWSI_CTRL_FREQ_SEL_400K 3
3399 +#define TWSI_CTRL_SMB_SLV_ADDR
3400 +#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
3401 +#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
3402 +
3403 +#define REG_PCIE_DEV_MISC_CTRL 0x21C
3404 +#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
3405 +#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
3406 +#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
3407 +#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
3408 +#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
3409 +
3410 +#define REG_PCIE_PHYMISC 0x1000
3411 +#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
3412 +
3413 +#define REG_PCIE_DLL_TX_CTRL1 0x1104
3414 +#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x0400
3415 +#define PCIE_DLL_TX_CTRL1_DEF 0x0568
3416 +
3417 +#define REG_LTSSM_TEST_MODE 0x12FC
3418 +#define LTSSM_TEST_MODE_DEF 0x6500
3419 +
3420 +/* Master Control Register */
3421 +#define REG_MASTER_CTRL 0x1400
3422 +#define MASTER_CTRL_SOFT_RST 0x1
3423 +#define MASTER_CTRL_MTIMER_EN 0x2
3424 +#define MASTER_CTRL_ITIMER_EN 0x4
3425 +#define MASTER_CTRL_MANUAL_INT 0x8
3426 +#define MASTER_CTRL_REV_NUM_SHIFT 16
3427 +#define MASTER_CTRL_REV_NUM_MASK 0xff
3428 +#define MASTER_CTRL_DEV_ID_SHIFT 24
3429 +#define MASTER_CTRL_DEV_ID_MASK 0xff
3430 +
3431 +/* Timer Initial Value Register */
3432 +#define REG_MANUAL_TIMER_INIT 0x1404
3433 +
3434 +/* IRQ ModeratorTimer Initial Value Register */
3435 +#define REG_IRQ_MODU_TIMER_INIT 0x1408
3436 +
3437 +#define REG_PHY_ENABLE 0x140C
3438 +// IRQ Anti-Lost Timer Initial Value Register
3439 +//#define REG_IRQ_CLR_TIMER 0x140c // Maximum allowance for software to clear the interrupt.
3440 +// IRQ Anti-Lost Timer Initial Value Register
3441 +#define REG_CMBDISDMA_TIMER 0x140E
3442 +
3443 +/* Block IDLE Status Register */
3444 +#define REG_IDLE_STATUS 0x1410
3445 +#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
3446 +#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
3447 +#define IDLE_STATUS_DMAR 8 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
3448 +#define IDLE_STATUS_DMAW 4 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
3449 +
3450 +/* MDIO Control Register */
3451 +#define REG_MDIO_CTRL 0x1414
3452 +#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
3453 +#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register. */
3454 +#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
3455 +#define MDIO_REG_ADDR_SHIFT 16
3456 +#define MDIO_RW 0x200000 /* 1: read, 0: write */
3457 +#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
3458 +#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle. */
3459 +#define MDIO_CLK_SEL_SHIFT 24
3460 +#define MDIO_CLK_25_4 0
3461 +#define MDIO_CLK_25_6 2
3462 +#define MDIO_CLK_25_8 3
3463 +#define MDIO_CLK_25_10 4
3464 +#define MDIO_CLK_25_14 5
3465 +#define MDIO_CLK_25_20 6
3466 +#define MDIO_CLK_25_28 7
3467 +#define MDIO_BUSY 0x8000000
3468 +#define MDIO_WAIT_TIMES 10
3469 +
3470 +/* SerDes Lock Detect Control and Status Register */
3471 +#define REG_SERDES_LOCK 0x1424
3472 +#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected. This signal comes from Analog SerDes. */
3473 +#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function. */
3474 +
3475 +/* MAC Control Register */
3476 +#define REG_MAC_CTRL 0x1480
3477 +#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
3478 +#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
3479 +#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
3480 +#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
3481 +#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
3482 +#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
3483 +#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
3484 +#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
3485 +#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length, it's 0x07 by standard */
3486 +#define MAC_CTRL_PRMLEN_MASK 0xf
3487 +#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
3488 +#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
3489 +#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: transmit maximum backoff (half-duplex test bit) */
3490 +#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
3491 +#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
3492 +#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: MAC-LoopBack clock from phy, 0:from sys_25M */
3493 +#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28
3494 +#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* When half-duplex mode, should hold some bytes for mac retry . (8*4bytes unit) */
3495 +
3496 +/* MAC IPG/IFG Control Register */
3497 +#define REG_MAC_IPG_IFG 0x1484
3498 +#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time. */
3499 +#define MAC_IPG_IFG_IPGT_MASK 0x7f
3500 +#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames. */
3501 +#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped. */
3502 +#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
3503 +#define MAC_IPG_IFG_IPGR1_MASK 0x7f
3504 +#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
3505 +#define MAC_IPG_IFG_IPGR2_MASK 0x7f
3506 +
3507 +/* MAC STATION ADDRESS */
3508 +#define REG_MAC_STA_ADDR 0x1488
3509 +
3510 +/* Hash table for multicast address */
3511 +#define REG_RX_HASH_TABLE 0x1490
3512 +
3513 +/* MAC Half-Duplex Control Register */
3514 +#define REG_MAC_HALF_DUPLX_CTRL 0x1498
3515 +#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window. */
3516 +#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
3517 +#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded. */
3518 +#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
3519 +#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
3520 +#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission. */
3521 +#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
3522 +#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
3523 +#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number. */
3524 +#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
3525 +#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
3526 +#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time. */
3527 +
3528 +/* Maximum Frame Length Control Register */
3529 +#define REG_MTU 0x149c
3530 +
3531 +/* Wake-On-Lan control register */
3532 +#define REG_WOL_CTRL 0x14a0
3533 +#define WOL_PATTERN_EN 0x00000001
3534 +#define WOL_PATTERN_PME_EN 0x00000002
3535 +#define WOL_MAGIC_EN 0x00000004
3536 +#define WOL_MAGIC_PME_EN 0x00000008
3537 +#define WOL_LINK_CHG_EN 0x00000010
3538 +#define WOL_LINK_CHG_PME_EN 0x00000020
3539 +#define WOL_PATTERN_ST 0x00000100
3540 +#define WOL_MAGIC_ST 0x00000200
3541 +#define WOL_LINKCHG_ST 0x00000400
3542 +#define WOL_PT0_EN 0x00010000
3543 +#define WOL_PT1_EN 0x00020000
3544 +#define WOL_PT2_EN 0x00040000
3545 +#define WOL_PT3_EN 0x00080000
3546 +#define WOL_PT4_EN 0x00100000
3547 +#define WOL_PT0_MATCH 0x01000000
3548 +#define WOL_PT1_MATCH 0x02000000
3549 +#define WOL_PT2_MATCH 0x04000000
3550 +#define WOL_PT3_MATCH 0x08000000
3551 +#define WOL_PT4_MATCH 0x10000000
3552 +
3553 +/* Internal SRAM Partition Register */
3554 +#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM default: 2byte*1024 */
3555 +#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM default: 2byte*102