{"payload":{"header_redesign_enabled":false,"results":[{"id":"68850972","archived":false,"color":"#b2b7f8","followers":442,"has_funding_file":false,"hl_name":"ZipCPU/wb2axip","hl_trunc_description":"Bus bridges and other odds and ends","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":68850972,"name":"wb2axip","owner_id":22348544,"owner_login":"ZipCPU","updated_at":"2024-01-12T21:08:36.485Z","has_issues":true}},"sponsorable":false,"topics":["fpga","gplv3","xilinx","wishbone","xilinx-vivado","wishbone-bus","axi-bus"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":67,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AZipCPU%252Fwb2axip%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ZipCPU/wb2axip/star":{"post":"FET-q7XGZwfq9fTOGCjZuwFNsR8B_4Fdiepvw9iug1L4dWZ2X5cWnQFZLhBx7BS5gDV-9qaFxxPl_YwkCgGHcQ"},"/ZipCPU/wb2axip/unstar":{"post":"HXCNOeA78UlM5eMD98jC4k4pslQJgB5WRxvY_QaTj_ynH2kptRck5h253yFUAWA-PPo2ylyxGOrtSTVX6NmetA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"rKxR_FokKvG_x40SrilIPKt9kLUBfvwz8ysaEXuj3E2oGsFPJIwQPtXcQp1SzBwLYGo7bPp-SKkuZefQ8dvoww"}}},"title":"Repository search results"}