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A fully functional MIPS simulator in python — Read more

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http://brianreily.com/projects/mips_simulator

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updated status 
Brian Reily (author)
Mon Oct 13 03:53:48 -0700 2008
commit  7b5130e82e8f24c30e6d5dd2e9c59e828008d41c
tree    0a0b435f2d0e0af80d98ba59793e5e6c0d4074ff
parent  da9fce2015d6d114f4efbb1bdd642bf1b28eec93
mipspy /
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file README Loading commit data...
file simulator.py
README
MIPSpy - A MIPS Simulator
=========================

    * by:  brian reily
    * url: http://brianreily.com/projects/mips_simulator

status
------
    * MIPSpy was written a while ago and just moved to github
      recently for safekeeping.  There may be a few bugs left
      but it is not being actively developed/maintained.

usage
-----
    * sample session:
        >>> import simulator
        >>> # Defaults are verbose=False, mem=1000, pc=0
        >>> s = simulator.Simulator()

        >>> s.run_line('line of code')
        >>> s.run_lines( ['line', 'line', 'line'] )

        >>> s.status()                  # show register, data, and pc status

        >>> s.get_register('$t0')       # manually retrieve a register value
        >>> s.get_register('$8')
        >>> s.get_register(9)

        >>> s.registers['$v0'] = 4      # manually set a register value
        >>> s.data[4] = 42              # manually set a data value

        >>> s.rerun()                   # reruns all previous instructions
        >>> s.instructions              # shows instructions in memory

        >>> s.reset()                   # reset all registers, data, pc

    * verbose mode will basically comment your code, as it shows you
      the starting values of operands, the operation, and then the ending
      values:
        >>> s.run_line('addi $t0, $0, 4')
        0: addi $t0, $0, 4      # $t0 = 0 + 4 = 4
        >>> s.run_line('addi $t0, $t0, 4')
        1: addi $t0, $t0, 4     # $t0 = 4 + 4 = 8

    * to read from a file:
        >>> s = simulator.Simulator()
        >>> s.run_lines( open(file, 'r').readlines() )

supported operations
--------------------
    syscall, j, b, jr, beq, bne, lw, sw, slt, slti, add, addi,
    sub, subi, and, andi, or, ori, sll, sllv, srl, srlv, div,
    mul, xor, xori, move

caveats
-------
    * div and mul are three register instructions like add and sub.

    * no memory addresses are assigned; memory is instead implemented
      as a list - this makes it very easy to test MIPS code but is bad
      if you need to use it for class.

    * there is no .data section - right now you have to manually input 
      your .data section using 'Simulator.data[index] = value'

issues
------
    * verbose mode seems to be a bit buggy, trying to track it down.
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