From 6aee3262885203352255d9777e1f6710f236543d Mon Sep 17 00:00:00 2001 From: Efe Yigitbasi Date: Wed, 2 Jun 2021 16:44:59 +0200 Subject: [PATCH 1/2] Changed OMTF inputs to fix missing muon in re-emulation (cherry picked from commit 87a8f4f94e02c2d102805ec4f40aa15205659c4f) --- L1Trigger/Configuration/python/customiseReEmul.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/L1Trigger/Configuration/python/customiseReEmul.py b/L1Trigger/Configuration/python/customiseReEmul.py index c26b3579249b6..22059db3e1429 100644 --- a/L1Trigger/Configuration/python/customiseReEmul.py +++ b/L1Trigger/Configuration/python/customiseReEmul.py @@ -261,6 +261,14 @@ def L1TReEmulMCFromRAW(process): L1TReEmulFromRAW(process) stage2L1Trigger.toModify(process.simEmtfDigis, CSCInput = 'simCscTriggerPrimitiveDigis:MPCSORTED') stage2L1Trigger.toModify(process.simOmtfDigis, srcCSC = 'simCscTriggerPrimitiveDigis:MPCSORTED') + + # Temporary fix for OMTF inputs in MC re-emulation + run3_GEM.toModify(process.simOmtfDigis, + srcRPC = 'muonRPCDigis', + srcDTPh = 'bmtfDigis', + srcDTTh = 'bmtfDigis' + ) + return process def L1TReEmulMCFromRAWSimEcalTP(process): From a2620dabac825604682792f193cf0fcad0bec32b Mon Sep 17 00:00:00 2001 From: Efe Yigitbasi Date: Thu, 3 Jun 2021 17:43:30 +0200 Subject: [PATCH 2/2] Changing OMTF DT inputs to simDtTriggerPrimitiveDigis and fixing simDtTriggerPrimitiveDigis input (cherry picked from commit 1479a2959bd03b0f7a34a67ceb5f2fe66f67d493) --- L1Trigger/Configuration/python/customiseReEmul.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/L1Trigger/Configuration/python/customiseReEmul.py b/L1Trigger/Configuration/python/customiseReEmul.py index 22059db3e1429..b88f182ac324a 100644 --- a/L1Trigger/Configuration/python/customiseReEmul.py +++ b/L1Trigger/Configuration/python/customiseReEmul.py @@ -61,7 +61,7 @@ def L1TReEmulFromRAW2015(process): cms.InputTag('hcalDigis') ) process.L1TReEmul = cms.Sequence(process.simEcalTriggerPrimitiveDigis * process.simHcalTriggerPrimitiveDigis * process.SimL1Emulator) - process.simDtTriggerPrimitiveDigis.digiTag = 'muonDTDigis' + process.simDtTriggerPrimitiveDigis.digiTag = 'muonDTDigis' process.simCscTriggerPrimitiveDigis.CSCComparatorDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCComparatorDigi') process.simCscTriggerPrimitiveDigis.CSCWireDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCWireDigi' ) @@ -131,6 +131,7 @@ def L1TReEmulFromRAW2016(process): cms.InputTag('hcalDigis'), cms.InputTag('hcalDigis') ) + process.simDtTriggerPrimitiveDigis.digiTag = cms.InputTag("muonDTDigis") process.simCscTriggerPrimitiveDigis.CSCComparatorDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCComparatorDigi') process.simCscTriggerPrimitiveDigis.CSCWireDigiProducer = cms.InputTag( 'muonCSCDigis', 'MuonCSCWireDigi' ) process.L1TReEmul = cms.Sequence(process.simEcalTriggerPrimitiveDigis * process.simHcalTriggerPrimitiveDigis * process.SimL1Emulator) @@ -265,8 +266,8 @@ def L1TReEmulMCFromRAW(process): # Temporary fix for OMTF inputs in MC re-emulation run3_GEM.toModify(process.simOmtfDigis, srcRPC = 'muonRPCDigis', - srcDTPh = 'bmtfDigis', - srcDTTh = 'bmtfDigis' + srcDTPh = 'simDtTriggerPrimitiveDigis', + srcDTTh = 'simDtTriggerPrimitiveDigis' ) return process