This repo contains example designs for the Opsero 96B Quad Ethernet Mezzanine board when used with the Avnet Ultra96 v1 and v2.
Important links:
- Datasheet and user guide for this project is hosted here: 96B Quad Ethernet Mezzanine documentation.
- To report a bug: Report an issue.
- For technical support: Contact Opsero.
- To purchase the mezzanine card: 96B Quad Ethernet Mezzanine order page.
This project is designed for Vivado 2020.2. If you are using an older version of the Xilinx tools, then refer to the release tags to find the version of this repository that matches your version of the tools.
- Vivado 2020.2
- Vitis 2020.2 (for standalone lwIP echo server)
- PetaLinux Tools 2020.2
- 96B Quad Ethernet Mezzanine
- Ultra96 v1 or v2
- For designs containing AXI Ethernet Subsystem IP: Xilinx Soft TEMAC license
- Ultra96 board files (see install instructions)
These are the different projects in the repo at the moment.
- AXI Ethernet (axi-eth):
- Uses soft AXI Ethernet IP to implement the MAC
- Uses PCS/PMA or SGMII IP to implement the SGMII over LVDS links
- Uses 625MHz clock from port 3 PHY, shared logic in SGMII core for port 3 RX
- All 4 ports have been tested on hardware with lwIP echo server and PetaLinux
- PS GEM (ps-gem):
- Uses PS integrated Gigabit Ethernet MACs (GEM)
- Uses PCS/PMA or SGMII IP to implement the SGMII over LVDS links
- Uses 625MHz clock from port 3 PHY, shared logic in SGMII core for ports 0 and 1
- All 4 ports have been tested on hardware with lwIP echo server and PetaLinux
For build and usage instructions, please refer to the Getting Started section of the user guide:
Getting started with the 96B Quad Ethernet Mezzanine
For questions or technical support, please contact Opsero or report an issue on the Github repo:
We welcome your contributions! If you would like to add something to the example designs, or you have fixed an issue, please make a pull request.