gps-sdr / gps-sdr

Open source GPS receiver based on USRP and GN3S

This URL has Read+Write access

gps-sdr / usrp / fpga_regs_common.h
raw normal view history
24362b52 » Gregory W. Heckler 2009-05-21 Hurrah! It all works. Will ... 1 /* -*- c++ -*- */
2 /*
3 * Copyright 2003,2004 Free Software Foundation, Inc.
4 *
5 * This file is part of GNU Radio
6 *
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
10 * any later version.
11 *
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
21 */
22 #ifndef INCLUDED_FPGA_REGS_COMMON_H
23 #define INCLUDED_FPGA_REGS_COMMON_H
24
25 // This file defines registers common to all FPGA configurations.
26 // Registers 0 to 31 are reserved for use in this file.
27
28
29 // The FPGA needs to know the rate that samples are coming from and
30 // going to the A/D's and D/A's. div = 128e6 / sample_rate
31
32 #define FR_TX_SAMPLE_RATE_DIV 0
33 #define FR_RX_SAMPLE_RATE_DIV 1
34
35 // 2 and 3 are defined in the ATR section
36
37 #define FR_MASTER_CTRL 4 // master enable and reset controls
38 # define bmFR_MC_ENABLE_TX (1 << 0)
39 # define bmFR_MC_ENABLE_RX (1 << 1)
40 # define bmFR_MC_RESET_TX (1 << 2)
41 # define bmFR_MC_RESET_RX (1 << 3)
42
43 // i/o direction registers for pins that go to daughterboards.
44 // Setting the bit makes it an output from the FPGA to the d'board.
45 // top 16 is mask, low 16 is value
46
47 #define FR_OE_0 5 // slot 0
48 #define FR_OE_1 6
49 #define FR_OE_2 7
50 #define FR_OE_3 8
51
52 // i/o registers for pins that go to daughterboards.
53 // top 16 is a mask, low 16 is value
54
55 #define FR_IO_0 9 // slot 0
56 #define FR_IO_1 10
57 #define FR_IO_2 11
58 #define FR_IO_3 12
59
60 #define FR_MODE 13
61 # define bmFR_MODE_NORMAL 0
62 # define bmFR_MODE_LOOPBACK (1 << 0) // enable digital loopback
63 # define bmFR_MODE_RX_COUNTING (1 << 1) // Rx is counting
64 # define bmFR_MODE_RX_COUNTING_32BIT (1 << 2) // Rx is counting with a 32 bit counter
65 // low and high 16 bits are multiplexed across channel I and Q
66
67
68 // If the corresponding bit is set, internal FPGA debug circuitry
69 // controls the i/o pins for the associated bank of daughterboard
70 // i/o pins. Typically used for debugging FPGA designs.
71
72 #define FR_DEBUG_EN 14
73 # define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
74 # define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
75 # define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
76 # define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o
77
78
79 // If the corresponding bit is set, enable the automatic DC
80 // offset correction control loop.
81 //
82 // The 4 low bits are significant:
83 //
84 // ADC0 = (1 << 0)
85 // ADC1 = (1 << 1)
86 // ADC2 = (1 << 2)
87 // ADC3 = (1 << 3)
88 //
89 // This control loop works if the attached daugherboard blocks DC.
90 // Currently all daughterboards do block DC. This includes:
91 // basic rx, dbs_rx, tv_rx, flex_xxx_rx.
92
93 #define FR_DC_OFFSET_CL_EN 15 // DC Offset Control Loop Enable
94
95
96 // offset corrections for ADC's and DAC's (2's complement)
97
98 #define FR_ADC_OFFSET_0 16
99 #define FR_ADC_OFFSET_1 17
100 #define FR_ADC_OFFSET_2 18
101 #define FR_ADC_OFFSET_3 19
102
103
104 // ------------------------------------------------------------------------
105 // Automatic Transmit/Receive switching
106 //
107 // If automatic transmit/receive (ATR) switching is enabled in the
108 // FR_ATR_CTL register, the presence or absence of data in the FPGA
109 // transmit fifo selects between two sets of values for each of the 4
110 // banks of daughterboard i/o pins.
111 //
112 // Each daughterboard slot has 3 16-bit registers associated with it:
113 // FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
114 //
115 // FR_ATR_MASK_{0,1,2,3}:
116 //
117 // These registers determine which of the daugherboard i/o pins are
118 // affected by ATR switching. If a bit in the mask is set, the
119 // corresponding i/o bit is controlled by ATR, else it's output
120 // value comes from the normal i/o pin output register:
121 // FR_IO_{0,1,2,3}.
122 //
123 // FR_ATR_TXVAL_{0,1,2,3}:
124 // FR_ATR_RXVAL_{0,1,2,3}:
125 //
126 // If the Tx fifo contains data, then the bits from TXVAL that are
127 // selected by MASK are output. Otherwise, the bits from RXVAL that
128 // are selected by MASK are output.
129
130 #define FR_ATR_MASK_0 20 // slot 0
131 #define FR_ATR_TXVAL_0 21
132 #define FR_ATR_RXVAL_0 22
133
134 #define FR_ATR_MASK_1 23 // slot 1
135 #define FR_ATR_TXVAL_1 24
136 #define FR_ATR_RXVAL_1 25
137
138 #define FR_ATR_MASK_2 26 // slot 2
139 #define FR_ATR_TXVAL_2 27
140 #define FR_ATR_RXVAL_2 28
141
142 #define FR_ATR_MASK_3 29 // slot 3
143 #define FR_ATR_TXVAL_3 30
144 #define FR_ATR_RXVAL_3 31
145
146 // Clock ticks to delay rising and falling edge of T/R signal
147 #define FR_ATR_TX_DELAY 2
148 #define FR_ATR_RX_DELAY 3
149
150 #endif /* INCLUDED_FPGA_REGS_COMMON_H */