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pc6001.cpp
1987 lines (1674 loc) · 79 KB
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pc6001.cpp
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// license:BSD-3-Clause
// copyright-holders:Angelo Salese
/**************************************************************************************************
PC-6001 series (c) 1981 NEC
driver by Angelo Salese
TODO:
- Move MCU HLE simulation in a device or even make an handcrafted LLE version
(assuming we'll never get the MCS48 dump). Additionally remove the 8255 hacks;
- Proper support for .cas/.wav/.p6/.p6t file formats used by the cassette interface;
- Make FDC to actually load images, also fix .dsk identification;
- Confirm irq model daisy chain behaviour, and add missing irqs and features
(namely the irq dispatch for SR mode should really honor I/O $fb and fallback to legacy
behaviour if masked);
- Several games are decidedly too fast, down to missing waitstates, no screen raw
parameters, crtkill signal and bus request;
- PC-6001mkII: refactor memory model to use address_map_bank_device;
- PC-6001mkII: confirm optional FDC used mapped at 0xd0-0xd3
(PC-6031? It looks like a 5'25 single drive with 8255 protocol, presumably earlier revision
of PC-80S31 with no dump available);
- PC-6601: current regression caused by an internal FDC sense interrupt status that expects a
DIO high that never occurs;
- PC-6601: mon r-0 type games doesn't seem to work at all on this system?
- PC-6001SR: Implement MK-2 compatibility mode via view handler(s)
(it changes the memory map to behave like the older versions);
- Merge PC-6001 video emulation with MC6847 (is it really one or rather a M5C6847P-1?);
- Pinpoint what VDG supersets PC-6001mkII and SR models really uses;
- upd7752 voice speech device needs to be properly emulated (device is currently a skeleton),
Chrith game is a good test case, it's supposed to talk before title screen;
- Video Telopper (superimposer) & TV tuner functions for later machines;
TODO (game specific):
- (several AX* games, namely Galaxy Mission Part 1/2 and others): inputs doesn't work;
- AX6 - Demo: When AY-based speech talks, other emus emulates the screen drawing to be
a solid green (plain PC-6001) or solid white (Mk2 version), but according to an
original video reference, that screen should actually some kind of weird garbage on it;
- AX6 - Powered Knight: doesn't work too well, according to the asm code it asks the
player to press either 'B' or 'C' then a number but nothing is shown on screen,
other emus behaves the same, bad dump?
(Mk2 mode 5 games)
- 3D Golf Simulation Super Version: gameplay / inputs seems broken;
- American Truck: Screen is offset at the loading screen, loading bug?
- Castle Excellent: copyright text drawing is quite bogus, scans text in vertical
instead of horizontal?
- Dezeni Land (ALL versions) / Hurry Fox 1/2: asks you to "load something", can't do it
with current cassette kludge, also, for Dezeni Land(s) keyboard irqs doesn't seem to
work too well with halt opcode execution?
- Dezeni Land 1/4: dies after loading of main program;
- Dezeni Land 2: dies at the "load something" screen with presumably wrong stack opcodes
- (MyCom BASIC games with multiple files): most of them refuses to run ... how to load them?
- Grobda: when "get ready" speech plays, screen should be full white but instead it's all
black, same issue as AX-6 Demo?
- Pac-Man / Tiny Xevious 2: gameplay is too fast (unrelated with timer irq);
- Salad no Kunino Tomato-Hime: can't start a play;
- Space Harrier: very sensitive with sub irq triggers, keyboard joy triggers doesn't work
properly (select F1 after loading), draws garbage on vanilla pc6001 and eventually crashes
MAME;
- The Black Onyx: dies when it attempts to save the character, that obviously means saving
on the tape;
- Yakyukyo / Punchball Mario: waits for an irq (fixed, wrong timer enable behaviour);
===================================================================================================
PC-6001 (1981-09):
* CPU: Z80A @ 4 MHz
* ROM: 16KB + 4KB (chargen) - no kanji
* RAM: 16KB, it can be expanded to 32KB
* Text Mode: 32x16 and 2 colors
* Graphic Modes: 64x48 (9 colors), 128x192 (4 colors), 256x192 (2 colors)
* Sound: BEEP + PSG - Optional Voice Synth Cart
* Keyboard: JIS Keyboard with 5 function keys, control key, TAB key,
HOME/CLR key, INS key, DEL key, GRAPH key, Japanese syllabary
key, page key, STOP key, and cursor key (4 directions)
* 1 cartslot, optional floppy drive, optional serial 232 port, 2
joystick ports
PC-6001 mkII (1983-07):
* CPU: Z80A @ 4 MHz
* ROM: 32KB + 16KB (chargen) + 32KB (kanji) + 16KB (Voice Synth)
* RAM: 64KB
* Text Mode: same as PC-6001 with N60-BASIC; 40x20 and 15 colors with
N60M-BASIC
* Graphic Modes: same as PC-6001 with N60-BASIC; 80x40 (15 colors),
160x200 (15 colors), 320x200 (4 colors) with N60M-BASIC
* Sound: BEEP + PSG
* Keyboard: JIS Keyboard with 5 function keys, control key, TAB key,
HOME/CLR key, INS key, DEL key, CAPS key, GRAPH key, Japanese
syllabary key, page key, mode key, STOP key, and cursor key (4
directions)
* 1 cartslot, floppy drive, optional serial 232 port, 2 joystick ports
PC-6001 mkIISR (1984-12):
* CPU: Z80A @ 3.58 MHz
* ROM: 64KB + 16KB (chargen) + 32KB (kanji) + 32KB (Voice Synth)
* RAM: 64KB
* Text Mode: same as PC-6001/PC-6001mkII with N60-BASIC; 40x20, 40x25,
80x20, 80x25 and 15 colors with N66SR-BASIC
* Graphic Modes: same as PC-6001/PC-6001mkII with N60-BASIC; 80x40 (15 colors),
320x200 (15 colors), 640x200 (15 colors) with N66SR-BASIC
* Sound: BEEP + PSG + FM
* Keyboard: JIS Keyboard with 5 function keys, control key, TAB key,
HOME/CLR key, INS key, DEL key, CAPS key, GRAPH key, Japanese
syllabary key, page key, mode key, STOP key, and cursor key (4
directions)
* 1 cartslot, floppy drive, optional serial 232 port, 2 joystick ports
info from http://www.geocities.jp/retro_zzz/machines/nec/6001/spc60.html
===================================================================================================
PC-6001 irq table:
irq vector 0x00: writes 0x00 to [$fa19] ;(unused)
irq vector 0x02: (A = 0, B = 0) tests ppi port c, does something with ay ports (plus more?) ;keyboard data ready, no kanji lock, no caps lock
irq vector 0x04: ;uart irq
irq vector 0x06: operates with $fa28, $fa2e, $fd1b ;timer irq
irq vector 0x08: tests ppi port c, puts port A to $fa1d,puts 0x02 to [$fa19] ;tape data ready
irq vector 0x0a: writes 0x00 to [$fa19] ;(unused)
irq vector 0x0c: writes 0x00 to [$fa19] ;(unused)
irq vector 0x0e: same as 2, (A = 0x03, B = 0x00) ;keyboard data ready, unknown type
irq vector 0x10: same as 2, (A = 0x03, B = 0x00) ;(unused)
irq vector 0x12: writes 0x10 to [$fa19] ;end of tape reached
irq vector 0x14: same as 2, (A = 0x00, B = 0x01) ;keyboard control irq (function keys)
irq vector 0x16: tests ppi port c, writes the result to $feca. ;joystick / sub irq trigger
irq vector 0x18: ;TVR (?)
irq vector 0x1a: ;Date
irq vector 0x1c: ;(unused)
irq vector 0x1e: ;(unused)
irq vector 0x20: ;uPD7752 voice irq
irq vector 0x22: ;VRTC (SR only?)
irq vector 0x24: ;(unused)
irq vector 0x26: ;(unused)
***************************************************************************************************/
#include "emu.h"
#include "pc6001.h"
#include "softlist_dev.h"
#define LOG_IRQ (1U << 1)
//#define VERBOSE (LOG_IRQ)
#define VERBOSE (0)
#include "logmacro.h"
#define LOGIRQ(...) LOGMASKED(LOG_IRQ, __VA_ARGS__)
inline void pc6001_state::cassette_latch_control(bool new_state)
{
// 0 -> 1 transition: send PLAY tape cmd to i8049
if((!(m_sys_latch & 8)) && new_state == true) //PLAY tape cmd
{
m_cas_switch = 1;
//m_cassette->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
//m_cassette->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
}
// 1 -> 0 transition: send STOP tape cmd to i8049
if((m_sys_latch & 8) && new_state == false) //STOP tape cmd
{
m_cas_switch = 0;
//m_cassette->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
//m_cassette->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
}
}
// TODO: this is explicitly needed for making all machines to boot
inline void pc6001_state::ppi_control_hack_w(uint8_t data)
{
if(data & 1)
m_port_c_8255 |= 1<<((data>>1)&0x07);
else
m_port_c_8255 &= ~(1<<((data>>1)&0x07));
#if 0
// this switch-case is overwritten below anyway!?
switch(data)
{
case 0x08: m_port_c_8255 |= 0x88; break;
case 0x09: m_port_c_8255 &= 0xf7; break;
case 0x0c: m_port_c_8255 |= 0x28; break;
case 0x0d: m_port_c_8255 &= 0xf7; break;
default: break;
}
#endif
m_port_c_8255 |= 0xa8;
}
inline void pc6001_state::set_subcpu_irq_vector(u8 vector_num)
{
// TODO: if anything the new vector must never override an old one
// sub CPU INT pin is directly connected to the OBFA (PC7) on PPI while WR is connected to INTRA (PC3),
// former should act as an handshake flag to inhibit further irqs until current is processed.
// (Also note tight loops in main CPU code that checks against masks 0x28 or 0x88 for I/O $92)
LOGIRQ("%s: sub CPU new irq vector old: %02x new: %02x\n", machine().describe_context(), m_sub_vector, vector_num);
m_sub_vector = vector_num;
set_irq_level(SUB_CPU_IRQ);
}
inline void pc6001_state::set_irq_level(int which)
{
m_irq_pending |= 1 << which;
m_maincpu->set_input_line(0, ASSERT_LINE);
LOGIRQ("%s: assert %d, state %02x\n", machine().describe_context(), which, m_irq_pending);
}
void pc6001_state::system_latch_w(uint8_t data)
{
static const uint16_t startaddr[] = {0xC000, 0xE000, 0x8000, 0xA000 };
m_video_base = &m_ram[startaddr[(data >> 1) & 0x03] - 0x8000];
cassette_latch_control((data & 8) == 8);
m_sys_latch = data;
m_timer_enable = !(data & 1);
set_timer_divider();
}
uint8_t pc6001_state::nec_ppi8255_r(offs_t offset)
{
if (offset==2)
return m_port_c_8255;
else if(offset==0)
{
uint8_t res;
res = m_cur_keycode;
//m_cur_keycode = 0;
return res;
}
return m_ppi->read(offset);
}
void pc6001_state::nec_ppi8255_w(offs_t offset, uint8_t data)
{
if (offset==3)
{
ppi_control_hack_w(data);
//printf("%02x\n",data);
if ((data & 0x0f) == 0x05 && m_cart_rom)
m_bank1->set_base(m_cart_rom->base() + 0x2000);
if ((data & 0x0f) == 0x04)
m_bank1->set_base(m_region_gfx1->base());
}
m_ppi->write(offset,data);
}
uint8_t pc6001_state::joystick_r()
{
uint8_t data = m_joymux->output_r();
// FIXME: bits 6 and 7 are supposed to be nHSYNC and nVSYNC
if (m_screen->hblank())
data &= 0xbf;
else
data |= 0x40;
if (m_screen->vblank())
data &= 0x7f;
else
data |= 0x80;
return data;
}
uint8_t pc6001_state::joystick_out_r()
{
return m_joystick_out;
}
void pc6001_state::joystick_out_w(uint8_t data)
{
// bit 7 is output enable for first part of 74LS367 buffer
m_joy[1]->pin_6_w(BIT(data, 7) ? 1 : BIT(data, 0));
m_joy[1]->pin_7_w(BIT(data, 7) ? 1 : BIT(data, 1));
m_joy[0]->pin_6_w(BIT(data, 7) ? 1 : BIT(data, 2));
m_joy[0]->pin_7_w(BIT(data, 7) ? 1 : BIT(data, 3));
m_joy[1]->pin_8_w(BIT(data, 4));
m_joy[0]->pin_8_w(BIT(data, 5));
m_joymux->select_w(BIT(data, 6));
m_joystick_out = data;
}
void pc6001_state::pc6001_map(address_map &map)
{
map.unmap_value_high();
map(0x0000, 0x3fff).rom().nopw();
// map(0x4000, 0x5fff) // mapped by the cartslot
map(0x6000, 0x7fff).bankr("bank1");
map(0x8000, 0xffff).ram().share("ram");
}
void pc6001_state::pc6001_io(address_map &map)
{
map.unmap_value_high();
map.global_mask(0xff);
map(0x80, 0x81).rw("uart", FUNC(i8251_device::read), FUNC(i8251_device::write));
map(0x90, 0x93).mirror(0x0c).rw(FUNC(pc6001_state::nec_ppi8255_r), FUNC(pc6001_state::nec_ppi8255_w));
map(0xa0, 0xa0).mirror(0x0c).w(m_ay, FUNC(ay8910_device::address_w));
map(0xa1, 0xa1).mirror(0x0c).w(m_ay, FUNC(ay8910_device::data_w));
map(0xa2, 0xa2).mirror(0x0c).r(m_ay, FUNC(ay8910_device::data_r));
map(0xa3, 0xa3).mirror(0x0c).nopw();
map(0xb0, 0xb0).mirror(0x0f).w(FUNC(pc6001_state::system_latch_w));
}
/*****************************************
*
* PC-6001Mk2 specific i/o
*
****************************************/
/*
ROM_REGION( 0x28000, "maincpu", ROMREGION_ERASEFF )
ROM_LOAD( "basicrom.62", 0x10000, 0x8000, CRC(950ac401) SHA1(fbf195ba74a3b0f80b5a756befc96c61c2094182) )
ROM_LOAD( "voicerom.62", 0x18000, 0x4000, CRC(49b4f917) SHA1(1a2d18f52ef19dc93da3d65f19d3abbd585628af) )
ROM_LOAD( "cgrom60.62", 0x1c000, 0x2000, CRC(81eb5d95) SHA1(53d8ae9599306ff23bf95208d2f6cc8fed3fc39f) )
ROM_LOAD( "cgrom60m.62", 0x1e000, 0x2000, CRC(3ce48c33) SHA1(f3b6c63e83a17d80dde63c6e4d86adbc26f84f79) )
ROM_LOAD( "kanjirom.62", 0x20000, 0x8000, CRC(20c8f3eb) SHA1(4c9f30f0a2ebbe70aa8e697f94eac74d8241cadd) )
*/
#define BASICROM(_v_) \
0x10000+0x2000*_v_
#define VOICEROM(_v_) \
0x18000+0x2000*_v_
#define TVROM(_v_) \
0x1c000+0x2000*_v_
#define KANJIROM(_v_) \
0x20000+0x2000*_v_
#define WRAM(_v_) \
0x28000+0x2000*_v_
#define EXWRAM(_v_) \
0x38000+0x2000*_v_
#define EXROM(_v_) \
0x48000+0x2000*_v_
#define INVALID(_v_) \
0x4c000+0x2000*_v_
// TODO: rewrite using bankdev
// TODO: some comments aren't right
static const uint32_t banksw_table_r0[0x10*4][4] = {
/* 0 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ TVROM(0), TVROM(1), VOICEROM(0), VOICEROM(1) }, //0x02: tv rom 0 & 1 / voice rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ TVROM(1), BASICROM(1), VOICEROM(0), BASICROM(3) }, //0x05: tv rom 1 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), TVROM(2), BASICROM(2), VOICEROM(1) }, //0x06: basic rom 0 & tv rom 2 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), TVROM(2), EXROM(0), VOICEROM(1) }, //0x0b: ex rom 0 & tv rom 2 / ex rom 0 & voice 1
{ TVROM(1), EXROM(0), VOICEROM(0), EXROM(0) }, //0x0c: tv rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(0), WRAM(1), WRAM(2), WRAM(3) }, //0x0d: ram 0 & 1 / ram 2 & 3
{ EXWRAM(0), EXWRAM(1), EXWRAM(2), EXWRAM(3) }, //0x0e: exram 0 & 1 / exram 2 & 3
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x0f: <invalid setting>
/* 1 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ KANJIROM(0), KANJIROM(1), KANJIROM(0), KANJIROM(1) }, //0x02: tv rom 0 & 1 / voice rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ KANJIROM(0), BASICROM(1), KANJIROM(0), BASICROM(3) }, //0x05: tv rom 1 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), KANJIROM(1), BASICROM(2), KANJIROM(1) }, //0x06: basic rom 0 & tv rom 2 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), KANJIROM(1), EXROM(0), KANJIROM(1) }, //0x0b: ex rom 0 & tv rom 2 / ex rom 0 & voice 1
{ KANJIROM(0), EXROM(0), KANJIROM(0), EXROM(0) }, //0x0c: tv rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(0), WRAM(1), WRAM(2), WRAM(3) }, //0x0d: ram 0 & 1 / ram 2 & 3
{ EXWRAM(0), EXWRAM(1), EXWRAM(2), EXWRAM(3) }, //0x0e: exram 0 & 1 / exram 2 & 3
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x0f: <invalid setting>
/* 2 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ TVROM(0), TVROM(1), VOICEROM(0), VOICEROM(1) }, //0x02: tv rom 0 & 1 / voice rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ TVROM(1), BASICROM(1), VOICEROM(0), BASICROM(3) }, //0x05: tv rom 1 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), TVROM(2), BASICROM(2), VOICEROM(1) }, //0x06: basic rom 0 & tv rom 2 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), TVROM(2), EXROM(0), VOICEROM(1) }, //0x0b: ex rom 0 & tv rom 2 / ex rom 0 & voice 1
{ TVROM(1), EXROM(0), VOICEROM(0), EXROM(0) }, //0x0c: tv rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(0), WRAM(1), WRAM(2), WRAM(3) }, //0x0d: ram 0 & 1 / ram 2 & 3
{ EXWRAM(0), EXWRAM(1), EXWRAM(2), EXWRAM(3) }, //0x0e: exram 0 & 1 / exram 2 & 3
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x0f: <invalid setting>
/* 3 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ KANJIROM(2), KANJIROM(3), KANJIROM(2), KANJIROM(3) }, //0x02: tv rom 0 & 1 / voice rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ KANJIROM(2), BASICROM(1), KANJIROM(2), BASICROM(3) }, //0x05: tv rom 1 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), KANJIROM(3), BASICROM(2), KANJIROM(3) }, //0x06: basic rom 0 & tv rom 2 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), KANJIROM(3), EXROM(0), KANJIROM(3) }, //0x0b: ex rom 0 & tv rom 2 / ex rom 0 & voice 1
{ KANJIROM(2), EXROM(0), KANJIROM(2), EXROM(0) }, //0x0c: tv rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(0), WRAM(1), WRAM(2), WRAM(3) }, //0x0d: ram 0 & 1 / ram 2 & 3
{ EXWRAM(0), EXWRAM(1), EXWRAM(2), EXWRAM(3) }, //0x0e: exram 0 & 1 / exram 2 & 3
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) } //0x0f: <invalid setting>
};
static const uint32_t banksw_table_r1[0x10*4][4] = {
/* 0 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ VOICEROM(0), VOICEROM(1), VOICEROM(0), VOICEROM(1) }, //0x02: voice rom 0 & 1 / voice rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ VOICEROM(0), BASICROM(1), VOICEROM(0), BASICROM(3) }, //0x05: voice rom 0 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), VOICEROM(1), BASICROM(2), VOICEROM(1) }, //0x06: basic rom 0 & voice rom 1 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), VOICEROM(1), EXROM(0), VOICEROM(1) }, //0x0b: ex rom 0 & voice rom 1 / ex rom 0 & voice 1
{ VOICEROM(0), EXROM(0), VOICEROM(0), EXROM(0) }, //0x0c: voice rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(4), WRAM(5), WRAM(6), WRAM(7) }, //0x0d: ram 4 & 5 / ram 6 & 7
{ EXWRAM(4), EXWRAM(5), EXWRAM(6), EXWRAM(7) }, //0x0e: exram 4 & 5 / exram 6 & 7
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x0f: <invalid setting>
/* 1 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ KANJIROM(0), KANJIROM(1), KANJIROM(0), KANJIROM(1) }, //0x02: kanji rom 0 & 1 / kanji rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ KANJIROM(0), BASICROM(1), KANJIROM(0), BASICROM(3) }, //0x05: voice rom 0 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), KANJIROM(1), BASICROM(2), KANJIROM(1) }, //0x06: basic rom 0 & voice rom 1 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), KANJIROM(1), EXROM(0), KANJIROM(1) }, //0x0b: ex rom 0 & voice rom 1 / ex rom 0 & voice 1
{ KANJIROM(0), EXROM(0), KANJIROM(0), EXROM(0) }, //0x0c: voice rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(4), WRAM(5), WRAM(6), WRAM(7) }, //0x0d: ram 4 & 5 / ram 6 & 7
{ EXWRAM(4), EXWRAM(5), EXWRAM(6), EXWRAM(7) }, //0x0e: exram 4 & 5 / exram 6 & 7
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x0f: <invalid setting>
/* 2 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ VOICEROM(0), VOICEROM(1), VOICEROM(0), VOICEROM(1) }, //0x02: voice rom 0 & 1 / voice rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ VOICEROM(0), BASICROM(1), VOICEROM(0), BASICROM(3) }, //0x05: voice rom 0 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), VOICEROM(1), BASICROM(2), VOICEROM(1) }, //0x06: basic rom 0 & voice rom 1 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), VOICEROM(1), EXROM(0), VOICEROM(1) }, //0x0b: ex rom 0 & voice rom 1 / ex rom 0 & voice 1
{ VOICEROM(0), EXROM(0), VOICEROM(0), EXROM(0) }, //0x0c: voice rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(4), WRAM(5), WRAM(6), WRAM(7) }, //0x0d: ram 4 & 5 / ram 6 & 7
{ EXWRAM(4), EXWRAM(5), EXWRAM(6), EXWRAM(7) }, //0x0e: exram 4 & 5 / exram 6 & 7
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x0f: <invalid setting>
/* 3 */
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) }, //0x00: <invalid setting>
{ BASICROM(0), BASICROM(1), BASICROM(2), BASICROM(3) }, //0x01: basic rom 0 & 1 / basic rom 2 & 3
{ KANJIROM(2), KANJIROM(3), KANJIROM(2), KANJIROM(3) }, //0x02: kanji rom 0 & 1 / kanji rom 0 & 1
{ EXROM(1), EXROM(1), EXROM(1), EXROM(1) }, //0x03: ex rom 1 & 1 / ex rom 1 & 1
{ EXROM(0), EXROM(0), EXROM(0), EXROM(0) }, //0x04: ex rom 0 & 0 / ex rom 0 & 0
{ KANJIROM(2), BASICROM(1), KANJIROM(2), BASICROM(3) }, //0x05: voice rom 0 & basic rom 1 / voice rom 0 & basic 3
{ BASICROM(0), KANJIROM(3), BASICROM(2), KANJIROM(3) }, //0x06: basic rom 0 & voice rom 1 / basic rom 2 & voice 1
{ EXROM(0), EXROM(1), EXROM(0), EXROM(1) }, //0x07: ex rom 0 & ex rom 1 / ex rom 0 & ex rom 1
{ EXROM(1), EXROM(0), EXROM(1), EXROM(0) }, //0x08: ex rom 1 & ex rom 0 / ex rom 1 & ex rom 0
{ EXROM(1), BASICROM(1), EXROM(1), BASICROM(3) }, //0x09: ex rom 1 & basic rom 1 / ex rom 1 & basic 3
{ BASICROM(0), EXROM(1), BASICROM(2), EXROM(1) }, //0x0a: basic rom 0 & ex rom 1 / basic rom 2 & ex rom 1
{ EXROM(0), KANJIROM(3), EXROM(0), KANJIROM(3) }, //0x0b: ex rom 0 & voice rom 1 / ex rom 0 & voice 1
{ KANJIROM(2), EXROM(0), KANJIROM(2), EXROM(0) }, //0x0c: voice rom 1 & ex rom 0 / voice rom 0 & ex rom 0
{ WRAM(4), WRAM(5), WRAM(6), WRAM(7) }, //0x0d: ram 4 & 5 / ram 6 & 7
{ EXWRAM(4), EXWRAM(5), EXWRAM(6), EXWRAM(7) }, //0x0e: exram 4 & 5 / exram 6 & 7
{ INVALID(0), INVALID(0), INVALID(0), INVALID(0) } //0x0f: <invalid setting>
};
void pc6001mk2_state::mk2_bank_r0_w(uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
uint8_t *gfx_data = m_region_gfx1->base();
// bankaddress = 0x10000 + (0x4000 * ((data & 0x40)>>6));
// membank(1)->set_base(&ROM[bankaddress]);
m_bank_r0 = data;
// printf("%02x BANK | %02x\n",data,m_bank_opt);
m_bank1->set_base(&ROM[banksw_table_r0[(data & 0xf)+(m_bank_opt*0x10)][0]]);
m_bank2->set_base(&ROM[banksw_table_r0[(data & 0xf)+(m_bank_opt*0x10)][1]]);
m_bank3->set_base(&ROM[banksw_table_r0[((data & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
if(!m_gfx_bank_on)
m_bank4->set_base(&ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
else
m_bank4->set_base(&gfx_data[m_cgrom_bank_addr]);
}
void pc6001mk2_state::mk2_bank_r1_w(uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
// bankaddress = 0x10000 + (0x4000 * ((data & 0x40)>>6));
// membank(1)->set_base(&ROM[bankaddress]);
m_bank_r1 = data;
// printf("%02x BANK\n",data);
m_bank5->set_base(&ROM[banksw_table_r1[(data & 0xf)+(m_bank_opt*0x10)][0]]);
m_bank6->set_base(&ROM[banksw_table_r1[(data & 0xf)+(m_bank_opt*0x10)][1]]);
m_bank7->set_base(&ROM[banksw_table_r1[((data & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
m_bank8->set_base(&ROM[banksw_table_r1[((data & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
}
void pc6001mk2_state::mk2_bank_w0_w(uint8_t data)
{
m_bank_w = data;
}
void pc6001mk2_state::mk2_opt_bank_w(uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
uint8_t *gfx_data = m_region_gfx1->base();
/*
0 - TVROM / VOICE ROM
1 - KANJI ROM bank 0
2 - KANJI ROM bank 1
3 - TVROM / VOICE ROM
*/
m_bank_opt = data & 3;
m_bank1->set_base(&ROM[banksw_table_r0[(m_bank_r0 & 0xf)+(m_bank_opt*0x10)][0]]);
m_bank2->set_base(&ROM[banksw_table_r0[(m_bank_r0 & 0xf)+(m_bank_opt*0x10)][1]]);
m_bank3->set_base(&ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
if(!m_gfx_bank_on)
m_bank4->set_base(&ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
else
m_bank4->set_base(&gfx_data[m_cgrom_bank_addr]);
m_bank4->set_base(&ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
m_bank5->set_base(&ROM[banksw_table_r1[(m_bank_r1 & 0xf)+(m_bank_opt*0x10)][0]]);
m_bank6->set_base(&ROM[banksw_table_r1[(m_bank_r1 & 0xf)+(m_bank_opt*0x10)][1]]);
m_bank7->set_base(&ROM[banksw_table_r1[((m_bank_r1 & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
m_bank8->set_base(&ROM[banksw_table_r1[((m_bank_r1 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
}
void pc6001mk2_state::mk2_work_ram0_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x01) ? WRAM(0) : EXWRAM(0))] = data;
}
void pc6001mk2_state::mk2_work_ram1_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x01) ? WRAM(1) : EXWRAM(1))] = data;
}
void pc6001mk2_state::mk2_work_ram2_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x04) ? WRAM(2) : EXWRAM(2))] = data;
}
void pc6001mk2_state::mk2_work_ram3_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x04) ? WRAM(3) : EXWRAM(3))] = data;
}
void pc6001mk2_state::mk2_work_ram4_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x10) ? WRAM(4) : EXWRAM(4))] = data;
}
void pc6001mk2_state::mk2_work_ram5_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x10) ? WRAM(5) : EXWRAM(5))] = data;
}
void pc6001mk2_state::mk2_work_ram6_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x40) ? WRAM(6) : EXWRAM(6))] = data;
}
void pc6001mk2_state::mk2_work_ram7_w(offs_t offset, uint8_t data)
{
uint8_t *ROM = m_region_maincpu->base();
ROM[offset+((m_bank_w & 0x40) ? WRAM(7) : EXWRAM(7))] = data;
}
void pc6001mk2_state::necmk2_ppi8255_w(offs_t offset, uint8_t data)
{
if (offset==3)
{
ppi_control_hack_w(data);
if((data & 0x0f) == 0x05)
{
uint8_t *ROM = m_region_maincpu->base();
m_gfx_bank_on = 0;
m_bank4->set_base(&ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
}
if((data & 0x0f) == 0x04)
{
uint8_t *gfx_data = m_region_gfx1->base();
m_gfx_bank_on = 1;
m_bank4->set_base(&gfx_data[m_cgrom_bank_addr]);
}
}
m_ppi->write(offset,data);
}
void pc6001mk2_state::vram_bank_change(uint8_t vram_bank)
{
uint32_t bank_base_values[8] = { 0x8000, 0xc000, 0xc000, 0xe000, 0x0000, 0x8000, 0x4000, 0xa000 };
uint8_t vram_bank_index = ((vram_bank & 0x60) >> 4) | ((vram_bank & 2) >> 1);
// uint8_t *work_ram = m_region_maincpu->base();
// bit 2 of vram_bank sets up 4 color mode
set_videoram_bank(0x28000 + bank_base_values[vram_bank_index]);
// popmessage("%02x",vram_bank);
}
void pc6001mk2_state::mk2_system_latch_w(uint8_t data)
{
cassette_latch_control((data & 8) == 8);
m_sys_latch = data;
m_timer_enable = !(data & 1);
set_timer_divider();
vram_bank_change((m_ex_vram_bank & 0x06) | ((m_sys_latch & 0x06) << 4));
}
inline void pc6001mk2_state::refresh_crtc_params()
{
/* Apparently bitmap modes changes the screen res to 320 x 200 */
rectangle visarea = m_screen->visible_area();
int y_height;
y_height = (m_exgfx_bitmap_mode || m_exgfx_2bpp_mode) ? 200 : 240;
visarea.set(0, (320) - 1, 0, (y_height) - 1);
m_screen->configure(m_screen->width(), m_screen->height(), visarea, m_screen->frame_period().attoseconds());
}
void pc6001mk2_state::mk2_vram_bank_w(uint8_t data)
{
//static const uint32_t startaddr[] = {WRAM(6), WRAM(6), WRAM(0), WRAM(4) };
m_ex_vram_bank = data;
vram_bank_change((m_ex_vram_bank & 0x06) | ((m_sys_latch & 0x06) << 4));
m_exgfx_text_mode = ((data & 2) == 0);
m_cgrom_bank_addr = (data & 2) ? 0x0000 : 0x2000;
m_exgfx_bitmap_mode = (data & 8);
m_exgfx_2bpp_mode = ((data & 6) == 0);
refresh_crtc_params();
// popmessage("%02x",data);
// m_video_base = work_ram + startaddr[(data >> 1) & 0x03];
}
void pc6001mk2_state::mk2_col_bank_w(uint8_t data)
{
m_bgcol_bank = (data & 7);
}
void pc6001mk2_state::mk2_0xf3_w(uint8_t data)
{
/*
x--- ---- M1 (?) wait setting
-x-- ---- ROM wait setting
--x- ---- RAM wait setting
---x ---- custom irq 2 address output
---- x--- custom irq 1 address output
---- -x-- timer irq mask 2 (mirror?)
---- --x- custom irq 2 mask
---- ---x custom irq 1 mask
*/
m_timer_irq_mask = BIT(data, 2);
}
inline u8 pc6001_state::get_timer_base_divider()
{
return 4;
}
inline u8 pc6001mk2sr_state::get_timer_base_divider()
{
// if (sr_mode == false)
// return pc6001mk2_state::get_timer_base_divider();
return 0x80;
}
inline void pc6001_state::set_timer_divider()
{
if (m_timer_enable == false)
{
m_timer_irq_timer->adjust(attotime::never);
return;
}
attotime period = attotime::from_hz((487.5 * get_timer_base_divider()) / (m_timer_hz_div+1));
m_timer_irq_timer->adjust(period, 0, period);
}
void pc6001mk2_state::mk2_timer_adj_w(uint8_t data)
{
m_timer_hz_div = data;
set_timer_divider();
}
void pc6001mk2_state::mk2_timer_irqv_w(uint8_t data)
{
m_timer_irq_vector = data;
}
uint8_t pc6001mk2_state::mk2_bank_r0_r()
{
return m_bank_r0;
}
uint8_t pc6001mk2_state::mk2_bank_r1_r()
{
return m_bank_r1;
}
uint8_t pc6001mk2_state::mk2_bank_w0_r()
{
return m_bank_w;
}
void pc6001mk2_state::pc6001mk2_map(address_map &map)
{
map.unmap_value_high();
map(0x0000, 0x1fff).bankr("bank1").w(FUNC(pc6001mk2_state::mk2_work_ram0_w));
map(0x2000, 0x3fff).bankr("bank2").w(FUNC(pc6001mk2_state::mk2_work_ram1_w));
map(0x4000, 0x5fff).bankr("bank3").w(FUNC(pc6001mk2_state::mk2_work_ram2_w));
map(0x6000, 0x7fff).bankr("bank4").w(FUNC(pc6001mk2_state::mk2_work_ram3_w));
map(0x8000, 0x9fff).bankr("bank5").w(FUNC(pc6001mk2_state::mk2_work_ram4_w));
map(0xa000, 0xbfff).bankr("bank6").w(FUNC(pc6001mk2_state::mk2_work_ram5_w));
map(0xc000, 0xdfff).bankr("bank7").w(FUNC(pc6001mk2_state::mk2_work_ram6_w));
map(0xe000, 0xffff).bankr("bank8").w(FUNC(pc6001mk2_state::mk2_work_ram7_w));
}
void pc6001mk2_state::pc6001mk2_io(address_map &map)
{
map.unmap_value_high();
map.global_mask(0xff);
map(0x80, 0x81).rw("uart", FUNC(i8251_device::read), FUNC(i8251_device::write));
map(0x90, 0x93).mirror(0x0c).rw(FUNC(pc6001mk2_state::nec_ppi8255_r), FUNC(pc6001mk2_state::necmk2_ppi8255_w));
map(0xa0, 0xa0).mirror(0x0c).w(m_ay, FUNC(ay8910_device::address_w));
map(0xa1, 0xa1).mirror(0x0c).w(m_ay, FUNC(ay8910_device::data_w));
map(0xa2, 0xa2).mirror(0x0c).r(m_ay, FUNC(ay8910_device::data_r));
map(0xa3, 0xa3).mirror(0x0c).noprw();
map(0xb0, 0xb0).mirror(0x0f).w(FUNC(pc6001mk2_state::mk2_system_latch_w));
map(0xc0, 0xc0).w(FUNC(pc6001mk2_state::mk2_col_bank_w));
map(0xc1, 0xc1).w(FUNC(pc6001mk2_state::mk2_vram_bank_w));
map(0xc2, 0xc2).w(FUNC(pc6001mk2_state::mk2_opt_bank_w));
map(0xe0, 0xe3).mirror(0x0c).rw("upd7752", FUNC(upd7752_device::read), FUNC(upd7752_device::write));
map(0xf0, 0xf0).rw(FUNC(pc6001mk2_state::mk2_bank_r0_r), FUNC(pc6001mk2_state::mk2_bank_r0_w));
map(0xf1, 0xf1).rw(FUNC(pc6001mk2_state::mk2_bank_r1_r), FUNC(pc6001mk2_state::mk2_bank_r1_w));
map(0xf2, 0xf2).rw(FUNC(pc6001mk2_state::mk2_bank_w0_r), FUNC(pc6001mk2_state::mk2_bank_w0_w));
map(0xf3, 0xf3).w(FUNC(pc6001mk2_state::mk2_0xf3_w));
// map(0xf4
// map(0xf5
map(0xf6, 0xf6).w(FUNC(pc6001mk2_state::mk2_timer_adj_w));
map(0xf7, 0xf7).w(FUNC(pc6001mk2_state::mk2_timer_irqv_w));
}
/*****************************************
*
* PC-6601 specific i/o
*
****************************************/
// disk device I/F
void pc6601_state::fdc_sel_w(uint8_t data)
{
// bit 2 selects between internal (0) and external (1) FDC interfaces
// other bits unknown purpose
m_fdc_intf_view.select((data & 4) >> 2);
}
u8 pc6601_state::fdc_mon_r()
{
// bit 0 reads the motor line status (active low)
return 0;
}
void pc6601_state::fdc_mon_w(u8 data)
{
m_floppy->get_device()->mon_w(!BIT(data,0));
}
// TODO: 0xd0, 0xd3 FIFO data buffer from/to FDC (external DMA?)
// PC-6001mk2SR / PC-6601SR tests these FIFO ports first,
// ditching attempt to floppy load if reading doesn't match 0x55aa previous writes.
// PC-6601 ignores this.
// TODO: hangs at first internal FDC command sense irq status in PC-6601 (and later machines if data buffer is enabled)
// It recalibrate and expects that uPD765 returns a DIO high that never happens.
void pc6601_state::pc6601_fdc_io(address_map &map)
{
map(0xb1, 0xb1).mirror(0x4).w(FUNC(pc6601_state::fdc_sel_w));
map(0xb2, 0xb2).lr8([this]() { return m_fdc->get_irq() ? 1 : 0; }, "FDCINT");
//map(0xb3, 0xb3).w b3 is written when b2 is read
map(0xd0, 0xdf).view(m_fdc_intf_view);
m_fdc_intf_view[0](0xd4, 0xd4).r(FUNC(pc6601_state::fdc_mon_r));
m_fdc_intf_view[0](0xd6, 0xd6).w(FUNC(pc6601_state::fdc_mon_w));
m_fdc_intf_view[0](0xdc, 0xdd).m(m_fdc, FUNC(upd765a_device::map));
m_fdc_intf_view[1](0xd0, 0xd3).mirror(0x4).m(m_pc80s31, FUNC(pc80s31_device::host_map));
}
void pc6601_state::pc6601_io(address_map &map)
{
map.unmap_value_high();
map.global_mask(0xff);
pc6001mk2_io(map);
pc6601_fdc_io(map);
}
/*****************************************
*
* PC-6001 SR specific i/o
*
****************************************/
u8 pc6001mk2sr_state::sr_bank_reg_r(offs_t offset)
{
return m_sr_bank_reg[offset];
}
// offset & 8 maps to bank writes
void pc6001mk2sr_state::sr_bank_reg_w(offs_t offset, u8 data)
{
// TODO: is bit 0 truly a NOP?
m_sr_bank_reg[offset] = data & 0xfe;
m_sr_bank[offset]->set_bank(m_sr_bank_reg[offset] >> 1);
}
void pc6001mk2sr_state::sr_bitmap_yoffs_w(u8 data)
{
m_bitmap_yoffs = data;
}
void pc6001mk2sr_state::sr_bitmap_xoffs_w(u8 data)
{
m_bitmap_xoffs = data;
if (data)
popmessage("xoffs write %02x", data);
}
u8 pc6001mk2sr_state::work_ram_r(offs_t offset)
{
// if (m_sr_text_mode == false && (offset & 0xe000) == 0) && m_sr_mode)
if (m_sr_text_mode == false && (offset & 0xe000) == 0)
return sr_gvram_r(offset);
return m_ram[offset];
}
void pc6001mk2sr_state::work_ram_w(offs_t offset, u8 data)
{
// if (m_sr_text_mode == false && (offset & 0xe000) == 0) && m_sr_mode)
if (m_sr_text_mode == false && (offset & 0xe000) == 0)
{
sr_gvram_w(offset, data);
return;
}
m_ram[offset] = data;
}
// TODO: does this maps to the work RAM in an alt fashion?
// Games that uses GVRAM never writes outside 0-0x13f, and xoffs is unconfirmed.
// Games also expects that GVRAM is read-back as 4-bit, otherwise fill issues happens
// By logic it should be a 320x204 8-bit area -> 0x7f80
// The interface is otherwise pretty inconvenient,
// and it is unconfirmed if raster effect over SR text mode is even possible (which would halve the time required for drawing)
// or if double buffering is possible (that would require EXRAM installed)
u8 pc6001mk2sr_state::sr_gvram_r(offs_t offset)
{
uint32_t real_offs = (m_bitmap_xoffs*16+m_bitmap_yoffs)*320;
real_offs += offset;
return m_gvram[real_offs];
}
void pc6001mk2sr_state::sr_gvram_w(offs_t offset, u8 data)
{
uint32_t real_offs = (m_bitmap_xoffs*16+m_bitmap_yoffs)*320;
real_offs += offset;
m_gvram[real_offs] = data;
}
void pc6001mk2sr_state::sr_mode_w(u8 data)
{
// if 1 text mode else bitmap mode
m_sr_text_mode = bool(BIT(data, 3));
// in theory we need a view,
// in practice this approach doesn't work cause we can't mix views with address banks
// m_gvram_view.select(m_sr_text_mode == false);
m_sr_text_rows = data & 4 ? 20 : 25;
refresh_crtc_params();
// bit 1: bus request
// bit 4: VRAM bank select
// if (data & 0x10)
// popmessage("VRAM bank select enabled");
if(data & 1)
throw emu_fatalerror("PC-6601SR in Mk-2 compatibility mode not yet supported!");
}
void pc6001mk2sr_state::sr_vram_bank_w(u8 data)
{
m_video_base = &m_ram[(data & 0x0f) * 0x1000];
// set_videoram_bank(0x70000 + ((data & 0x0f)*0x1000));
}
void pc6001mk2sr_state::sr_system_latch_w(u8 data)
{
cassette_latch_control((data & 8) == 8);
m_sys_latch = data;
m_timer_enable = !(data & 1);
set_timer_divider();
//vram_bank_change((m_ex_vram_bank & 0x06) | ((m_sys_latch & 0x06) << 4));
//printf("%02x B0\n",data);
}
void pc6001mk2sr_state::necsr_ppi8255_w(offs_t offset, u8 data)
{
if (offset==3)
{
ppi_control_hack_w(data);
#if 0
{
//printf("%02x\n",data);
if ((data & 0x0f) == 0x05 && m_cart_rom)
m_bank1->set_base(m_cart_rom->base() + 0x2000);
if ((data & 0x0f) == 0x04)
m_bank1->set_base(m_region_gfx1->base());
}
#endif
}
m_ppi->write(offset,data);
}
u8 pc6001mk2sr_state::hw_rev_r()
{
// bit 1 is active for pc6601sr (and shows the "PC6601SR World" screen in place of the "PC6001mkIISR World"),