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Autogenerate most ARM platform intrinsics.
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huonw committed Aug 29, 2015
1 parent 3ef610b commit 083f613
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396 changes: 396 additions & 0 deletions src/etc/platform-intrinsics/arm.json
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{
"platform": "arm",
"intrinsic_prefix": "arm_v",
"llvm_prefix": "llvm.neon.v",
"number_info": {
"signed": {
"kind": "s",
"data_type": { "pattern": "s{bitwidth}" }
},
"unsigned": {
"kind": "u",
"data_type": { "pattern": "u{bitwidth}" }
},
"float": {
"kind": "f",
"data_type": { "pattern": "f{bitwidth}" }
}
},
"widths": {
"64": "",
"128": "q"
},
"intrinsics": [
{
"intrinsic": "hadd{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "hadd{0.kind}.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "rhadd{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "rhadd{0.kind}.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "qadd{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "qadd{0.kind}.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0"]
},
{
"intrinsic": "raddhn_{1.data_type}",
"width": [64],
"llvm": "raddhn.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0w", "0w"]
},
{
"intrinsic": "fma{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "!llvm.fma.{0.llvm_name}",
"ret": "f32",
"args": ["0", "0"]
},
{
"intrinsic": "qdmulh{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "sqdmulh.{0.llvm_name}",
"ret": "s(16-32)",
"args": ["0", "0"]
},
{
"intrinsic": "qrdmulh{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "sqrdmulh.{0.llvm_name}",
"ret": "s(16-32)",
"args": ["0", "0"]
},
{
"intrinsic": "mull_{1.data_type}",
"width": [128],
"llvm": "mull{0.kind}.{0.llvm_name}",
"ret": "i(16-64)",
"args": ["0n", "0n"]
},
{
"intrinsic": "qdmull{0.width}_{1.data_type}",
"width": [128],
"llvm": "sqdmull.{0.llvm_name}",
"ret": "s(16-32)",
"args": ["0n", "0n"]
},
{
"intrinsic": "hsub{0.width}_{1.data_type}",
"width": [64, 128],
"llvm": "hsub{0.kind}.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "qsub{0.width}_{1.data_type}",
"width": [64, 128],
"llvm": "qsub{0.kind}.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0"]
},
{
"intrinsic": "rsubhn_{1.data_type}",
"width": [64],
"llvm": "rsubhn.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0w", "0w"]
},
{
"intrinsic": "abd{0.width}_{1.data_type}",
"width": [64, 128],
"llvm": "abd{0.kind}.{0.llvm_name}",
"ret": ["i(8-32)","f32"],
"args": ["0", "0"]
},
{
"intrinsic": "max{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "max{0.kind}.{0.llvm_name}",
"ret": ["i(8-32)","f32"],
"args": ["0", "0"]
},
{
"intrinsic": "min{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "min{0.kind}.{0.llvm_name}",
"ret": ["i(8-32)","f32"],
"args": ["0", "0"]
},
{
"intrinsic": "shl{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "shl{0.kind}.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0s"]
},
{
"intrinsic": "qshl{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "qshl{0.kind}.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0s"]
},
{
"intrinsic": "rshl{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "rshl{0.kind}.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0s"]
},
{
"intrinsic": "qrshl{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "qrshl{0.kind}.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0s"]
},
{
"intrinsic": "qshrun_n_{1.data_type}",
"width": [64],
"llvm": "sqshrun.{0.llvm_name}",
"ret": "s(8-32)",
"args": ["0w", "U32"]
},
{
"intrinsic": "qrshrun_n_{1.data_type}",
"width": [64],
"llvm": "sqrshrun.{0.llvm_name}",
"ret": "s(8-32)",
"args": ["0w", "U32"]
},
{
"intrinsic": "qshrn_n_{1.data_type}",
"width": [64],
"llvm": "qshrn{0.kind}.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0w", "U32"]
},
{
"intrinsic": "rshrn_n_{1.data_type}",
"width": [64],
"llvm": "rshrn.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0w", "U32"]
},
{
"intrinsic": "qrshrn_n_{1.data_type}",
"width": [64],
"llvm": "qrshrn{0.kind}.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0w", "U32"]
},
{
"intrinsic": "sri{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "vsri.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0"]
},
{
"intrinsic": "sli{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "vsli.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0", "0"]
},
{
"intrinsic": "vqmovn_{1.data_type}",
"width": [64],
"llvm": "qxtn{0.kind}.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0w"]
},
{
"intrinsic": "abs{0.width}_{0.data_type}",
"width": [64,128],
"llvm": "abs.{0.llvm_name}",
"ret": "s(8-32)",
"args": ["0"]
},
{
"intrinsic": "abs{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "!llvm.fabs.{0.llvm_name}",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "qabs{0.width}_{0.data_type}",
"width": [64,128],
"llvm": "sqabs.{0.llvm_name}",
"ret": "s(8-32)",
"args": ["0"]
},
{
"intrinsic": "qneg{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "sqneg.{0.llvm_name}",
"ret": "s(8-32)",
"args": ["0"]
},
{
"intrinsic": "clz{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "!llvm.ctlz.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0"]
},
{
"intrinsic": "cls{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "cls.{0.llvm_name}",
"ret": "i(8-32)",
"args": ["0"]
},
{
"intrinsic": "cnt{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "!llvm.ctpop.{0.llvm_name}",
"ret": "i8",
"args": ["0"]
},
{
"intrinsic": "recpe{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "recpe.{0.llvm_name}",
"ret": ["u32","f32"],
"args": ["0"]
},
{
"intrinsic": "recps{0.width}_{0.data_type}",
"width": [64,128],
"llvm": "frecps.{0.llvm_name}",
"ret": "f32",
"args": ["0", "0"]
},
{
"intrinsic": "sqrt{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "!llvm.sqrt.{0.llvm_name}",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "rsqrte{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "rsqrte.{0.llvm_name}",
"ret": ["u32","f32"],
"args": ["0"]
},
{
"intrinsic": "rsqrts{0.width}_{0.data_type}",
"width": [64,128],
"llvm": "rsqrts.{0.llvm_name}",
"ret": "f32",
"args": ["0", "0"]
},
{
"intrinsic": "bsl{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "bsl.{0.llvm_name}",
"ret": "i(8-64)",
"args": ["0u", "0"]
},
{
"intrinsic": "padd{0.width}_{0.data_type}",
"width": [64],
"llvm": "padd.{0.llvm_name}",
"ret": ["i(8-32)","f32"],
"args": ["0", "0"]
},
{
"intrinsic": "paddl{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "paddl{0.kind}.{0.llvm_name}.{1.llvm_name}",
"ret": "i(16-64)",
"args": ["0dn"]
},
{
"intrinsic": "padal{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "padal{0.kind}.{0.llvm_name}.{1.llvm_name}",
"ret": "i(16-64)",
"args": ["0", "0dn"]
},
{
"intrinsic": "pmax{0.width}_{0.data_type}",
"width": [64],
"llvm": "pmax{0.kind}.{0.llvm_name}",
"ret": ["i(8-32)","f32"],
"args": ["0", "0"]
},
{
"intrinsic": "pmin{0.width}_{0.data_type}",
"width": [64, 128],
"llvm": "pmin{0.kind}.{0.llvm_name}",
"ret": ["i(8-32)","f32"],
"args": ["0", "0"]
},
{
"intrinsic": "qtbl1_{0.data_type}",
"width": [64],
"llvm": "tbl1",
"ret": "i8",
"args": ["0x128", "0u"]
},
{
"intrinsic": "qtbx1_{0.data_type}",
"width": [64],
"llvm": "tbx1",
"ret": "i8",
"args": ["0", "0", "0u"]
},
{
"intrinsic": "qtbl2_{0.data_type}",
"width": [64],
"llvm": "tbl2",
"ret": "i8",
"args": ["(0,0)f", "0u"]
},
{
"intrinsic": "qtbx2_{0.data_type}",
"width": [64],
"llvm": "tbx2",
"ret": "i8",
"args": ["(0,0)f", "0u"]
},
{
"intrinsic": "qtbl3_{0.data_type}",
"width": [64],
"llvm": "tbl3",
"ret": "i8",
"args": ["(0,0,0)f", "0u"]
},
{
"intrinsic": "qtbx3_{0.data_type}",
"width": [64],
"llvm": "tbx3",
"ret": "i8",
"args": ["0", "(0,0,0)f", "0u"]
},
{
"intrinsic": "qtbl4_{0.data_type}",
"width": [64],
"llvm": "tbl4",
"ret": "i8",
"args": ["(0,0,0,0)f", "0u"]
},
{
"intrinsic": "qtbx4_{0.data_type}",
"width": [64],
"llvm": "tbx4",
"ret": "i8",
"args": ["0", "(0,0,0,0)f", "0u"]
}
]
}

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