mips32: Add f64 hard-float support

co-authored-by: Amanieu <amanieu@gmail.com>
rust-lang · Oct 4, 2020 · 6cb062d · 6cb062d
1 parent 446f86e
commit 6cb062d
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Showing 3 changed files with 26 additions and 2 deletions.
diff --git a/compiler/rustc_target/src/asm/mips.rs b/compiler/rustc_target/src/asm/mips.rs
@@ -36,7 +36,7 @@ impl MipsInlineAsmRegClass {
     ) -> &'static [(InlineAsmType, Option<&'static str>)] {
         match self {
             Self::reg => types! { _: I8, I16, I32, F32; },
-            Self::freg => types! { _: F32; },
+            Self::freg => types! { _: F32, F64; },
         }
     }
 }

diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md
@@ -551,7 +551,7 @@ Each register class has constraints on which value types they can be used with.
 | ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
 | ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
 | MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
-| MIPS32 | `freg` | None | `f32` |
+| MIPS32 | `freg` | None | `f32`, `f64` |
 | NVPTX | `reg16` | None | `i8`, `i16` |
 | NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
 | NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |

diff --git a/src/test/assembly/asm/mips-types.rs b/src/test/assembly/asm/mips-types.rs
@@ -108,6 +108,30 @@ pub unsafe fn f0_f32(x: f32) -> f32 {
     y
 }
 
+// CHECK-LABEL: reg_f64:
+// CHECK: #APP
+// CHECK: mov.d $f{{[0-9]+}}, $f{{[0-9]+}}
+// CHECK: #NO_APP
+#[no_mangle]
+pub unsafe fn reg_f64(x: f64) -> f64 {
+    dont_merge("reg_f64");
+    let y;
+    asm!("mov.d {}, {}", out(freg) y, in(freg) x);
+    y
+}
+
+// CHECK-LABEL: f0_f64:
+// CHECK: #APP
+// CHECK: mov.d $f0, $f0
+// CHECK: #NO_APP
+#[no_mangle]
+pub unsafe fn f0_f64(x: f64) -> f64 {
+    dont_merge("f0_f64");
+    let y;
+    asm!("mov.d $f0, $f0", lateout("$f0") y, in("$f0") x);
+    y
+}
+
 // CHECK-LABEL: reg_ptr:
 // CHECK: #APP
 // CHECK: move ${{[0-9]+}}, ${{[0-9]+}}