From 8c904d8e5d7fc175916a13c8a37346e7fff8f9f7 Mon Sep 17 00:00:00 2001 From: nerdyscout Date: Fri, 12 Jun 2020 08:34:54 +0000 Subject: [PATCH] add tests --- .github/workflows/test.yml | 146 +++++++++++++++++++++++++++++++++ Dockerfile | 2 +- README.md | 2 +- commands.sh | 11 +-- kicad-exports.sh | 18 ++--- opt/ibom/ibom.sh | 2 +- test/test.kicad_pcb | 160 +++++++++++++++++++++++++++++++++++++ test/test.pro | 33 ++++++++ test/test.sch | 27 +++++++ 9 files changed, 383 insertions(+), 18 deletions(-) create mode 100644 .github/workflows/test.yml create mode 100644 test/test.kicad_pcb create mode 100644 test/test.pro create mode 100644 test/test.sch diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 0000000..d6d6524 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,146 @@ +name: test + +on: + push: + branches: + - master + - develop + pull_request: + branches: + - master + - develop + +jobs: + schematic: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: kicad-exports schematic docs + uses: nerdyscout/kicad-exports@master + with: + cmd: schematic + dir: test/docs + board: test/test.kicad_pcb + schematic: test/test.sch + - name: kicad-schematic + uses: andstor/file-existence-action@v1 + with: + files: "test/docs/test_schematic.svg, test/docs/test_schematic.pdf" + - uses: actions/upload-artifact@v2 + if: success() + with: + name: schematic + path: test/docs/* + + bom: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: kicad-exports ibom docs/bom + uses: nerdyscout/kicad-exports@master + with: + cmd: bom + dir: test/docs/bom + board: test/test.kicad_pcb + schematic: test/test.sch + - name: "check output: bom" + if: success() + uses: andstor/file-existence-action@v1 + with: + files: "test/docs/bom/ibom.html, test/docs/bom/test.csv, test/docs/bom/test.xlsx" + - uses: actions/upload-artifact@v2 + if: success() + with: + name: bom + path: test/docs/bom/* + + fabrication: + runs-on: ubuntu-latest + continue-on-error: true + steps: + - uses: actions/checkout@v2 + - name: kicad-exports fabrication gerber + uses: nerdyscout/kicad-exports@master + with: + cmd: fabrication + dir: test/gerber + board: test/test.kicad_pcb + schematic: test/test.sch + - name: "check output: kiplot-position" + uses: andstor/file-existence-action@v1 + with: + files: "test/gerber/test-both-pos.csv" + - name: "check output: kiplot-drills" + uses: andstor/file-existence-action@v1 + with: + files: "test/gerber/test-PTH.drl, test/gerber/test-NPTH.drl" + - uses: andstor/file-existence-action@v1 + with: + files: "test/gerber/test-PTH-drl.gbr, test/gerber/test-NPTH-drl.gbr" + - name: "check output: kiplot-gerber" + uses: andstor/file-existence-action@v1 + with: + files: "test/gerber/test-Edge_Cuts.gbr, test/gerber/test-F_Cu.gbr, test/gerber/test-B_SilkS.gbr" + - uses: actions/upload-artifact@v2 + with: + name: gerber + path: test/gerber/* + + report: + runs-on: ubuntu-latest + continue-on-error: true + steps: + - uses: actions/checkout@v2 + - name: kicad-exports report + uses: nerdyscout/kicad-exports@master + with: + cmd: report + dir: test + schematic: test/test.sch + board: test/test.kicad_pcb + - name: "check output: erc" + uses: andstor/file-existence-action@v1 + with: + files: "test/test.erc" + - name: "check output: drc" + uses: andstor/file-existence-action@v1 + with: + files: "test/test.rpt" + - uses: actions/upload-artifact@v2 + with: + name: report + path: test/ + + tracespace: + runs-on: ubuntu-latest + continue-on-error: true + steps: + - uses: actions/checkout@v2 + - name: kicad-exports tracespace-board + uses: nerdyscout/kicad-exports@master + with: + cmd: tracespace-board + dir: test/docs/img + schematic: test/test.sch + board: test/test.kicad_pcb + - name: "check output: tracespace-board" + uses: andstor/file-existence-action@v1 + with: + files: "test/docs/img/test_Board_Top.svg, test/docs/img/test_Board_Bottom.svg" + + - name: kicad-exports tracespace-assembly + uses: nerdyscout/kicad-exports@master + with: + cmd: tracespace-assembly + dir: test/docs/img + schematic: test/test.sch + board: test/test.kicad_pcb + - name: "check output: tracespace-assembly" + uses: andstor/file-existence-action@v1 + with: + files: "test/docs/img/test_Assembly_Top.svg, test/docs/img/test_Assembly_Bottom.svg" + + - uses: actions/upload-artifact@v2 + with: + name: images + path: test/docs/img/* \ No newline at end of file diff --git a/Dockerfile b/Dockerfile index 15eb81b..4bb47f1 100644 --- a/Dockerfile +++ b/Dockerfile @@ -3,7 +3,7 @@ FROM setsoft/kicad_debian as kicad LABEL MAINTAINER nerdyscout LABEL Description="export various files from KiCad projects" -LABEL VERSION="v0.3" +LABEL VERSION="v1.0" # update packages diff --git a/README.md b/README.md index 97b1852..2c16b88 100644 --- a/README.md +++ b/README.md @@ -47,7 +47,7 @@ on: *1: kicad-exports tries to set schematic and board file automatically. For most commands atleast one of both parameters are requiered, so they are not completly optional. -For examples of more full workflows see [kicad-exports-test](https://github.com/nerdyscout/kicad-exports-test/blob/v0.2/.github/workflows). +For examples of more full workflows see [kicad-exports-test](https://github.com/nerdyscout/kicad-exports/blob/master/.github/workflows/test.yml). # use kicad-exports local diff --git a/commands.sh b/commands.sh index 18e3313..3f4eeda 100755 --- a/commands.sh +++ b/commands.sh @@ -108,6 +108,7 @@ function bom() { function kicad-bom() { eeschema_do $VERBOSE bom_xml $SCHEMATIC $DIR rm -f $DIR/$NAME.xml + rm -f $NAME.xml } # REQUIRES: $BOARD @@ -122,10 +123,10 @@ function kicad-board() { # REQUIRES: $NAME.xml # OPTIONAL: $DIR # OUTPUT: $DIR/$NAME.xlsx -function kibom-xlsx() { - eeschema_do $VERBOSE bom_xml $SCHEMATIC $DIR - python3 -m kibom $VERBOSE -d $DIR --cfg /opt/kibom/bom.ini $NAME.xml $DIR/$NAME.xlsx - rm -f $NAME.xml +function kibom() { + eeschema_do $VERBOSE bom_xml $SCHEMATIC /tmp + find . -name $NAME.xml -exec mv -t /tmp {} + + python3 -m kibom $VERBOSE -d $DIR --cfg /opt/kibom/bom.ini /tmp/$NAME.xml $DIR/$NAME.xlsx } # REQUIRES: $BOARD @@ -140,7 +141,7 @@ function ibom() { # OUTPUT: $DIR/$NAME.xlsx function kicost() { eeschema_do $VERBOSE bom_xml $SCHEMATIC /tmp - mv -f $DIR/*.xml /tmp + find . -name $NAME.xml -exec mv -t /tmp {} + python3 -m kicost -i /tmp/$NAME.xml -o $DIR/$NAME.xlsx -w --eda kicad $PARAMETERS } diff --git a/kicad-exports.sh b/kicad-exports.sh index 0d0ccb2..c3674f2 100755 --- a/kicad-exports.sh +++ b/kicad-exports.sh @@ -1,21 +1,18 @@ #!/bin/bash if [ `basename $0 .sh` == 'kicad-exports' ]; then - echo "running OUTSIDE docker..." + echo "starting docker..." docker run -it \ --volume $PWD:/mnt \ kicad-exports $@ - else - echo "running INSIDE docker..." - export DIR="${2:-$PWD}" export SCHEMATIC="${3:-$(ls -1 *.sch)}" export BOARD="${4:-$(ls -1 *.kicad_pcb)}" export MANUFACTURER="$5" export PARAMETERS="$6" export NAME="$(basename -s .kicad_pcb $BOARD)" - export VERBOSE=-v +# export VERBOSE=-v if [ -n "$VERBOSE" ]; then echo "DIR=$DIR" @@ -25,10 +22,11 @@ else echo "PARAMETERS=$PARAMETERS" echo "NAME=$NAME" echo "VERBOSE=$VERBOSE" - - echo $DIR - ls -la $DIR fi - /commands.sh $1 -fi + if [ -n "$SCHEMATIC" ] || [ -n "$BOARD" ]; then + /commands.sh $1 + else + echo "neither board nor schematic found!" + fi +fi \ No newline at end of file diff --git a/opt/ibom/ibom.sh b/opt/ibom/ibom.sh index b720bef..cfedc7a 100644 --- a/opt/ibom/ibom.sh +++ b/opt/ibom/ibom.sh @@ -6,4 +6,4 @@ xvfb=$! export DISPLAY=:99 -python3 /opt/ibom/generate_interactive_bom.py $1 $3 --no-browser --dest-dir=$2 \ No newline at end of file +python3 /opt/ibom/generate_interactive_bom.py $1 $3 --no-browser --dest-dir=$(realpath $2) \ No newline at end of file diff --git a/test/test.kicad_pcb b/test/test.kicad_pcb new file mode 100644 index 0000000..d101126 --- /dev/null +++ b/test/test.kicad_pcb @@ -0,0 +1,160 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2build2) + + (general + (thickness 1.6) + (drawings 4) + (tracks 0) + (zones 0) + (modules 1) + (nets 1) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.051) + (solder_mask_min_width 0.25) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net "Net-(R1-Pad1)") + (add_net "Net-(R1-Pad2)") + ) + + (module Resistor_SMD:R_1206_3216Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5EE19554) + (at 114.3 88.9) + (descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags resistor) + (path /5EE13BA3) + (attr smd) + (fp_text reference R1 (at 0 -1.82) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value R (at 0 1.82) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (fp_line (start 2.28 1.12) (end -2.28 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.28 -1.12) (end 2.28 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.28 -1.12) (end 2.28 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.28 1.12) (end -2.28 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.602064 0.91) (end 0.602064 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.602064 -0.91) (end 0.602064 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 1.4 0) (size 1.25 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2)) + (pad 1 smd roundrect (at -1.4 0) (size 1.25 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_line (start 127 76.2) (end 101.6 76.2) (layer Edge.Cuts) (width 0.05) (tstamp 5EE19533)) + (gr_line (start 127 101.6) (end 127 76.2) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 101.6 101.6) (end 127 101.6) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 101.6 76.2) (end 101.6 101.6) (layer Edge.Cuts) (width 0.05)) + + (zone (net 0) (net_name "") (layer F.Cu) (tstamp 0) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 127 101.6) (xy 101.6 101.6) (xy 101.6 76.2) (xy 127 76.2) + ) + ) + (filled_polygon + (pts + (xy 126.34 100.94) (xy 102.26 100.94) (xy 102.26 76.86) (xy 126.340001 76.86) + ) + ) + ) +) diff --git a/test/test.pro b/test/test.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/test/test.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/test/test.sch b/test/test.sch new file mode 100644 index 0000000..57b5977 --- /dev/null +++ b/test/test.sch @@ -0,0 +1,27 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Device:R R1 +U 1 1 5EE13BA3 +P 5000 2500 +F 0 "R1" H 5100 2550 50 0000 L CNN +F 1 "R" H 5100 2500 50 0000 L CNN +F 2 "Resistor_SMD:R_1206_3216Metric" V 4930 2500 50 0001 C CNN +F 3 "~" H 5000 2500 50 0001 C CNN + 1 5000 2500 + 1 0 0 -1 +$EndComp +$EndSCHEMATC