Title | dlx (DLX functional model for ArchC) |
Author | Nikolaos Kavvadias 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016 |
Contact | nikos@nkavvadias.com |
Website | http://www.nkavvadias.com |
Release Date | 02 December 2014 |
Version | 0.1.3 |
Rev. history | |
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2014-12-02 Added project logo in README. |
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2014-10-23 Documentation corrections. |
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2014-10-23
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2014-10-22
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2006-11-15
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2006-07-01
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2006-01-01
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2005-12-26
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This is the DLX ArchC (http://www.archc.org) functional model. This model has the system call emulation functions implemented, so it is a good idea to turn on the ABI option.
The dlx
distribution includes the following files:
/dlx | Top-level directory |
AUTHORS | List of dlx authors. |
LICENSE | The modified BSD license governs dlx . |
README.html | HTML version of README. |
README.pdf | PDF version of README. |
README.rst | This file. |
VERSION | Current version of the project sources. |
bp_conf.ac | Branch predictor description (only for archc-1.5.1.bp2). |
defines_gdb | Macro definitions for GDB integration. |
dlx.ac | Register, memory and cache model for dlx . |
dlx.png | PNG image for the dlx project logo. |
dlx_gdb_funcs.cpp | GDB support for the DLX simulator. |
dlx_isa.ac | Instruction encodings and assembly formats. |
dlx_opcode_map.vsd | Incomplete MS Visio drawing of the DLX opcode map. |
dlx_opcode_map.xls | Excel spreadsheet containing the DLX opcode map. |
dlx_syscall.cpp | OS call emulation support for DLX. |
dlx_isa.cpp | Instruction behaviors. |
modifiers | Instruction encoding and decoding modifiers. |
rst2docs.sh | Bash script for generating the HTML and PDF versions of the documentation (README). |
To generate the interpreted simulator, the acsim
executable is ran:
$ acsim dlx.ac [-g -abi -gdb] # (create the simulator)
$ make -f Makefile.archc # (compile)
$ ./dlx.x --load=<file-path> [args] # (run an application)
To generate the compiled application simulator, the accsim
executable is ran:
$ accsim dlx.ac <file-path> # (create specialized simulator)
$ make -f Makefile.archc # (compile)
$ ./dlx.x [args] # (run the application)
The [args]
are optional arguments for the application.
There are two formats recognized for application <file-path>:
- ELF binary matching ArchC specifications
- hexadecimal text file for ArchC
In order to generate the binary utilities port (binutils
port), the acbingen.sh
driver script must be used. This should be called as follows:
$ acbingen.sh -adlx -i`pwd`/../dlx-tools/ dlx.ac
for generating the binutils
port executables. This includes the following tools:
addr2line
ar
as
c++filt
gdb
(the GDB port is also generated in the same directory)gdbtui
ld
nm
objcopy
objdump
ranlib
readelf
size
strings
strip
- Some non-classical DLX instructions (available in the DLX binutils target) might be added in the future. These are:
bswap
(BSWAPF) --> A byte swap instructionldstbu
(LSBUOP) --> Atomic load-store byte unsignedldsthu
(LSHUOP) --> Atomic load-store halfword unsignedldstw
(LSWOP) --> Atomic load-store word
mult
,multu
,div
,divu
instructions have different opcodes to the binutils DLX. Also,div
,divu
produce a single 32-bit result (the quotient). Probably,rem
,remu
instructions will be added to produce the remainder of a division. For 64-bit result multiplication maybe a good choice is to providemultl
,multlu
primitives, for which results are written in two consecutive registers (integer registers).- There are no
HI/LO
registers (I think this is the actual intent in the Patterson book). - Multiplication and division DONNOT use the floating-point register file. For this reason,
mvts
,mvfs
instructions are currently unimplemented. - Loading 32-bit constants will be available via appropriate pseudo-instructions not requiring the
HI/LO
registers, and for the following formats:
li %dest, #hi-16bit-constant, #lo-16bit-constant
li %dest, #32bit-constant
- For future provision of a coprocessor (maybe this is an overkill for the DLX?) some opcodes MIGHT be moved, e.g.:
- Move opcode(J)=0x02, opcode(JAL)=0x03 to e.g. 0x06,0x07, respectively. (PREFERRED)
- Move opcode(BEQZ), opcode(BNEZ) to 0x16, 0x17.
- Then the 0x01-0x04 primary opcodes would be used for 4 optional coprocessors.