From 03991067ed8552f7f4cdcb734c62d72b310af035 Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Thu, 7 Jan 2016 14:35:20 -0600 Subject: [PATCH] Add mcbist L2 function Change-Id: I067143fab02217fe50e8848ed099604d046173d9 Original-Change-Id: I8b98c188d6a642eb49d89deffcbd697d9cf7afdc Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23895 Tested-by: Jenkins Server Reviewed-by: Craig C. Hamilton Reviewed-by: Andre A. Marin Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37390 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell --- .../p9/procedures/hwp/memory/lib/mc/xlate.C | 220 ++++++++++++++++++ 1 file changed, 220 insertions(+) create mode 100644 src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C new file mode 100644 index 00000000000..ce65a3e1c1d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -0,0 +1,220 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file xlate.C +/// @brief Subroutines to manipulate the memory controller translation registers +/// +// *HWP HWP Owner: Brian Silver +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include + +#include "p9_mc_scom_addresses.H" +#include "p9_mc_scom_addresses_fld.H" + +#include "mss_attribute_accessors.H" + +#include "mc.H" +#include "../utils/scom.H" +#include "../dimm/kind.H" + +using fapi2::TARGET_TYPE_MCBIST; +using fapi2::TARGET_TYPE_PROC_CHIP; +using fapi2::TARGET_TYPE_SYSTEM; +using fapi2::TARGET_TYPE_MCA; +using fapi2::TARGET_TYPE_MCS; +using fapi2::TARGET_TYPE_DIMM; + +using fapi2::FAPI2_RC_SUCCESS; + + +namespace mss +{ + +/// +/// @brief Perform initializations of the MC translation +/// @tparm P, the fapi2::TargetType of the port +/// @tparm TT, the typename of the traits +/// @param[in] i_target, the target which has the MCA to map +/// @return FAPI2_RC_SUCCESS iff ok +/// +template<> +template<> +fapi2::ReturnCode mc::setup_xlate_map(const fapi2::Target& i_target) +{ + fapi2::buffer l_xlate; + fapi2::buffer l_xlate1; + fapi2::buffer l_xlate2; + + const auto l_dimms = i_target.getChildren(); + + FAPI_INF("Setting up xlate registers for MCA%d (%d)", mss::pos(i_target), mss::index(i_target)); + + // We enable the DIMM select bit for slot1 if we have two DIMM installed + l_xlate.writeBit(l_dimms.size() == 2); + + // Get the functional DIMM on this port. + for (auto d : l_dimms) + { + // Our slot (0, 1) is the same as our general index. + const uint64_t l_slot = mss::index(d); + + // Our slot offset tells us which 16 bit section in the xlt register to use for this DIMM + // We'll either use the left most bits (slot 0) or move 16 bits to the right for slot 1. + const uint64_t l_slot_offset = l_slot * 16; + + // Get the translation array, based on this specific DIMM's config + dimm::kind l_dimm(d); + + // TK: Get the information from the translation table for this DIMM. + + FAPI_DBG("address translation for DIMM %s %dR %dgbx%d in slot %d", + mss::c_str(d), l_dimm.iv_master_ranks, l_dimm.iv_dram_density, l_dimm.iv_dram_width, l_slot); + + + // Set the proper bit if there is a DIMM in this slot. If there wasn't, we wouldn't see + // this DIMM in the vector, so this is always safe. + l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_VALID + l_slot_offset); + + + // Set the 12G DIMM bit if either DIMM is 12G + // Is this correct? BRS + l_xlate.writeBit(l_dimm.iv_size == 12); + + // Check our master ranks, and enable the proper bits. + // Note this seems a little backward. M0 is the left most bit, M1 the right most. + // So, M1 changes for ranks 0,1 and M0 changes for ranks 3,4 + if (l_dimm.iv_master_ranks > 0) + { + l_xlate.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID + l_slot_offset); + } + + if (l_dimm.iv_master_ranks > 2) + { + l_xlate.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID + l_slot_offset); + } + + + // Check slave ranks + // Note this sems a little backward. S0 is the left-most slave bit. So, + // if there are more than 0 slave ranks, S2 will increment first. + if (l_dimm.iv_slave_ranks > 0) + { + l_xlate.setBit(MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID + l_slot_offset); + } + + if (l_dimm.iv_slave_ranks > 2) + { + l_xlate.setBit(MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID + l_slot_offset); + } + + if (l_dimm.iv_slave_ranks > 4) + { + l_xlate.setBit(MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID + l_slot_offset); + } + + + // Tell the MC which of the row bits are valid. + if (l_dimm.iv_rows >= 16) + { + l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + l_slot_offset); + } + + if (l_dimm.iv_rows >= 17) + { + l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + l_slot_offset); + } + + if (l_dimm.iv_rows >= 18) + { + l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + l_slot_offset); + } + + } + + // TK: remove and make general in the loop above BRS + + // Two rank DIMM, so master bit 1 (least significant) bit needs to be mapped. + l_xlate.insertFromRight(0b01111); + + // Slot 1 isn't populated, so forget those bits for now. + + // DIMM bit map isn't exactly ignored for only one populated slot. It still needs to be + // set in the map. Per S. Powell. + // Master rank 0, 1 bit maps are ignored. + // Row 16,17 bit maps are ignored. + // Row 15 maps to Port Address bit 6 + l_xlate.insertFromRight(0b00101); + l_xlate.insertFromRight(0b00110); + + // Drop down the column assignments + l_xlate1.insertFromRight(0b01101); + + l_xlate1.insertFromRight(0b01100); + + l_xlate1.insertFromRight(0b01011); + + l_xlate1.insertFromRight(0b01010); + + l_xlate2.insertFromRight(0b01001); + + l_xlate2.insertFromRight(0b00111); + + l_xlate2.insertFromRight(0b01110); + + l_xlate2.insertFromRight(0b10000); + + l_xlate2.insertFromRight(0b10001); + + l_xlate2.insertFromRight(0b10010); + + FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT0", l_xlate); + FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT1", l_xlate1); + FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT2", l_xlate2); + + FAPI_TRY( mss::putScom(i_target.getParent(), MCS_0_PORT02_MCP0XLT0, l_xlate) ); + FAPI_TRY( mss::putScom(i_target.getParent(), MCS_0_PORT02_MCP0XLT1, l_xlate1) ); + FAPI_TRY( mss::putScom(i_target.getParent(), MCS_0_PORT02_MCP0XLT2, l_xlate2) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +} // namespace