From 0483af65824cddb936e3450fa99234371929340b Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Mon, 12 Jun 2017 13:01:28 -0500 Subject: [PATCH] L3 update -- p9_smp_link_layer whitespace, line length updates Change-Id: Iaa312ba533e99c4a018ca768c0c71edcfe7648ea Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41698 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Benjamin Gass Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41701 Reviewed-by: Hostboot Team Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../procedures/hwp/nest/p9_smp_link_layer.C | 53 +++++++++++-------- .../procedures/hwp/nest/p9_smp_link_layer.H | 20 ++++--- 2 files changed, 39 insertions(+), 34 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C index 252624ef3f5..37cde2793b2 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,7 @@ // *HWP HWP Owner: Joe McGill // *HWP FW Owner: Thi Tran // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB,FSP // @@ -43,47 +43,48 @@ #include #include - //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ - /// /// @brief Engage DLL/TL training for a single fabric link (X/A) /// -/// @param[in] i_target Reference to processor chip target -/// @param[in] i_ctl Reference to link control structure +/// @param[in] i_target Reference to processor chip target +/// @param[in] i_ctl Reference to link control structure /// /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// fapi2::ReturnCode -p9_smp_link_layer_train_link(const fapi2::Target& i_target, - const p9_fbc_link_ctl_t& i_ctl) - +p9_smp_link_layer_train_link( + const fapi2::Target& i_target, + const p9_fbc_link_ctl_t& i_ctl) { FAPI_DBG("Start"); - fapi2::buffer l_dll_control; + // optical (IOOOL)/electrical (IOEL) control registers share common bit + // layout, R-M-W control register to set link startup bits + fapi2::buffer l_dll_control; FAPI_TRY(fapi2::getScom(i_target, i_ctl.dl_control_addr, l_dll_control), - "Error reading DLL control register!"); - // optical (IOOOL)/electrical (IOEL) control registers share common bit layout + "Error reading DLL control register (0x%08X)!", + i_ctl.dl_control_addr); l_dll_control.setBit(); l_dll_control.setBit(); FAPI_TRY(fapi2::putScom(i_target, i_ctl.dl_control_addr, l_dll_control), - "Error writing DLL control register!"); + "Error writing DLL control register (0x%08X)!", + i_ctl.dl_control_addr); fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; } - // NOTE: see doxygen comments in header fapi2::ReturnCode -p9_smp_link_layer(const fapi2::Target& i_target, - const bool i_train_electrical, - const bool i_train_optical) +p9_smp_link_layer( + const fapi2::Target& i_target, + const bool i_train_electrical, + const bool i_train_optical) { FAPI_INF("Start"); @@ -93,10 +94,14 @@ p9_smp_link_layer(const fapi2::Target& i_target, uint8_t l_a_en[P9_FBC_UTILS_MAX_A_LINKS]; // process set of enabled links - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG, i_target, l_x_en), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG, + i_target, + l_x_en), "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG, i_target, l_a_en), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG, + i_target, + l_a_en), "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG"); for (uint8_t l_link = 0; l_link < P9_FBC_UTILS_MAX_X_LINKS; l_link++) @@ -109,8 +114,9 @@ p9_smp_link_layer(const fapi2::Target& i_target, (P9_FBC_XBUS_LINK_CTL_ARR[l_link].endp_type == OPTICAL))) { FAPI_DBG("Training link X%d", l_link); - FAPI_TRY(p9_smp_link_layer_train_link(i_target, - P9_FBC_XBUS_LINK_CTL_ARR[l_link]), + FAPI_TRY(p9_smp_link_layer_train_link( + i_target, + P9_FBC_XBUS_LINK_CTL_ARR[l_link]), "Error from p9_smp_link_layer_train_link (X)"); } } @@ -128,8 +134,9 @@ p9_smp_link_layer(const fapi2::Target& i_target, (P9_FBC_ABUS_LINK_CTL_ARR[l_link].endp_type == OPTICAL)) { FAPI_DBG("Training link A%d", l_link); - FAPI_TRY(p9_smp_link_layer_train_link(i_target, - P9_FBC_ABUS_LINK_CTL_ARR[l_link]), + FAPI_TRY(p9_smp_link_layer_train_link( + i_target, + P9_FBC_ABUS_LINK_CTL_ARR[l_link]), "Error from p9_smp_link_layer_train_link (A)"); } } diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H index 6453930680f..abf9fab0691 100755 --- a/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_smp_link_layer.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,20 +42,18 @@ // *HWP HWP Owner: Joe McGill // *HWP FW Owner: Thi Tran // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB,FSP // #ifndef _P9_SMP_LINK_LAYER_H_ #define _P9_SMP_LINK_LAYER_H_ - //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ #include - //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ @@ -66,7 +64,6 @@ typedef fapi2::ReturnCode (*p9_smp_link_layer_FP_t) ( const bool, const bool); - //------------------------------------------------------------------------------ // Function prototypes //------------------------------------------------------------------------------ @@ -77,15 +74,16 @@ extern "C" /// /// @brief Train fabric DLL/TL layers /// -/// @param[in] i_target Reference to processor chip target -/// @param[in] i_train_electrical Train electrical links? -/// @param[in] i_train_optical Train optical links? +/// @param[in] i_target Reference to processor chip target +/// @param[in] i_train_electrical Train electrical links? +/// @param[in] i_train_optical Train optical links? /// /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_smp_link_layer(const fapi2::Target& i_target, - const bool i_train_electrical, - const bool i_train_optical); + fapi2::ReturnCode p9_smp_link_layer( + const fapi2::Target& i_target, + const bool i_train_electrical, + const bool i_train_optical); } // extern "C"