diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
index d54f6be4005..8e40f6dcbfe 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H
@@ -386,7 +386,6 @@ enum
     CME_INSTRUMENTATION_SIZE    = HALF_KB,      // per CME
     INSTRUMENTATION_COUNTERS    = HALF_KB,      // (???)
     CME_SRAM_HCODE_OFFSET       = 0x00, //(???)
-    CME_INST_SPEC_RING_START    = 300 * ONE_KB,
     CME_REGION_START            =  (CORE_SCOM_START + CORE_SCOM_RES_SIZE),
     CME_BLOCK_READ_LEN          = 32,
     CME_BLK_SIZE_SHIFT          = 0x05,
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 3e5d1f45a22..a8d74098de0 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -672,7 +672,12 @@ extern "C"
 
         if( pCmeHdr->g_cme_max_spec_ring_length )
         {
-            pCpmrHdr->coreSpecRingOffset        =   SWIZZLE_4_BYTE(CME_INST_SPEC_RING_START);
+            pCpmrHdr->coreSpecRingOffset        =   ( SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) << CME_BLK_SIZE_SHIFT ) +
+                                                    SWIZZLE_4_BYTE( pCpmrHdr->cmeImgLength) +
+                                                    SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength) +
+                                                    SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength);
+            pCpmrHdr->coreSpecRingOffset        =   (pCpmrHdr->coreSpecRingOffset + CME_BLOCK_READ_LEN - 1) >> CME_BLK_SIZE_SHIFT;
+            pCpmrHdr->coreSpecRingOffset        =   SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset);
             pCpmrHdr->coreSpecRingLength        =   pCmeHdr->g_cme_max_spec_ring_length; // already swizzled
         }