diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index 648f52922e1..56fb3329b79 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -31,7 +31,7 @@ // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : sunil kumar // *HWP Team : Perv -// *HWP Level : 2 +// *HWP Level : 3 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ @@ -266,9 +266,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( l_sl_clkregion_status &= l_regions; FAPI_ASSERT(l_sl_clkregion_status == l_regions, - fapi2::NEST_SL_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_SL(l_sl_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL) + .set_REGIONS(i_regions) + .set_READ_CLK(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -280,9 +283,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( l_sl_clkregion_status &= l_regions; FAPI_ASSERT(l_sl_clkregion_status == l_regions, - fapi2::NEST_SL_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_SL(l_sl_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL) + .set_REGIONS(i_regions) + .set_READ_CLK(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } } @@ -304,9 +310,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( l_nsl_clkregion_status &= l_regions; FAPI_ASSERT(l_nsl_clkregion_status == l_regions, - fapi2::NEST_NSL_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_NSL(l_nsl_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL) + .set_REGIONS(i_regions) + .set_READ_CLK(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -318,9 +327,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( l_nsl_clkregion_status &= l_regions; FAPI_ASSERT(l_nsl_clkregion_status == l_regions, - fapi2::NEST_NSL_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_NSL(l_nsl_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL) + .set_REGIONS(i_regions) + .set_READ_CLK(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } } @@ -342,9 +354,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( l_ary_clkregion_status &= l_regions; FAPI_ASSERT(l_ary_clkregion_status == l_regions, - fapi2::NEST_ARY_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_ARY(l_ary_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY) + .set_REGIONS(i_regions) + .set_READ_CLK(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -356,9 +371,12 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( l_ary_clkregion_status &= l_regions; FAPI_ASSERT(l_ary_clkregion_status == l_regions, - fapi2::NEST_ARY_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_ARY(l_ary_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY) + .set_REGIONS(i_regions) + .set_READ_CLK(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } } @@ -547,9 +565,12 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const l_exp_sl_clock_status, l_sl_clock_status); FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, - fapi2::SL_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_SL(l_sl_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_SL) + .set_REGIONS(i_regions) + .set_READ_CLK(l_sl_clock_status), "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); FAPI_DBG("Check for clocks running NSL"); @@ -560,9 +581,12 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const l_exp_nsl_clock_status, l_nsl_clock_status); FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, - fapi2::NSL_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_NSL(l_nsl_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_NSL) + .set_REGIONS(i_regions) + .set_READ_CLK(l_nsl_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); FAPI_DBG("Check for clocks running ARY"); @@ -573,9 +597,12 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const l_exp_ary_clock_status, l_ary_clock_status); FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, - fapi2::ARY_ERR() + fapi2::THOLD_ERR() .set_TARGET_CHIPLET(i_target) - .set_READ_CLK_ARY(l_ary_clock_status), + .set_CLOCK_CMD(i_clock_cmd) + .set_CLOCK_TYPE(PERV_CLOCK_STAT_ARY) + .set_REGIONS(i_regions) + .set_READ_CLK(l_ary_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H index aa4fddc690a..43a422c4439 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,7 +31,7 @@ // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : sunil kumar // *HWP Team : Perv -// *HWP Level : 2 +// *HWP Level : 3 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml index 2c05ad2f939..09982af9166 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml @@ -190,9 +190,13 @@ - RC_ARY_ERR - ary_thold status not matching the expected value in clock start stop sequence + RC_THOLD_ERR + thold status not matching the expected value in clock start stop sequence TARGET_CHIPLET + CLOCK_CMD + CLOCK_TYPE + REGIONS + READ_CLK NET_CTRL_REGISTERS TARGET_CHIPLET @@ -233,103 +237,20 @@ TARGET_CHIPLET TARGET_TYPE_PERV - READ_CLK_ARY - - - - - RC_NSL_ERR - nsl_thold status not matching the expected value in clock start stop sequence - TARGET_CHIPLET - - NET_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CONFIG_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OTHER_CPLT_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OPCG_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_STATUS_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - ERROR_STATUS_OF_CC - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - READ_CLK_NSL - - - - - RC_SL_ERR - sl_thold status not matching the expected value in clock start stop sequence - TARGET_CHIPLET - - NET_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CONFIG_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OTHER_CPLT_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OPCG_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_STATUS_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - ERROR_STATUS_OF_CC - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - READ_CLK_SL + + TARGET_CHIPLET + HIGH + + + CODE + LOW + + + TARGET_CHIPLET + + + TARGET_CHIPLET + @@ -380,6 +301,20 @@ PERV_CPLT_STAT0 LOOP_COUNT HW_DELAY + + TARGET_CHIPLET + HIGH + + + CODE + LOW + + + TARGET_CHIPLET + + + TARGET_CHIPLET + @@ -430,150 +365,20 @@ PERV_CPLT_STAT0 LOOP_COUNT HW_DELAY - - - - - RC_NEST_ARY_ERR - ary_thold status not matching the expected value in clock start stop sequence - TARGET_CHIPLET - - NET_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CONFIG_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OTHER_CPLT_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OPCG_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_STATUS_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - ERROR_STATUS_OF_CC - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - READ_CLK_ARY - - - - - RC_NEST_NSL_ERR - nsl_thold status not matching the expected value in clock start stop sequence - TARGET_CHIPLET - - NET_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CONFIG_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OTHER_CPLT_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OPCG_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_STATUS_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - ERROR_STATUS_OF_CC - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - READ_CLK_NSL - - - - - RC_NEST_SL_ERR - sl_thold status not matching the expected value in clock start stop sequence - TARGET_CHIPLET - - NET_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CPLT_CONFIG_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OTHER_CPLT_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - OPCG_CTRL_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_STATUS_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - - ERROR_STATUS_OF_CC - TARGET_CHIPLET - TARGET_TYPE_PERV - - - CC_REGISTERS - TARGET_CHIPLET - TARGET_TYPE_PERV - - READ_CLK_SL + + TARGET_CHIPLET + HIGH + + + CODE + LOW + + + TARGET_CHIPLET + + + TARGET_CHIPLET +