diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H index 194d7a67390..b49ad89255c 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H @@ -212,8 +212,11 @@ enum CHIPLET_TYPE PCI2_TYPE, EQ_TYPE, EC_TYPE, + SBE_NOOF_CHIPLETS }; +#define CME_NOOF_CHIPLETS 12 + struct CHIPLET_DATA { // This is the chiplet-ID of the first instance of the Chiplet diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.C b/src/import/chips/p9/utils/imageProcs/p9_tor.C index 913d876fd86..ccc9d180d27 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.C +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.C @@ -1048,13 +1048,12 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr uint32_t i_dbgl ) // Debug option { int rc = 0; - TorPpeBlock_t l_TorPpeBlock; uint8_t bDdCheck = 0; uint32_t ddLevelOffset = 0; uint32_t ddLevelCount = 0; uint32_t ddLevel = 0; uint32_t ddBlockSize = 0; - uint32_t temp = 0, temp1 = 0, local = 0; + uint32_t temp = 0, local = 0; if (i_dbgl > 1) @@ -1275,483 +1274,8 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr return TOR_RING_BLOCKS_FOUND; } - else if (i_RingBlockType == GET_CPLT_LEVEL_RINGS) - { - if (i_dbgl > 1) - { - MY_INF( "TOR_ACCESS_RING(9): CPLT_LEVEL_RING COPY called... \n"); - } - - if (io_RingType == ALLRING) - { - MY_INF("Ambiguity on input PARMS. ALLRING RingType is invalid for CPLT level ring copy \n"); - return TOR_AMBIGUOUS_API_PARMS; - - } - - uint32_t l_cplt_offset = 0; - uint32_t l_ppe_offset = 0; - uint32_t l_cplt_size = 0; - - if (i_PpeType == SBE) - { - SbeTorId_t l_sbeTorId = SBE_NOOF_CHIPLETS; - - switch (io_instanceId) - { - case 1 : - l_sbeTorId = PERV_CPLT; - break; - - case 2 : - l_sbeTorId = N0_CPLT; - break; - - case 3 : - l_sbeTorId = N1_CPLT; - break; - - case 4 : - l_sbeTorId = N2_CPLT; - break; - - case 5 : - l_sbeTorId = N3_CPLT; - break; - - case 6 : - l_sbeTorId = XB_CPLT; - break; - - case 7 : - l_sbeTorId = MC_CPLT; - break; - - case 9 : - l_sbeTorId = OB0_CPLT; - break; - - case 10 : - l_sbeTorId = OB1_CPLT; - break; - - case 11 : - l_sbeTorId = OB2_CPLT; - break; - - case 12 : - l_sbeTorId = OB3_CPLT; - break; - - case 13 : - l_sbeTorId = PCI0_CPLT; - break; - - case 14 : - l_sbeTorId = PCI1_CPLT; - break; - - case 15 : - l_sbeTorId = PCI2_CPLT; - break; - - case 16: - case 17: - case 18: - case 19: - case 20: - case 21: - case 22: - case 23: - case 24: - case 25: - case 26: - case 27: - l_sbeTorId = EQ_CPLT; - break; - - case 32: - case 33: - case 34: - case 35: - case 36: - case 37: - case 38: - case 39: - case 40: - case 41: - case 42: - case 43: - case 44: - case 45: - case 46: - case 47: - case 48: - case 49: - case 50: - case 51: - case 52: - case 53: - case 54: - case 55: - l_sbeTorId = EC_CPLT; - break; - - default : - MY_ERR("io_instanceId=0x%x is not a valid chiplet ID (for SBE)\n", io_instanceId); - return TOR_INVALID_INSTANCE_ID; - } - - temp = (ddLevelOffset >> 2); - int l_word; - - if (i_magic == P9_XIP_MAGIC_HW) - { - l_cplt_offset = *((uint32_t*)i_ringSection + temp); - } - else - { - l_cplt_offset = 0; - } - - if (i_dbgl > 1) - { - MY_INF("SBE(1):Offset 0x%08x \n", l_cplt_offset); - } - - l_cplt_offset = be32toh(l_cplt_offset); - uint32_t l_ppe_cplt_offset = l_cplt_offset; - temp = temp + 2; - l_ppe_offset = *((uint32_t*)i_ringSection + temp); - l_ppe_offset = be32toh(l_ppe_offset); - temp1 = l_cplt_offset; - - if (i_dbgl > 1) - { - MY_INF("SBE(2):Offset 0x%08x 0x%08x 0x%08x 0x%08x\n", l_cplt_offset, - l_ppe_offset, temp, ddLevelOffset); - } - - if (io_RingType == COMMON) - { - temp = l_cplt_offset + ddLevelOffset + (l_sbeTorId * sizeof(TorPpeBlock_t)); - l_word = temp >> 2; - temp = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("SBE(3):COMMON Offset 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, - l_ppe_offset, temp); - } - } - else - { - temp = l_cplt_offset + ddLevelOffset - + (l_sbeTorId * sizeof(TorPpeBlock_t)) - + sizeof(l_TorPpeBlock.TorPpeTypeOffset); - l_word = temp >> 2; - temp = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("SBE(4):INSTANCE Offset 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, - l_ppe_offset, temp); - } - } - - l_cplt_offset = *((uint32_t*)i_ringSection + l_word); - l_cplt_offset = be32toh(l_cplt_offset); - l_word++; - - if (i_dbgl > 1) - { - MY_INF("SBE(5):Offset 0x%08x size 0x%08x \n", l_cplt_offset, l_ppe_offset); - } - - l_cplt_size = *((uint32_t*)i_ringSection + l_word ); - l_cplt_size = be32toh(l_cplt_size); - - if (l_sbeTorId == EC_CPLT && io_RingType == INSTANCE) - { - if (i_magic == P9_XIP_MAGIC_SEEPROM) - { - l_cplt_size = io_ringBlockSize - (l_cplt_offset + l_ppe_cplt_offset); - } - else - { - l_cplt_size = l_ppe_offset - (l_cplt_offset + l_ppe_cplt_offset); - } - } - else - { - l_cplt_size = l_cplt_size - l_cplt_offset; - } - - l_cplt_offset = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("SBE(6): Ring pointer Offset 0x%08x size 0x%08x \n", l_cplt_offset, - l_cplt_size); - } - } - else if (i_PpeType == CME) - { - CmeTorId_t l_cmeTorId = CME_NOOF_CHIPLETS; - - switch (io_instanceId) - { - case 32: - case 33: - l_cmeTorId = CME0_CPLT; - break; - - case 34: - case 35: - l_cmeTorId = CME1_CPLT; - break; - - case 36: - case 37: - l_cmeTorId = CME2_CPLT; - break; - - case 38: - case 39: - l_cmeTorId = CME3_CPLT; - break; - - case 40: - case 41: - l_cmeTorId = CME4_CPLT; - break; - - case 42: - case 43: - l_cmeTorId = CME5_CPLT; - break; - - case 44: - case 45: - l_cmeTorId = CME6_CPLT; - break; - - case 46: - case 47: - l_cmeTorId = CME7_CPLT; - break; - - case 48: - case 49: - l_cmeTorId = CME8_CPLT; - break; - - case 50: - case 51: - l_cmeTorId = CME9_CPLT; - break; - - case 52: - case 53: - l_cmeTorId = CME10_CPLT; - break; - - case 54: - case 55: - l_cmeTorId = CME11_CPLT; - break; - - default : - MY_ERR("io_instanceId=0x%x is not a valid chiplet ID (for CME)\n", io_instanceId); - return TOR_INVALID_INSTANCE_ID; - } - - temp = (ddLevelOffset >> 2) + (sizeof(TorPpeBlock_t) >> 2); - int l_word; - l_cplt_offset = *((uint32_t*)i_ringSection + temp); - - if (i_dbgl > 1) - { - MY_INF("CME(1):ppe type Offset 0x%08x \n", l_cplt_offset); - } - - l_cplt_offset = be32toh(l_cplt_offset); - uint32_t l_ppe_cplt_offset = l_cplt_offset; - temp = temp + 2; - l_ppe_offset = *((uint32_t*)i_ringSection + temp); - l_ppe_offset = be32toh(l_ppe_offset); - temp1 = l_cplt_offset; - - if (i_dbgl > 1) - { - MY_INF("CME(2): Offsets 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, l_ppe_offset, - temp); - } - - if (io_RingType == COMMON) - { - temp = l_cplt_offset + ddLevelOffset; - l_word = temp >> 2; - - if (i_dbgl > 1) - { - MY_INF("CME(3):COMMON Offsets 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, - l_ppe_offset, temp); - } - } - else - { - temp = l_cplt_offset + ddLevelOffset - + (l_cmeTorId * sizeof(l_TorPpeBlock.TorPpeTypeOffset)) - + sizeof(l_TorPpeBlock.TorPpeTypeOffset); - l_word = temp >> 2; - temp = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("CME(4):INSTANCE Offset 0x%08x 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, - l_ppe_offset, l_ppe_cplt_offset, temp); - } - } - - l_cplt_offset = *((uint32_t*)i_ringSection + l_word); - l_cplt_offset = be32toh(l_cplt_offset); - l_word++; - - if (i_dbgl > 1) - { - MY_INF("CME(5):Offset 0x%08x size 0x%08x \n", l_cplt_offset, l_ppe_offset); - } - - l_cplt_size = *((uint32_t*)i_ringSection + l_word ); - l_cplt_size = be32toh(l_cplt_size); - - if (l_cmeTorId == CME11_CPLT && io_RingType == INSTANCE) - { - l_cplt_size = l_ppe_offset - (l_cplt_offset + l_ppe_cplt_offset); - } - else - { - l_cplt_size = l_cplt_size - l_cplt_offset; - } - - l_cplt_offset = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("CME(6): Ring pointer Offset 0x%08x size 0x%08x \n", l_cplt_offset, - l_cplt_size); - } - } - else if (i_PpeType == SGPE) - { - - temp = (ddLevelOffset >> 2) + (2 * (sizeof(TorPpeBlock_t) >> 2)); - int l_word; - l_cplt_offset = *((uint32_t*)i_ringSection + temp); - - if (i_dbgl > 1) - { - MY_INF("SGPE(1):Offset 0x%08x \n", l_cplt_offset); - } - - l_cplt_offset = be32toh(l_cplt_offset); - - temp = temp + 1; - l_ppe_offset = *((uint32_t*)i_ringSection + temp); - l_ppe_offset = be32toh(l_ppe_offset); - temp1 = l_cplt_offset; - - if (i_dbgl > 1) - { - MY_INF("SGPE(2):Offset 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, l_ppe_offset, - temp); - } - - if (io_RingType == COMMON) - { - temp = l_cplt_offset + ddLevelOffset; - l_word = temp >> 2; - - if (i_dbgl > 1) - { - MY_INF("SGPE(3):COMMON Offset 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, - l_ppe_offset, temp); - } - } - else - { - temp = l_cplt_offset + ddLevelOffset - + sizeof(l_TorPpeBlock.TorPpeBlockSize); - l_word = temp >> 2; - temp = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("SGPE(4):INSTANCE Offset 0x%08x 0x%08x 0x%08x \n", l_cplt_offset, - l_ppe_offset, temp); - } - } - - l_cplt_offset = *((uint32_t*)i_ringSection + l_word); - l_cplt_offset = be32toh(l_cplt_offset); - l_word++; - l_cplt_size = *((uint32_t*)i_ringSection + l_word ); - l_cplt_size = be32toh(l_cplt_size); - - if ( io_RingType == INSTANCE) - { - l_cplt_size = l_ppe_offset - l_cplt_offset; - } - else - { - l_cplt_size = l_cplt_size - l_cplt_offset; - } - - l_cplt_offset = l_cplt_offset + ddLevelOffset; - - if (i_dbgl > 1) - { - MY_INF("SGPE(5): Ring pointer Offset 0x%08x size 0x%08x \n", l_cplt_offset, - l_cplt_size); - } - } - else - { - MY_ERR("\t i_PpeType=%d is not supported\n", i_PpeType); - - return TOR_AMBIGUOUS_API_PARMS; - } - - if (io_ringBlockSize >= l_cplt_size) - { - memcpy( (uint8_t*)(*io_ringBlockPtr), - (uint8_t*)i_ringSection + l_cplt_offset + temp1, - (size_t)l_cplt_size); - - io_ringBlockSize = l_cplt_size; - - return TOR_RING_BLOCKS_FOUND; - } - else if (io_ringBlockSize == 0) - { - if (i_dbgl > 0) - { - MY_INF("\tio_ringBlockSize is zero. Returning required size.\n"); - } - - io_ringBlockSize = l_cplt_size; - - return 0; - } - else - { - MY_ERR("\tio_ringBlockSize is less than required size, but not zero.\n"); - - return TOR_BUFFER_TOO_SMALL; - } - } - else + else if ( i_RingBlockType == GET_SINGLE_RING || + i_RingBlockType == PUT_SINGLE_RING ) { if (i_PpeType == SBE && ( i_magic == P9_XIP_MAGIC_HW || @@ -1935,6 +1459,13 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr } } + else + { + MY_ERR("\t RingBlockType=0x%x is not supported. Caller error.\n", + i_RingBlockType); + + return TOR_INVALID_RING_BLOCK_TYPE; + } return TOR_AMBIGUOUS_API_PARMS; } @@ -2054,25 +1585,6 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section i_ringName, i_dbgl ); } - else if (l_ringType == COMMON || l_ringType == INSTANCE) - { - // Get Chiplet level block of ringscopy - // CMO-20161004: This won't work w/VPD rings since they are appended to the end - // of the section, i.e. not immediately after the TOR offset section. - rc = tor_access_ring( i_ringSection, - P9_XIP_MAGIC_HW, - NUM_RING_IDS, - i_ddLevel, - i_PpeType, - l_ringType, - i_RingVariant, - l_instanceId, - GET_CPLT_LEVEL_RINGS, - io_ringBlockPtr, - io_ringBlockSize, - i_ringName, - i_dbgl ); - } else { MY_ERR("TOR_GET_BLOCK_OF_RINGS(2): Wrong input params. Please check passing params\n"); diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.H b/src/import/chips/p9/utils/imageProcs/p9_tor.H index c342ea265fe..0393391585a 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.H +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.H @@ -93,8 +93,7 @@ typedef enum RingBlockType GET_SINGLE_RING = 0x00, GET_DD_LEVEL_RINGS = 0x01, GET_PPE_LEVEL_RINGS = 0x02, - GET_CPLT_LEVEL_RINGS = 0x03, - PUT_SINGLE_RING = 0x04 + PUT_SINGLE_RING = 0x03 } RingBlockType_t; typedef enum RingType @@ -112,44 +111,6 @@ typedef enum PpeType NUM_PPE_TYPES = 0x03 } PpeType_t; -typedef enum SbeTorId -{ - PERV_CPLT = 0, - N0_CPLT = 1, - N1_CPLT = 2, - N2_CPLT = 3, - N3_CPLT = 4, - XB_CPLT = 5, - MC_CPLT = 6, - OB0_CPLT = 7, - OB1_CPLT = 8, - OB2_CPLT = 9, - OB3_CPLT = 10, - PCI0_CPLT = 11, - PCI1_CPLT = 12, - PCI2_CPLT = 13, - EQ_CPLT = 14, - EC_CPLT = 15, - SBE_NOOF_CHIPLETS = 16 -} SbeTorId_t; - -typedef enum CmeTorId -{ - CME0_CPLT = 0, - CME1_CPLT = 1, - CME2_CPLT = 2, - CME3_CPLT = 3, - CME4_CPLT = 4, - CME5_CPLT = 5, - CME6_CPLT = 6, - CME7_CPLT = 7, - CME8_CPLT = 8, - CME9_CPLT = 9, - CME10_CPLT = 10, - CME11_CPLT = 11, - CME_NOOF_CHIPLETS = 12 -} CmeTorId_t; - typedef enum TorOffsetSize { RING_OFFSET_SIZE = 2,