diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index d9ce7dbe561..0f959069cb9 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -214,6 +214,7 @@ HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000)
HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000)
HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000)
HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000)
+HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS, 0x08000000)
HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000)
/// SGPE Hcode
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index dd468116eef..79a0909c5ba 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -655,7 +655,7 @@ extern "C"
* @param i_pChipHomer points to HOMER image.
* @return fapi2 return code.
*/
- fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer )
+ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt )
{
uint8_t attrVal = 0;
uint32_t cmeFlag = 0;
@@ -666,7 +666,6 @@ extern "C"
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE];
-
//Handling flags common to CME and SGPE
FAPI_DBG(" ==================== CME/SGPE Flags =================");
@@ -720,7 +719,19 @@ extern "C"
sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS;
}
- FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" );
+ FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" );
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE,
+ i_procTgt,
+ attrVal),
+ "Error from FAPI_ATTR_GET for attribute ATTR_CME_INSTRUCTION_TRACE_ENABLE");
+
+ if( attrVal )
+ {
+ sgpeFlag |= SGPE_CME_INSTRUCTION_TRACE_BIT_POS;
+ }
+
+ FAPI_DBG("CME Instruction Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" );
// Set PGPE Header Flags from Attributes
FAPI_DBG(" -------------------- PGPE Flags -----------------");
@@ -3450,7 +3461,7 @@ extern "C"
"Final SRAM Image Size Check Failed" );
//Update CME/SGPE Flags in respective image header.
- FAPI_TRY( updateImageFlags( pChipHomer ),
+ FAPI_TRY( updateImageFlags( pChipHomer, i_procTgt ),
"updateImageFlags Failed" );
//Set the Fabric IDs
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
index 3509ac6c172..86c509eabf2 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -841,8 +841,8 @@
This is matched to pbax_groupid of the PMISC Address phase.
Provided by the Machine Readable Workbook.
-
- Platform default: Nimbus systems = 0
+
+ Platform default: Nimbus systems = 0
uint8
@@ -858,8 +858,8 @@
pbax_type=unicast.
Provided by the Machine Readable Workbook.
-
- Platform default: Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID
+
+ Platform default: Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID
uint8
@@ -875,12 +875,12 @@
bit in this vector at the decoded bit location is a 1, then this receive
engine will participate in the broadcast operation.
- Override attribute. Platform value of 0 indiates the OCC firmware will
+ Override attribute. Platform value of 0 indiates the OCC firmware will
perform this function.
uint8
-
+
@@ -1566,6 +1566,27 @@
+
+ ATTR_CME_INSTRUCTION_TRACE_ENABLE
+
+ Enables the SGPE Hcode to enable the CME instruction traces into the L3
+ Trace array for debug. Note: all configured CMEs will be put into this
+ mode if this attribute is ON.
+
+ Consumer: p9_hcode_image_build.c ->
+ SGPE Header field
+
+ Platform default: OFF
+
+ TARGET_TYPE_PROC_CHIP
+ uint8
+
+ OFF = 0x00, ON = 0x01
+
+
+
+
+
ATTR_PGPE_HCODE_FUNCTION_ENABLE
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index 9a4c0ab135e..69739e65816 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -99,6 +99,10 @@
0x0
+
+ ATTR_CME_INSTRUCTION_TRACE_ENABLE
+ 0x0
+
ATTR_IO_OBUS_DCCAL_FLAGS
0x0
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 3be640af91e..370210c6e38 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -32424,6 +32424,31 @@ Measured in GB
+
+ CME_INSTRUCTION_TRACE_ENABLE
+
+ Enables the SGPE Hcode to enable the CME instruction traces into the L3
+ Trace array for debug. Note: all configured CMEs will be put into this
+ mode if this attribute is ON.
+
+ Consumer: p9_hcode_image_build.c ->
+ SGPE Header field
+
+ Platform default: OFF
+
+
+
+
+
+ volatile-zeroed
+
+
+
+ ATTR_CME_INSTRUCTION_TRACE_ENABLE
+ DIRECT
+
+
+
CP_REFCLOCK_RCVR_TERM
@@ -32995,9 +33020,9 @@ Measured in GB
SKIP_HW_VREF_CAL
-
+
In sub DD1.02 Nimbus the HW VREF calibrations should not be run
-
+
@@ -33015,9 +33040,9 @@ Measured in GB
SKIP_RD_VREF_VREFSENSE_OVERRIDE
-
+
In sub DD1.03 Nimbus the HW VREF calibrations should not be run
-
+
@@ -33155,13 +33180,13 @@ Measured in GB
EFF_RANK_GROUP_OVERRIDE
-
+
Override PHY RANK_PAIR settings. First uint16 value is for RANK_PAIR0
register value, and second is for RANK_PAIR1. Note that DIMM1 ranks in
a dual-drop config will be converted from Centaur canonical number
(4,5) to correct PHY settings (2,3). Set this attribute to zero
to use default settings.
-
+
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 86a9608f0f9..92666f3000d 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1305,6 +1305,7 @@
TOD_CPU_DATA
PM_SPWUP_IGNORE_XSTOP_FLAG
SECUREBOOT_PROTECT_DECONFIGURED_TPM
+ CME_INSTRUCTION_TRACE_ENABLE
DO_MSS_WR_VREF
DO_MSS_VREF_DAC