From 52306946f268d843e6b14230d84672983d4a4d58 Mon Sep 17 00:00:00 2001 From: Zane Shelley Date: Wed, 15 Feb 2017 14:27:51 -0600 Subject: [PATCH] PRD: Nimbus DD1.0 workaround for cache CEs Change-Id: I5cab640c9525a710aad751a5a099c27986744cbb CQ: SW380162 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36529 Reviewed-by: Benjamin J. Weisenbeck Reviewed-by: Caleb N. Palmer Reviewed-by: Brian J. Stegmiller Tested-by: Jenkins Server Reviewed-by: Zane C. Shelley Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36566 Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins --- src/usr/diag/prdf/common/plat/p9/p9_ex.rule | 2 +- .../prdf/common/plat/p9/p9_ex_actions.rule | 11 +++++- src/usr/diag/prdf/common/plat/p9/prdfP9Ex.C | 38 +++++++++++++++++++ 3 files changed, 49 insertions(+), 2 deletions(-) diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ex.rule b/src/usr/diag/prdf/common/plat/p9/p9_ex.rule index 91d615c1804..45876f7f1d9 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_ex.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_ex.rule @@ -723,7 +723,7 @@ group gL3FIR filter singlebit, cs_root_cause /** L3FIR[28] * L3 LRU array parity error */ - (rL3FIR, bit(28)) ? self_th_1; + (rL3FIR, bit(28)) ? l3_lru_parity_error; /** L3FIR[29] * L3 cache congruence cache deleted diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule index 72147a05323..8a1afc902cb 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_ex_actions.rule @@ -28,6 +28,7 @@ actionclass l3_cache_ce calloutSelfHigh; threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L3_CACHE_CES) ); funccall("L3CE"); + funccall("cacheCeWorkaround"); }; actionclass l3_cache_ue @@ -39,13 +40,21 @@ actionclass l3_dir_ce { calloutSelfHigh; threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L3_DIR_CES) ); + funccall("cacheCeWorkaround"); +}; + +actionclass l3_lru_parity_error +{ + self_th_1; + funccall("cacheCeWorkaround"); }; actionclass l2_cache_ce { calloutSelfHigh; threshold( field(32 / day), mfg_file(ATTR_MNFG_TH_P8EX_L2_CACHE_CES) ); -# funccall("L2CE"); TODO: RTC 152593 + funccall("L2CE"); + funccall("cacheCeWorkaround"); }; actionclass l2_cache_ue diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9Ex.C b/src/usr/diag/prdf/common/plat/p9/prdfP9Ex.C index 4df843f7815..fbd61cd03fc 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfP9Ex.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9Ex.C @@ -168,6 +168,44 @@ int32_t PostAnalysis( ExtensibleChip * i_exChip, } PRDF_PLUGIN_DEFINE( p9_ex, PostAnalysis ); +/** + * @brief For L2/L3 Cache CEs, L3 Directory CEs, and L3 LRU Parity Errors. + * @param i_chip EX chip. + * @param io_sc Step code data struct. + * @return SUCCESS always + */ +int32_t cacheCeWorkaround( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & io_sc ) +{ + // WORKAROUND: Nimbus DD1.x only. + if ( TARGETING::MODEL_NIMBUS == getChipModel(i_chip->getTrgt()) && + 0x20 > getChipLevel(i_chip->getTrgt()) ) + { + // If we are unable to issue any more line deletes, mask the attention + // and do not make the error log predictive. + if ( io_sc.service_data->IsAtThreshold() ) + io_sc.service_data->clearServiceCall(); + } + // END WORKAROUND + + return SUCCESS; + +} PRDF_PLUGIN_DEFINE( p9_ex, cacheCeWorkaround ); + +/** + * @brief L2FIR[0] - CE detected on L3 cache read + * @param i_chip EX chip. + * @param io_sc Step code data struct. + * @return SUCCESS always + */ +int32_t L2CE( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & io_sc ) +{ + // TODO: RTC 152593 add line delete support + + return SUCCESS; + +} PRDF_PLUGIN_DEFINE( p9_ex, L2CE ); + /** * @brief Handle an L3 CE * @param i_chip Ex chip.