From e346dc4483d3c7b4d0fc16b7ae4d95e448618dad Mon Sep 17 00:00:00 2001 From: Ben Gass Date: Wed, 11 Jan 2017 13:31:41 -0600 Subject: [PATCH] Adding chip_ec_feature attributes for dd2 build Resulting dd10 hw_image file matches the one generated from initfiles in master. Grub boots with resulting image and procedures. Change-Id: I2257448a7dcdb6be44da6196da847cca8ad4077d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34736 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran Tested-by: Hostboot CI Reviewed-by: Matt K. Light Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34865 Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../chips/p9/initfiles/p9.mc.scan.initfile | 16 +- .../chips/p9/initfiles/p9.mca.scom.initfile | 4 +- .../chips/p9/initfiles/p9.mcs.scom.initfile | 2 +- .../xml/attribute_info/chip_ec_attributes.xml | 1312 +++++++++++++++++ 4 files changed, 1323 insertions(+), 11 deletions(-) diff --git a/src/import/chips/p9/initfiles/p9.mc.scan.initfile b/src/import/chips/p9/initfiles/p9.mc.scan.initfile index d93e921083f..9e483d097d6 100644 --- a/src/import/chips/p9/initfiles/p9.mc.scan.initfile +++ b/src/import/chips/p9/initfiles/p9.mc.scan.initfile @@ -10,35 +10,35 @@ target_type 0 TARGET_TYPE_PROC_CHIP; # FOR DD1 Prefetch Limit needs to be scan init to 0 because SCOM is broken (HW366248) # Always OR-ed with previous value. Essentially we can only set bits, not clear. So we want to scan init to 0. # these are n1 n3 -ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC01.PORT1.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC01.PORT1.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC01.PORT2.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC01.PORT2.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC01.PORT3.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC01.PORT3.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC23.PORT0.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC23.PORT0.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC23.PORT1.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC23.PORT1.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC23.PORT2.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC23.PORT2.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } -ispy MC23.PORT3.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L] { +ispy MC23.PORT3.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] { spyv; 0b111111; } diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile index 7560f08b5d4..c3b5a0bf340 100644 --- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile @@ -704,7 +704,7 @@ ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] { # HW366164 - SRQ Fullness Control -ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S] { +ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL [when=S && ATTR_CHIP_EC_FEATURE_HW366164] { spyv; 0b0100; } @@ -725,7 +725,7 @@ ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_RCTRL_CONFIG [when=S] { } # Max 24 64-byte read buffers (HW375534) -ispy MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT [when=S] { +ispy MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_HW375534] { spyv; 0b011000; } diff --git a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile index f1fb2db0b89..38bfd8b9971 100644 --- a/src/import/chips/p9/initfiles/p9.mcs.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mcs.scom.initfile @@ -81,7 +81,7 @@ espy MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_FP_M_BIT [when=S] { } # HW376110 -ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S] { +ispy MC01.PBI01.SCOMFIR.MCPERF1_MERGE_CAPACITY_LIMIT [when=S && ATTR_CHIP_EC_FEATURE_HW376110] { spyv; 0b0111; } diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index a8fb979a05a..e129c58b179 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -29,6 +29,41 @@ --> + + + ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES + TARGET_TYPE_PROC_CHIP + + Returns true if spy name has changed from dd1 to dd2. + Less than Nimbus ec 0x20 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX + TARGET_TYPE_PROC_CHIP + + Returns true if MPW2 bits should be set + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE @@ -182,6 +217,1283 @@ + + ATTR_CHIP_EC_FEATURE_THREAD_REBALANCING + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: Thread rebalancing to lower SMT level not supported. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW365079 + TARGET_TYPE_PROC_CHIP + + DD1 only config, issue: HW365079 + Planning on enabling it with an irritator. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW367017 + TARGET_TYPE_PROC_CHIP + + HW367017 P9N DD1 + Collision with scrubber correcting a CE and a castout operation, resulting in cache corruption + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW393692 + TARGET_TYPE_PROC_CHIP + + HW393692 - need to turn off NCU hardware checker (fir bit 2) for illegal tlbies/slbie formats for DD1. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW372146 + TARGET_TYPE_PROC_CHIP + + HW372146 For turning off clock gating on nctlbsm + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW367321 + TARGET_TYPE_PROC_CHIP + + HW367321 clock gating bug on err_rpt + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW376110 + TARGET_TYPE_PROC_CHIP + + HW376110 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW375534 + TARGET_TYPE_PROC_CHIP + + Max 24 64-byte read buffers (HW375534) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW366164 + TARGET_TYPE_PROC_CHIP + + HW366164 - SRQ Fullness Control + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW366248 + TARGET_TYPE_PROC_CHIP + + FOR P9N DD1 Prefetch Limit needs to be scan init to 0 because SCOM is broken (HW366248) + Always OR-ed with previous value. Essentially we can only set bits, not clear. So we want to scan init to 0. + these are n1 n3 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW395756 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW395756 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW396288 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW396288 - Dispatch Serialize all mtmsrd + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW394497 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW394497 - Turn all mtfpscr/mffspcr ops Dispatch Serialize to enable speculative FPSCR. (HW374002) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW394447_HW394186 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW394447 / HW394186 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW393129 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW393129 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW393318 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW393318 - Turn all decimal quad ops Dispatch Serialize. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW393547 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW393547 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW393929_HW394578 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW393929 / HW394578 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW362088 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW362088 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW391334_HW391367 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW391334 / HW391367 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW387890 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW387890 + NOTE: should be turned back off if LSU gets stuck in a cyclical ntc_plz loop. + This switch was added in RITB as part of a large, multiple-fix solution + for the cycling ntc_plz with DEFAULT=OFF. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW384613 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW384613 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW373955 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW373955 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW381889 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW381889 - Disable TM ROT mode + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW379315 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW379315 - Fix tiered hangbuster triggering ntc_plz + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW347876 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW347876 - default not correct + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_DISABLE_PAGE_WALK_CACHE_HITS + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW373955 - In Radix Mode: Page Walk Cache unsupported + HW361596 / HW371500 / HW373955 - In SDR1 mode and UPRT=1 mode: + Disable Page Walk Cache hits + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_RFC02491 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: DD1 Defer -ldmx not supported (i.e. Garbage Collection RFC02491) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW359913_HW356752 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW359913 / HW356752 + ltptr not supported - will be treated as an illegal instruction + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW364229 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW364229 - enb_reduce_spec mode, causes a tlbie hang + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW330187 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW330187 - Instruction Fusion not supported + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW371453 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW371453 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW379562 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW379562 - Turn off store-forward to LQ + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW376310 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW376310 - Disable forcing TM loads to miss the DDIR1 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW371047 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW371047 - TMDIR disabled due to multi-threaded issue. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW373589 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW373589 - Reject 2nd of lqarx pair ops if they are on back-to-back cycles. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW373167 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW373167 - Problems with arbitrating between NTC and NTC+1 flush requests when one is + recoverable and the other involves trechkpt. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW372808 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW372808 - TM hwsync does not wait on load + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW372208 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW372208 - larx missed bad dval + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW373137 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW373137 - Stop prefetch and invalidate erat collison causing erat multihits + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW371867 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW371867 - Performance enhancement that is too buggy to leave enabled + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW368478 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW368478 - S2Q clock gate has to be disabled + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW360131 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW360131 - POR value is an invalid combination and is not represented in the dial. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW370085 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW370085 - IFU can send an erroneous 2nd "force miss" to the LSU on a shared translation, + causing an unnecessary table walk. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW369677 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW369677 - Dynamic set delete not implemented + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW367863 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW367863 - Workaround when EAT thinks it's empty and IDU still reports that it's out + of itags. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW365384 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW365384 - data prefetch clock gate needed + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW365576 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW365576 - Need to disable reset of LRQ deallocate bit + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW365510 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW365510 - TM merging in the LRQ not supported - disable with chicken switch + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_DISABLE_SPEC_STWCX + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW353069 / HW358383 / HW358418 / HW358662 / HW358824 / HW363605 + Not doing Performance: MB State - Need to disable speculative stwcx + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW363926 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW363926 - Workaround for clockgating bug for Local Very Good Mode (performance) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW339090_HW354135 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW339090 / HW354135 - Branch flush performance + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW361821 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW361821 - Icache way prediction must be disabled for all SMT modes except SMT1 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW380199 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW380199 - L2 store reordering induced consistency bug + Only set at safest risk level + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW396388 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW396388 - Disable recovery by default + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW399524 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW399524 disable functionality, can only be enabled on non-FP/VMX tests + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW375255 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW375255; Defer to DD2: Rd mach goes inactive without sending PF data bypass to L2 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW369979 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW369979; Defer to DD2: [GRUB multi chiplet] l3_fir_reg_l3_hw_control_err L3 FIR bit 24 (mask control_err(2) by setting dial: err_rpt0_mask(2) to ON) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW378093 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW378093; Defer to DD2: edram_info_capture_cfg defaults to wrong value + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW288205_HW392168 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: HW288205 (P8 CQ) : L3 PF Hang fix. Change behavior of L3 Prefetch Back-off mechanism + HW392168 (P9 CQ) : This bug existed in P8 and was set to 0x4. The bug was not fixed + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW392009 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: Enable work around for HW392009 + Auto Special Wakeup Disables [LMCR(12:13)]. Do not scan flush to 1s. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW377094 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU + while lfsr bits being reused in L2 stq causes entry to never be selected due to high priority ld-hit-st override. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW374111 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW374111 snapshot doesn't work for domestic copy that hits the L2 cache. all 16 RC machines need to turn off clock gating + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW373819 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW373819 PEC SBCE could cause coherency problems when running in conjunction with copy/paste + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW371141_HW371628 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW371141 lvext causes unforseen cgc lockouts, bad for performance + HW371628 coherency hole in LVEXT also found must turn off LVEXT. + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW370687 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW370687 xlate_addr_to_id clock gating bug + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW363605 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW363605 Core MB-demote-ack bug + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW370692 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW370692 deadlock allowing snptlbcmp to pass around stcxf + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW394803 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW394803 - Fatal Venus: Critical section fail + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW370984 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW370984 - No wakeup from hypdbell to core 1 stopped in level 2 ESL=0 (SMT1 test) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW376874 + TARGET_TYPE_PROC_CHIP + + DD1 only: HW376874 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW319315 + TARGET_TYPE_PROC_CHIP + + DD1 only: mask TFAC parity errors (HW319315) + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW385178 + TARGET_TYPE_PROC_CHIP + + DD1 only: enable workarounds for HW385178 - Force SMT4 mode for Stop 1 and 2 SPR loss + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW393734 + TARGET_TYPE_PROC_CHIP + + DD1 only: enable workarounds for HW393734 - Stop2 hang workaround + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + ATTR_CHIP_EC_FEATURE_HW396520 TARGET_TYPE_PROC_CHIP