diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
index a87326d973b..cfae24efbbd 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
@@ -105,30 +105,30 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x201105cull, l_scom_buffer ));
 
-            constexpr auto l_NX_DMA_CH0_WATCHDOG_REF_DIV_DIVIDE_BY_4 = 0x2;
-            l_scom_buffer.insert<1, 4, 60, uint64_t>(l_NX_DMA_CH0_WATCHDOG_REF_DIV_DIVIDE_BY_4 );
+            constexpr auto l_NX_DMA_CH0_WATCHDOG_REF_DIV_DIVIDE_BY_512 = 0x9;
+            l_scom_buffer.insert<1, 4, 60, uint64_t>(l_NX_DMA_CH0_WATCHDOG_REF_DIV_DIVIDE_BY_512 );
             constexpr auto l_NX_DMA_CH0_WATCHDOG_TIMER_ENBL_ON = 0x1;
             l_scom_buffer.insert<0, 1, 63, uint64_t>(l_NX_DMA_CH0_WATCHDOG_TIMER_ENBL_ON );
-            constexpr auto l_NX_DMA_CH1_WATCHDOG_REF_DIV_DIVIDE_BY_4 = 0x2;
-            l_scom_buffer.insert<6, 4, 60, uint64_t>(l_NX_DMA_CH1_WATCHDOG_REF_DIV_DIVIDE_BY_4 );
+            constexpr auto l_NX_DMA_CH1_WATCHDOG_REF_DIV_DIVIDE_BY_512 = 0x9;
+            l_scom_buffer.insert<6, 4, 60, uint64_t>(l_NX_DMA_CH1_WATCHDOG_REF_DIV_DIVIDE_BY_512 );
             constexpr auto l_NX_DMA_CH1_WATCHDOG_TIMER_ENBL_ON = 0x1;
             l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NX_DMA_CH1_WATCHDOG_TIMER_ENBL_ON );
-            constexpr auto l_NX_DMA_CH2_WATCHDOG_REF_DIV_DIVIDE_BY_4 = 0x2;
-            l_scom_buffer.insert<11, 4, 60, uint64_t>(l_NX_DMA_CH2_WATCHDOG_REF_DIV_DIVIDE_BY_4 );
+            constexpr auto l_NX_DMA_CH2_WATCHDOG_REF_DIV_DIVIDE_BY_512 = 0x9;
+            l_scom_buffer.insert<11, 4, 60, uint64_t>(l_NX_DMA_CH2_WATCHDOG_REF_DIV_DIVIDE_BY_512 );
             constexpr auto l_NX_DMA_CH2_WATCHDOG_TIMER_ENBL_ON = 0x1;
             l_scom_buffer.insert<10, 1, 63, uint64_t>(l_NX_DMA_CH2_WATCHDOG_TIMER_ENBL_ON );
-            constexpr auto l_NX_DMA_CH3_WATCHDOG_REF_DIV_DIVIDE_BY_4 = 0x2;
-            l_scom_buffer.insert<16, 4, 60, uint64_t>(l_NX_DMA_CH3_WATCHDOG_REF_DIV_DIVIDE_BY_4 );
+            constexpr auto l_NX_DMA_CH3_WATCHDOG_REF_DIV_DIVIDE_BY_512 = 0x9;
+            l_scom_buffer.insert<16, 4, 60, uint64_t>(l_NX_DMA_CH3_WATCHDOG_REF_DIV_DIVIDE_BY_512 );
             constexpr auto l_NX_DMA_CH3_WATCHDOG_TIMER_ENBL_ON = 0x1;
             l_scom_buffer.insert<15, 1, 63, uint64_t>(l_NX_DMA_CH3_WATCHDOG_TIMER_ENBL_ON );
-            constexpr auto l_NX_DMA_CH4_WATCHDOG_REF_DIV_DIVIDE_BY_4 = 0x2;
-            l_scom_buffer.insert<21, 4, 60, uint64_t>(l_NX_DMA_CH4_WATCHDOG_REF_DIV_DIVIDE_BY_4 );
+            constexpr auto l_NX_DMA_CH4_WATCHDOG_REF_DIV_DIVIDE_BY_512 = 0x9;
+            l_scom_buffer.insert<21, 4, 60, uint64_t>(l_NX_DMA_CH4_WATCHDOG_REF_DIV_DIVIDE_BY_512 );
             constexpr auto l_NX_DMA_CH4_WATCHDOG_TIMER_ENBL_ON = 0x1;
             l_scom_buffer.insert<20, 1, 63, uint64_t>(l_NX_DMA_CH4_WATCHDOG_TIMER_ENBL_ON );
             constexpr auto l_NX_DMA_DMA_HANG_TIMER_ENBL_ON = 0x1;
             l_scom_buffer.insert<25, 1, 63, uint64_t>(l_NX_DMA_DMA_HANG_TIMER_ENBL_ON );
-            constexpr auto l_NX_DMA_DMA_HANG_TIMER_REF_DIV_DIVIDE_BY_32 = 0x3;
-            l_scom_buffer.insert<26, 4, 60, uint64_t>(l_NX_DMA_DMA_HANG_TIMER_REF_DIV_DIVIDE_BY_32 );
+            constexpr auto l_NX_DMA_DMA_HANG_TIMER_REF_DIV_DIVIDE_BY_1024 = 0x8;
+            l_scom_buffer.insert<26, 4, 60, uint64_t>(l_NX_DMA_DMA_HANG_TIMER_REF_DIV_DIVIDE_BY_1024 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x201105cull, l_scom_buffer));
         }
         {