From db153208ff2010b1920d5622d4a6aa3ffcbc26eb Mon Sep 17 00:00:00 2001 From: mbroyles Date: Fri, 3 Mar 2017 13:35:13 -0600 Subject: [PATCH] Remove verify pstate RTC: 164718 Change-Id: I4c02e5d118d6492dd48fac972c5d8046aa281f8e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37479 Reviewed-by: Andres A. Lugo-Reyes Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan Reviewed-by: Martha Broyles --- src/occ_405/amec/amec_freq.c | 228 +----------------------------- src/occ_405/amec/amec_freq.h | 42 ------ src/occ_405/amec/amec_slave_smh.c | 40 +++--- src/occ_405/occ_service_codes.h | 3 - src/occ_405/state.c | 2 +- 5 files changed, 30 insertions(+), 285 deletions(-) diff --git a/src/occ_405/amec/amec_freq.c b/src/occ_405/amec/amec_freq.c index b7417ef1..57ac0470 100755 --- a/src/occ_405/amec/amec_freq.c +++ b/src/occ_405/amec/amec_freq.c @@ -77,58 +77,6 @@ BOOLEAN G_non_dps_power_limited = FALSE; opal_proc_voting_reason_t G_amec_opal_proc_throt_reason = NO_THROTTLE; opal_mem_voting_reason_t G_amec_opal_mem_throt_reason = NO_MEM_THROTTLE; -uint16_t G_time_until_freq_check = FREQ_CHG_CHECK_TIME; - -//FFDC SCOM addresses as requested by Greg Still in defect SW247927 -//If new SCOM addresses are added, update the size of the array. -const uint32_t G_pmc_ffdc_scom_addrs[PMC_FFDC_SCOM_ADDRS_SIZE] = -{ - PMC_LFIR_ERR_REG, - PMC_LFIR_ERR_MASK_REG, - OCB_OCCLFIR, - PBA_FIR, - TOD_VALUE_REG -}; - -//FFDC OCI addresses as requested by Greg Still in defect SW247927 -//If new OCI addresses are added, update the size of the array. -const uint32_t G_pmc_ffdc_oci_addrs[PMC_FFDC_OCI_ADDRS_SIZE] = -{ - PMC_MODE_REG, - PMC_PSTATE_MONITOR_AND_CTRL_REG, - PMC_RAIL_BOUNDS_REGISTER, - PMC_PARAMETER_REG0, - PMC_PARAMETER_REG1, - PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG, - PMC_STATUS_REG, - PMC_INTCHP_CTRL_REG1, - PMC_INTCHP_CTRL_REG4, - PMC_INTCHP_STATUS_REG, - PMC_INTCHP_COMMAND_REG, - PMC_INTCHP_PSTATE_REG, - PMC_SPIV_CTRL_REG0A, - PMC_SPIV_CTRL_REG0B, - PMC_SPIV_CTRL_REG1, - PMC_SPIV_CTRL_REG2, - PMC_SPIV_CTRL_REG3, - PMC_SPIV_CTRL_REG4, - PMC_SPIV_STATUS_REG, - PMC_SPIV_COMMAND_REG, - PMC_O2S_CTRL_REG0A, - PMC_O2S_CTRL_REG0B, - PMC_O2S_CTRL_REG1, - PMC_O2S_CTRL_REG2, - PMC_O2S_CTRL_REG4, - PMC_O2S_STATUS_REG, - PMC_O2S_COMMAND_REG, - PMC_O2S_WDATA_REG, - PMC_CORE_DECONFIGURATION_REG, - PMC_FSMSTATE_STATUS_REG, - PMC_GPSA_ACK_COLLECTION_REG, - PMC_GPSA_ACK_COLLECTION_MASK_REG, - PMC_OCC_HEARTBEAT_REG, - 0 //0 marks last OCI address -}; //************************************************************************* // Function Prototypes @@ -292,7 +240,6 @@ void amec_slv_proc_voting_box(void) uint32_t l_core_reason = 0; amec_proc_voting_reason_t l_kvm_throt_reason = NO_THROTTLE; amec_part_t *l_part = NULL; - bool l_freq_req_changed = FALSE; /*------------------------------------------------------------------------*/ /* Code */ @@ -492,13 +439,6 @@ void amec_slv_proc_voting_box(void) l_core_reason = AMEC_VOTING_REASON_OVERRIDE_CORE; } - // If frequency has changed, set the flag - if ( (l_core_freq != g_amec->proc[0].core[k].f_request) || - (l_core_freq != g_amec->sys.fmax)) - { - l_freq_req_changed = TRUE; - } - //STORE core frequency and reason g_amec->proc[0].core[k].f_request = l_core_freq; g_amec->proc[0].core[k].f_reason = l_core_reason; @@ -509,9 +449,12 @@ void amec_slv_proc_voting_box(void) //CURRENT_MODE() may be OCC_MODE_NOCHANGE because STATE change is processed //before MODE change - if ((CURRENT_MODE() != OCC_MODE_DYN_POWER_SAVE) && + if ((CURRENT_MODE() != OCC_MODE_DYN_POWER_SAVE) && (CURRENT_MODE() != OCC_MODE_DYN_POWER_SAVE_FP) && - (CURRENT_MODE() != OCC_MODE_NOCHANGE) && + (CURRENT_MODE() != OCC_MODE_NOM_PERFORMANCE) && + (CURRENT_MODE() != OCC_MODE_MAX_PERFORMANCE) && + (CURRENT_MODE() != OCC_MODE_FMF) && + (CURRENT_MODE() != OCC_MODE_NOCHANGE) && (l_core_reason & NON_DPS_POWER_LIMITED)) { G_non_dps_power_limited = TRUE; @@ -552,16 +495,6 @@ void amec_slv_proc_voting_box(void) } }//End of for loop - // Check if the frequency is going to be changing - if( l_freq_req_changed == TRUE ) - { - G_time_until_freq_check = FREQ_CHG_CHECK_TIME; - } - else if (G_time_until_freq_check != 0) - { - G_time_until_freq_check--; - } - //convert POWERCAP reason to POWER_SUPPLY_FAILURE if ovs is asserted if((l_kvm_throt_reason == POWERCAP) && AMEC_INTF_GET_OVERSUBSCRIPTION()) { @@ -787,9 +720,6 @@ void amec_slv_check_perf(void) /* Code */ /*------------------------------------------------------------------------*/ - // Verify that cores are at proper frequency - amec_verify_pstate(); - do { // was frequency limited by power ? @@ -982,154 +912,6 @@ void amec_slv_check_perf(void) return; } -// Verifies that each core is at the correct frequency after they have had -// time to stabilize -void amec_verify_pstate() -{ -// @TODO - TEMP Pstate functions not defined yet. RTC:164718 -#if 0 - uint8_t l_core = 0; - int8_t l_pstate_from_fmax = 0; - CoreData * l_core_data_ptr; - pmc_pmsr_ffcdc_data_t l_pmc_pmsr_ffdc; - errlHndl_t l_err = NULL; - - if ( (G_time_until_freq_check == 0) && - ( CURRENT_MODE() != OCC_MODE_DYN_POWER_SAVE ) && - ( CURRENT_MODE() != OCC_MODE_DYN_POWER_SAVE_FP ) && - (!G_sysConfigData.system_type.kvm)) - { - // Reset the counter - G_time_until_freq_check = FREQ_CHG_CHECK_TIME; - - // Convert fmax to the corresponding pstate - l_pstate_from_fmax = proc_freq2pstate(g_amec->sys.fmax); - - for( l_core = 0; l_core < MAX_NUM_CORES; l_core++ ) - { - // If the core isn't present, skip it - if(!CORE_PRESENT(l_core)) - { - l_pmc_pmsr_ffdc.pmsr_ffdc_data.data[l_core].value = 0; - continue; - } - - // Get pointer to core data - l_core_data_ptr = proc_get_bulk_core_data_ptr(l_core); - - // Get the core's pmsr data - l_pmc_pmsr_ffdc.pmsr_ffdc_data.data[l_core] = l_core_data_ptr->pcb_slave.pmsr; - - // Verify that the core is running at the correct frequency - // If not, log an error - if( (l_pstate_from_fmax != l_pmc_pmsr_ffdc.pmsr_ffdc_data.data[l_core].fields.local_pstate_actual) && - (l_pstate_from_fmax > l_pmc_pmsr_ffdc.pmsr_ffdc_data.data[l_core].fields.pv_min) && - (l_err == NULL) ) - { - TRAC_ERR("Frequency mismatch in core %d: actual_ps[%d] req_ps[%d] fmax[%d] mode[%d].", - l_core, - l_pmc_pmsr_ffdc.pmsr_ffdc_data.data[l_core].fields.local_pstate_actual, - l_pstate_from_fmax, - g_amec->sys.fmax, - CURRENT_MODE()); - - fill_pmc_ffdc_buffer(&l_pmc_pmsr_ffdc.pmc_ffcdc_data); - - /* @ - * @moduleid AMEC_VERIFY_FREQ_MID - * @reasonCode TARGET_FREQ_FAILURE - * @severity ERRL_SEV_PREDICTIVE - * @userdata1 0 - * @userdata2 0 - * @userdata4 OCC_NO_EXTENDED_RC - * @devdesc A core is not running at the expected frequency - */ - l_err = createErrl( AMEC_VERIFY_FREQ_MID, // i_modId, - TARGET_FREQ_FAILURE, // i_reasonCode, - OCC_NO_EXTENDED_RC, - ERRL_SEV_UNRECOVERABLE, - NULL, // i_trace, - DEFAULT_TRACE_SIZE, // i_traceSz, - 0, // i_userData1, - 0); // i_userData2 - - //Add firmware callout - addCalloutToErrl(l_err, - ERRL_CALLOUT_TYPE_COMPONENT_ID, - ERRL_COMPONENT_ID_FIRMWARE, - ERRL_CALLOUT_PRIORITY_HIGH); - - //Add processor callout - addCalloutToErrl(l_err, - ERRL_CALLOUT_TYPE_HUID, - G_sysConfigData.proc_huid, - ERRL_CALLOUT_PRIORITY_MED); - } - } - - if( l_err != NULL) - { - //Add our register dump to the error log - addUsrDtlsToErrl(l_err, - (uint8_t*) &l_pmc_pmsr_ffdc, - sizeof(l_pmc_pmsr_ffdc), - ERRL_USR_DTL_STRUCT_VERSION_1, - ERRL_USR_DTL_BINARY_DATA); - - REQUEST_RESET(l_err); - } - } -#endif // #if 0: @TODO - TEMP Pstate functions not defined yet -} - -// Fills in a pmc ffdc buffer with lots of PMC related OCI and SCOM registers -void fill_pmc_ffdc_buffer(pmc_ffdc_data_t* i_ffdc_ptr) -{ - int i; - uint32_t l_rc, l_addr, l_data32; - uint64_t l_data64; - - //clear out the entire buffer - memset(i_ffdc_ptr, 0, sizeof(pmc_ffdc_data_t)); - - //first get the OCI accessible FFDC data - for(i = 0; i < PMC_FFDC_OCI_ADDRS_SIZE; i++) - { - l_addr = G_pmc_ffdc_oci_addrs[i]; - if(l_addr) - { - l_data32 = in32(l_addr); - } - else - { - //leave an entry with all zero address and data for eye catcher - break; - } - - //store address along with data for easier parsing - i_ffdc_ptr->oci_regs[i].addr = l_addr; - i_ffdc_ptr->oci_regs[i].data = l_data32; - } - - //then get the SCOM accessible FFDC data - for(i = 0; i < PMC_FFDC_SCOM_ADDRS_SIZE; i++) - { - l_addr = G_pmc_ffdc_scom_addrs[i]; - l_rc = (uint32_t)_getscom(l_addr, &l_data64, SCOM_TIMEOUT); - if(l_rc) - { - //indicate there was a scom failure in collecting the data - l_data64 = 0xFEEDB0B000000000ull; - - //store rc in lower word - l_data64 |= l_rc; - } - - //store address along with data for easier parsing - i_ffdc_ptr->scom_regs[i].addr = l_addr; - i_ffdc_ptr->scom_regs[i].data = l_data64; - } -} /*----------------------------------------------------------------------------*/ /* End */ diff --git a/src/occ_405/amec/amec_freq.h b/src/occ_405/amec/amec_freq.h index bffb6aaa..d2b9c906 100644 --- a/src/occ_405/amec/amec_freq.h +++ b/src/occ_405/amec/amec_freq.h @@ -127,44 +127,6 @@ typedef amec_proc_voting_reason_t opal_proc_voting_reason_t; // Structures //*************************************************************************/ -#define PMC_FFDC_OCI_ADDRS_SIZE 34 -#define PMC_FFDC_SCOM_ADDRS_SIZE 5 - -// scom ffdc format -typedef struct __attribute__ ((packed)) -{ - uint32_t addr; - uint64_t data; -} pmc_ffdc_scom_entry_t; - -// OCI ffdc format -typedef struct -{ - uint32_t addr; - uint32_t data; -} pmc_ffdc_oci_entry_t; - -//PMC FFDC format for user detail section of error log -typedef struct -{ - pmc_ffdc_oci_entry_t oci_regs[PMC_FFDC_OCI_ADDRS_SIZE]; - pmc_ffdc_scom_entry_t scom_regs[PMC_FFDC_SCOM_ADDRS_SIZE]; -} pmc_ffdc_data_t; - -/* TEMP -- This PCBS PMS REG type no longer exists within SSX -typedef struct -{ - pcbs_power_management_status_reg_t data[MAX_NUM_CORES]; -} pmsr_ffdc_data_t; -*/ - -/* TEMP -- PMSR FFDC data doesn't exist due to reason above -typedef struct -{ - pmc_ffdc_data_t pmc_ffcdc_data; - pmsr_ffdc_data_t pmsr_ffdc_data; -} pmc_pmsr_ffcdc_data_t; -*/ //*************************************************************************/ // Globals @@ -173,7 +135,6 @@ typedef struct //*************************************************************************/ // Function Prototypes //*************************************************************************/ -void fill_pmc_ffdc_buffer(pmc_ffdc_data_t* i_ffdc_ptr); // Used to set the freq range that amec can control between. errlHndl_t amec_set_freq_range(const OCC_MODE i_mode); @@ -190,8 +151,5 @@ void amec_slv_mem_voting_box(void); // Amec Detect and log degraded performance errors void amec_slv_check_perf(void); -// Verifies that each core is at the correct frequency -void amec_verify_pstate(); - #endif diff --git a/src/occ_405/amec/amec_slave_smh.c b/src/occ_405/amec/amec_slave_smh.c index c2daa545..e9fd3781 100755 --- a/src/occ_405/amec/amec_slave_smh.c +++ b/src/occ_405/amec/amec_slave_smh.c @@ -318,33 +318,41 @@ void amec_slv_common_tasks_pre(void) // End Function Specification void amec_slv_common_tasks_post(void) { + static bool L_active_1tick = FALSE; + AMEC_DBG("\tAMEC Slave Post-State Common\n"); // Only execute if OCC is in the active state if ( IS_OCC_STATE_ACTIVE() ) { - // Check if we need to change Pmax_clip register setting due to not - // getting any APSS data from Master - amec_slv_check_apss_fail(); + // wait 1 tick after going active to allow pwr sensors to be updated + if(L_active_1tick) + { + // Check if we need to change Pmax_clip register setting due to not + // getting any APSS data from Master + amec_slv_check_apss_fail(); - // Call amec_power_control - amec_power_control(); + // Call amec_power_control + amec_power_control(); - // Call the OCC slave's processor voting box - amec_slv_proc_voting_box(); + // Call the OCC slave's processor voting box + amec_slv_proc_voting_box(); - // Call the frequency state machine - amec_slv_freq_smh(); + // Call the frequency state machine + amec_slv_freq_smh(); - // Call the OCC slave's memory voting box - amec_slv_mem_voting_box(); + // Call the OCC slave's memory voting box + amec_slv_mem_voting_box(); - // Call the OCC slave's performance check - amec_slv_check_perf(); + // Call the OCC slave's performance check + amec_slv_check_perf(); - // Call the 250us trace recording if it has been configured via Amester. - // If not configured, this call will return immediately. - amec_tb_record(AMEC_TB_250US); + // Call the 250us trace recording if it has been configured via Amester. + // If not configured, this call will return immediately. + amec_tb_record(AMEC_TB_250US); + } + else + L_active_1tick = TRUE; } // if an OPAL system & just transitioned to CHAR or OBS state, set proc mnfg override else if ( (IS_OCC_STATE_CHARACTERIZATION() || IS_OCC_STATE_OBSERVATION()) && diff --git a/src/occ_405/occ_service_codes.h b/src/occ_405/occ_service_codes.h index 5df9ecc4..83b1ed0f 100644 --- a/src/occ_405/occ_service_codes.h +++ b/src/occ_405/occ_service_codes.h @@ -92,8 +92,6 @@ enum occReasonCode PMC_FAILURE = 0xB2, /// Data passed as an argument or returned from a function is invalid INTERNAL_INVALID_INPUT_DATA = 0xB3, - /// A core was not at the expected frequency - TARGET_FREQ_FAILURE = 0xB4, /// RTL detected a system checkstop OCC_SYSTEM_HALTED = 0xB5, /// Request to read APSS data failed. @@ -280,7 +278,6 @@ enum occModuleId GETSCOM_FFDC_MID = MAIN_COMP_ID | 0x0a, PUTSCOM_FFDC_MID = MAIN_COMP_ID | 0x0b, HMON_ROUTINE_MID = MAIN_COMP_ID | 0x0c, - AMEC_VERIFY_FREQ_MID = MAIN_COMP_ID | 0x0d, FIR_DATA_MID = MAIN_COMP_ID | 0x0e, CMDH_DBUG_MID = MAIN_COMP_ID | 0x0f, I2C_LOCK_UPDATE = MAIN_COMP_ID | 0x10, diff --git a/src/occ_405/state.c b/src/occ_405/state.c index ce1b4fbf..15990851 100755 --- a/src/occ_405/state.c +++ b/src/occ_405/state.c @@ -677,7 +677,7 @@ errlHndl_t SMGR_observation_to_active() // Set the actual STATE now that we have finished everything else CURRENT_STATE() = OCC_STATE_ACTIVE; - TRAC_IMP("SMGR: Observation to Active Transition Completed"); + TRAC_IMP("SMGR: Observation to Active Transition Completed. OCC role = %d", G_occ_role); } else {