From 69184204d4d86b53f795acc25867c03f4885bf3b Mon Sep 17 00:00:00 2001 From: Dan Crowell Date: Thu, 8 Jun 2017 21:44:44 -0500 Subject: [PATCH] Fix alignment issues in SBE-HB structure Add padding to keep all fields aligned to 8-bytes Add explicit attribute to ensure structure is packed Change-Id: I55ca10034d7adf3e766edb4d0071f649c7c90446 CQ: SW391259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41584 Reviewed-by: Martin Gloff Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Sachin Gupta Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41613 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins --- .../procedures/hwp/nest/p9_sbe_hb_structures.H | 10 +++++++--- .../hwp/nest/p9_sbe_load_bootloader.C | 17 +++++++++++------ 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H index 38ce24c16..d82448e9b 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H @@ -74,6 +74,8 @@ union BootloaderSecureSettings }; // Structure starts at the bootloader zero address +// Note - this structure must remain 64-bit aligned to +// maintain compatibility with Hostboot struct BootloaderConfigData_t { uint32_t version; // bytes 4:7 Version field so we know if there is new data being added @@ -82,8 +84,10 @@ struct BootloaderConfigData_t uint16_t pnorSizeMB; // bytes 10:11 Size of PNOR in MB [ATTR_PNOR_SIZE] uint64_t blLoadSize; // bytes 12:19 Size of Load (Exception vectors and Bootloader) BootloaderSecureSettings secureSettings ; // byte 20 - uint64_t xscomBAR; // bytes 21:28 XSCOM MMIO BAR - uint64_t lpcBAR; // bytes 29:36 LPC MMIO BAR -}; + uint8_t reserved[7]; // bytes 21:27 Reserved space to maintain 64-bit alignment + uint64_t xscomBAR; // bytes 28:35 XSCOM MMIO BAR + uint64_t lpcBAR; // bytes 36:43 LPC MMIO BAR +}; // Note: Want to use '__attribute__((packed))' but compiler won't let us + #endif diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index b4138e1e8..3ad213b56 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -296,15 +296,20 @@ fapi2::ReturnCode p9_sbe_load_bootloader( { l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.secureSettings.data8; } - //At address X + 0x1B (21-28) put the XSCOM BAR - else if (i < 29) + //At address X + 0x15 (21-27) put a zero + else if (i < 28) { - l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.xscomBAR >> (56 - 8 * ((i - 21) % 8))) & 0xFF; + l_data_to_pass_to_pba_array[i] = 0; } - //At address X + 0x1B (29-36) put the LPC BAR - else if (i < 37) + //At address X + 0x1B (28-35) put the XSCOM BAR + else if (i < 36) { - l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.lpcBAR >> (56 - 8 * ((i - 29) % 8))) & 0xFF; + l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.xscomBAR >> (56 - 8 * ((i - 28) % 8))) & 0xFF; + } + //At address X + 0x1B (36-43) put the LPC BAR + else if (i < 44) + { + l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.lpcBAR >> (56 - 8 * ((i - 36) % 8))) & 0xFF; } //Fill the rest with the exception vector instruction else