From d27f5c37d91ae86ee893fdf918a4b497a0553c5e Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Tue, 30 May 2017 07:48:09 -0500 Subject: [PATCH] L3 updates -- p9_sbe_mcs_setup, p9_revert_sbe_mcs_setup p9_revert_sbe_mcs_setup query ATTR_CHIP_UNIT_POS to eliminate dependence on platform getChildren() call returning targets in chip unit position order p9_sbe_mcs_setup merge specialization definitions for set_hb_dcbz_config add FFDC collection p9_sbe_mcs_setup_errors add FFDC, callout actions Change-Id: I26bae24d7686bbba78c5844197a17295ce0de167 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41108 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Benjamin Gass Reviewed-by: Thi N. Tran Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41112 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../p9/procedures/hwp/nest/p9_sbe_mcs_setup.C | 203 ++++++++---------- .../p9/procedures/hwp/nest/p9_sbe_mcs_setup.H | 11 +- .../error_info/p9_sbe_mcs_setup_errors.xml | 20 +- 3 files changed, 110 insertions(+), 124 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C index 2e743e7a0..51206f869 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -25,8 +25,6 @@ /// /// @file p9_sbe_mcs_setup.C /// @brief Configure MC unit to support HB execution (FAPI2) -/// - /// /// @author Joe McGill /// @@ -35,7 +33,7 @@ // *HWP HWP Owner: Joe McGill // *HWP FW Owner: Thi Tran // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: SBE // @@ -48,37 +46,27 @@ #include #include - //------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ const uint8_t MCS_MCFGP_BASE_ADDRESS_START_BIT = 8; //------------------------------------------------------------------------------ -// Function prototypes +// Function definitions //------------------------------------------------------------------------------ /// -/// @brief Set hostboot dcbz MC configuration for one unit target +/// @brief Set hostboot dcbz configuration for one unit target /// +/// @tparam T template parameter, passed in target. /// @param[in] i_target Reference to an MC target (MCS/MI) /// @param[in] i_chip_base_address Chip non-mirrored base address -////// @return FAPI2_RC_SUCCESS if success, else error code. +/// @return FAPI2_RC_SUCCESS if success, else error code. /// template -fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target& i_target, - const uint64_t i_chip_base_address); - - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - - -// specialization for MCS target type -template<> -fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target& i_target, - const uint64_t i_chip_base_address) +fapi2::ReturnCode set_hb_dcbz_config( + const fapi2::Target& i_target, + const uint64_t i_chip_base_address) { FAPI_DBG("Start"); fapi2::buffer l_mcfgp; @@ -87,7 +75,8 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target fapi2::buffer l_mcfirmask_and; fapi2::buffer l_mcaction; - // MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address + // MCFGP -- set BAR valid, configure single MC group with minimum size at + // chip base address FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp), "Error from getScom (MCS_MCFGP)"); l_mcfgp.setBit(); @@ -124,7 +113,6 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target "Error from putScom (MCS_MCPERF1)"); // Unmask MC FIR - // Set MC Fault Isolation Action1 Register l_mcaction.setBit(); FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRACT1, l_mcaction), @@ -137,80 +125,13 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target l_mcfirmask_and.clearBit(); l_mcfirmask_and.clearBit(); l_mcfirmask_and.clearBit(); - l_mcfirmask_and.clearBit(); - FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and), - "Error from putScom (MCS_MCFIRMASK_AND)"); - -fapi_try_exit: - FAPI_DBG("End"); - return fapi2::current_err; -} - - -// specialization for MI target type -template<> -fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target& i_target, - const uint64_t i_chip_base_address) -{ - FAPI_DBG("Start"); - fapi2::buffer l_mcfgp; - fapi2::buffer l_mcmode1; - fapi2::buffer l_mcperf1; - fapi2::buffer l_mcfirmask_and; - fapi2::buffer l_mcaction; - - // MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address - FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp), - "Error from getScom (MCS_MCFGP)"); - l_mcfgp.setBit(); - l_mcfgp.clearBit(); - l_mcfgp.clearBit(); - l_mcfgp.clearBit(); - // group base address field covers RA 8:31 - l_mcfgp.insert(i_chip_base_address, - MCS_MCFGP_GROUP_BASE_ADDRESS, - MCS_MCFGP_GROUP_BASE_ADDRESS_LEN, - MCS_MCFGP_BASE_ADDRESS_START_BIT); - FAPI_TRY(fapi2::putScom(i_target, MCS_MCFGP, l_mcfgp), - "Error from putScom (MCS_MCFGP)"); - // MCMODE1 -- disable speculation, cmd bypass, fp command bypass - FAPI_TRY(fapi2::getScom(i_target, MCS_MCMODE1, l_mcmode1), - "Error from getScom (MCS_MCMODE1)"); - l_mcmode1.setBit(); - l_mcmode1.setBit(); - l_mcmode1.setBit(); - l_mcmode1.setBit(); - FAPI_TRY(fapi2::putScom(i_target, MCS_MCMODE1, l_mcmode1), - "Error from putScom (MCS_MCMODE1)"); - - // MCS_MCPERF1 -- disable fast path - FAPI_TRY(fapi2::getScom(i_target, MCS_MCPERF1, l_mcperf1), - "Error from getScom (MCS_MCPERF1)"); - l_mcperf1.setBit(); - FAPI_TRY(fapi2::putScom(i_target, MCS_MCPERF1, l_mcperf1), - "Error from putScom (MCS_MCPERF1)"); - - // Unmask MC FIR - - // Set MC Fault Isolation Action1 Register - l_mcaction.setBit(); - FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRACT1, l_mcaction), - "Error from putScom (MCS_MCFIRACT1)"); + if (T != fapi2::TARGET_TYPE_MI) + { + // unimplemented for Cumulus/MI type + l_mcfirmask_and.clearBit(); + } - // Clear FIR bits in MC Fault Isolation Mask Register - l_mcfirmask_and.flush<1>(); - l_mcfirmask_and.clearBit(); - l_mcfirmask_and.clearBit(); - l_mcfirmask_and.clearBit(); - l_mcfirmask_and.clearBit(); - l_mcfirmask_and.clearBit(); - // There is no MCS_MCFIR_INVALID_ADDRESS for cumulus. - // l_mcfirmask_and.clearBit(); FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and), "Error from putScom (MCS_MCFIRMASK_AND)"); @@ -221,45 +142,90 @@ fapi_try_exit: // HWP entry point -fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target& i_target) +fapi2::ReturnCode +p9_sbe_mcs_setup(const fapi2::Target& i_target) { FAPI_INF("Start"); - uint8_t l_is_master_sbe; - uint8_t l_is_mpipl; - uint8_t l_ipl_type; - uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, l_chip_base_address_mmio; - uint64_t l_hostboot_hrmor_offset; + fapi2::ATTR_PROC_SBE_MASTER_CHIP_Type l_is_master_sbe; + fapi2::ATTR_IS_MPIPL_Type l_is_mpipl; + fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_ipl_type; auto l_mcs_chiplets = i_target.getChildren(); auto l_mi_chiplets = i_target.getChildren(); const fapi2::Target FAPI_SYSTEM; - // configure one MC on master chip (only if IPL is loading hostboot, and is not memory - // preserving) - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target, l_is_master_sbe), + // configure one MC on master chip (only if IPL is loading hostboot, and is + // not memory preserving) + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, + i_target, + l_is_master_sbe), "Error from FAPI_ATTR_GET (ATTR_PROC_SBE_MASTER_CHIP)"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, + FAPI_SYSTEM, + l_is_mpipl), "Error from FAPI_ATTR_GET (ATTR_IS_MPIPL)"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_ipl_type), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, + FAPI_SYSTEM, + l_ipl_type), "Error from FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)"); if ((l_ipl_type == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL) && - l_is_master_sbe && - !l_is_mpipl) + (l_is_master_sbe == fapi2::ENUM_ATTR_PROC_SBE_MASTER_CHIP_TRUE) && + (l_is_mpipl == fapi2::ENUM_ATTR_IS_MPIPL_FALSE)) { + uint64_t l_chip_base_address_nm0; + uint64_t l_chip_base_address_nm1; + uint64_t l_chip_base_address_m; + uint64_t l_chip_base_address_mmio; + uint64_t l_hostboot_hrmor_offset; #ifdef __PPE__ + // assert that a viable MCS/MI chiplet is found to service dcbz on the // master processor - FAPI_ASSERT(l_mcs_chiplets.size() || l_mi_chiplets.size(), - fapi2::P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR().set_CHIP(i_target), - "No functional MC unit target found"); + if (!l_mcs_chiplets.size() && + !l_mi_chiplets.size()) + { + // collect PG FFDC + uint16_t l_n1_pg = 0xFFFF; + uint16_t l_n3_pg = 0xFFFF; + + for (auto l_tgt : i_target.getChildren( + static_cast( + fapi2::TARGET_FILTER_NEST_WEST | + fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + uint8_t l_attr_chip_unit_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + l_tgt, + l_attr_chip_unit_pos), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, + l_tgt, + ((l_attr_chip_unit_pos == N3_CHIPLET_ID) ? + (l_n3_pg) : + (l_n1_pg))), + "Error from FAPI_ATTR_GET(ATTR_PG)"); + } + + FAPI_ASSERT(false, + fapi2::P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR() + .set_CHIP(i_target) + .set_IS_MASTER_SBE(l_is_master_sbe) + .set_IS_MPIPL(l_is_mpipl) + .set_IPL_TYPE(l_ipl_type) + .set_N1_PG(l_n1_pg) + .set_N3_PG(l_n3_pg), + "No functional MC unit target found on master chip"); + } + #endif // determine base address - // = (drawer non-mirrored base address) + (hostboot HRMOR offset) - // min MCS base size is 4GB, local HB will always be below + // = (drawer non-mirrored base address) + (hostboot HRMOR offset) + // min MCS base size is 4GB, local HB will always be below FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, EFF_FBC_GRP_ID_ONLY, l_chip_base_address_nm0, @@ -268,7 +234,8 @@ fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target( + l_mcs_chiplets.front(), + l_chip_base_address_nm0), "Error from set_hb_dcbz_config (MCS)"); } else if (l_mi_chiplets.size()) { - FAPI_TRY(set_hb_dcbz_config(l_mi_chiplets.front(), - l_chip_base_address_nm0), + FAPI_TRY(set_hb_dcbz_config( + l_mi_chiplets.front(), + l_chip_base_address_nm0), "Error from set_hb_dcbz_config (MI)"); } else diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H index fad6629b1..d780cdc30 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,7 @@ // *HWP HWP Owner: Joe McGill // *HWP FW Owner: Thi Tran // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: SBE // @@ -56,7 +56,8 @@ //------------------------------------------------------------------------------ /// function pointer typedef definition for HWP call support -typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)(const fapi2::Target&); +typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)( + const fapi2::Target&); //------------------------------------------------------------------------------ // Function prototypes @@ -71,7 +72,9 @@ extern "C" /// @param[in] i_target Reference to processor chip target /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. - fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target& i_target); + fapi2::ReturnCode p9_sbe_mcs_setup( + const fapi2::Target& i_target); + } // extern "C" #endif // _P9_SBE_MCS_SETUP_H_ diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml index b12dc9e1d..2e3541411 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml @@ -5,7 +5,7 @@ - + @@ -25,10 +25,24 @@ - RC_P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR - There is no functional MC chiplet (MCS/MI) present on the master chip + + There is no functional MCS/MI unit target configured on the master chip + CHIP + IS_MASTER_SBE + IS_MPIPL + IPL_TYPE + N1_PG + N3_PG + + CHIP + HIGH + + + CODE + LOW +