From 0247540839c42e554426eb7e9a5acefdbbba5a4d Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Fri, 10 Feb 2017 12:20:01 +1100 Subject: [PATCH] hw/phb3: Apply config register filter after HW change The PCI config register is applied before the HW register is changed. It won't work when this mechanism is used to capture the change to SRIOV capability in subsequent patch. This moves the logic around so that the filter is applied after HW register is changed. Currently, it's used to cache bridge's pref window base/length. The code change shouldn't affect that. So no functional changes introduced by this. Signed-off-by: Gavin Shan Reviewed-by: Russell Currey Signed-off-by: Stewart Smith --- hw/phb3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index cdb52cb1165a..6ac10fdd84bf 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -318,9 +318,6 @@ static int64_t phb3_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \ return OPAL_HARDWARE; \ } \ \ - phb3_pcicfg_filter(phb, bdfn, offset, sizeof(type), \ - (uint32_t *)&data, true); \ - \ addr = PHB_CA_ENABLE; \ addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \ addr = SETFIELD(PHB_CA_REG, addr, offset); \ @@ -337,6 +334,9 @@ static int64_t phb3_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \ (offset & (4 - sizeof(type))), data); \ } \ \ + phb3_pcicfg_filter(phb, bdfn, offset, sizeof(type), \ + (uint32_t *)&data, true); \ + \ return OPAL_SUCCESS; \ }