diff --git a/src/librustc_middle/arena.rs b/src/librustc_middle/arena.rs
index a97db3134dc9e..2df878c3fb220 100644
--- a/src/librustc_middle/arena.rs
+++ b/src/librustc_middle/arena.rs
@@ -76,6 +76,12 @@ macro_rules! arena_types {
             [few] hir_definitions: rustc_hir::definitions::Definitions,
             [] hir_owner: rustc_middle::hir::Owner<$tcx>,
             [] hir_owner_nodes: rustc_middle::hir::OwnerNodes<$tcx>,
+
+            // Note that this deliberately duplicates items in the `rustc_hir::arena`,
+            // since we need to allocate this type on both the `rustc_hir` arena
+            // (during lowering) and the `librustc_middle` arena (for decoding MIR)
+            [decode] asm_template: rustc_ast::ast::InlineAsmTemplatePiece,
+
         ], $tcx);
     )
 }
diff --git a/src/test/incremental/issue-72386.rs b/src/test/incremental/issue-72386.rs
new file mode 100644
index 0000000000000..3dc7f502a5992
--- /dev/null
+++ b/src/test/incremental/issue-72386.rs
@@ -0,0 +1,22 @@
+// revisions: rpass1 cfail1 rpass3
+// only-x86_64
+// Regression test for issue #72386
+// Checks that we don't ICE when switching to an invalid register
+// and back again
+
+#![feature(asm)]
+
+#[cfg(any(rpass1, rpass3))]
+fn main() {
+    unsafe {
+        asm!("nop")
+    }
+}
+
+#[cfg(cfail1)]
+fn main() {
+    unsafe {
+        asm!("nop",out("invalid_reg")_)
+        //[cfail1]~^ ERROR invalid register
+    }
+}