From c19e7b629b42fc2e153893762397a336423e6ec3 Mon Sep 17 00:00:00 2001 From: Huon Wilson Date: Thu, 3 Sep 2015 14:50:20 -0700 Subject: [PATCH] Add various pointer & void-using x86 intrinsics. --- src/etc/platform-intrinsics/x86/avx.json | 42 ++++ src/etc/platform-intrinsics/x86/avx2.json | 48 ++++- src/etc/platform-intrinsics/x86/sse.json | 7 + src/etc/platform-intrinsics/x86/sse2.json | 42 ++++ src/etc/platform-intrinsics/x86/sse3.json | 7 + src/librustc_platform_intrinsics/x86.rs | 245 +++++++++++++++++++++- 6 files changed, 378 insertions(+), 13 deletions(-) diff --git a/src/etc/platform-intrinsics/x86/avx.json b/src/etc/platform-intrinsics/x86/avx.json index 4ac82fb90e900..2c1492c2954c8 100644 --- a/src/etc/platform-intrinsics/x86/avx.json +++ b/src/etc/platform-intrinsics/x86/avx.json @@ -36,6 +36,20 @@ "ret": "f(32-64)", "args": ["0", "0"] }, + { + "intrinsic": "{0.width_mm}_maskload_{0.data_type}", + "width": [128, 256], + "llvm": "maskload.{0.data_type_short}{0.width_suffix}", + "ret": ["f(32-64)"], + "args": ["0SPc/S8", "0s->0"] + }, + { + "intrinsic": "{3.width_mm}_maskstore_{3.data_type}", + "width": [128, 256], + "llvm": "maskstore.{3.data_type_short}{3.width_suffix}", + "ret": "V", + "args": ["F(32-64)Pm/S8", "1Dsv->1Dv", "1Dv"] + }, { "intrinsic": "256_min_{0.data_type}", "width": [256], @@ -78,6 +92,20 @@ "ret": "f32", "args": ["f32"] }, + { + "intrinsic": "256_storeu_{2.data_type}", + "width": [256], + "llvm": "storeu.ps.256", + "ret": "V", + "args": ["f(32-64)Pm/U8", "1D"] + }, + { + "intrinsic": "256_storeu_si256", + "width": [256], + "llvm": "storeu.dq.256", + "ret": "V", + "args": ["u8Pm/U8", "1D"] + }, { "intrinsic": "256_sqrt_{0.data_type}", "width": [256], @@ -147,6 +175,20 @@ "llvm": "ptestz.256", "ret": "S32", "args": ["u64", "u64"] + }, + { + "intrinsic": "256_zeroall", + "width": [256], + "llvm": "vzeroall", + "ret": "V", + "args": [] + }, + { + "intrinsic": "256_zeroupper", + "width": [256], + "llvm": "vzeroupper", + "ret": "V", + "args": [] } ] } diff --git a/src/etc/platform-intrinsics/x86/avx2.json b/src/etc/platform-intrinsics/x86/avx2.json index bd260ec02e930..e88ff3d2b806d 100644 --- a/src/etc/platform-intrinsics/x86/avx2.json +++ b/src/etc/platform-intrinsics/x86/avx2.json @@ -4,21 +4,21 @@ { "intrinsic": "256_abs_{0.data_type}", "width": [256], - "llvm": "avx2.pabs.{0.data_type_short}", + "llvm": "pabs.{0.data_type_short}", "ret": "s(8-32)", "args": ["0"] }, { "intrinsic": "256_adds_{0.data_type}", "width": [256], - "llvm": "avx2.padd{0.kind_short}s.{0.data_type_short}", + "llvm": "padd{0.kind_short}s.{0.data_type_short}", "ret": "i(8-16)", "args": ["0", "0"] }, { "intrinsic": "256_avg_{0.data_type}", "width": [256], - "llvm": "avx2.pavg.{0.data_type_short}", + "llvm": "pavg.{0.data_type_short}", "ret": "u(8-16)", "args": ["0", "0"] }, @@ -64,6 +64,48 @@ "ret": "s16", "args": ["s8", "s8"] }, + { + "intrinsic": "{0.width_mm}_mask_i32gather_{0.data_type}", + "width": [128, 256], + "llvm": "gather.d.{0.data_type_short}{0.width_suffix}", + "ret": ["s32", "f32"], + "args": ["0", "0SPc/S8", "s32", "0s->0", "S32/8"] + }, + { + "intrinsic": "{0.width_mm}_mask_i32gather_{0.data_type}", + "width": [128, 256], + "llvm": "gather.d.{0.data_type_short}{0.width_suffix}", + "ret": ["s64", "f64"], + "args": ["0", "0SPc/S8", "s32x128", "0s->0", "S32/8"] + }, + { + "intrinsic": "{3.width_mm}_mask_i64gather_{0.data_type}", + "width": [128, 256], + "llvm": "gather.q.{0.data_type_short}{0.width_suffix}", + "ret": ["s32x128", "f32x128"], + "args": ["0", "0SPc/S8", "s64", "0s->0", "S32/8"] + }, + { + "intrinsic": "{0.width_mm}_mask_i64gather_{0.data_type}", + "width": [128, 256], + "llvm": "gather.q.{0.data_type_short}{0.width_suffix}", + "ret": ["s64", "f64"], + "args": ["0", "0SPc/S8", "s64", "0s->0", "S32/8"] + }, + { + "intrinsic": "{0.width_mm}_maskload_{0.data_type}", + "width": [128, 256], + "llvm": "maskload.{0.data_type_short}{0.width_suffix}", + "ret": ["s(32-64)"], + "args": ["0Pc/S8", "0"] + }, + { + "intrinsic": "{2.width_mm}_maskstore_{2.data_type}", + "width": [128, 256], + "llvm": "maskstore.{2.data_type_short}{2.width_suffix}", + "ret": "V", + "args": ["S(32-64)Pm/S8", "1Dv", "2"] + }, { "intrinsic": "256_max_{0.data_type}", "width": [256], diff --git a/src/etc/platform-intrinsics/x86/sse.json b/src/etc/platform-intrinsics/x86/sse.json index 27da842934c0c..adff0dc41b2af 100644 --- a/src/etc/platform-intrinsics/x86/sse.json +++ b/src/etc/platform-intrinsics/x86/sse.json @@ -42,6 +42,13 @@ "llvm": "!llvm.sqrt.v4f32", "ret": "f32", "args": ["0"] + }, + { + "intrinsic": "_storeu_ps", + "width": [128], + "llvm": "storeu.ps", + "ret": "V", + "args": ["F32Pm/S8", "f32"] } ] } diff --git a/src/etc/platform-intrinsics/x86/sse2.json b/src/etc/platform-intrinsics/x86/sse2.json index abd0b369573a0..d09980d95f31b 100644 --- a/src/etc/platform-intrinsics/x86/sse2.json +++ b/src/etc/platform-intrinsics/x86/sse2.json @@ -15,6 +15,13 @@ "ret": "u(8-16)", "args": ["0", "0"] }, + { + "intrinsic": "_lfence", + "width": [128], + "llvm": "lfence", + "ret": "V", + "args": [] + }, { "intrinsic": "_madd_epi16", "width": [128], @@ -22,6 +29,13 @@ "ret": "s32", "args": ["s16", "s16"] }, + { + "intrinsic": "_maskmoveu_si128", + "width": [128], + "llvm": "maskmov.dqu", + "ret": "V", + "args": ["u8", "u8", "U8Pm"] + }, { "intrinsic": "_max_{0.data_type}", "width": [128], @@ -36,6 +50,13 @@ "ret": "f64", "args": ["0", "0"] }, + { + "intrinsic": "_mfence", + "width": [128], + "llvm": "fence", + "ret": "V", + "args": [] + }, { "intrinsic": "_min_{0.data_type}", "width": [128], @@ -99,6 +120,13 @@ "ret": "u64", "args": ["u8", "u8"] }, + { + "intrinsic": "_sfence", + "width": [128], + "llvm": "sfence", + "ret": "V", + "args": [] + }, { "intrinsic": "_sqrt_pd", "width": [128], @@ -106,6 +134,20 @@ "ret": "f64", "args": ["0"] }, + { + "intrinsic": "_storeu_pd", + "width": [128], + "llvm": "storeu.pd", + "ret": "V", + "args": ["F64Pm/U8", "f64"] + }, + { + "intrinsic": "_storeu_si128", + "width": [128], + "llvm": "storeu.dq", + "ret": "V", + "args": ["u8Pm/U8", "u8"] + }, { "intrinsic": "_subs_{0.data_type}", "width": [128], diff --git a/src/etc/platform-intrinsics/x86/sse3.json b/src/etc/platform-intrinsics/x86/sse3.json index 376e32fa91568..ed13595929d1b 100644 --- a/src/etc/platform-intrinsics/x86/sse3.json +++ b/src/etc/platform-intrinsics/x86/sse3.json @@ -21,6 +21,13 @@ "llvm": "hsub.{0.data_type}", "ret": "f(32-64)", "args": ["0", "0"] + }, + { + "intrinsic": "_lddqu_si128", + "width": [128], + "llvm": "ldu.dq", + "ret": "u8", + "args": ["0Pc/S8"] } ] } diff --git a/src/librustc_platform_intrinsics/x86.rs b/src/librustc_platform_intrinsics/x86.rs index 26421cb3e80ee..2dfd00e9ce3bf 100644 --- a/src/librustc_platform_intrinsics/x86.rs +++ b/src/librustc_platform_intrinsics/x86.rs @@ -13,7 +13,7 @@ #![allow(unused_imports)] -use {Intrinsic, i, i_, u, u_, f, v, agg, p, void}; +use {Intrinsic, i, i_, u, u_, f, v, v_, agg, p, void}; use IntrinsicDef::Named; use rustc::middle::ty; @@ -50,6 +50,11 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(f(32), 4), definition: Named("llvm.sqrt.v4f32") }, + "_storeu_ps" => Intrinsic { + inputs: vec![p(false, f(32), Some(i(8))), v(f(32), 4)], + output: void(), + definition: Named("llvm.x86.sse.storeu.ps") + }, "_adds_epi8" => Intrinsic { inputs: vec![v(i(8), 16), v(i(8), 16)], output: v(i(8), 16), @@ -80,11 +85,21 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(u(16), 8), definition: Named("llvm.x86.sse2.pavg.w") }, + "_lfence" => Intrinsic { + inputs: vec![], + output: void(), + definition: Named("llvm.x86.sse2.lfence") + }, "_madd_epi16" => Intrinsic { inputs: vec![v(i(16), 8), v(i(16), 8)], output: v(i(32), 4), definition: Named("llvm.x86.sse2.pmadd.wd") }, + "_maskmoveu_si128" => Intrinsic { + inputs: vec![v(u(8), 16), v(u(8), 16), p(false, u(8), None)], + output: void(), + definition: Named("llvm.x86.sse2.maskmov.dqu") + }, "_max_epi16" => Intrinsic { inputs: vec![v(i(16), 8), v(i(16), 8)], output: v(i(16), 8), @@ -100,6 +115,11 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(f(64), 2), definition: Named("llvm.x86.sse2.max.pd") }, + "_mfence" => Intrinsic { + inputs: vec![], + output: void(), + definition: Named("llvm.x86.sse2.fence") + }, "_min_epi16" => Intrinsic { inputs: vec![v(i(16), 8), v(i(16), 8)], output: v(i(16), 8), @@ -160,11 +180,26 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(u(64), 2), definition: Named("llvm.x86.sse2.psad.bw") }, + "_sfence" => Intrinsic { + inputs: vec![], + output: void(), + definition: Named("llvm.x86.sse2.sfence") + }, "_sqrt_pd" => Intrinsic { inputs: vec![v(f(64), 2)], output: v(f(64), 2), definition: Named("llvm.sqrt.v2f64") }, + "_storeu_pd" => Intrinsic { + inputs: vec![p(false, f(64), Some(u(8))), v(f(64), 2)], + output: void(), + definition: Named("llvm.x86.sse2.storeu.pd") + }, + "_storeu_si128" => Intrinsic { + inputs: vec![p(false, v(u(8), 16), Some(u(8))), v(u(8), 16)], + output: void(), + definition: Named("llvm.x86.sse2.storeu.dq") + }, "_subs_epi8" => Intrinsic { inputs: vec![v(i(8), 16), v(i(8), 16)], output: v(i(8), 16), @@ -215,6 +250,11 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(f(64), 2), definition: Named("llvm.x86.sse3.hsub.pd") }, + "_lddqu_si128" => Intrinsic { + inputs: vec![p(true, v(u(8), 16), Some(i(8)))], + output: v(u(8), 16), + definition: Named("llvm.x86.sse3.ldu.dq") + }, "_abs_epi8" => Intrinsic { inputs: vec![v(i(8), 16)], output: v(i(8), 16), @@ -490,6 +530,46 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(f(64), 4), definition: Named("llvm.x86.avx.max.pd.256") }, + "_maskload_ps" => Intrinsic { + inputs: vec![p(true, f(32), Some(i(8))), v_(i(32), f(32), 4)], + output: v(f(32), 4), + definition: Named("llvm.x86.avx.maskload.ps") + }, + "_maskload_pd" => Intrinsic { + inputs: vec![p(true, f(64), Some(i(8))), v_(i(64), f(64), 2)], + output: v(f(64), 2), + definition: Named("llvm.x86.avx.maskload.pd") + }, + "256_maskload_ps" => Intrinsic { + inputs: vec![p(true, f(32), Some(i(8))), v_(i(32), f(32), 8)], + output: v(f(32), 8), + definition: Named("llvm.x86.avx.maskload.ps.256") + }, + "256_maskload_pd" => Intrinsic { + inputs: vec![p(true, f(64), Some(i(8))), v_(i(64), f(64), 4)], + output: v(f(64), 4), + definition: Named("llvm.x86.avx.maskload.pd.256") + }, + "_maskstore_ps" => Intrinsic { + inputs: vec![p(false, f(32), Some(i(8))), v_(i(32), f(32), 4), v(f(32), 4)], + output: void(), + definition: Named("llvm.x86.avx.maskstore.ps") + }, + "_maskstore_pd" => Intrinsic { + inputs: vec![p(false, f(64), Some(i(8))), v_(i(64), f(64), 2), v(f(64), 2)], + output: void(), + definition: Named("llvm.x86.avx.maskstore.pd") + }, + "256_maskstore_ps" => Intrinsic { + inputs: vec![p(false, f(32), Some(i(8))), v_(i(32), f(32), 8), v(f(32), 8)], + output: void(), + definition: Named("llvm.x86.avx.maskstore.ps.256") + }, + "256_maskstore_pd" => Intrinsic { + inputs: vec![p(false, f(64), Some(i(8))), v_(i(64), f(64), 4), v(f(64), 4)], + output: void(), + definition: Named("llvm.x86.avx.maskstore.pd.256") + }, "256_min_ps" => Intrinsic { inputs: vec![v(f(32), 8), v(f(32), 8)], output: v(f(32), 8), @@ -540,6 +620,21 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(f(32), 8), definition: Named("llvm.x86.avx.rsqrt.ps.256") }, + "256_storeu_ps" => Intrinsic { + inputs: vec![p(false, v(f(32), 8), Some(u(8))), v(f(32), 8)], + output: void(), + definition: Named("llvm.x86.avx.storeu.ps.256") + }, + "256_storeu_pd" => Intrinsic { + inputs: vec![p(false, v(f(64), 4), Some(u(8))), v(f(64), 4)], + output: void(), + definition: Named("llvm.x86.avx.storeu.ps.256") + }, + "256_storeu_si256" => Intrinsic { + inputs: vec![p(false, v(u(8), 32), Some(u(8))), v(u(8), 32)], + output: void(), + definition: Named("llvm.x86.avx.storeu.dq.256") + }, "256_sqrt_ps" => Intrinsic { inputs: vec![v(f(32), 8)], output: v(f(32), 8), @@ -625,50 +720,60 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: i(32), definition: Named("llvm.x86.avx.ptestz.256") }, + "256_zeroall" => Intrinsic { + inputs: vec![], + output: void(), + definition: Named("llvm.x86.avx.vzeroall") + }, + "256_zeroupper" => Intrinsic { + inputs: vec![], + output: void(), + definition: Named("llvm.x86.avx.vzeroupper") + }, "256_abs_epi8" => Intrinsic { inputs: vec![v(i(8), 32)], output: v(i(8), 32), - definition: Named("llvm.x86.avx2.avx2.pabs.b") + definition: Named("llvm.x86.avx2.pabs.b") }, "256_abs_epi16" => Intrinsic { inputs: vec![v(i(16), 16)], output: v(i(16), 16), - definition: Named("llvm.x86.avx2.avx2.pabs.w") + definition: Named("llvm.x86.avx2.pabs.w") }, "256_abs_epi32" => Intrinsic { inputs: vec![v(i(32), 8)], output: v(i(32), 8), - definition: Named("llvm.x86.avx2.avx2.pabs.d") + definition: Named("llvm.x86.avx2.pabs.d") }, "256_adds_epi8" => Intrinsic { inputs: vec![v(i(8), 32), v(i(8), 32)], output: v(i(8), 32), - definition: Named("llvm.x86.avx2.avx2.padds.b") + definition: Named("llvm.x86.avx2.padds.b") }, "256_adds_epu8" => Intrinsic { inputs: vec![v(u(8), 32), v(u(8), 32)], output: v(u(8), 32), - definition: Named("llvm.x86.avx2.avx2.paddus.b") + definition: Named("llvm.x86.avx2.paddus.b") }, "256_adds_epi16" => Intrinsic { inputs: vec![v(i(16), 16), v(i(16), 16)], output: v(i(16), 16), - definition: Named("llvm.x86.avx2.avx2.padds.w") + definition: Named("llvm.x86.avx2.padds.w") }, "256_adds_epu16" => Intrinsic { inputs: vec![v(u(16), 16), v(u(16), 16)], output: v(u(16), 16), - definition: Named("llvm.x86.avx2.avx2.paddus.w") + definition: Named("llvm.x86.avx2.paddus.w") }, "256_avg_epu8" => Intrinsic { inputs: vec![v(u(8), 32), v(u(8), 32)], output: v(u(8), 32), - definition: Named("llvm.x86.avx2.avx2.pavg.b") + definition: Named("llvm.x86.avx2.pavg.b") }, "256_avg_epu16" => Intrinsic { inputs: vec![v(u(16), 16), v(u(16), 16)], output: v(u(16), 16), - definition: Named("llvm.x86.avx2.avx2.pavg.w") + definition: Named("llvm.x86.avx2.pavg.w") }, "256_hadd_epi16" => Intrinsic { inputs: vec![v(i(16), 16), v(i(16), 16)], @@ -710,6 +815,126 @@ pub fn find<'tcx>(_tcx: &ty::ctxt<'tcx>, name: &str) -> Option { output: v(i(16), 16), definition: Named("llvm.x86.avx2.pmadd.ub.sw") }, + "_mask_i32gather_epi32" => Intrinsic { + inputs: vec![v(i(32), 4), p(true, i(32), Some(i(8))), v(i(32), 4), v(i(32), 4), i_(32, 8)], + output: v(i(32), 4), + definition: Named("llvm.x86.avx2.gather.d.d") + }, + "_mask_i32gather_ps" => Intrinsic { + inputs: vec![v(f(32), 4), p(true, f(32), Some(i(8))), v(i(32), 4), v_(i(32), f(32), 4), i_(32, 8)], + output: v(f(32), 4), + definition: Named("llvm.x86.avx2.gather.d.ps") + }, + "256_mask_i32gather_epi32" => Intrinsic { + inputs: vec![v(i(32), 8), p(true, i(32), Some(i(8))), v(i(32), 8), v(i(32), 8), i_(32, 8)], + output: v(i(32), 8), + definition: Named("llvm.x86.avx2.gather.d.d.256") + }, + "256_mask_i32gather_ps" => Intrinsic { + inputs: vec![v(f(32), 8), p(true, f(32), Some(i(8))), v(i(32), 8), v_(i(32), f(32), 8), i_(32, 8)], + output: v(f(32), 8), + definition: Named("llvm.x86.avx2.gather.d.ps.256") + }, + "_mask_i32gather_epi64" => Intrinsic { + inputs: vec![v(i(64), 2), p(true, i(64), Some(i(8))), v(i(32), 4), v(i(64), 2), i_(32, 8)], + output: v(i(64), 2), + definition: Named("llvm.x86.avx2.gather.d.q") + }, + "_mask_i32gather_pd" => Intrinsic { + inputs: vec![v(f(64), 2), p(true, f(64), Some(i(8))), v(i(32), 4), v_(i(64), f(64), 2), i_(32, 8)], + output: v(f(64), 2), + definition: Named("llvm.x86.avx2.gather.d.pd") + }, + "256_mask_i32gather_epi64" => Intrinsic { + inputs: vec![v(i(64), 4), p(true, i(64), Some(i(8))), v(i(32), 4), v(i(64), 4), i_(32, 8)], + output: v(i(64), 4), + definition: Named("llvm.x86.avx2.gather.d.q.256") + }, + "256_mask_i32gather_pd" => Intrinsic { + inputs: vec![v(f(64), 4), p(true, f(64), Some(i(8))), v(i(32), 4), v_(i(64), f(64), 4), i_(32, 8)], + output: v(f(64), 4), + definition: Named("llvm.x86.avx2.gather.d.pd.256") + }, + "_mask_i64gather_epi32" => Intrinsic { + inputs: vec![v(i(32), 4), p(true, i(32), Some(i(8))), v(i(64), 2), v(i(32), 4), i_(32, 8)], + output: v(i(32), 4), + definition: Named("llvm.x86.avx2.gather.q.d") + }, + "_mask_i64gather_ps" => Intrinsic { + inputs: vec![v(f(32), 4), p(true, f(32), Some(i(8))), v(i(64), 2), v_(i(32), f(32), 4), i_(32, 8)], + output: v(f(32), 4), + definition: Named("llvm.x86.avx2.gather.q.ps") + }, + "256_mask_i64gather_epi32" => Intrinsic { + inputs: vec![v(i(32), 4), p(true, i(32), Some(i(8))), v(i(64), 4), v(i(32), 4), i_(32, 8)], + output: v(i(32), 4), + definition: Named("llvm.x86.avx2.gather.q.d") + }, + "256_mask_i64gather_ps" => Intrinsic { + inputs: vec![v(f(32), 4), p(true, f(32), Some(i(8))), v(i(64), 4), v_(i(32), f(32), 4), i_(32, 8)], + output: v(f(32), 4), + definition: Named("llvm.x86.avx2.gather.q.ps") + }, + "_mask_i64gather_epi64" => Intrinsic { + inputs: vec![v(i(64), 2), p(true, i(64), Some(i(8))), v(i(64), 2), v(i(64), 2), i_(32, 8)], + output: v(i(64), 2), + definition: Named("llvm.x86.avx2.gather.q.q") + }, + "_mask_i64gather_pd" => Intrinsic { + inputs: vec![v(f(64), 2), p(true, f(64), Some(i(8))), v(i(64), 2), v_(i(64), f(64), 2), i_(32, 8)], + output: v(f(64), 2), + definition: Named("llvm.x86.avx2.gather.q.pd") + }, + "256_mask_i64gather_epi64" => Intrinsic { + inputs: vec![v(i(64), 4), p(true, i(64), Some(i(8))), v(i(64), 4), v(i(64), 4), i_(32, 8)], + output: v(i(64), 4), + definition: Named("llvm.x86.avx2.gather.q.q.256") + }, + "256_mask_i64gather_pd" => Intrinsic { + inputs: vec![v(f(64), 4), p(true, f(64), Some(i(8))), v(i(64), 4), v_(i(64), f(64), 4), i_(32, 8)], + output: v(f(64), 4), + definition: Named("llvm.x86.avx2.gather.q.pd.256") + }, + "_maskload_epi32" => Intrinsic { + inputs: vec![p(true, v(i(32), 4), Some(i(8))), v(i(32), 4)], + output: v(i(32), 4), + definition: Named("llvm.x86.avx2.maskload.d") + }, + "_maskload_epi64" => Intrinsic { + inputs: vec![p(true, v(i(64), 2), Some(i(8))), v(i(64), 2)], + output: v(i(64), 2), + definition: Named("llvm.x86.avx2.maskload.q") + }, + "256_maskload_epi32" => Intrinsic { + inputs: vec![p(true, v(i(32), 8), Some(i(8))), v(i(32), 8)], + output: v(i(32), 8), + definition: Named("llvm.x86.avx2.maskload.d.256") + }, + "256_maskload_epi64" => Intrinsic { + inputs: vec![p(true, v(i(64), 4), Some(i(8))), v(i(64), 4)], + output: v(i(64), 4), + definition: Named("llvm.x86.avx2.maskload.q.256") + }, + "_maskstore_epi32" => Intrinsic { + inputs: vec![p(false, i(32), Some(i(8))), v(i(32), 4), v(i(32), 4)], + output: void(), + definition: Named("llvm.x86.avx2.maskstore.d") + }, + "_maskstore_epi64" => Intrinsic { + inputs: vec![p(false, i(64), Some(i(8))), v(i(64), 2), v(i(64), 2)], + output: void(), + definition: Named("llvm.x86.avx2.maskstore.q") + }, + "256_maskstore_epi32" => Intrinsic { + inputs: vec![p(false, i(32), Some(i(8))), v(i(32), 8), v(i(32), 8)], + output: void(), + definition: Named("llvm.x86.avx2.maskstore.d.256") + }, + "256_maskstore_epi64" => Intrinsic { + inputs: vec![p(false, i(64), Some(i(8))), v(i(64), 4), v(i(64), 4)], + output: void(), + definition: Named("llvm.x86.avx2.maskstore.q.256") + }, "256_max_epi8" => Intrinsic { inputs: vec![v(i(8), 32), v(i(8), 32)], output: v(i(8), 32),