somaproject / eproc

FPGA-core event processor

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eproc /
name age message
file .gitignore Wed Dec 17 05:20:39 -0800 2008 added gitignore [ericmjonas]
file README Mon Jan 07 08:09:37 -0800 2008 * The event processor, a picoblaze-inspired p... [/C=US/ST=Massachusetts/O=Massachusetts Institute of Technology/OU=Client CA v1/CN=Eric M Jonas/emailAddress=jonas@MIT.EDU]
directory assemble/ Mon Feb 18 18:34:31 -0800 2008 * updated with txcounters; now to test in hw ... [/C=US/ST=Massachusetts/O=Massachusetts Institute of Technology/OU=Client CA v1/CN=Eric M Jonas/emailAddress=jonas@MIT.EDU]
directory docs/ Sat Feb 09 15:41:20 -0800 2008 eventprocnow with TX Request buffer git-svn-id... [/C=US/ST=Massachusetts/O=Massachusetts Institute of Technology/OU=Client CA v1/CN=Eric M Jonas/emailAddress=jonas@MIT.EDU]
directory sim/ Wed Dec 17 12:47:04 -0800 2008 Unit sim tests all pass [ericmjonas]
directory test/ Tue Dec 16 10:50:10 -0800 2008 Added gitignores [ericmjonas]
directory vhdl/ Thu Jun 25 10:04:43 -0700 2009 Updated txreqbrambuffer to now have a clock ena... [ericmjonas]
README
The EventProc is a general-purpose event processor designed to run at
50 MIPS/100 MHz and be synthesizable in a spartan-3. It was designed
to simplify some of the more complex state-control logic present when
trying to operate on the event bus, and is loosly modeled off of the
Xilinx PicoBlaze series of constant programmable state machines.

A DSL has been created in python to aid in the programming of the
device. Up to 16 hardware-accelerated event-processing handlers can be
installed, each with a range of acceptable cmds and srcs to respond
to.

The "EProc" design consists of an ecore, the core processor element
which can be tested and used independently.

TODO:
ecore: test the other jumps
ecore: implement INPORT instructions
ecore: is this the final state of the ALU? 
ecore: document instruction menumonics
assemble: other ALU ops? 
assemble: specialized event-based ALU ops? 
eproc: verify that the event tx stuff