{"payload":{"header_redesign_enabled":false,"results":[{"id":"309937041","archived":false,"color":"#b2b7f8","followers":150,"has_funding_file":false,"hl_name":"wuxx/icesugar-pro","hl_trunc_description":"iCESugar series FPGA dev board","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":309937041,"name":"icesugar-pro","owner_id":1648489,"owner_login":"wuxx","updated_at":"2022-11-17T08:07:52.797Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":51,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Awuxx%252Ficesugar-pro%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/wuxx/icesugar-pro/star":{"post":"R2dm7vz0QOIst5-z7kohUwSRGOWzBC6Yj5OOJ0mN3LGApmVhAQAlrTAfXKiUtwiQBmiPzLwGw6iH8B5n-pLD7A"},"/wuxx/icesugar-pro/unstar":{"post":"LV-SGTr7Snl0xesED4prd7JfHfhAtny49ges-y7C-IntR9DNoTHvI9xLyiZgHTIJN9CXl_Y0wvYo_zVyO4wa8g"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"VwVG-v4MkINz44-Fl0nGZdL-TtgMtvqoEZyajbdIcn614KVc2A3xnS9_XFflURry0T0gaDslDsRn504sWKDYSQ"}}},"title":"Repository search results"}