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Pull requests: Xilinx/RapidWright
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Test that Versal site pins are acquired correctly
needs new release
Dependent on the next future release
#1247
opened Jul 8, 2025 by
eddieh-xlnx
•
Draft
[EDIFNetlist] Create a wrapper EDIFCell constructor
#1238
opened Jun 27, 2025 by
clavin-xlnx
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Fix DesignTools.getConnectionPips for sinks driven by lut constant generators
#1231
opened Jun 20, 2025 by
reillymck
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Array Builder Tool - Replicate Optimized Kernels in an Array
#1163
opened Apr 10, 2025 by
clavin-xlnx
•
Draft
[EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()
#1148
opened Feb 14, 2025 by
eddieh-xlnx
•
Draft
[DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA
#1137
opened Jan 13, 2025 by
eddieh-xlnx
•
Draft
[RWRoute] Adjust wire base costs + cross SLR estimates
#1030
opened Jul 12, 2024 by
eddieh-xlnx
•
Draft
[DesignTools.deletePblock()]: utility to delete a pblock
#1020
opened Jun 30, 2024 by
Licheng-Guo
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[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017
opened Jun 25, 2024 by
clavin-xlnx
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Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011
opened Jun 21, 2024 by
clavin-xlnx
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Node.getAllWiresInNode() returns empty list when Vivado doesn't
bug
#1002
opened Jun 12, 2024 by
eddieh-xlnx
•
Draft
[DeviceResourcesWriter] Output resource timings for US+
#1001
opened Jun 12, 2024 by
eddieh-xlnx
•
Draft
Adds a tieoff method for module instances with unconnected inputs
#811
opened Sep 7, 2023 by
clavin-xlnx
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Inconsistent behaviour for Cell.getSitePinFromLogicalPin()
bug
#473
opened Jul 14, 2022 by
eddieh-xlnx
•
Draft
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