Skip to content

MIPS/ASM: may optimize SW + ADDIU #132685

@wzssyqa

Description

@wzssyqa
Contributor

An asm code like

        .set    reorder
xxx:
$BB0_1:                                 # %for.body
        sw      $4, 0($2)
        addiu   $2, $2, 4
        bne     $2, $3, $BB0_1

may be optimized to

        .set    reorder
xxx:
$BB0_1:                                 # %for.body
        addiu   $2, $2, 4
        sw      $4, -4($2)
        bne     $2, $3, $BB0_1

So that the sw can be placed into delay slot.

Activity

wzssyqa

wzssyqa commented on Mar 24, 2025

@wzssyqa
ContributorAuthor

@yingopq do you have any interesting on it?

yingopq

yingopq commented on Mar 24, 2025

@yingopq
Contributor

OK, I would do research on it.

wzssyqa

wzssyqa commented on Mar 24, 2025

@wzssyqa
ContributorAuthor

The C code for it is like

int x[114500];
void f() {
   for (int i = 0; i < 114500; i++)
       x[i] = 5;
}

llvmbot

llvmbot commented on Mar 24, 2025

@llvmbot
Member

@llvm/issue-subscribers-backend-mips

Author: YunQiang Su (wzssyqa)

An asm code like ``` .set reorder xxx: $BB0_1: # %for.body sw $4, 0($2) addiu $2, $2, 4 bne $2, $3, $BB0_1 ```

may be optimized to

        .set    reorder
xxx:
$BB0_1:                                 # %for.body
        addiu   $2, $2, 4
        sw      $4, -4($2)
        bne     $2, $3, $BB0_1

So that the sw can be placed into delay slot.

yingopq

yingopq commented on Mar 25, 2025

@yingopq
Contributor

After ./build/bin/clang --target=mipsel-linux-gnu -O3 -S 1.c -o 1.s, the result is:

$BB0_1:                                 # %for.body
                                        # =>This Inner Loop Header: Depth=1
	addu	$1, $3, $2
	addiu	$2, $2, 4
	bne	$2, $5, $BB0_1
	sw	$4, 0($1)
# %bb.2:                                # %for.cond.cleanup
	jr	$ra
	nop

sw has been placed in the delay slot of bne.

I can not reproduce sw+addiu+bne.

brad0

brad0 commented on May 14, 2025

@brad0
Contributor
wzssyqa

wzssyqa commented on May 14, 2025

@wzssyqa
ContributorAuthor

After ./build/bin/clang --target=mipsel-linux-gnu -O3 -S 1.c -o 1.s, the result is:

$BB0_1:                                 # %for.body
                                        # =>This Inner Loop Header: Depth=1
	addu	$1, $3, $2
	addiu	$2, $2, 4
	bne	$2, $5, $BB0_1
	sw	$4, 0($1)
# %bb.2:                                # %for.cond.cleanup
	jr	$ra
	nop

sw has been placed in the delay slot of bne.

I can not reproduce sw+addiu+bne.

Just use my asm example.

wzssyqa

wzssyqa commented on May 14, 2025

@wzssyqa
ContributorAuthor

Another example that delay slot is not used

        .set    reorder
xxx:
$BB0_1:                                 # %for.body
        mfhc1   $2, $f12
        jr      $ra
brad0

brad0 commented on Jun 7, 2025

@brad0
Contributor

Ping.

yingopq

yingopq commented on Jun 10, 2025

@yingopq
Contributor

After ./build/bin/clang --target=mipsel-linux-gnu -O3 -S 1.c -o 1.s, the result is:

$BB0_1:                                 # %for.body
                                        # =>This Inner Loop Header: Depth=1
	addu	$1, $3, $2
	addiu	$2, $2, 4
	bne	$2, $5, $BB0_1
	sw	$4, 0($1)
# %bb.2:                                # %for.cond.cleanup
	jr	$ra
	nop

sw has been placed in the delay slot of bne.
I can not reproduce sw+addiu+bne.

Just use my asm example.

Did you mean doing optimization in MipsAsmParser?

added a commit that references this issue on Jun 20, 2025
1c055e8

2 remaining items

Loading
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Assignees

No one assigned

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

      Development

      Participants

      @wzssyqa@MaskRay@brad0@EugeneZelenko@llvmbot

      Issue actions

        MIPS/ASM: may optimize SW + ADDIU · Issue #132685 · llvm/llvm-project