This gem contains Ruby routines for parsing org-mode files. The most significant thing this library does today is convert org-mode files to HTML or textile.

Project Interaction Library for Emacs

An Emacs web feeds client

Web Extension for saving a faithful copy of a complete web page in a single HTML file

A Firefox Add-on (WebExtension) to copy selected web page into Org-mode formatted text!

A presenter console with multi-monitor support for PDF files.

Blogging with Org-mode for very lazy people

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

Python packages providing a library for Verification Stimulus and Coverage

Generate address space documentation HTML from compiled SystemRDL input

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

🌊 Digital timing diagram rendering engine

write beautiful state charts 🙀

lowRISC Style Guides

Sail RISC-V model

Spike, a RISC-V ISA Simulator

Icarus Verilog

Yosys Open SYnthesis Suite

SystemVerilog to Verilog conversion

Rewrite of tree-sitter-verilog

SystemVerilog grammar for tree-sitter

SystemVerilog parser library fully compliant with IEEE 1800-2017

SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

SystemVerilog compiler and language services

Test suite designed to check compliance with the SystemVerilog standard.

BookSim 2.0

Network on Chip Simulator

GNU toolchain for RISC-V, including GCC

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux