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Tool <code>verible-verilog-lint</code>: fatal flex scanner internal error

rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).

Status: Open.

#2438 In chipsalliance/verible;

· Toliak opened on Jul 15, 2025

Flex and Bison toolchain switching stopped working with bazel 8

Status: Open.

#2435 In chipsalliance/verible;

· hzeller opened on Jul 14, 2025

verible-verilog-ls not operated in vs code

language-serverLanguage server related issuesLanguage server related issues

Status: Open.

#2434 In chipsalliance/verible;

· krcowboy opened on Jul 5, 2025

Add ifdef formatting

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2433 In chipsalliance/verible;

· wsnyder opened on Jun 26, 2025

vscode plugin verible Format is unavailable

language-serverLanguage server related issuesLanguage server related issues

Status: Open.

#2432 In chipsalliance/verible;

· LinYu369 opened on Jun 25, 2025

SVA Multi-clocked property leads to parser error

rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).

Status: Open.

#2431 In chipsalliance/verible;

· ajeethakv opened on Jun 19, 2025

Doc: broken links

style-linterVerilog style-linter issuesVerilog style-linter issues

Status: Open.

#2430 In chipsalliance/verible;

· franky920920 opened on Jun 16, 2025

Non ANSI-C style input,output port declaration Verilog code linter issue

style-linterVerilog style-linter issuesVerilog style-linter issues

Status: Open.

#2429 In chipsalliance/verible;

· sscarfi opened on Jun 11, 2025

SVA sequence fails to parse

rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).

Status: Open.

#2427 In chipsalliance/verible;

· svenka3 opened on Jun 4, 2025

Formatted output is lexically different from the input (inside comment).

formatterVerilog code formatter issuesVerilog code formatter issues

Status: Open.

#2424 In chipsalliance/verible;

· daniel-s-larsen opened on Jun 2, 2025

LSP crashes on rename (symbol-table.cc:1188:20)

fuzzing

language-serverLanguage server related issuesLanguage server related issues

Status: Open.

#2421 In chipsalliance/verible;

· henryhchchc opened on May 26, 2025

LSP crashes on rename (symbol-table.cc:162:5)

fuzzing

language-serverLanguage server related issuesLanguage server related issues

project-toolIssues related to the project tool/symbol tableIssues related to the project tool/symbol table

Status: Open.

#2420 In chipsalliance/verible;

· henryhchchc opened on May 26, 2025