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@Panda-Cores

Panda-Cores

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  1. PandaZero Public

    A pipelined, in-order implementation of the RV32I ISA

    SystemVerilog 7 1

Repositories

Showing 8 of 8 repositories
  • caches Public

    simple WB cache, WorkInProgress

    SystemVerilog 0 0 0 0 Updated Aug 18, 2020
  • PandaZero Public

    A pipelined, in-order implementation of the RV32I ISA

    SystemVerilog 7 1 0 0 Updated Aug 9, 2020
  • gpio_module Public
    SystemVerilog 0 0 0 0 Updated Aug 9, 2020
  • timer_module Public
    SystemVerilog 1 0 0 0 Updated Aug 9, 2020
  • wishbone Public
    SystemVerilog 2 0 0 0 Updated Aug 9, 2020
  • load_store_unit Public
    SystemVerilog 1 0 1 0 Updated Aug 4, 2020
  • debug_module Public
    SystemVerilog 1 0 1 0 Updated Aug 3, 2020
  • common Public archive
    SystemVerilog 2 1 5 0 Updated Aug 3, 2020

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