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Skandakm29/README.md

MasterHead

Typing Animation

A 2nd year ECE student at BMSCE.
Passionate About Silicon, Circuits & Innovation.

Coding
  • 🚀 Currently Working On: FPGA design, ASIC flow, and Physical Design (PnR).
  • 📚 Currently Learning: SystemVerilog, Python, and advanced ASIC methodologies.
  • 🤝 Looking to Collaborate On: VLSI, FPGA, and Physical Design projects.
  • 📩 Email: kmskanda29@gmail.com

🌍 Connect with Me

Skanda LinkedIn GitHub Email

🔧 Tech Stack

Verilog Python OpenROAD Yosys Synthesis Vivado Quartus Prime

📊 GitHub Stats

GitHub Streak

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  1. uart_loopback Public

    Universal Asynchronous Receiver-Transmitter (UART) loopback on the VSD Squadcom Mini FPGA board

    Verilog 2

  2. Real-Time-Sensor-Data-Acquisition-and-Transmission-System Public

    This theme focuses on developing systems that interface with various sensors to collect data, process it using the FPGA, and transmit the information to external devices through communication proto…

    Verilog 1

  3. vsd_sqaudron_mini_fpga Public

    This repo contains four FPGA-based projects showcasing real-time UART communication, LED control, and sensor data acquisition. Designed using Verilog, Yosys, and NextPNR, running on the VSD Squadro…

    Verilog 3 1