The Institute for Complex Systems (ICS) targets the ever-increasing complexity of hardware/software systems. Here, the institute considers suitable abstraction levels, i.e. Virtual Prototypes (VPs) in SystemC for HW/SW systems at the Electronic System Level (ESL), HW designs in Verilog/VHDL at the Register Transfer Level (RTL), down to the gate-level. Primary research areas are verification, debugging, and synthesis, all major problems in Electronic Design Automation (EDA). We heavily use the RISC-V ISA in our research work (see e.g. our open-source RISC-V VP++).
Institute for Complex Systems (ICS), Johannes Kepler University Linz
ICS conducts research in EDA with focus on verification, debugging, and synthesis; abstraction levels: SystemC virtual prototypes, RTL downto gate-level.
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riscv-vp-plusplus
riscv-vp-plusplus PublicRISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.
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epex-formal-rv32-model
epex-formal-rv32-model PublicA RISC-V RV32 model ready for SMT program synthesis.
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- riscv-vp-plusplus Public
RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.
- GUI-VP_Kit Public
Quick-to-create and easy-to-use platform for experimentation with Linux on the open-source SystemC RISC-V based virtual prototype GUI-VP
- pyinstruction-decoder Public
- instruction-decoder Public
- relation_coverage Public
