RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
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Updated
Nov 16, 2023 - Verilog
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design, Placement Legalization, Global Routing)
A GPT-GNN based verilog netlist partitioner for 3D IC design
Coursework of NTHU CS613500 VLSI Physical Design Automation
This is the PowerSynth backend with the command line interface (CLI)
Courseworks of VLSI Physical Design Automation, NTHU CS course teached by prof. Ting-Chi Wang in fall 2023
PowerSynth 1 Series (v1.0-v1.9) Source Code
This is the cross-platform PowerSynth 2 front end based on QT
🧱 Physical design C++ Code
This contains the materials for the PowerSynth 2 release package excluding the source code
Fall 2024 NYCU Physical Design Automation (PDA)
PowerSynth 1 Series (v1.0-v1.9) Package Materials
NYCU Physical Design Automation
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