Verilator open-source SystemVerilog simulator and lint system
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Updated
May 3, 2025 - C++
Verilator open-source SystemVerilog simulator and lint system
RISC-V CPU Core (RV32IM)
A small, light weight, RISC CPU soft core
32-bit Superscalar RISC-V CPU
VeeR EH1 core
An abstraction library for interfacing EDA tools
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
HDL support for VS Code
A simple, basic, formally verified UART controller
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
VeeR EL2 Core
A utility for Composing FPGA designs from Peripherals
A wishbone controlled scope for FPGA's
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
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