{"payload":{"header_redesign_enabled":false,"results":[{"id":"160406579","archived":false,"color":"#adb2cb","followers":165,"has_funding_file":false,"hl_name":"Gowtham1729/Image-Processing","hl_trunc_description":"Image Processing Toolbox in Verilog using Basys3 FPGA","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":160406579,"name":"Image-Processing","owner_id":25081151,"owner_login":"Gowtham1729","updated_at":"2023-09-19T06:07:53.684Z","has_issues":true}},"sponsorable":false,"topics":["python","fpga","ram","pixel","vhdl","image-processing","python3","verilog","convolution","vivado","motion-blur","verilog-hdl","basys3","digital-systems","hsync","basys","basys-board","coe","verilog-project","basys3-fpga"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":56,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AGowtham1729%252FImage-Processing%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/Gowtham1729/Image-Processing/star":{"post":"Z4QtLBIPzeeGkouUVBQOuH8HAM5CerEsmGl5KuiixIus6mkgmwojFQg_3CSrqluCglg4OXM8ON-AEAc-6HPoCQ"},"/Gowtham1729/Image-Processing/unstar":{"post":"tlO1rMwnk3NaeZOi_2cBp8gdC46Rr3P1ijapW9GDFfJDqSW6Ea04Zm6dBmKgo3XfUREQ8ibEqdD-B3quwC_lDg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"ynaMWgu2A6-gU2wDu8lg-lQaCyEn2xkMa1RLtXOHu3pxTFg9Fx-vUFoZYO3o1LodlSIsPlyMCBfIgOZxoZKt1A"}}},"title":"Repository search results"}