{"payload":{"header_redesign_enabled":false,"results":[{"id":"202815014","archived":false,"color":"#DAE1C2","followers":1034,"has_funding_file":true,"hl_name":"hdl-util/hdmi","hl_trunc_description":"Send video/audio over HDMI on an FPGA","language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":202815014,"name":"hdmi","owner_id":60591791,"owner_login":"hdl-util","updated_at":"2024-02-03T21:20:10.758Z","has_issues":true}},"sponsorable":false,"topics":["audio","video","fpga","intel","xilinx","vivado","altera","hdmi","systemverilog","dvi","quartus","hdlmake"],"type":"Public","help_wanted_issues_count":1,"good_first_issue_issues_count":1,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":87,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ahdl-util%252Fhdmi%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/hdl-util/hdmi/star":{"post":"IexmjwQ-DaInBVXJao_h7cP95cw4XWrwcWEoV8dlmbOSFjkgiGa-LOxzNBZgDcQtLNtTMNyaVoztWzuuCRH02w"},"/hdl-util/hdmi/unstar":{"post":"QsAGOrsKEYD6zA7qvRTqn3v00IGq7IUJ3Sd79iotpQ-qvoVnagwmEEXrAqpzNbSDgI8n-AwUR7LDs9JpEj8nwg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"btBMjataB3pRRfZ_5hYKSkriv5viLeGX4XYdtwWoSYYTa-yulGQGVXLkqE3JLSwfXu9ARINUN3fERh6l6jEUiA"}}},"title":"Repository search results"}