{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"Cores-VeeR-EL2","owner":"chipsalliance","isFork":false,"description":"VeeR EL2 Core","allTopics":["fpga","processor","riscv","rtl","risc-v","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","el2"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":28,"starsCount":228,"forksCount":68,"license":"Apache License 2.0","participation":[8,24,23,0,0,0,0,0,1,2,11,12,10,23,25,26,22,4,0,0,2,4,3,11,9,20,8,4,0,2,2,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,4,5,14],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T14:03:11.558Z"}},{"type":"Public","name":"caliptra-rtl","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra RoT IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":12,"issueCount":47,"starsCount":57,"forksCount":30,"license":"Apache License 2.0","participation":[8,18,9,6,15,3,12,4,7,5,12,3,14,14,3,10,14,4,11,12,29,13,11,12,10,13,10,1,2,4,3,14,2,0,0,1,5,0,1,5,3,4,5,3,1,5,2,1,2,0,1,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-11T00:30:39.251Z"}},{"type":"Public","name":"sv-tests","owner":"chipsalliance","isFork":false,"description":"Test suite designed to check compliance with the SystemVerilog standard.","allTopics":["rtl","verilog","systemverilog","hdl","compliance-testing","symbiflow"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":23,"issueCount":48,"starsCount":261,"forksCount":69,"license":"ISC License","participation":[2,30,55,39,41,45,41,40,36,27,50,41,34,45,18,33,29,49,29,29,23,38,36,33,29,37,38,36,25,49,33,55,32,41,20,12,36,22,53,15,2,0,0,0,0,0,0,0,2,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-20T14:53:48.267Z"}},{"type":"Public","name":"aib-protocols","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":2,"starsCount":21,"forksCount":6,"license":"Apache License 2.0","participation":[0,0,1,0,0,0,0,0,0,0,0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-20T10:50:35.085Z"}},{"type":"Public","name":"verible-formatter-action","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":3,"starsCount":7,"forksCount":8,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-02-02T13:24:44.655Z"}},{"type":"Public","name":"uvm-verilator","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":58,"forksCount":15,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-09-20T11:28:22.526Z"}},{"type":"Public","name":"Cores-VeeR-EH1","owner":"chipsalliance","isFork":false,"description":"VeeR EH1 core","allTopics":["processor","rtl","risc","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","veer","fpga","riscv","risc-v"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":3,"issueCount":14,"starsCount":781,"forksCount":210,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-05-29T19:16:55.794Z"}},{"type":"Public","name":"Cores-VeeR-EH2","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":12,"starsCount":204,"forksCount":56,"license":"Apache License 2.0","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-12-22T16:53:54.638Z"}}],"repositoryCount":8,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}