{"payload":{"pageCount":4,"repositories":[{"type":"Public","name":"chisel-interface","owner":"chipsalliance","isFork":false,"description":"The 'missing header' for Chisel","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":32,"issueCount":0,"starsCount":12,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-11T01:22:35.187Z"}},{"type":"Public","name":"t1","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":12,"issueCount":14,"starsCount":91,"forksCount":18,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-11T01:08:39.182Z"}},{"type":"Public","name":"caliptra-rtl","owner":"chipsalliance","isFork":false,"description":"HW Design Collateral for Caliptra RoT IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":12,"issueCount":47,"starsCount":57,"forksCount":30,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-11T00:30:39.251Z"}},{"type":"Public","name":"f4pga","owner":"chipsalliance","isFork":false,"description":"FOSS Flow For FPGA","allTopics":["documentation","sphinx","symbiflow"],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":11,"issueCount":13,"starsCount":328,"forksCount":45,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-11T00:17:36.582Z"}},{"type":"Public","name":"verible","owner":"chipsalliance","isFork":false,"description":"Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server","allTopics":["productivity","analysis","style-linter","language-server-protocol","syntax-tree","lexer","yacc","systemverilog","hacktoberfest","lsp-server","systemverilog-parser","systemverilog-developer","sv-lrm","verible","parser","formatter","linter"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":29,"issueCount":449,"starsCount":1241,"forksCount":195,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T22:57:29.518Z"}},{"type":"Public","name":"caliptra-dpe","owner":"chipsalliance","isFork":false,"description":"High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":5,"issueCount":10,"starsCount":14,"forksCount":19,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T20:55:12.361Z"}},{"type":"Public","name":"caliptra-sw","owner":"chipsalliance","isFork":false,"description":"Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test","allTopics":[],"primaryLanguage":{"name":"Rust","color":"#dea584"},"pullRequestCount":55,"issueCount":66,"starsCount":47,"forksCount":34,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T16:18:39.923Z"}},{"type":"Public","name":"Cores-VeeR-EL2","owner":"chipsalliance","isFork":false,"description":"VeeR EL2 Core","allTopics":["fpga","processor","riscv","rtl","risc-v","open-source-hardware","fusesoc","verilator","riscv32","western-digital","axi4","ahb-lite","asic-design","el2"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":28,"starsCount":228,"forksCount":68,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T14:03:11.558Z"}},{"type":"Public","name":"chisel","owner":"chipsalliance","isFork":false,"description":"Chisel: A Modern Hardware Design Language","allTopics":["chip-generator","chisel","rtl","chisel3","firrtl","scala","verilog"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":141,"issueCount":290,"starsCount":3785,"forksCount":575,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T07:10:13.804Z"}},{"type":"Public","name":"sv-tests-results","owner":"chipsalliance","isFork":false,"description":"Output of the sv-tests runs.","allTopics":[],"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-10T02:51:35.634Z"}},{"type":"Public","name":"dromajo","owner":"chipsalliance","isFork":false,"description":"RISC-V RV64GC emulator designed for RTL co-simulation","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":6,"issueCount":18,"starsCount":201,"forksCount":60,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-09T22:26:49.578Z"}},{"type":"Public","name":"verilator","owner":"chipsalliance","isFork":true,"description":"Verilator open-source SystemVerilog simulator and lint system","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":33,"forksCount":548,"license":"GNU Lesser General Public License v3.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-09T10:12:40.519Z"}},{"type":"Public","name":"Caliptra","owner":"chipsalliance","isFork":false,"description":"Caliptra IP and firmware for integrated Root of Trust block","allTopics":[],"primaryLanguage":null,"pullRequestCount":2,"issueCount":11,"starsCount":104,"forksCount":27,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-07T21:52:56.539Z"}},{"type":"Public","name":"rocket-chip-fpga-shells","owner":"chipsalliance","isFork":false,"description":"Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":1,"issueCount":1,"starsCount":15,"forksCount":17,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-06T17:57:36.575Z"}},{"type":"Public","name":"rocket-chip","owner":"chipsalliance","isFork":false,"description":"Rocket Chip Generator","allTopics":["chisel","scala","rocket-chip","chip-generator","riscv","rtl"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":58,"issueCount":221,"starsCount":3064,"forksCount":1080,"license":"Other","participation":[15,0,5,3,5,0,8,1,2,19,2,0,0,2,1,9,0,0,0,0,2,2,2,4,0,0,1,0,2,1,1,5,2,0,0,2,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-06T17:38:10.460Z"}},{"type":"Public","name":"firrtl-spec","owner":"chipsalliance","isFork":false,"description":"The specification for the FIRRTL language","allTopics":[],"primaryLanguage":{"name":"TeX","color":"#3D6117"},"pullRequestCount":18,"issueCount":23,"starsCount":35,"forksCount":26,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-06T02:11:06.445Z"}},{"type":"Public","name":"chips-alliance-website","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SCSS","color":"#c6538c"},"pullRequestCount":3,"issueCount":9,"starsCount":3,"forksCount":3,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-06T01:30:11.588Z"}},{"type":"Public","name":"rocket-chip-inclusive-cache","owner":"chipsalliance","isFork":false,"description":"An RTL generator for a last-level shared inclusive TileLink cache controller","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":4,"issueCount":5,"starsCount":15,"forksCount":13,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T20:01:09.025Z"}},{"type":"Public","name":"rocket-chip-blocks","owner":"chipsalliance","isFork":false,"description":"RTL blocks compatible with the Rocket Chip Generator","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":5,"issueCount":0,"starsCount":14,"forksCount":14,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T19:59:29.161Z"}},{"type":"Public","name":"diplomacy","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":2,"issueCount":8,"starsCount":16,"forksCount":7,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T19:05:20.117Z"}},{"type":"Public","name":"UHDM","owner":"chipsalliance","isFork":false,"description":"Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX","allTopics":["vpi-api","serialization","listener","systemverilog","ieee-standard","vpi-interface"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":14,"starsCount":184,"forksCount":38,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-04T18:39:53.118Z"}},{"type":"Public","name":"tac","owner":"chipsalliance","isFork":false,"description":"CHIPS Alliance Technical Advisory Council","allTopics":[],"primaryLanguage":null,"pullRequestCount":1,"issueCount":19,"starsCount":5,"forksCount":21,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-31T20:47:22.871Z"}},{"type":"Public","name":"firrtl","owner":"chipsalliance","isFork":false,"description":"Flexible Intermediate Representation for RTL","allTopics":["compiler","hardware","representation","transformation","intermediate","firrtl"],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":111,"issueCount":175,"starsCount":703,"forksCount":175,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-31T16:14:01.438Z"}},{"type":"Public","name":"rocket-pcb","owner":"chipsalliance","isFork":false,"description":"PCB libraries and templates for rocket-chip based FPGA/ASIC designs ","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":1,"issueCount":0,"starsCount":6,"forksCount":2,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-30T09:09:56.039Z"}},{"type":"Public","name":"riscv-dv","owner":"chipsalliance","isFork":false,"description":"Random instruction generator for RISC-V processor verification","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":10,"issueCount":109,"starsCount":964,"forksCount":310,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-29T02:34:53.567Z"}},{"type":"Public","name":"homebrew-verible","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"Ruby","color":"#701516"},"pullRequestCount":1,"issueCount":3,"starsCount":15,"forksCount":8,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-28T23:46:50.587Z"}},{"type":"Public","name":"rocket-pcblib","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":0,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-26T08:01:14.715Z"}},{"type":"Public template","name":"chisel-template","owner":"chipsalliance","isFork":false,"description":"A template project for beginning new Chisel work","allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":3,"issueCount":11,"starsCount":543,"forksCount":175,"license":"The Unlicense","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-26T06:51:00.234Z"}},{"type":"Public","name":"VeeRwolf","owner":"chipsalliance","isFork":false,"description":"FuseSoC-based SoC for VeeR EH1 and EL2","allTopics":["tools","fusesoc","swerv","veer"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":21,"starsCount":265,"forksCount":59,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-25T14:30:01.500Z"}},{"type":"Public","name":"verible-actions-common","owner":"chipsalliance","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":1,"issueCount":0,"starsCount":1,"forksCount":4,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-23T19:37:26.989Z"}}],"repositoryCount":97,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}