{"payload":{"header_redesign_enabled":false,"results":[{"id":"378749586","archived":false,"color":"#b2b7f8","followers":104,"has_funding_file":true,"hl_name":"ultraembedded/openlogicbit","hl_trunc_description":"Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":378749586,"name":"openlogicbit","owner_id":7809581,"owner_login":"ultraembedded","updated_at":"2021-06-24T19:24:26.694Z","has_issues":true}},"sponsorable":true,"topics":["fpga","verilog","logic-analyzer","xilinx-fpga","altera-fpga","lattice-fpga","digital-signal-analyzer","ftdi232h","ftdi2232h"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":59,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aultraembedded%252Fopenlogicbit%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/ultraembedded/openlogicbit/star":{"post":"rIuMPMnhZPMezwoK8VBepTpffalmGrKHqZRXM0G81UKn_oP2PSVTjExxGEFiXdaMbmO9v_VhkG3o_S4EZE00Tg"},"/ultraembedded/openlogicbit/unstar":{"post":"W-ZZVJFqxX1jlBshiq5oiyUImAi6ugYA5H7Q2AfOcJmcga2kXJxeZ4PviN1tLVCsQD3bTjSpY3G1VbrAf0zYug"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"BKNCJ3m-SuOlXMM5gDsDZKFGsCm_t8VKfxkJ8F76NKAHoaTipNpezmojydiZ7rSd0rPZSPY8IcrDu2V1k8YDHQ"}}},"title":"Repository search results"}