alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
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Verilog Ethernet components for FPGA implementation
HDL libraries and projects
PicoRV32 - A Size-Optimized RISC-V CPU
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
The USRP™ Hardware Driver Repository
SERV - The SErial RISC-V CPU
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
The Ultra-Low Power RISC-V Core