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aie2p Bitwise Intrinsics Support for int16_t

Status: Open.

#2406 In Xilinx/mlir-aie;

· yenjames opened on Jun 18, 2025

How to compile kernel into my IRON py code

Status: Open.

#2404 In Xilinx/mlir-aie;

· derekharker opened on Jun 18, 2025

Seeking Suggestions: aie.masterset Port Binding Error using packet flow

Status: Open.

#2403 In Xilinx/mlir-aie;

· ngdymx opened on Jun 18, 2025

The conversion from AIE Vector to C++ via <code>aie-translate --aievec-to-cpp</code> encountered an error during single kernel simulation.

Status: Open.

#2400 In Xilinx/mlir-aie;

· micropuma opened on Jun 17, 2025

GEMM whole array example matrix A tiling issue

Status: Open.

#2392 In Xilinx/mlir-aie;

· RonZ13 opened on Jun 12, 2025

<code>i8</code>x<code>i8</code> GEMM not functional using Peano on Phoenix for certain sizes

bugSomething isn't workingSomething isn't working

Status: Open.

#2388 In Xilinx/mlir-aie;

· andrej opened on Jun 11, 2025

Feature Request: Driver bump to allow user define buffer during bo buffer allocation

Status: Open.

#2380 In Xilinx/mlir-aie;

· joeldushouyu opened on Jun 5, 2025

Feature idea: explicit design with memTiles in IRON

enhancementNew feature or requestNew feature or request

Status: Open.

#2376 In Xilinx/mlir-aie;

· userVector opened on Jun 5, 2025

CI needs more OpenCV

Status: Open.

#2369 In Xilinx/mlir-aie;

· fifield opened on Jun 4, 2025

Incorrect kernel in documentation

Status: Open.

#2364 In Xilinx/mlir-aie;

· planetA opened on Jun 3, 2025

VCK190 platform file outdated

aie1

questionFurther information is requestedFurther information is requested

Status: Open.

#2357 In Xilinx/mlir-aie;

· derekharker opened on Jun 2, 2025

Add trace overrun check so invalid trace capture is flagged and reported during trace generation

enhancementNew feature or requestNew feature or request

Status: Open.

#2356 In Xilinx/mlir-aie;

· jackl-xilinx opened on Jun 2, 2025