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While exploring the toolset and fiddling around with Calyx/CF code, I found this:
func.func @main(%arg0 : i32, %arg1 : i32) -> i32 {
%0 = arith.cmpi slt, %arg0, %arg1 : i32
cf.cond_br %0, ^bb1, ^bb2
^bb1:
cf.br ^bb3(%arg0 : i32)
^bb2:
cf.br ^bb3(%arg1 : i32)
^bb3(%1 : i32):
return %1 : i32
}
$ ./bin/hlstool --calyx-hw --verilog test02.mlir --lowering-options=noAlwaysComb | grep always_comb
always_comb begin // test02.mlir:1:1
end // always_comb
The above was done with a download of firtool-1.112.0
from the releases page.
This is problematic because unfortunately yosys is very anal about this issue and absolutely refuses to synthesize if this is the case:
3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
ERROR: Latch inferred for signal `\control_main.\state_next' from always_comb process `\control_main.$proc$control_main.sv:0$2'.
Though it's unclear to me if it's actually a yosys bug (other synthesis tools apparently accept it?) I also might be holding hlstool
wrong too.
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