[ImportVerilog] Request to expose a SystemVerilog Top in FIRRTL

[sequencer]

We are trying to link SystemVerilog against FIRRTL at CIRCT time.
I'm requesting a API to expose SystemVerilog as FIRRTL Blackbox, being able to inspect via C-API, which can be linked to other modules later in the FIRRTL.
This feature originally is done in AutoBlackBox in Chisel, however to do it more elegantly, it's necessary to migrate this feature to CIRCT.