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vitis

Here are 109 public repositories matching this topic...

Xilinx / Vitis-Tutorials

Vitis In-Depth Tutorials

embedded fpga embedded-systems versal alveo zcu102 xrt vitis aiengine zcu104 kria

Updated Aug 20, 2025
C

Xilinx / XRT

Run Time for AIE and FPGA based platforms

fpga linux-kernel xrt vitis

Updated Aug 20, 2025
C++

Vitis_Accel_Examples

Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Aug 15, 2025
Makefile

pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Aug 19, 2025
Tcl

definelicht / hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga hpc xilinx sdaccel high-level-synthesis vivado-hls intel-fpga vitis intel-fpga-opencl

Updated Jan 20, 2025
C++

fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

tcp xilinx vitis network-kernel

Updated Apr 23, 2024
C++

Xilinx / xup_vitis_network_example

VNx: Vitis Network Examples

networking xilinx alveo vnx vitis vitis-network alveo-card

Updated Aug 1, 2024
Jupyter Notebook

Xilinx / Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

fpga hls acap vitis aiengine

Updated Aug 13, 2025
C++

metr0jw / Spiking-Neural-Network-on-FPGA

FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch

hls computational-neuroscience verilog xilinx spiking-neural-networks vivado pynq verilog-hdl snn neuromorphic-computing leaky-integrate-and-fire-neuron lif-neuron spiking-neural-network vitis leaky-integrate-and-fire-model lif-model

Updated Jun 30, 2025
Verilog

Xilinx / xup_compute_acceleration

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

fpga xilinx vitis xup

Updated Jul 24, 2024
C++

FedericoSerafini / HLS-CNN

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

asic fpga stream hls pipeline hardware accelerator parallel cnn rtl synthesis hdl high-level-synthesis vitis

Updated Jul 25, 2024
C

spcl / apfp

FPGA acceleration of arbitrary precision floating point computations.

fpga hls hpc bignum arbitrary-precision high-performance-computing xilinx gmp mpfr high-level-synthesis vivado-hls vitis multiple-precision

Updated May 17, 2022
C++

lvgl / lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

embedded usb tcp amd mouse freertos ntp xilinx vivado touchscreen zedboard vga digilent lvgl vitis

Updated Oct 12, 2023
C

noecochetel / North_American_Vitis_Pangenome

Construct and Analyze the North American Vitis pangenome

genomics grapevine pangenomics vitis

Updated Aug 19, 2025
R

jasonlin316 / GCN-Inference-Acceleration-HLS

An end-to-end GCN inference accelerator written in HLS

neural-network hls end-to-end inference xilinx gcn vitis

Updated Apr 5, 2022
C++

salehjg / DeepPoint-V2-FPGA

The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs

fpga deep-learning hls xilinx pointcloud sdaccel shapenet-dataset modelnet-dataset vitis

Updated Mar 6, 2023
C++

CGCL-codes / ScalaBFS

A Scalable BFS Accelerator on FPGA-HBM Platform

fpga bfs computing hbm xrt vitis

Updated Feb 22, 2024
Scala

IMPETUS-UdeS / rule4ml

Resource Utilization and Latency Estimation for ML on FPGA.

python machine-learning fpga neural-network hls keras prediction pytorch vivado regression-models resource-utilization onnx surrogate-models vitis

Updated Jul 16, 2025
Python

pavel-demin / eclypse-z7-notes

Notes on the Eclypse Z7 development board

fpga zynq dsp tcl verilog xilinx sdr vivado digilent vitis eclypse-z7

Updated Jul 2, 2025
C

Mapping-Multiple-LSTM-Models-on-FPGAs

ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAs

Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.

machine-learning fpga hls cpp14 xilinx fpga-accelerator svd-matrix-factorisation vitis

Updated Mar 3, 2023
Jupyter Notebook

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